SN54/74LS373 SN54/74LS374 OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54 / 74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. The SN54 / 74LS374 is a high-speed, low-power Octal D-type Flip-Flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) is common to all flip-flops. The SN54 / 74LS374 is manufactured using advanced Low Power Schottky technology and is compatible with all Motorola TTL families. • • • • • • • LOW POWER SCHOTTKY 20 1 Eight Latches in a Single Package 3-State Outputs for Bus Interfacing Hysteresis on Latch Enable Edge-Triggered D-Type Inputs Buffered Positive Edge-Triggered Clock Hysteresis on Clock Input to Improve Noise Margin Input Clamp Diodes Limit High Speed Termination Effects PIN NAMES J SUFFIX CERAMIC CASE 732-03 N SUFFIX PLASTIC CASE 738-03 20 1 DW SUFFIX SOIC CASE 751D-03 LOADING (Note a) 20 HIGH 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 65 (25) U.L. Data Inputs Latch Enable (Active HIGH) Input Clock (Active HIGH going edge) Input Output Enable (Active LOW) Input Outputs (Note b) D0 – D7 LE CP OE O0 – O7 LOW 1 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 15 (7.5) U.L. ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC NOTES: a) 1 TTL Units Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 7.5 U.L. for Military (54) and 25 U.L. for Commercial (74) Temperature Ranges. The Output HIGH drive factor is 25 U.L. for Military (54) and 65 U.L. for Commercial (74) Temperature Ranges. CONNECTION DIAGRAM DIP (TOP VIEW) SN54 / 74LS374 SN54 / 74LS373 VCC O7 D7 D6 O6 O5 D5 D4 O4 LE VCC O7 D7 D6 O6 O5 D5 D4 O4 CP 20 19 18 17 16 15 14 13 12 11 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 OE O0 D0 D1 O1 O2 D2 D3 O3 GND NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 2 3 4 5 6 7 8 9 10 OE O0 D0 D1 O1 O2 D2 D3 O3 GND FAST AND LS TTL DATA 5-521 SN54/74LS373 • SN54/74LS374 TRUTH TABLE LS373 LS374 Dn LE OE On Dn H H L H H L H L L L X L L Q0 X X X H Z* LE X OE On L H L L H Z* H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance * Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE). LOGIC DIAGRAMS SN54LS / 74LS373 SN54LS / 74LS374 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 – 55 0 25 25 125 70 °C IOH Output Current — High 54 74 – 1.0 – 2.6 mA IOL Output Current — Low 54 74 12 24 mA FAST AND LS TTL DATA 5-522 SN54/74LS373 • SN54/74LS374 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Min Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IOZH Typ Max Unit 2.0 54 0.7 74 0.8 – 0.65 – 1.5 Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA 54 2.4 3.4 V 74 2.4 3.1 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 54, 74 0.25 0.4 V IOL = 12 mA 74 0.35 0.5 V IOL = 24 mA Output Off Current HIGH 20 µA VCC = MAX, VOUT = 2.7 V IOZL Output Off Current LOW – 20 µA VCC = MAX, VOUT = 0.4 V IIH Input HIGH Current IIL Input LOW Current IOS Short Circuit Current (Note 1) ICC Power Supply Current – 30 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V – 0.4 mA VCC = MAX, VIN = 0.4 V – 130 mA VCC = MAX 40 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits LS373 Symbol Parameter Min LS374 Typ Max Min Typ 35 50 Unit Max fMAX Maximum Clock Frequency tPLH tPHL Propagation Delay, Data to Output 12 12 18 18 tPLH tPHL Clock or Enable to Output 20 18 30 30 15 19 28 28 ns tPZH tPZL Output Enable Time 15 25 28 36 20 21 28 28 ns tPHZ tPLZ Output Disable Time 12 15 20 25 12 15 20 25 ns Test Conditions MHz ns CL = 45 pF, RL = 667 Ω CL = 5.0 pF AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits LS373 Symbol Parameter Min LS374 Max Min Max Unit tW Clock Pulse Width 15 15 ns ts Setup Time 5.0 20 ns th Hold Time 20 0 ns DEFINITION OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to LE transition from HIGH-to-LOW in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the LE transition from HIGH-to-LOW that the logic level must be maintained at the input in order to ensure continued recognition. FAST AND LS TTL DATA 5-523 SN54/74LS373 AC WAVEFORMS Figure 1 Figure 2 Figure 3 AC LOAD CIRCUIT SWITCH POSITIONS Ω * Includes Jig and Probe Capacitance. Figure 4 FAST AND LS TTL DATA 5-524 SYMBOL SW1 SW2 tPZH Open Closed tPZL Closed Open tPLZ Closed Closed tPHZ Closed Closed SN54/74LS374 AC WAVEFORMS ≈ Figure 6 Figure 5 ≥ ≈ Figure 7 AC LOAD CIRCUIT SWITCH POSITIONS Ω * Includes Jig and Probe Capacitance. Figure 8 FAST AND LS TTL DATA 5-525 SYMBOL SW1 SW2 tPZH Open Closed tPZL Closed Open tPLZ Closed Closed tPHZ Closed Closed Case 751D-03 DW Suffix 20-Pin Plastic SO-20 (WIDE) "! ! " -A11 1 10 ! " # P C -T- " #! D J F K ! #! * * !" $ !" M * R X 45° " " %# G ! " ! -B- ! " 20 & ! ! ° ° ° ° ) ) ) ! Case 732-03 J Suffix 20-Pin Ceramic Dual In-Line "! ! $" '' " # !" " !" " %# 20 " 11 1 10 B L C F N H G D J M K Case 738-03 N Suffix 20-Pin Plastic ! ! ° ° ° ° ! " " ! ( " " B ! ! $ ! ( ! " # ! C -T- L K G ! & 11 E ! 10 1 #! !#! "! -A20 ! $ A " " " N M F J D " " FAST AND LS TTL DATA 5-526 * !" $ !" * ! ! ! ! ! ° ° ! ° ° Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. 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SYMBOL SW1 SW2 tPLZ Closed Closed tPHZ Closed Closed Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. tPZH Open Closed EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. tPZL Closed Open ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. ◊ FAST AND LS TTL DATA 5-527