TI SN74ABT162825

SN54ABT162825, SN74ABT162825
18-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS474C – JUNE 1994 – REVISED MAY 1997
D
D
D
D
D
D
D
D
SN54ABT162825 . . . WD PACKAGE
SN74ABT162825 . . . DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus  Family
Output Ports Have Equivalent 25-Ω Series
Resistors, So No External Resistors Are
Required
State-of-the-Art EPIC-ΙΙB  BiCMOS Design
Significantly Reduces Power Dissipation
Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
High-Impedance State During Power Up
and Power Down
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Package and
380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center
Spacings
1OE1
1Y1
1Y2
GND
1Y3
1Y4
VCC
1Y5
1Y6
1Y7
GND
1Y8
1Y9
GND
GND
2Y1
2Y2
GND
2Y3
2Y4
2Y5
VCC
2Y6
2Y7
GND
2Y8
2Y9
2OE1
description
The ’ABT162825 are 18-bit buffers and line
drivers designed specifically to improve both the
performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented
receivers and transmitters. These devices
provide true data, and can be used as two 9-bit
buffers or one 18-bit buffer.
The 3-state control gate is a 2-input AND gate with
active-low inputs so that if either output-enable
(OE1 or OE2) input is high, all nine affected
outputs are in the high-impedance state.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OE2
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
1A7
GND
1A8
1A9
GND
GND
2A1
2A2
GND
2A3
2A4
2A5
VCC
2A6
2A7
GND
2A8
2A9
2OE2
The outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors to
reduce overshoot and undershoot.
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT162825 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT162825 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Copyright  1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ABT162825, SN74ABT162825
18-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS474C – JUNE 1994 – REVISED MAY 1997
FUNCTION TABLE
(each 9-bit buffer)
INPUTS
OE1
OE2
A
OUTPUT
Y
L
L
L
L
H
L
L
H
H
X
X
Z
X
H
X
Z
logic symbol†
1
1OE1
1OE2
2OE2
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1A9
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2A9
&
29
55
54
1OE1
EN1
56
28
2OE1
logic diagram (positive logic)
1OE2
&
1A1
EN2
1
2
3
52
5
51
6
49
8
48
9
47
10
45
12
44
13
41
40
2
16
17
38
19
37
20
36
21
34
23
33
24
31
26
30
27
56
55
2
1Y1
1Y1
To Eight Other Channels
1Y2
1Y3
1Y4
2OE1
1Y5
2OE2
1Y6
1Y7
2A1
28
29
41
16
1Y8
1Y9
To Eight Other Channels
2Y1
2Y2
2Y3
2Y4
2Y5
2Y6
2Y7
2Y8
2Y9
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
2
1
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• DALLAS, TEXAS 75265
2Y1
SN54ABT162825, SN74ABT162825
18-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS474C – JUNE 1994 – REVISED MAY 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 3)
SN54ABT162825
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
High-level input voltage
SN74ABT162825
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
2
2
0.8
Input voltage
0
Low-level output current
Control inputs
∆t/∆v
Input transition rise or fall rate
∆t/∆VCC
TA
Power-up ramp rate
200
Operating free-air temperature
–55
Data inputs
VCC
–12
V
V
0.8
0
UNIT
V
VCC
–12
mA
12
12
mA
9
9
10
10
–40
ns/V
µs/V
200
125
V
85
°C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54ABT162825, SN74ABT162825
18-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS474C – JUNE 1994 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = –18 mA
IOH = –1 mA
VCC = 5 V,
IOH = –1 mA
IOH = –3 mA
VCC = 4
4.5
5V
VOL
VCC = 4
4.5
5V
Vhys
II
MIN
TA = 25°C
SN54ABT162825
TYP†
MAX
MIN
MAX
–1.2
IOH = –12 mA
IOL = 8 mA
SN74ABT162825
MIN
–1.2
–1.2
2.5
2.5
2.5
3
3
3
2.4
2.4
2.4
2
2
0.4
0.8
UNIT
V
V
2
0.8
0.65
IOL = 12 mA
0.8
100
VCC = 0 to 5.5 V, VI = VCC or GND
VCC = 0 to 2.1 V,
VO = 0.5 V to 2.7 V, OE = X
IOZPU‡
V
mV
±1
±1
±1
µA
±50
±50
±50
µA
±50
±50
±50
µA
IOZPD‡
VCC = 2.1 V to 0,
VO = 0.5 V to 2.7 V, OE = X
IOZH§
VCC = 2.1 V to 5.5 V,
VO = 2.7 V, OE ≥ 2 V
10
10
10
µA
IOZL§
VCC = 2.1 V to 5.5 V,
VO = 0.5 V, OE ≥ 2 V
–10
–10
–10
µA
±100
µA
50
µA
–100
mA
Ioff
ICEX
Outputs high
IO¶
VCC = 0,
VCC = 5.5 V,
VI or VO ≤ 4.5 V
VO = 5.5 V
VCC = 5.5 V,
VO = 2.5 V
±100
50
–25
–75
Outputs high
ICC
Outputs low
Outputs
disabled
Data inputs
∆ICC#
Control inputs
Ci
VCC = 5.5 V, IO = 0,
VI = VCC or GND
VCC = 5.5 V,
One input at
3 4 V,
3.4
V
Other inputs at
VCC or GND
–100
50
–25
–100
–25
2
2
2
32
32
32
2
2
2
Outputs enabled
1
1.5
1
Outputs disabled
0.05
1
0.05
1.5
1.5
1.5
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
3.5
Co
8
† All typical values are at VCC = 5 V.
‡ This parameter is characterized, but not production tested.
§ The parameters IOZH and IOZL include the input leakage current.
¶ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
# This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
MAX
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• DALLAS, TEXAS 75265
mA
mA
pF
pF
SN54ABT162825, SN74ABT162825
18-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS474C – JUNE 1994 – REVISED MAY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
Y
tPZH
tPZL
OE
Y
tPHZ
tPLZ
OE
Y
PARAMETER
VCC = 5 V,
TA = 25°C
SN54ABT162825
SN74ABT162825
MIN
TYP
MAX
MIN
MAX
MIN
MAX
1
2.1
3.6
1
4.1
1
3.9
1.1
2.8
4.2
1.1
5
1.1
4.7
1.5
3.4
6.3
1.5
7.2
1.5
6.9
1.6
3.5
7.3
1.6
6.6
1.6
6.3
2.1
4.1
6.5
2.1
6.8
2.1
6.6
1.5
3.5
5.9
1.5
7.3
1.5
6.3
UNIT
ns
ns
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN54ABT162825, SN74ABT162825
18-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS474C – JUNE 1994 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
7V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
3V
LOAD CIRCUIT
Timing Input
1.5 V
0V
tw
tsu
3V
Input
1.5 V
1.5 V
th
3V
Data Input
1.5 V
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
VOH
1.5 V
Output
1.5 V
VOL
VOH
Output
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
tPLH
tPHL
1.5 V
tPZL
tPHL
tPLH
3V
Output
Control
Output
Waveform 2
S1 at Open
(see Note B)
1.5 V
tPZH
3.5 V
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright  1998, Texas Instruments Incorporated