TI SN74ABT16821DLR

SN54ABT16821, SN74ABT16821
20-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS216B – JUNE 1992 – REVISED JANUARY 1997
D
D
D
D
D
D
D
D
SN54ABT16821 . . . WD PACKAGE
SN74ABT16821 . . . DGG OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus  Family
State-of-the-Art EPIC-ΙΙB  BiCMOS Design
Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
High-Drive Outputs (–32-mA IOH,
64-mA IOL )
Package Options Include Plastic Thin
Shrink Small-Outline (DGG), 300-mil Shrink
Small-Outline (DL) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2Q10
2OE
description
These 20-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing wider buffer
registers, I/O ports, bidirectional bus drivers with
parity, and working registers.
The ’ABT16821 can be used as two 10-bit
flip-flops or one 20-bit flip-flop. The 20 flip-flops
are edge-triggered D-type flip-flops. On the
positive transition of the clock (CLK) input, the
device provides true data at the Q outputs.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1CLK
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9
2D10
2CLK
A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high
or low logic level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16821 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16821 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Copyright  1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ABT16821, SN74ABT16821
20-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS216B – JUNE 1992 – REVISED JANUARY 1997
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
L
X
Q0
H
X
X
Z
logic symbol†
1OE
1CLK
2OE
2CLK
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1D9
1D10
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2D9
2D10
1
56
28
EN2
C1
EN4
29
C3
55
1D
2
3
52
5
51
6
49
8
48
9
47
10
45
12
44
13
43
14
42
3D
4
15
41
16
40
17
38
19
37
20
36
21
34
23
33
24
31
26
30
27
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
2
54
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• DALLAS, TEXAS 75265
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2Q9
2Q10
SN54ABT16821, SN74ABT16821
20-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS216B – JUNE 1992 – REVISED JANUARY 1997
logic diagram (positive logic)
1OE
1CLK
1
56
One of Ten
Channels
1D1
C1
55
2
1D
1Q1
To Nine Other Channels
2OE
2CLK
28
29
One of Ten
Channels
C1
42
2D1
1D
15
2Q1
To Nine Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT16821 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT16821 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54ABT16821, SN74ABT16821
20-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS216B – JUNE 1992 – REVISED JANUARY 1997
recommended operating conditions (see Note 3)
SN54ABT16821
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
∆t /∆v
Input transition rise or fall rate
High-level input voltage
SN74ABT16821
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
2
2
0.8
Input voltage
0
Low-level output current
Outputs enabled
TA
Operating free-air temperature
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
–55
0
V
V
0.8
VCC
–24
UNIT
VCC
–32
V
V
mA
48
64
mA
10
10
ns/ V
85
°C
125
–40
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = –18 mA
IOH = –3 mA
VCC = 5 V,
VCC = 4
4.5
5V
VOL
Vhys
II
IOZH
IOZL
Ioff
ICEX
IO‡
VCC = 4
4.5
5V
TA = 25°C
TYP†
MAX
SN54ABT16821
MIN
–1.2
MAX
SN74ABT16821
MIN
–1.2
2.5
2.5
IOH = –3 mA
IOH = –24 mA
3
3
3
2
2
IOH = –32 mA
IOL = 48 mA
2*
IOL = 64 mA
0.55
100
VI = VCC or GND
VO = 2.7 V
VCC = 5.5 V,
VCC = 0,
VO = 0.5 V
VI or VO ≤ 4.5 V
VCC = 5.5 V,
VCC = 5.5 V,
VO = 5.5 V
VO = 2.5 V
±1
±1
±1
µA
50
50
50
µA
–50
– 50
– 50
µA
±100
µA
50
µA
–200
mA
50
–100
V
mV
±100
Outputs high
–50
V
V
0.55
0.55*
VCC = 5.5 V,
VCC = 5.5 V,
UNIT
2
0.55
–200
50
–50
–200
–50
Outputs high
500
500
500
µA
Outputs low
89
89
89
mA
500
500
500
µA
1.5
1.5
1.5
mA
5 5 V,
V IO = 0,
0
VCC = 5.5
VI = VCC or GND
∆ICC§
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
Ci
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
Outputs disabled
3.5
pF
7.5
pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
† All typical values are at VCC = 5 V.
‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
§ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
MAX
–1.2
2.5
ICC
Co
MIN
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ABT16821, SN74ABT16821
20-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS216B – JUNE 1992 – REVISED JANUARY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,
TA = 25°C
SN54ABT16821
SN74ABT16821
MIN
MAX
MIN
MAX
MIN
MAX
0
150
0
150
0
150
UNIT
fclock
tw
Clock frequency
MHz
Pulse duration, CLK high or low
3.3
3.3
3.3
ns
tsu
th
Setup time, data before CLK↑
1.8
1.8
1.8
ns
Hold time, data after CLK↑
1.3
1.3
1.3
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°C
MIN
SN54ABT16821
TYP
MAX
1.3
3.7
5.1
1.3
6.7
1.3
6.1
1.6
3.9
5.1
1.6
5.8
1.6
5.4
1.1
3.2
4.7
1.1
5.8
1.1
5.7
1.6
3.8
5
1.6
5.7
1.6
5.6
2
4.5
5.7
2
6.6
2
6.5
1.8
4.1
5.8
1.8
8.4
1.8
7.1
150
CLK
Q
OE
Q
OE
Q
MIN
MAX
SN74ABT16821
150
MIN
UNIT
MAX
150
MHz
ns
ns
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN54ABT16821, SN74ABT16821
20-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS216B – JUNE 1992 – REVISED JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
7V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
LOAD CIRCUIT
3V
Timing Input
1.5 V
0V
tw
tsu
3V
Input
1.5 V
th
3V
1.5 V
Data Input
1.5 V
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
Input
1.5 V
0V
VOH
1.5 V
Output
1.5 V
VOL
VOH
Output
1.5 V
1.5 V
VOL
1.5 V
0V
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
tPLH
tPHL
1.5 V
tPZL
tPHL
tPLH
3V
Output
Control
1.5 V
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
tPZH
3.5 V
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
[0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
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PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74ABT16821DGGRE4
ACTIVE
TSSOP
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74ABT16821DGGRG4
ACTIVE
TSSOP
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT16821DGGR
ACTIVE
TSSOP
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT16821DL
ACTIVE
SSOP
DL
56
20
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT16821DLG4
ACTIVE
SSOP
DL
56
20
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT16821DLR
ACTIVE
SSOP
DL
56
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT16821DLRG4
ACTIVE
SSOP
DL
56
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74ABT16821DGGR
TSSOP
DGG
56
2000
330.0
24.4
8.6
15.6
1.8
12.0
24.0
Q1
SN74ABT16821DLR
SSOP
DL
56
1000
330.0
32.4
11.35
18.67
3.1
16.0
32.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74ABT16821DGGR
TSSOP
DGG
56
2000
346.0
346.0
41.0
SN74ABT16821DLR
SSOP
DL
56
1000
346.0
346.0
49.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
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MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
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logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lprf
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