SN54ABT657A, SN74ABT657A OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS SCBS192E – JANUARY 1991 – REVISED JUNE 1997 D D D D D D D State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C High-Impedance State During Power Up and Power Down Flow-Through Architecture Optimizes PCB Layout High-Drive Outputs (–32-mA IOH, 64-mA IOL) Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs SN54ABT657A . . . JT PACKAGE SN74ABT657A . . . DW OR NT PACKAGE (TOP VIEW) T/R A1 A2 A3 A4 A5 VCC A6 A7 A8 ODD/EVEN ERR Odd or even parity is selected by a logic high or low level on the ODD/EVEN input. PARITY carries the parity-bit value; it is an output from the parity generator/checker in the transmit mode and an input to the parity generator/checker in the receive mode. 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 OE B1 B2 B3 B4 GND GND B5 B6 B7 B8 PARITY SN54ABT657A . . . FK PACKAGE (TOP VIEW) description 4 ODD/EVEN ERR PARITY NC B8 B7 B6 5 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 19 11 12 13 14 15 16 17 18 A3 A2 A1 NC T/R OE B1 B5 GND GND NC B4 B3 B2 The 'ABT657A transceivers have eight noninverting buffers with parity-generator/ checker circuits and control signals. The transmit/receive (T/R) input determines the direction of data flow. When T/R is high, data flows from the A port to the B port (transmit mode); when T/R is low, data flows from the B port to the A port (receive mode). When the output-enable (OE) input is high, both the A and B ports are in the high-impedance state. 1 A8 A7 A6 NC VCC A5 A4 D NC – No internal connection In the transmit mode, after the A bus is polled to determine the number of high bits, PARITY is set to the logic level that maintains the parity sense selected by the level at ODD/EVEN. For example, if ODD/EVEN is low (even parity selected) and there are five high bits on the A bus, PARITY is set to the logic high level so that an even number of the nine total bits (eight A-bus bits plus parity bit) are high. In the receive mode, after the B bus is polled to determine the number of high bits, the error (ERR) output logic level indicates whether or not the data to be received exhibits the correct parity sense. For example, if ODD/EVEN is high (odd parity selected), PARITY is high, and there are three high bits on the B bus, ERR is low, indicating a parity error. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-ΙΙB is a trademark of Texas Instruments Incorporated. Copyright 1997, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABT657A, SN74ABT657A OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS SCBS192E – JANUARY 1991 – REVISED JUNE 1997 description (continued) When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT657A is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT657A is characterized for operation from –40°C to 85°C. FUNCTION TABLE NUMBER OF A OR B INPUTS THAT ARE HIGH 0 2 0, 2, 4 4, 6 6, 8 1 3 1, 3, 5 5, 7 Don’t care 2 INPUTS OUTPUTS OE T/R ODD/EVEN I/O PARITY L H H H L H L L Z Transmit L L H H H Receive L L H L L Receive L L L H L Receive L L L L H Receive L H H L Z Transmit L H L H Z Transmit L L H H L Receive L L H L H Receive L L L H H Receive L L L L L Receive H X X Z Z Z POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ERR OUTPUT MODE Z Transmit SN54ABT657A, SN74ABT657A OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS SCBS192E – JANUARY 1991 – REVISED JUNE 1997 logic symbol† OE T/R ODD/EVEN A1 24 1 11 2 G3 3 EN1/3G5 [REC] 3 EN2 [XMIT] N4 1 Z11 A2 A3 A4 A5 A6 A7 A8 23 1 2 3 22 4 21 5 20 6 17 8 16 9 15 10 14 11 12 13 14 15 16 17 18 B1 2k 13 4, 2 B2 B3 B4 B5 B6 B7 B8 PARITY 5 4, 1 12 ERR † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, JT, and NT packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABT657A, SN74ABT657A OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS SCBS192E – JANUARY 1991 – REVISED JUNE 1997 logic diagram (positive logic) T/R 1 24 OE 2 A1 23 3 22 4 21 5 20 6 17 8 16 9 15 10 14 A2 A3 A4 A5 A6 A7 A8 ODD/EVEN B1 B2 B3 B4 B5 B6 B7 B8 13 11 12 Pin numbers shown are for the DW, JT, and NT packages. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARITY ERR SN54ABT657A, SN74ABT657A OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS SCBS192E – JANUARY 1991 – REVISED JUNE 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT657A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT657A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero. recommended operating conditions (see Note 3) SN54ABT657A MAX MIN MAX 4.5 5.5 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current VCC –24 Low-level output current 48 ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature –55 High-level input voltage SN74ABT657A MIN 2 2 0.8 Input voltage 0 Outputs enabled 5 mA 64 mA 5 –40 V VCC –32 V ns/V µs/V 200 125 V V 0.8 0 UNIT 85 °C NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ABT657A, SN74ABT657A OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS SCBS192E – JANUARY 1991 – REVISED JUNE 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –3 mA VCC = 5 V, VCC = 4 4.5 5V VOL VCC = 4 4.5 5V MIN SN54ABT657A MIN –1.2 MAX SN74ABT657A MIN –1.2 2.5 2.5 IOH = –3 mA IOH = –24 mA 3 3 3 2 2 IOH = –32 mA IOL = 48 mA 2* A or B ports UNIT V V 2 0.55 IOL = 64 mA 0.55 0.55* 0.55 100 Control inputs VCC = 0 to 5.5 V, VI = VCC or GND VCC = 2.1 V to 5.5 V, VI = VCC or GND V mV ±1 ±1 ±1 ±20 ±20 ±20 µA IOZPU‡ VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X ±50 ±50 ±50 µA IOZPD‡ VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X ±50 ±50 ±50 µA IOZH§ VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE ≥ 2 V 10 10 10 µA IOZL§ VCC = 2.1 V to 5.5 V, VO = 0.5 V, OE ≥ 2 V –10 –10 –10 µA Ioff VCC = 0, VCC = 5.5 V, VO = 5.5 V VI or VO ≤ 4.5 V ±100 µA 50 µA VCC = 5.5 V, VO = 2.5 V Outputs high –200 mA ICEX IO¶ VCC = 5.5 V, IO = 0, VI = VCC or GND ICC Data inputs ∆ICC# Control inputs Ci Control inputs VCC = 5.5 V, One input at 3.4 V,, Other inputs at VCC or GND ±100 Outputs high 50 –50 –100 –200 50 –50 –200 –50 250 250 250 µA 40 40 40 mA Outputs disabled 250 250 250 µA Outputs enabled 1.5 1.5 1.5 Outputs disabled 0.25 0.25 0.25 1.5 1.5 1.5 Outputs low VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V 4 Cio A or B ports 10 * On products compliant to MIL-PRF-38535, this parameter does not apply. † All typical values are at VCC = 5 V. ‡ This parameter is characterized, but not production tested. § The parameters IOZH and IOZL include the input leakage current. ¶ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. # This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 MAX –1.2 2.5 Vhys II TA = 25°C TYP† MAX POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 mA pF pF SN54ABT657A, SN74ABT657A OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS SCBS192E – JANUARY 1991 – REVISED JUNE 1997 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPLH tPHL A PARITY tPLH tPHL ODD/EVEN PARITY ERR PARITY, tPLH tPHL B ERR tPLH tPHL PARITY ERR tPZH tPZL OE A B, B PARITY A, tPZH tPZL OE ERR tPHZ tPLZ OE A,, B,, PARITY,, or ERR PARAMETER VCC = 5 V, TA = 25°C SN54ABT657A SN74ABT657A MIN TYP MAX MIN MAX MIN MAX 1 3.2 4.2 1 5 1 4.6 1 2.8 3.8 1 4.5 1 4.3 1.8 4.8 6.3 1.8 8.5 1.8 8.1 2.3 4.9 6.4 2.3 8.1 2.3 7.7 1.1 3.3 4.2 1.1 5.3 1.1 4.9 1.3 3.4 4.5 1.3 5.1 1.3 4.9 1.6 4.7 6.5 1.6 8.4 1.6 7.9 2.1 4.9 6.9 2.1 8 2.1 7.8 2 4.8 6.3 2 8.1 2 7.7 2.1 4.9 6.7 2.1 8 2.1 7.5 1.4 4 5.4 1.4 6.8 1.4 6.5 1.7 4.1 5.8 1.7 6.7 1.7 6.5 1.8 4.1 5.4 1.8 6.9 1.8 6.6 3.3 6.2 7.6 3.3 9.7 3.3 9.2 2.4 4.2 5.6 2.4 6.3 2.4 6.2 1.8 4.2 6.2 1.8 8.9 1.8 7.8 UNIT ns ns ns ns ns ns ns ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54ABT657A, SN74ABT657A OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS SCBS192E – JANUARY 1991 – REVISED JUNE 1997 PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT 3V Timing Input 1.5 V 0V tw tsu 3V Input 1.5 V 1.5 V th 3V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V VOH 1.5 V Output 1.5 V VOL VOH Output 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V tPLZ Output Waveform 1 S1 at 7 V (see Note B) tPLH tPHL 1.5 V tPZL tPHL tPLH 3V Output Control Output Waveform 2 S1 at Open (see Note B) 1.5 V tPZH 3.5 V VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated