SN54ABT16833, SN74ABT16833 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS097D – FEBRUARY 1991 – REVISED JANUARY 1997 D D D D D D D D D D SN54ABT16833 . . . WD PACKAGE SN74ABT16833 . . . DGG OR DL PACKAGE (TOP VIEW) Members of the Texas Instruments Widebus Family State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout High-Drive Outputs (–32-mA IOH, 64-mA IOL) Parity-Error Flag With Parity Generator/Checker Register for Storage of Parity-Error Flag Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings 1OEB 1CLK 1ERR GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2ERR 2CLK 2OEB description The ’ABT16833 consist of two noninverting 8-bit to 9-bit parity bus transceivers and are designed for communication between data buses. For each transceiver, when data is transmitted from the A bus to the B bus, an odd-parity bit is generated and output on the parity I/O pin (1PARITY or 2PARITY). When data is transmitted from the B bus to the A bus, 1PARITY (or 2PARITY) is configured as an input and combined with the B-input data to generate an active-low error flag if odd parity is not detected. 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 1OEA 1CLR 1PARITY GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2PARITY 2CLR 2OEA The error (1ERR or 2ERR) output is configured as an open-collector output. The B-to-A parity-error flag is clocked into 1ERR (or 2ERR) on the low-to-high transition of the clock (1CLK or 2CLK) input. 1ERR (or 2ERR) is cleared (set high) by taking the clear (1CLR or 2CLR) input low. The output-enable (OEA and OEB) inputs can be used to disable the device so that the buses are effectively isolated. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated. Copyright 1997, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABT16833, SN74ABT16833 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS097D – FEBRUARY 1991 – REVISED JANUARY 1997 description (continued) The SN54ABT16833 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT16833 is characterized for operation from –40°C to 85°C. FUNCTION TABLE INPUTS OUTPUT AND I/O Ai Σ OF H OEB OEA CLR CLK L H X X H L H ↑ NA X X H L H L Odd Even L X X H No↑ X L No↑ X H ↑ Odd H ↑ Even X X Odd Even Bi† Σ OF H A B NA NA A B NA NA X NA NA Odd Even X PARITY L H NA H FUNCTION A data to B bus and generate parity L B data to A bus and check parity H Check error-flag register NC X Z Z Z H H Isolation§ L NA NA A H L NA = not applicable, NC = no change, X = don’t care † Summation of high-level inputs includes PARITY along with Bi inputs. ‡ Output states shown assume ERR was previously high. § In this mode, ERR (when clocked) shows inverted parity of the A bus. 2 ERR‡ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 NA A data to B bus and generate inverted parity SN54ABT16833, SN74ABT16833 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS097D – FEBRUARY 1991 – REVISED JANUARY 1997 logic symbol† 1CLK 1CLR 1OEA 1OEB 2CLK 2CLR 2OEA 2OEB 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 Φ PARITY XCVR SN74ABT16833 2 55 56 1 1CLK 29 28 5 1OEB 1PARITY 54 1PARITY 2CLK 26 2ERR 2CLR 2ERR 2OEA 2OEB 2PARITY 1 1 31 52 6 51 8 49 9 48 10 A Bus 47 B Bus 12 45 13 44 14 43 15 1ERR 1OEA 27 30 3 1ERR 1CLR 8 8 1 1 42 16 41 17 40 19 38 20 A Bus 37 B Bus 21 36 23 34 24 33 8 8 2PARITY 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABT16833, SN74ABT16833 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS097D – FEBRUARY 1991 – REVISED JANUARY 1997 logic diagram (positive logic) 8 1A1–1A8 8x 8 1B1–1B8 EN 8x 8 EN 1OEB 1OEA 1 54 56 8 1PARITY 8 1 MUX 1 2k 9 1 P 1 G1 1CLK 1CLR 1D C1 R 2 55 8 2A1–2A8 8x 3 8 1ERR 2B1–2B8 EN 8x 8 EN 2OEB 2OEA 28 31 29 8 2PARITY 8 1 MUX 1 1 9 2k P 1 G1 2CLK 2CLR 4 1D C1 R 27 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 26 2ERR SN54ABT16833, SN74ABT16833 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS097D – FEBRUARY 1991 – REVISED JANUARY 1997 ERROR-FLAG FUNCTION TABLE INPUTS INTERNAL TO DEVICE OUTPUT PRE-STATE OUTPUT ERR CLR CLK POINT P ERRn–1† H ↑ H H H H ↑ X L L H ↑ L X L FUNCTION Sample L X X X H † State of ERR before changes at CLR, CLK, or point P Clear error-flag waveforms H OEB L H OEA L Even Bi + PARITY Odd tsu th H CLK L tw tw CLR tsu H L tPHL tPLH H ERR L POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ABT16833, SN74ABT16833 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS097D – FEBRUARY 1991 – REVISED JANUARY 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT16833 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT16833 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51. recommended operating conditions (see Note 3) SN54ABT16833 VCC VIH Supply voltage VIL VI Low-level input voltage VOH IOH High-level output voltage ERR High-level output current Except ERR IOL ∆t/∆v Low-level output current High-level input voltage MAX MIN MAX 4.5 5.5 4.5 5.5 2 2 0.8 Input voltage 0 Input transition rise or fall rate Outputs enabled TA Operating free-air temperature NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 SN74ABT16833 MIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 –55 UNIT V V 0.8 V VCC 5.5 V –24 –32 mA 48 64 mA 10 10 ns/V 85 °C VCC 5.5 125 0 –40 V SN54ABT16833, SN74ABT16833 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS097D – FEBRUARY 1991 – REVISED JANUARY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH All outputs except ERR TEST CONDITIONS 2.5 3.4 3 IOH = –3 mA IOH = –24 mA 3 IOH = –32 mA IOL = 24 mA 2* VCC = 4 4.5 5V Ioff ICEX VOH = 5.5 V VI or VO ≤ 4.5 V Outputs high VCC = 5.5 V, VO = 5.5 V SN54ABT16833 MIN –1.2 MAX SN74ABT16833 MIN –1.2 MAX –1.2 3 2.7 A or B ports 0.55 0.3 0.55* 0.55 0.55 A or B ports IOZH§ IOZL§ A or B ports 50 VI = GND VO = 2.5 V VCC =5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.5 V VCC = 5.5 V, IO = 0, VI = VCC or GND Outputs high 1.5 Outputs low –50 Outputs disabled –100 Ci Control inputs Cio A or B ports VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V 50 20 µA ±100 µA 50 µA ±1 ±1 ±1 ±100 ±100 ±100 –50 –50 –50 µA –180 –50 –180 –50 µA –180 mA 50 50 50 µA –50 –50 –50 µA 2 2 2 28 36 36 36 1 2 2 2 50 50 50 VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND ∆ICC¶ 20 ±100 VCC = 0, VCC = 5.5 V, V mV 20 VCC = 5 5.5 5 V, V VI = VCC or GND V 2 0.25 100 Control inputs UNIT V 2 IOL = 64 mA VCC = 4.5 V, VCC = 0, ICC 3 VCC = 5 V, ERR IIL IO‡ 2.5 II = –18 mA IOH = –3 mA Vhys IOH II TA = 25°C TYP† MAX VCC = 4.5 V, VCC = 4.5 V, VCC = 4 4.5 5V VOL MIN mA µA 3 pF 9 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. † All typical values are at VCC = 5 V. ‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. § The parameters IOZH and IOZL include the input leakage current. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54ABT16833, SN74ABT16833 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS097D – FEBRUARY 1991 – REVISED JANUARY 1997 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 5 V, TA = 25°C MIN tw Pulse duration, CLK high or low tsu Setup time before CLK↑ ↑ A port th Hold time after CLK↑ SN54ABT16833 MAX MIN MAX SN74ABT16833 MIN 3 3 3 4.5 4.5 4.5 CLR 1 1 1 OEA 5 5 5 A port or OEA 0 0 0 UNIT MAX ns ns ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPZH tPZL OE A or B tPHZ tPLZ OE A or B tPLH tPHL A or OE PARITY tPZH tPZL OE PARITY tPHZ tPLZ OE PARITY PARAMETER tPLH tPHL CLK, CLR CLK ERR VCC = 5 V, TA = 25°C SN54ABT16833 MIN TYP MAX MIN MAX MIN MAX 1.5 2.5 3.3 1.5 4.2 1.5 4.1 2 3.1 3.9 2 4.5 2 4.3 2 3.9 4.9 2 5.8 2 5.6 2.5 4.3 5.1 2.5 6.2 2.5 6 2 3.6 4.5 2 5.5 2 5.4 1.5 3 3.8 1.5 4.7 1.5 4.3 2 4.6 5.4 2 7 2 6.7 2 4.3 5.1 2 6.5 2 6.1 2 3.6 5 2 5.8 2 5.7 2.5 4.4 5.8 2.5 6.7 2.5 6.5 1.5 3.2 4 1.5 4.8 1.5 4.7 1.5 2.9 3.7 1.5 4.2 1.5 4.1 2 3.4 4.2 2 4.8 2 4.6 2 2.8 3.6 2 4.1 2 3.9 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 8 POST OFFICE BOX 655303 SN74ABT16833 • DALLAS, TEXAS 75265 UNIT ns ns ns ns ns ns ns SN54ABT16833, SN74ABT16833 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS097D – FEBRUARY 1991 – REVISED JANUARY 1997 PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF 500 Ω (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open ERR S1 tPHL (see Note E) tPLH (see Note F) 7V 7V LOAD CIRCUIT 3V Timing Input 1.5 V 0V tw tsu 3V th 3V Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Input 1.5 V 1.5 V 0V VOH 1.5 V Output 1.5 V VOL VOH Output 1.5 V 1.5 V VOL 1.5 V 0V tPLZ Output Waveform 1 S1 at 7 V (see Note B) tPLH tPHL 1.5 V tPZL tPHL tPLH 3V Output Control Output Waveform 2 S1 at Open (see Note B) 1.5 V tPZH 3.5 V VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPHL is measured at 1.5 V. F. tPLH is measured at VOL + 0.3 V. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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