TI SN74ACT534DB

SN54ACT534, SN74ACT534
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS556B – NOVEMBER 1995 – REVISED JANUARY 2000
D
D
D
D
D
Inputs Are TTL-Voltage Compatible
3-State Inverting Outputs Drive Bus Lines
Directly
Full Parallel Access for Loading
EPIC  (Enhanced-Performance Implanted
CMOS) 1-µm Process
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK) and
Flatpacks (W), and Standard Plastic (N) and
Ceramic (J) DIPs
SN54ACT534 . . . J OR W PACKAGE
SN74ACT534 . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
description
On the positive transition of the clock (CLK) input,
the Q outputs are set to the complements of the
logic levels set up at the data (D) inputs.
2D
2Q
3Q
3D
4D
8Q
1D
1Q
OE
VCC
SN54ACT534 . . . FK PACKAGE
(TOP VIEW)
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
8D
7D
7Q
6Q
6D
4Q
GND
CLK
5Q
5D
These octal edge-triggered D-type flip-flops
feature 3-state outputs designed specifically for
driving
highly
capacitive
or
relatively
low-impedance loads. The devices are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without need for interface or pullup
components.
OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN54ACT534 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ACT534 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ACT534, SN74ACT534
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS556B – NOVEMBER 1995 – REVISED JANUARY 2000
FUNCTION TABLE
(each flip-flop)
INPUTS
CLK
D
L
↑
H
L
L
↑
L
H
L
H or L
X
Q0
H
X
X
Z
logic symbol†
OE
CLK
1D
2D
3D
4D
5D
6D
7D
8D
1
11
3
4
OUTPUT
Q
OE
logic diagram (positive logic)
1
OE
EN
CLK
C1
1D
1
2
5
7
6
8
9
13
12
14
15
17
16
18
19
C1
1Q
2Q
11
3
1D
2
1Q
1D
3Q
4Q
To Seven Other Channels
5Q
6Q
7Q
8Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ACT534, SN74ACT534
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS556B – NOVEMBER 1995 – REVISED JANUARY 2000
recommended operating conditions (see Note 3)
SN54ACT534
MAX
MIN
MAX
4.5
5.5
4.5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
High-level output current
IOL
∆t/∆v
Low-level output current
High-level input voltage
SN74ACT534
MIN
2
2
0.8
Input transition rise or fall rate
0
UNIT
V
V
0.8
V
VCC
VCC
V
–24
–24
mA
24
24
mA
8
ns/V
VCC
VCC
8
0
0
0
V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –50
50 µA
VOH
IOH = –24
24 mA
IOH = –50 mA†
IOH = –75 mA†
MIN
TA = 25°C
TYP
MAX
SN54ACT534
MIN
MAX
MIN
4.4
4.49
4.4
5.5 V
5.4
5.49
5.4
5.4
4.5 V
3.8
3.7
3.76
5.5 V
4.86
4.7
4.76
MAX
UNIT
4.4
V
3.85
5.5 V
IOL = 24 mA
SN74ACT534
4.5 V
5.5 V
IOL = 50 µA
VOL
VCC
3.85
4.5 V
0.1
0.1
5.5 V
0.1
0.1
0.1
0.1
4.5 V
0.36
0.5
0.44
5.5 V
0.36
0.5
0.44
V
IOL = 50 mA†
IOL = 75 mA†
5.5 V
IOZ
II
VO = VCC or GND
VI = VCC or GND
5.5 V
±0.25
±5
±2.5
µA
5.5 V
±0.1
±1
±1
µA
ICC
VI = VCC or GND,
IO = 0
One input at 3.4 V,
Other inputs at GND or VCC
5.5 V
4
80
40
µA
1.6
1.5
mA
∆ICC‡
1.65
5.5 V
5.5 V
1.65
0.6
Ci
VI = VCC or GND
5V
4.5
† Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
pF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
SN54ACT534
MIN
MAX
SN74ACT534
MIN
MAX
UNIT
tw
tsu
Pulse duration, CLK high or low
3.5
5
3.5
ns
Setup time, data before CLK↑
3.5
5
4
ns
th
Hold time, data after CLK↑
1
3
1.5
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54ACT534, SN74ACT534
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS556B – NOVEMBER 1995 – REVISED JANUARY 2000
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
MIN
MAX
100
CLK
Q
OE
Q
OE
Q
SN54ACT534
MIN
MAX
85
SN74ACT534
MIN
MAX
120
UNIT
MHz
2.5
11.5
1.5
14
2
12.5
2
10.5
1.5
13
2
12
2.5
12
1.5
14
2
12.5
2
11
1.5
13
2
11.5
1.5
12.5
1.5
14.5
1
13.5
1.5
10.5
1.5
11.5
1
10.5
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
f = 1 MHz
TYP
40
UNIT
pF
SN54ACT534, SN74ACT534
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS556B – NOVEMBER 1995 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
CL = 50 pF
(see Note A)
Open
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
Open
3V
1.5 V
Timing Input
LOAD CIRCUIT
0V
th
tsu
3V
1.5 V
Data Input
tw
0V
3V
1.5 V
Input
1.5 V
VOLTAGE WAVEFORMS
1.5 V
0V
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
3V
1.5 V
1.5 V
0V
tPZL
3V
Input
1.5 V
1.5 V
0V
tPLH
Output
tPHL
50% VCC
VOH
50% VCC
VOL
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLZ
≈VCC
50% VCC
tPZH
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
VOL + 0.3 V
VOL
tPHZ
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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• DALLAS, TEXAS 75265
5
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Copyright  2000, Texas Instruments Incorporated