SN54ALS1244A, SN74ALS1244A OCTAL BUFFERS AND DRIVERS WITH 3-STATE OUTPUTS SDAS186B – JULY 1990 – REVISED JANUARY 1995 • • Low-Power Versions of ′ALS244 Series 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers pnp Inputs Reduce dc Loading Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs SN54ALS1244A . . . J PACKAGE SN74ALS1244A . . . DW OR N PACKAGE (TOP VIEW) 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND description These octal buffers and drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 SN54ALS1244A . . . FK PACKAGE (TOP VIEW) 2Y4 1A1 1OE VCC Taken together with the SN74ALS1240, these devices provide the choice of inverting and noninverting outputs. 1A2 2Y3 1A3 2Y2 1A4 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 1Y1 2A4 1Y2 2A3 1Y3 2Y1 GND 2A1 1Y4 2A2 The SN54ALS1244A is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74ALS1244A is characterized for operation from 0°C to 70°C. 1 2OE • • Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ALS1244A, SN74ALS1244A OCTAL BUFFERS AND DRIVERS WITH 3-STATE OUTPUTS SDAS186B – JULY 1990 – REVISED JANUARY 1995 logic symbol† 1OE 1A1 1A2 1A3 1A4 1 logic diagram (positive logic) 1OE 2 18 4 16 6 14 8 12 1Y1 1A1 2OE 1Y3 1A2 2A2 2A3 2A4 18 4 16 6 14 8 12 1Y1 1Y2 1Y4 1Y3 EN 1A4 2A1 2 1Y2 1A3 19 1 EN 11 9 13 7 15 5 17 3 1Y4 2Y1 2Y2 2Y3 2OE 19 2Y4 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2A1 2A2 2A3 2A4 11 9 13 7 15 5 17 3 2Y1 2Y2 2Y3 2Y4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA: SN54ALS1244A . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74ALS1244A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALS1244A, SN74ALS1244A OCTAL BUFFERS AND DRIVERS WITH 3-STATE OUTPUTS SDAS186B – JULY 1990 – REVISED JANUARY 1995 recommended operating conditions SN54ALS1244A SN74ALS1244A MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.7 0.8 V High-level output current – 12 – 15 mA IOL TA Low-level output current 8 16 mA 70 °C High-level input voltage 2 Operating free-air temperature 2 – 55 125 V V 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 0.4 mA VCC = 4.5 V IOH = – 3 mA IOH = – 12 mA VOL VCC = 4 4.5 5V IOZH IOZL VCC = 5.5 V, VCC = 5.5 V, II IIH VCC = 5.5 V, VCC = 5.5 V, IIL IO‡ VCC = 5.5 V, VCC = 5.5 V, ICC VCC = 5.5 V SN54ALS1244A TYP† MAX MIN – 1.5 VCC – 2 2.4 – 1.5 VCC – 2 2.4 3.2 3.2 UNIT V V 2 IOH = – 15 mA IOL = 8 mA 2 0.25 IOL = 16 mA VO = 2.7 V VO = 0.4 V VI = 7 V VI = 2.7 V VI = 0.4 V VO = 2.25 V Outputs high SN74ALS1244A TYP† MAX MIN – 20 0.4 0.25 0.4 0.35 0.5 V 20 20 µA – 20 – 20 µA 0.1 0.1 mA 20 20 µA – 0.1 – 0.1 mA – 112 mA – 112 – 30 6 15 6 11 Outputs low 10 20 10 17 Outputs disabled 11 25 11 20 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ALS1244A, SN74ALS1244A OCTAL BUFFERS AND DRIVERS WITH 3-STATE OUTPUTS SDAS186B – JULY 1990 – REVISED JANUARY 1995 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = MIN to MAX† SN54ALS1244A tPLH tPHL A Y tPZH tPZL OE Y tPHZ tPLZ OE Y SN74ALS1244A MIN MAX MIN MAX 3 21 3 14 3 16 3 14 6 28 6 22 6 26 6 22 2 15 2 13 3 25 3 16 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns ns SN54ALS1244A, SN74ALS1244A OCTAL BUFFERS AND DRIVERS WITH 3-STATE OUTPUTS SDAS186B – JULY 1990 – REVISED JANUARY 1995 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 1.3 V 1.3 V 0.3 V 0.3 V tsu Data Input tw th 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Output Control (low-level enabling) 1.3 V 1.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ [3.5 V 1.3 V tPHZ tPZH Waveform 2 S1 Open (see Note B) 1.3 V VOL 0.3 V VOH 1.3 V 0.3 V [0 V 3.5 V 1.3 V Input 1.3 V 0.3 V tPHL tPLH VOH In-Phase Output 1.3 V 1.3 V VOL tPLH tPHL VOH Out-of-Phase Output (see Note C) 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 5962-88738012A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC 5962-8873801RA ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC Level-NC-NC-NC SN54ALS1244AJ ACTIVE CDIP J 20 1 TBD Call TI SN74ALS1244ADW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS1244ADWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS1244ADWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS1244ADWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS1244AN ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74ALS1244ANE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SNJ54ALS1244AFK ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC SNJ54ALS1244AJ ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. 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