TI SN74AS30N

SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30
8-INPUT POSITIVE-NAND GATES
SDAS010C – MARCH 1984 – REVISED NOVEMBER 2000
SN54ALS30A, SN54AS30 . . . J PACKAGE
SN74ALS30A, SN74AS30 . . . D OR N PACKAGE
SN74AS30 . . . DB PACKAGE
(TOP VIEW)
description
These devices contain an 8-input positive-NAND
gate and perform the following Boolean functions
in positive logic:
A
B
C
D
E
F
GND
Y = A • B • C • D • E • F • G • H or
Y=A+B+C+D+E+F+G+H
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
NC
H
G
NC
NC
Y
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
H
NC
G
NC
NC
Y
NC
4
F
GND
NC
C
NC
D
NC
E
NC
B
A
NC
VCC
SN54ALS30A, SN54AS30 . . . FK PACKAGE
(TOP VIEW)
NC – No internal connection
ORDERING INFORMATION
PDIP – N
0°C to 70°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SOIC – D
SSOP – DB
CDIP – J
Tube
SN74ALS30AN
SN74ALS30AN
SN74AS30N
SN74AS30N
Tube
SN74ALS30AD
Tape and reel
SN74ALS30AD
Tube
SN74AS30D
Tape and reel
SN74AS30D
Tape and reel
SN74AS30DBR
AS30
SNJ54ALS30AJ
SNJ54ALS30AJ
SNJ54AS30J
SNJ54AS30J
SNJ54ALS30AFK
SNJ54ALS30AFK
Tube
–55°C
55°C to 125°C
LCCC – FK
TOP-SIDE
MARKING
Tube
ALS30A
AS30
SNJ54AS30FK
SNJ54AS30FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30
8-INPUT POSITIVE-NAND GATES
SDAS010C – MARCH 1984 – REVISED NOVEMBER 2000
FUNCTION TABLE
OUTPUT
Y
INPUTS
A–H
All inputs H
L
One or more inputs L
H
logic symbol†
A
B
C
D
E
F
G
H
1
2
3
4
8
5
Y
6
11
12
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, and N packages.
logic diagram (positive logic)
A
B
C
D
E
F
G
H
1
2
3
4
5
8
Y
6
11
12
Pin numbers shown are for the D, DB, J, and N packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Package thermal impedance, θJA (see Note 1): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30
8-INPUT POSITIVE-NAND GATES
SDAS010C – MARCH 1984 – REVISED NOVEMBER 2000
recommended operating conditions
VCC
VIH
Supply voltage
High-level input voltage
VIL
Low level input voltage
Low-level
IOH
High level output current
High-level
IOL
Low-level output current
MIN
NOM
MAX
4.5
5
5.5
2
’ALS30A
–0.4
’AS30
–2
8
’AS30
mA
mA
20
SN54ALS30A
–55
125
SN54AS30
–55
125
0
70
SN74ALS30A
V
4
SN74ALS30A
Operating free
free-air
air temperature
V
V
0.8†
0.7‡
SN54ALS30A
TA
UNIT
°C
SN74AS30
0
70
† Applies to the ’AS30 and SN74ALS30A across the full operating temperature range, and SN54ALS30A over the temperature range of
–55°C to 70°C.
‡ Applies to the SN54ALS30A over the temperature range of 70°C to 125°C.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP§
MAX
’ALS30A
–1.5
’AS30
–1.2
VIK
VCC = 4
4.5
5V
V,
II = –18
18 mA
VOH
VCC = 4.5
4 5 V to 5.5
55V
IOH = –0.4 mA
IOH = –2 mA
’ALS30A
0.25
0.4
VCC = 4.5 V
IOL = 4 mA
IOL = 8 mA
’ALS30A
VOL
SN74ALS30A
0.35
0.5
0.35
0.5
VCC = 5.5 V,
VCC = 5.5 V,
IOL = 20 mA
VI = 7 V
’AS30
II
IIH
IIL
5V
VCC = 5
5.5
V,
4V
VI = 0
0.4
IO¶
VCC = 5.5 V,
VO = 2.25 V
’AS30
VCC–2
VCC–2
5V
VCC = 5
5.5
V,
VI = 0
ICCL
VCC = 5
5.5
5V
V,
VI = 4
4.5
5V
mA
20
µA
–0.1
’AS30
–0.5
SN54ALS30A
–20
–112
SN74ALS30A
–30
–112
’AS30
–30
–112
’AS30
’ALS30A
’AS30
V
0.1
’ALS30A
’ALS30A
V
V
VI = 2.7 V
ICCH
UNIT
0.22
0.36
0.9
1.5
0.54
0.9
3
4.9
mA
mA
mA
mA
§ All typical values are at VCC = 5 V, TA = 25°C.
¶ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30
8-INPUT POSITIVE-NAND GATES
SDAS010C – MARCH 1984 – REVISED NOVEMBER 2000
switching characteristics over recommended operating free-air temperature range (see Figure 1)
PARAMETER
tPLH
tPHL
4
FROM
(INPUT)
A B,
A,
B C,
C D,
D E,
E F,
F G,
G or H
A B,
A,
B C,
C D,
D E,
E F,
F G,
G or H
POST OFFICE BOX 655303
TO
(OUTPUT)
Y
Y
• DALLAS, TEXAS 75265
MIN
MAX
SN54ALS30A
3
15
SN74ALS30A
3
10
SN54AS30
1
5.5
SN74AS30
1
5
SN54ALS30A
3
15
SN74ALS30A
3
12
SN54AS30
1
5
SN74AS30
1
4.5
UNIT
ns
ns
SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30
8-INPUT POSITIVE-NAND GATES
SDAS010C – MARCH 1984 – REVISED NOVEMBER 2000
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7V
VCC
From Output
Under Test
CL = 50 pF
(see Note A)
From Output
Under Test
Test
Point
500 Ω
500 Ω
Test
Point
500 Ω
3V
500 Ω
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
3V
High-Level
Pulse
1.5 V
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR
BI-STATE TOTEM-POLE OUTPUTS
Timing
Input
S1
1.5 V
1.5 V
0V
0V
tw
th
tsu
3V
Data
Input
1.5 V
3V
Low-Level
Pulse
1.5 V
0V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
VOLTAGE WAVEFORMS
PULSE DURATIONS
3V
1.5 V
1.5 V
0V
tPZL
tPLZ
1.5 V
tPHZ
VOL
0.3 V
tPZH
VOH
1.5 V
3V
Input
≈3 V
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
1.5 V
0.3 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
1.5 V
1.5 V
0V
tPLH
In-Phase
Output
tPHL
VOH
1.5 V
VOL
tPHL
Out-of-Phase
Output
(see Note C)
1.5 V
tPLH
VOH
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
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Copyright © 2007, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
5962-86837012A
ACTIVE
LCCC
FK
20
1
TBD
5962-8683701DA
ACTIVE
CFP
W
14
1
TBD
Lead/Ball Finish
MSL Peak Temp (3)
POST-PLATE N / A for Pkg Type
A42
N / A for Pkg Type
5962-9755801Q2A
ACTIVE
LCCC
FK
20
1
TBD
5962-9755801QCA
ACTIVE
CDIP
J
14
1
TBD
POST-PLATE N / A for Pkg Type
JM38510/37004B2A
ACTIVE
LCCC
FK
20
1
TBD
JM38510/37004BCA
ACTIVE
CDIP
J
14
1
TBD
A42 SNPB
N / A for Pkg Type
SN54ALS30AJ
ACTIVE
CDIP
J
14
1
TBD
A42 SNPB
N / A for Pkg Type
SN54AS30J
ACTIVE
CDIP
J
14
1
TBD
A42 SNPB
N / A for Pkg Type
SN74ALS30AD
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS30ADE4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS30ADG4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS30ADR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS30ADRE4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS30ADRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS30AN
ACTIVE
PDIP
N
14
CU NIPDAU
N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
POST-PLATE N / A for Pkg Type
25
Pb-Free
(RoHS)
TBD
Call TI
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74ALS30AN3
OBSOLETE
PDIP
N
14
SN74ALS30ANE4
ACTIVE
PDIP
N
14
SN74ALS30ANSR
ACTIVE
SO
NS
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS30ANSRE4
ACTIVE
SO
NS
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS30ANSRG4
ACTIVE
SO
NS
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS30D
NRND
SOIC
D
14
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS30DBR
NRND
SSOP
DB
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS30DBRE4
NRND
SSOP
DB
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS30DBRG4
NRND
SSOP
DB
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS30DE4
NRND
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS30DG4
NRND
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS30DR
NRND
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS30DRE4
NRND
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS30DRG4
NRND
SOIC
D
14
2500 Green (RoHS &
CU NIPDAU
Level-1-260C-UNLIM
50
Addendum-Page 1
Call TI
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74AS30N
NRND
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74AS30NE4
NRND
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74AS30NSR
NRND
SO
NS
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS30NSRE4
NRND
SO
NS
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS30NSRG4
NRND
SO
NS
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SNJ54ALS30AFK
ACTIVE
LCCC
FK
20
1
TBD
SNJ54ALS30AJ
ACTIVE
CDIP
J
14
1
TBD
SNJ54ALS30AW
ACTIVE
CFP
W
14
1
TBD
SNJ54AS30FK
ACTIVE
LCCC
FK
20
1
TBD
SNJ54AS30J
ACTIVE
CDIP
J
14
1
TBD
Lead/Ball Finish
MSL Peak Temp (3)
no Sb/Br)
POST-PLATE N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
A42
N / A for Pkg Type
POST-PLATE N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
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to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
16-Jul-2007
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74ALS30ADR
D
14
MLA
330
16
6.5
9.0
2.1
8
16
Q1
SN74ALS30ANSR
NS
14
MLA
330
16
8.2
10.5
2.5
12
16
Q1
SN74AS30DBR
DB
14
MLA
330
16
8.2
6.6
2.5
12
16
Q1
SN74AS30DR
D
14
MLA
330
16
6.5
9.0
2.1
8
16
Q1
SN74AS30NSR
NS
14
MLA
330
16
8.2
10.5
2.5
12
16
Q1
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
SN74ALS30ADR
D
14
MLA
346.0
346.0
33.0
SN74ALS30ANSR
NS
14
MLA
346.0
346.0
33.0
SN74AS30DBR
DB
14
MLA
346.0
346.0
33.0
SN74AS30DR
D
14
MLA
346.0
346.0
33.0
SN74AS30NSR
NS
14
MLA
346.0
346.0
33.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2007
Pack Materials-Page 3
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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