SN74ALS679 12-BIT ADDRESS COMPARATOR SDAS003C – JUNE 1982 – REVISED JANUARY 1995 • • DW OR N PACKAGE (TOP VIEW) 12-Bit Address Comparator With Enable Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (N) 300-mil DIPs A1 A2 A3 A4 A5 A6 A7 A8 A9 GND description 1 20 2 19 3 18 4 17 VCC G Y P3 P2 P1 P0 A12 A11 A10 This 12-bit address comparator simplifies 5 16 addressing of memory boards and/or other 6 15 peripheral devices. The four P inputs are normally 7 14 hardwired with a preprogrammed address. An 8 13 internal decoder determines what input 9 12 information applied to the A inputs must be low or 10 11 high to cause a low state at the Y output. For example, a positive-logic bit combination of 0111 (decimal 7) at the P input determines that inputs A1 through A7 must be low and that inputs A8 through A12 must be high to cause the output to go low. Equality of the address applied at the A inputs to the preprogrammed address is indicated by the output being low. This device features an enable (G) input. When G is low, the device is enabled. When G is high, the device is disabled and the output is high, regardless of the A and P inputs. The SN74ALS679 is characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS G P3 P2 P1 L L L L L L L L L L L L L L H L L H L L H L L L H L H L H L A10 A11 A12 OUTPUT Y H H H H L H H H H L H H H H H L H H H H H L H H H H H H L H H H H H H L H H H H H H L L L H H H H H L L L L H H H H L L L L L L H H H L L L L L L L H H L L L L L L L L L H L L L L L L H H H L L L† L L L L L L L H H L L L L L L L L L L H L L L L L L L L L L L L P0 A1 A2 A3 A4 A5 A6 A7 A8 A9 L L H H L H L H H H H H H H H H H H H H H L L H H L L H H H H H L L H H H H L L L L H L L L L H H L L L L H H L L L L L L L H H L L H L L L L L L L L L L L L L L H L L L L H L L L L L H L H H L L L L H H L H H L L L L L H L L L H H L H H H L L H H L L All other combinations L† L† L H H Any combination H † The three shaded rows of the function table show combinations that would normally not be used in address comparator applications. The logic symbols above are not valid for these combinations in which P = 12, 13, and 14. If symbols valid for all combinations are required, starting with the fourth exclusive-OR from the bottom, change P ≥ 9 to P = 9 . . . 11/13 . . . 15, P ≥ 10 to P = 10/11/14/15, and P ≥ 11 to P = 11/15. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALS679 12-BIT ADDRESS COMPARATOR SDAS003C – JUNE 1982 – REVISED JANUARY 1995 logic symbol† 19 G P0 P1 P2 P3 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 14 [ADDRESS COMP] [P assumed ≠ 12, 13, 14] EN 0 15 16 17 1 2 3 4 5 6 7 8 9 11 12 13 P 3 Z1 Z2 Z3 Z4 Z5 Z6 Z7 Z8 Z9 Z10 Z11 Z12 P≥1 1 P≥2 2 P≥3 3 P≥4 4 =1 P≥5 5 P≥6 6 P≥7 7 P≥8 8 P≥9 9 =1 P ≥ 10 10 P ≥ 11 11 P ≥ 12 12 =1 & =1 =1 =1 =1 =1 =1 =1 =1 =1 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 18 Y SN74ALS679 12-BIT ADDRESS COMPARATOR SDAS003C – JUNE 1982 – REVISED JANUARY 1995 logic diagram (positive logic) A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 1 2 3 4 5 6 7 8 18 Y 9 11 A11 12 A12 P0 P1 P2 P3 13 14 15 16 17 G 19 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ALS679 12-BIT ADDRESS COMPARATOR SDAS003C – JUNE 1982 – REVISED JANUARY 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions MIN NOM MAX 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage High-level output current – 2.6 mA IOL TA Low-level output current 24 mA 70 °C High-level input voltage 2 V 0.8 Operating free-air temperature V 0 V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS MIN VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 0.4 mA VCC = 4.5 V, IOH = – 2.6 mA IOL = 12 mA VOL VCC = 4 4.5 5V II VCC = 5.5 V, IOL = 24 mA VI = 7 V IIH VCC = 5.5 V, VI = 2.7 V IIL IO§ VCC = 5.5 V, VI = 0.4 V VCC = 5.5 V, VO = 2.25 V TYP‡ VCC – 2 2.4 MAX UNIT – 1.5 V V 3.2 – 30 0.25 0.4 0.35 0.5 V 0.1 mA 20 µA – 0.1 mA –112 mA ICC VCC = 5.5 V 17 28 mA ‡ All typical values are at VCC = 5 V, TA = 25°C. § The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. switching characteristics (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL Any P Y tPLH tPHL Any A Y tPLH tPHL G Y VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX¶ MIN MAX 4 25 8 35 5 22 5 30 3 13 5 25 ¶ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns ns SN74ALS679 12-BIT ADDRESS COMPARATOR SDAS003C – JUNE 1982 – REVISED JANUARY 1995 APPLICATION INFORMATION The SN74ALS679 can be wired to recognize any one of 212 addresses. The number of lows in the address determines the input pattern for the P inputs. The system address lines that are low in the address to be recognized are connected to the lowest-numbered A inputs of the address comparator. The system address lines that are high are connected to the highest-numbered A inputs. For example, assume the comparator is to enable a device when the 12-bit system address is: A11 A10 A9 H H L A8 A7 A6 A5 A4 A3 A2 A1 A0 L H H L L H H H H Because the address contains four lows and eight highs, the following connections are made: • • • P3 to 0 V, P2 to VCC, P1 to 0 V, and P0 to 0 V System address lines A9, A8, A5, and A4 to comparator inputs A1 through A4 in any convenient order The remaining eight system address lines to comparator inputs A5 through A12 in any convenient order The output provides an active-low enabling signal. Figure 1 is a register-bank decoder that examines the 14 most significant bits (A0 through A13) of a 20-bit address to select banks corresponding to the hex addresses 10000, 10040, 10080, and 100C0. SN74ALS679 [ADDRESS COMP] G MEMEN VCC EN P0 1000016 1004016 1008016 100C016 = = = = 0 LLLH LLLH LLLH LLLH 4 LLLL LLLL LLLL LLLL 8 LLLL LLLL LLLL LLLL 12 LLLL LHLL HLLL HHLL 16 LLLL LLLL LLLL LLLL 0 P1 System Address Lines A0 (MSB) – A19 P2 P3 3 1/2 ′ALS139 P X/Y A0 – A2 A4 – A11 11 A1 – A11 [P=11] A12 A3 A A12 B A13 A14 – A19 G 0 1000016 1 1004016 2 1008016 3 100C016 1 2 6 64 X n-Bit Registers S0 – S5 Figure 1. Register-Bank Decoder POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ALS679 12-BIT ADDRESS COMPARATOR SDAS003C – JUNE 1982 – REVISED JANUARY 1995 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 1.3 V 1.3 V 0.3 V 0.3 V Data Input tw th tsu 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Output Control (low-level enabling) 1.3 V 1.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ [3.5 V 1.3 V tPHZ tPZH Waveform 2 S1 Open (see Note B) 1.3 V VOL 0.3 V VOH 1.3 V 0.3 V [0 V 3.5 V 1.3 V Input 1.3 V 0.3 V tPHL tPLH VOH In-Phase Output 1.3 V 1.3 V VOL tPLH tPHL VOH Out-of-Phase Output (see Note C) 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 2. Load Circuits and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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