SN74CB3Q3125 QUADRUPLE FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH www.ti.com SCDS143B – OCTOBER 2003 – REVISED MARCH 2005 FEATURES • • • • • • • • • High-Bandwidth Data Path (up to 500 MHz (1)) 5-V Tolerant I/Os With Device Powered Up or Powered Down Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 3 Ω Typ) Rail-to-Rail Switching on Data I/O Ports – 0- to 5-V Switching With 3.3-V VCC – 0- to 3.3-V Switching With 2.5-V VCC Bidirectional Data Flow With Near-Zero Propagation Delay Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 4 pF Typ) Fast Switching Frequency (fOE = 20 MHz Max) Data and Control Inputs Provide Undershoot Clamp Diodes Low Power Consumption (ICC = 0.3 mA Typ) VCC Operating Range From 2.3 V to 3.6 V Data I/Os Support 0- to 5-V Signaling Levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V) Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 – 2000-V Human-Body Model (A114-B, Class II) – 1000-V Charged-Device Model (C101) Supports Both Digital and Analog Applications: USB Interface, Differential Signal Interface, Bus Isolation, Low-Distortion Signal Gating • • • • • • • For additional information regarding the performance characteristics of the CB3Q family, refer to the TI application report, CBT-C, CB3T, and CB3Q Signal-Switch Families, literature number SCDA008. DGV OR PW PACKAGE (TOP VIEW) 13 3 12 4 11 5 10 6 7 9 8 VCC 4OE 4A 4B 3OE 3A 3B 1 16 2 15 3 14 4 13 5 12 6 7 10 8 9 VCC 4OE 4A 4B 3OE 3A 3B NC 7 8 NC 1OE 1A 1B 2OE 2A 2B GND NC - No internal connection 1 1A 1B 2OE 2A 2B VCC 14 2 3B 1 1OE 1OE 1A 1B 2OE 2A 2B GND DBQ PACKAGE (TOP VIEW) RGY PACKAGE (TOP VIEW) GND (1) 14 2 13 4OE 3 4 12 4A 5 6 10 3OE 11 4B 9 3A 11 DESCRIPTION/ORDERING INFORMATION The SN74CB3Q3125 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q3125 provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2005, Texas Instruments Incorporated SN74CB3Q3125 QUADRUPLE FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH www.ti.com SCDS143B – OCTOBER 2003 – REVISED MARCH 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) The SN74CB3Q3125 is organized as four 1-bit bus switches with separate output-enable (1OE, 2OE, 3OE, 4OE) inputs. It can be used as four 1-bit bus switches or as one 4-bit bus switch. When OE is low, the associated 1-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 1-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C TOP-SIDE MARKING QFN – RGY Tape and reel SN74CB3Q3125RGYR BU125 SSOP (QSOP) – DBQ Tape and reel SN74CB3Q3125DBQR BU125 Tube SN74CB3Q3125PW Tape and reel SN74CB3Q3125PWR Tape and reel SN74CB3Q3125DGVR TSSOP – PW TVSOP – DGV (1) ORDERABLE PART NUMBER BU125 BU125 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (EACH BUS SWITCH) INPUT OE INPUT/OUTPUT A FUNCTION L B A port = B port H Z Disconnect LOGIC DIAGRAM (POSITIVE LOGIC) 2 1A 1OE 3 5 1B SW 2A 1 4 9 12 8 SW 3B 4A 4OE Pin numbers shown are for the DGV, PW, and RGY packages. 11 SW 13 10 2 2B 2OE 3A 3OE 6 SW 4B SN74CB3Q3125 QUADRUPLE FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH www.ti.com SCDS143B – OCTOBER 2003 – REVISED MARCH 2005 SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW) A B VCC Charge Pump EN(1) (1) EN is the internal enable signal applied to the switch. Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX –0.5 4.6 V VIN Control input voltage range (2) (3) –0.5 7 V VI/O Switch I/O voltage range (2) (3) (4) –0.5 7 II/K Control input clamp current VIN < 0 –50 mA II/OK I/O port clamp current VI/O < 0 –50 mA IIO ON-state switch current (5) ±64 mA ±100 mA VCC Supply voltage range Continuous current through VCC or GND package (6) 90 DGV package (6) 127 PW package (6) 113 RGY package (7) 47 DBQ θJA Tstg (1) (2) (3) (4) (5) (6) (7) Package thermal impedance Storage temperature range –65 150 UNIT V °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground, unless otherwise specified. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. VI and VO are used to denote specific conditions for VI/O. II and IO are used to denote specific conditions for II/O. The package thermal impedance is calculated in accordance with JESD 51-7. The package thermal impedance is calculated in accordance with JESD 51-5. 3 SN74CB3Q3125 QUADRUPLE FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH www.ti.com SCDS143B – OCTOBER 2003 – REVISED MARCH 2005 Recommended Operating Conditions (1) MIN MAX VCC Supply voltage VIH High-level control input voltage VIL Low-level control input voltage VI/O Data input/output voltage TA Operating free-air temperature (1) UNIT 2.3 3.6 VCC = 2.3 V to 2.7 V 1.7 5.5 V VCC = 2.7 V to 3.6 V 2 5.5 VCC = 2.3 V to 2.7 V 0 0.7 VCC = 2.7 V to 3.6 V 0 0.8 0 5.5 V –40 85 °C V V All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Electrical Characteristics (1) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS VCC = 3.6 V, II = –18 mA VCC = 3.6 V, VIN = 0 to 5.5 V VCC = 3.6 V, VO = 0 to 5.5 V, VI = 0, Switch OFF, VIN = VCC or GND Ioff VCC = 0, VO = 0 to 5.5 V, VI = 0 ICC VCC = 3.6 V, II/O = 0, Switch ON or OFF, VIN = VCC or GND Other inputs at VCC or GND IIN IOZ Control inputs (3) MIN TYP (2) MAX UNIT –1.8 V ±1 µA ±1 µA 1 µA 1 mA 30 µA 0.04 0.2 mA/ MHz 2.5 3.5 pF 0.3 ∆ICC (4) Control inputs VCC = 3.6 V, One input at 3 V, ICCD (5) Per control input VCC = 3.6 V, A and B ports open, Cin Control inputs VCC = 3.3 V, VIN = 5.5 V, 3.3 V, or 0 Cio(OFF) VCC = 3.3 V, Switch OFF, VIN = VCC or GND, VI/O = 5.5 V, 3.3 V, or 0 4 5 pF Cio(ON) VCC = 3.3 V, Switch ON, VIN = VCC or GND, VI/O = 5.5 V, 3.3 V, or 0 8 10 pF VI = 0, IO = 30 mA 4 8 VI = 1.7 V, IO = –15 mA 4 9 VI = 0, IO = 30 mA 4 6 VI = 2.4 V, IO = –15 mA 4 8 ron (6) Control input switching at 50% duty cycle VCC = 2.3 V, TYP at VCC = 2.5 V VCC = 3 V (1) (2) (3) (4) (5) (6) 4 VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (see Figure 2). Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals. Ω SN74CB3Q3125 QUADRUPLE FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH www.ti.com SCDS143B – OCTOBER 2003 – REVISED MARCH 2005 Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) VCC = 3.3 V ± 0.3 V TO (OUTPUT) fOE (1) OE A or B 10 20 MHz tpd (2) A or B B or A 0.12 0.2 ns ten OE A or B 1.5 6.7 1.5 6.6 ns tdis OE A or B 1 4.6 1 5.3 ns MIN MAX MIN UNIT MAX Maximum switching frequency for control input (VO > VCC, VI = 5 V, RL ≥ 1 MΩ, CL = 0) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). TYPICAL ron vs VI ron - ON-State Resistance - 16 VCC = 3.3 V TA = 25°C IO = -15 mA 14 12 10 8 6 4 2 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 18 20 VI - V Figure 1. Typical ron vs VI TYPICAL ICC vs OE SWITCHING FREQUENCY 12 VCC = 3.3 V TA = 25°C A and B Ports Open 10 8 ICC − mA (1) (2) VCC = 2.5 V ± 0.2 V FROM (INPUT) PARAMETER 6 4 2 One OE Switching 0 0 2 4 6 8 10 12 14 16 OE Switching Frequency − MHz Figure 2. Typical ICC vs OE Switching Frequency 5 SN74CB3Q3125 QUADRUPLE FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH www.ti.com SCDS143B – OCTOBER 2003 – REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION VCC Input Generator VIN 50 Ω 50 Ω VG1 TEST CIRCUIT DUT 2 × VCC Input Generator S1 RL VO VI 50 Ω 50 Ω VG2 CL (see Note A) RL TEST VCC S1 RL VI CL tpd(s) 2.5 V ± 0.2 V 3.3 V ± 0.3 V Open Open 500 Ω 500 Ω VCC or GND VCC or GND 30 pF 50 pF tPLZ/tPZL 2.5 V ± 0.2 V 3.3 V ± 0.3 V 2 × VCC 2 × VCC 500 Ω 500 Ω GND GND 30 pF 50 pF 0.15 V 0.3 V tPHZ/tPZH 2.5 V ± 0.2 V 3.3 V ± 0.3 V GND GND 500 Ω 500 Ω VCC VCC 30 pF 50 pF 0.15 V 0.3 V V∆ VCC Output Control (VIN) VCC/2 VCC VCC/2 VCC/2 0V tPLH VOH Output VCC/2 VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (tpd(s)) Output Waveform 1 S1 at 2 × VCC (see Note B) tPLZ VCC VCC/2 VOL + V∆ VOL tPZH tPHL VCC/2 0V tPZL Output Control (VIN) Open GND Output Waveform 2 S1 at GND (see Note B) tPHZ VOH VCC/2 VOH − V∆ 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices. Figure 3. Test Circuit and Voltage Waveforms 6 PACKAGE OPTION ADDENDUM www.ti.com 3-May-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) SN74CB3Q3125DBQR ACTIVE SSOP/ QSOP DBQ 16 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74CB3Q3125DGVR ACTIVE TVSOP DGV 14 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SN74CB3Q3125PW ACTIVE TSSOP PW 14 90 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SN74CB3Q3125PWE4 ACTIVE TSSOP PW 14 90 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SN74CB3Q3125PWR ACTIVE TSSOP PW 14 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SN74CB3Q3125PWRE4 ACTIVE TSSOP PW 14 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SN74CB3Q3125RGYR ACTIVE QFN RGY 14 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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