SCDS123A − JULY 2003 − REVISED OCTOBER 2003
D
D
D
D
D
D
D
D
D
D
D
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
2OE
S0
2B4
2B3
2B2
2B1
2A
RGY PACKAGE
(TOP VIEW)
S1
1B4
1B3
1B2
1B1
1A
VCC
D
1OE
S1
1B4
1B3
1B2
1B1
1A
GND
1
16
15 2OE
14 S0
2
3
13 2B4
12 2B3
4
5
11 2B2
10 2B1
6
7
8
9
2A
D
D, DB, DBQ, OR PW PACKAGE
(TOP VIEW)
1OE
D
Industry-Standard ’3253 Function
Undershoot Protection for Off-Isolation on
A and B Ports Up To −2 V
Bidirectional Data Flow, With Near-Zero
Propagation Delay
Low ON-State Resistance (ron)
Characteristics (ron = 3 Ω Typical)
Low Input/Output Capacitance Minimizes
Loading and Signal Distortion
(Cio(OFF) = 5.5 pF Typical)
Data and Control Inputs Provide
Undershoot Clamp Diodes
Low Power Consumption
(ICC = 3 µA Max)
VCC Operating Range From 4 V to 5.5 V
Data I/Os Support 0 to 5-V Signaling Levels
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 1000-V Charged-Device Model (C101)
Supports I2C Bus Expansion
Supports Both Digital and Analog
Applications: USB Interface, Bus Isolation,
Low-Distortion Signal Gating
GND
D SN74CBT3253C Functionally Identical to
description/ordering information
The SN74CBT3253C is a high-speed TTL-compatible FET multiplexer/demultiplexer with low ON-state
resistance (ron), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and
B ports of the SN74CBT3253C provides protection for undershoot up to −2 V by sensing an undershoot event
and ensuring that the switch remains in the proper OFF state.
The SN74CBT3253C is organized as two 1-of-4 multiplexer/demultiplexers with separate output-enable
(1OE, 2OE) inputs. The select (S0, S1) inputs control the data path of each multiplexer/demultiplexer. When
OE is low, the associated multiplexer/demultiplexer is enabled, and the A port is connected to the B port, allowing
bidirectional data flow between ports. When OE is high, the associated multiplexer/demultiplexer is disabled,
and a high-impedance state exists between the A and B ports.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
!"#$%&" ' ()##*& %' "! +),-(%&" .%&*/
#".)(&' ("!"#$ &" '+*(!(%&"' +*# &0* &*#$' "! *1%' '&#)$*&'
'&%.%#. 2%##%&3/ #".)(&" +#"(*''4 ."*' "& *(*''%#-3 (-).*
&*'&4 "! %-- +%#%$*&*#'/
POST OFFICE BOX 655303
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1
SCDS123A − JULY 2003 − REVISED OCTOBER 2003
description/ordering information (continued)
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
QFN − RGY
SOIC − D
−40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SSOP − DB
SSOP (QSOP) − DBQ
TSSOP − PW
Tape and reel
SN74CBT3253CRGYR
Tube
SN74CBT3253CD
Tape and reel
SN74CBT3253CDR
Tube
SN74CBT3253CDB
Tape and reel
SN74CBT3253CDBR
Tape and reel
SN74CBT3253CDBQR
Tube
SN74CBT3253CPW
Tape and reel
SN74CBT3253CPWR
TOP-SIDE
MARKING
CU253C
CBT3253C
CU253C
CBT3253C
CU253C
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each multiplexer/demultiplexer)
INPUTS
2
OE
S1
S0
INPUT/OUTPUT
A
FUNCTION
L
L
L
B1
A port = B1 port
L
L
H
B2
A port = B2 port
L
H
L
B3
A port = B3 port
L
H
H
B4
A port = B4 port
H
X
X
Z
Disconnect
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SCDS123A − JULY 2003 − REVISED OCTOBER 2003
logic diagram (positive logic)
7
1A
6
SW
5
SW
4
SW
3
SW
1B1
1B2
1B3
1B4
10
9
2A
2B1
SW
11
SW
12
SW
SW
13
2B2
2B3
2B4
14
S0
2
S1
1
1OE
2OE
15
simplified schematic, each FET switch (SW)
A
B
Undershoot
Protection Circuit
EN†
† EN is the internal enable signal applied to the switch.
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3
SCDS123A − JULY 2003 − REVISED OCTOBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
ON-state switch current, II/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±128 mA
Continuous current through VCC or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 5): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
(see Note 5): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
(see Note 5): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
(see Note 5): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
(see Note 6): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. VI and VO are used to denote specific conditions for VI/O.
4. II and IO are used to denote specific conditions for II/O.
5. The package thermal impedance is calculated in accordance with JESD 51-7.
6. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 7)
MIN
MAX
UNIT
VCC
VIH
Supply voltage
4
5.5
V
High-level control input voltage
2
5.5
V
VIL
VI/O
Low-level control input voltage
0
0.8
V
Data input/output voltage
0
5.5
V
TA
Operating free-air temperature
−40
85
°C
NOTE 7: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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SCDS123A − JULY 2003 − REVISED OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Control inputs
VCC = 4.5 V,
VIKU
Data inputs
VCC = 5 V,
IIN
Control inputs
VCC = 5.5 V,
IOZ‡
VCC = 5.5 V,
Ioff
VCC = 0,
ICC
VCC = 5.5 V,
∆ICC§
Cin
Control inputs
Control inputs
IIN = −18 mA
0 mA > II ≥ −50 mA,
VIN = VCC or GND,
VIN = VCC or GND
VO = 0 to 5.5 V,
VI = 0,
VCC = 5.5 V,
VIN = 3 V or 0
MIN
Switch OFF
Switch OFF,
VIN = VCC or GND
VO = 0 to 5.5 V,
II/O = 0,
VIN = VCC or GND,
VI = 0
One input at 3.4 V,
Other inputs at VCC or GND
B port
Cio(ON)
MAX
UNIT
−1.8
V
−2
V
±1
µA
±10
µA
10
µA
3
µA
2.5
mA
Switch ON or OFF
A port
Cio(OFF)
TYP†
3.5
pF
14
pF
5.5
pF
22
pF
VI/O = 3 V or 0,
Switch OFF,
VIN = VCC or GND
VI/O = 3 V or 0,
Switch ON,
VIN = VCC or GND
VCC = 4 V,
TYP at VCC = 4 V
VI = 2.4 V,
IO = −15 mA
8
12
IO = 64 mA
IO = 30 mA
3
6
VI = 0
3
6
ron¶
VCC = 4.5 V
Ω
VI = 2.4 V,
IO = −15 mA
5
10
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
† All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
§ This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND.
¶ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 3)
PARAMETER
tpd#
tpd(s)
ten
tdis
VCC = 4 V
VCC = 5 V
± 0.5 V
MIN
MIN
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
0.24
S
A
5.9
MAX
UNIT
MAX
0.15
ns
1.5
5.4
ns
S
B
6.2
1.5
5.8
OE
A or B
5.7
1.5
5.3
S
B
6.2
1.5
5.8
OE
A or B
5.7
1.5
5.3
ns
ns
# The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,
when driven by an ideal voltage source (zero output impedance).
POST OFFICE BOX 655303
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5
SCDS123A − JULY 2003 − REVISED OCTOBER 2003
undershoot characteristics (see Figures 1 and 2)
PARAMETER
TEST CONDITIONS
VOUTU
VCC = 5.5 V,
Switch OFF,
† All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
VCC
Input
Generator
Ax
VS
DUT
2
VOH−0.3
VIN = VCC or GND
Input
(Open
Socket)
Bx
100 kΩ
90 %
2 ns
MAX
UNIT
V
POST OFFICE BOX 655303
5.5 V
2 ns
10 %
−2 V
20 ns
10 pF
Figure 1. Device Test Setup
90 %
10 %
Output
(VOUTU)
6
TYP†
11 V
100 kΩ
50 Ω
MIN
VOH
VOH − 0.3
Figure 2. Transient Input Voltage (VI) and Output
Voltage (VOUTU) Waveforms
(Switch OFF)
• DALLAS, TEXAS 75265
SCDS123A − JULY 2003 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
VCC
Input Generator
VIN
50 Ω
50 Ω
VG1
TEST CIRCUIT
DUT
7V
Input Generator
VI
S1
RL
VO
GND
50 Ω
50 Ω
VG2
CL
(see Note A)
RL
TEST
VCC
S1
RL
VI
CL
tpd(s)
5 V ± 0.5 V
4V
Open
Open
500 Ω
500 Ω
VCC or GND
VCC or GND
50 pF
50 pF
tPLZ/tPZL
5 V ± 0.5 V
4V
7V
7V
500 Ω
500 Ω
GND
GND
50 pF
50 pF
0.3 V
0.3 V
tPHZ/tPZH
5 V ± 0.5 V
4V
Open
Open
500 Ω
500 Ω
VCC
VCC
50 pF
50 pF
0.3 V
0.3 V
Output
Control
(VIN)
V∆
3V
1.5 V
3V
1.5 V
1.5 V
0V
tPLH
VOH
Output
1.5 V
Output
Waveform 1
S1 at 7 V
(see Note B)
tPLZ
3.5 V
1.5 V
tPZH
tPHL
1.5 V
VOL
1.5 V
0V
tPZL
Output
Control
(VIN)
Open
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (tpd(s))
VOL + V∆
VOL
tPHZ
1.5 V
VOH − V∆
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state
resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Test Circuit and Voltage Waveforms
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7
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
SN74CBT3253CD
ACTIVE
SOIC
D
16
40
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74CBT3253CDB
PREVIEW
SSOP
DB
16
80
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74CBT3253CDBQR
ACTIVE
SSOP/
QSOP
DBQ
16
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74CBT3253CDBR
ACTIVE
SSOP
DB
16
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74CBT3253CDR
ACTIVE
SOIC
D
16
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74CBT3253CPW
ACTIVE
TSSOP
PW
16
90
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74CBT3253CPWR
ACTIVE
TSSOP
PW
16
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74CBT3253CRGYR
ACTIVE
QFN
RGY
16
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
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