SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004 D Output Voltage Translation Tracks VCC D Supports Mixed-Mode Signal Operation On D D D D D D D VCC Operating Range From 2.3 V to 3.6 V D Data I/Os Support 0- to 5-V Signaling All Data I/O Ports − 5-V Input Down To 3.3-V Output Level Shift With 3.3-V VCC − 5-V/3.3-V Input Down To 2.5-V Output Level Shift With 2.5-V VCC 5-V-Tolerant I/Os With Device Powered Up or Powered Down Bidirectional Data Flow, With Near-Zero Propagation Delay Low ON-State Resistance (ron) Characteristics (ron = 5 Ω Typical) Low Input/Output Capacitance Minimizes Loading (Cio(OFF) = 8 pF Typical) Data and Control Inputs Provide Undershoot Clamp Diodes Low Power Consumption (ICC = 20 µA Max) D D D D D D Levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V) Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Performance Tested Per JESD 22 − 2000-V Human-Body Model (A114-B, Class II) − 1000-V Charged-Device Model (C101) Supports Digital Applications: Level Translation, Memory Interleaving, Bus Isolation Ideal for Low-Power Portable Equipment DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW) BE 1B1 1A1 1A2 1B2 2B1 2A1 2A2 2B2 3B1 3A1 GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC 5B2 5A2 5A1 5B1 4B2 4A2 4A1 4B1 3B2 3A2 BX description/ordering information ORDERING INFORMATION SOIC − DW −40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA SSOP (QSOP) − DBQ TSSOP − PW Tube SN74CB3T3383DW Tape and reel SN74CB3T3383DWR Tape and reel SN74CB3T3383DBQR Tube SN74CB3T3383PW Tape and reel SN74CB3T3383PWR TOP-SIDE MARKING CB3T3383 CB3T3383 KS383 TVSOP − DGV Tape and reel SN74CB3T3383DGVR KS383 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated !"#$%&'(!$" !) *+%%,"( ') $# -+./!*'(!$" 0'(, %$0+*() *$"#$%& ($ )-,*!#!*'(!$") -,% (1, (,%&) $# ,2') ")(%+&,"() )('"0'%0 3'%%'"(4 %$0+*(!$" -%$*,))!"5 0$,) "$( ",*,))'%!/4 !"*/+0, (,)(!"5 $# '// -'%'&,(,%) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004 description/ordering information (continued) The SN74CB3T3383 is a high-speed TTL-compatible FET bus-exchange switch with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC. The SN74CB3T3383 supports systems using 5-V TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1). VCC 5.5 V VCC IN ≈VCC − 1 V ≈VCC OUT ≈VCC − 1 V CB3T 0V 0V Input Voltages Output Voltages NOTE A: If the input high voltage (VIH) level is greater than or equal to VCC − 1 V, and less than or equal to 5.5 V, then the output high voltage (VOH) level will be equal to approximately the VCC voltage level. Figure 1. Typical DC Voltage Translation Characteristics The SN74CB3T3383 is organized as a 10-bit bus switch or as a 5-bit bus-exchange with enable (BE) input. When used as a 5-bit bus-exchange, the device provides data exchanging between four signal ports. When BE is low, the bus-exchange switch is ON, and the select input (BX) controls the data path. When BE is high, the bus-exchange switch is OFF, and a high-impedance state exists between the A and B ports. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, BE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004 FUNCTION TABLE (each 5-bit switch) INPUTS INPUTS/OUTPUTS FUNCTION BE BX A1 A2 L L B1 B2 A1 port = B1 port A2 port = B2 port L H B2 B1 A1 port = B2 port A2 port = B1 port H X Z Z Disconnect logic diagram (positive logic) 2 3 1A1 1B1 SW SW SW 5 4 1A2 1B2 SW 20 21 5A1 5B1 SW SW SW 23 22 5A2 5B2 SW 1 BE 13 BX POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004 simplified schematic, each FET switch (SW) A B VG† Control Circuit EN‡ † Gate Voltage (VG) is approximately equal to VCC + VT when the switch is ON and VI > VCC + VT. ‡ EN is the internal enable signal applied to the switch. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)§ Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA ON-state switch current, II/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±128 mA Continuous current through VCC or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 5): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C § Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground unless otherwise specified. 2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. VI and VO are used to denote specific conditions for VI/O. 4. II and IO are used to denote specific conditions for II/O. 5. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 6) VCC Supply voltage VIH High-level control input voltage VIL Low-level control input voltage VI/O TA Data input/output voltage MIN MAX 2.3 3.6 VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V 1.7 5.5 2 5.5 0 0.7 VCC = 2.7 V to 3.6 V 0 0.8 0 5.5 V −40 85 °C Operating free-air temperature UNIT V V V NOTE 6: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VCC = 3 V, II = −18 mA VOH See Figures 3 and 4 IIN‡ Control inputs IOZ§ VCC = 3.6 V, VO = 0 to 5.5 V, VI = 0, Switch OFF, VIN = VCC or GND Ioff VCC = 0, VO = 0 to 5.5 V, VI = 0, ICC ∆ICC¶ Control inputs Cin Control inputs TYP† VCC = 3.6 V, VIN‡ = 3.6 V to 5.5 V or GND VCC = 3.6 V, Switch ON, VIN = VCC or GND II MIN VCC = 3.6 V, II/O = 0, Switch ON or OFF, VIN = VCC or GND VCC = 3 V to 3.6 V, One input at VCC − 0.6 V, Other inputs at VCC or GND MAX UNIT −1.2 V ±10 µA ±20 VI = VCC − 0.7 V to 5.5 V VI = 0.7 V to VCC − 0.7 V −40 µA ±5 VI = 0 to 0.7 V ±10 µA 10 µA VI = VCC or GND 20 VI = 5.5 V 20 A µA 300 µA VCC = 3.3 V, VIN = VCC or GND 4 pF Cio(OFF) VCC = 3.3 V, VI/O = 5.5 V, 3.3 V, or GND, Switch OFF, VIN = VCC or GND 8 pF VCC = 3.3 V, Switch ON, VIN = VCC or GND VI/O = 5.5 V or 3.3 V Cio(ON) VI/O = GND 21 VCC = 2.3 V, TYP at VCC = 2.5 V, VI = 0 IO = 24 mA 5 9 IO = 16 mA 5 9 VCC = 3 V, VI = 0 IO = 64 mA IO = 32 mA 5 8 ron# 7 pF Ω 5 8 † All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. ‡ VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. § For I/O ports, the parameter IOZ includes the input leakage current. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. # Measured by the voltage drop between A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V FROM (INPUT) TO (OUTPUT) A or B B or A tpd(s) ten BX A or B 1 15 1 BE A or B 1 13.5 1 9 ns tdis BE A or B 1 7 1 8.5 ns PARAMETER tpd† MIN MAX MIN 0.15 UNIT MAX 0.25 10 ns † The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004 PARAMETER MEASUREMENT INFORMATION VCC Input Generator VIN 50 Ω 50 Ω VG1 TEST CIRCUIT DUT Input Generator VI S1 RL VO 50 Ω VG2 CL (see Note A) RL TEST VCC S1 RL VI CL tpd(s) 2.5 V ± 0.2 V 3.3 V ± 0.3 V Open Open 500 Ω 500 Ω 3.6 V or GND 5.5 V or GND 30 pF 50 pF tPLZ/tPZL 2.5 V ± 0.2 V 3.3 V ± 0.3 V 2 × VCC 2 × VCC 500 Ω 500 Ω GND GND 30 pF 50 pF 0.15 V 0.3 V tPHZ/tPZH 2.5 V ± 0.2 V 3.3 V ± 0.3 V Open Open 500 Ω 500 Ω 3.6 V 5.5 V 30 pF 50 pF 0.15 V 0.3 V Output Control (VIN) V∆ VCC VCC/2 VCC VCC/2 0V tPLH VOH Output VCC/2 Output Waveform 1 S1 at 2 × VCC (see Note B) tPLZ VCC VCC/2 tPZH tPHL VCC/2 VOL VCC/2 0V tPZL VCC/2 Open GND 50 Ω Output Control (VIN) 2 × VCC Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (tpd(s)) VOL + V∆ VOL tPHZ VCC/2 VOH − V∆ VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices. Figure 2. Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE vs INPUT VOLTAGE OUTPUT VOLTAGE vs INPUT VOLTAGE 4.0 VCC = 2.3 V IO = 1 µA TA = 25°C 3.0 V − Output Voltage − V O V − Output Voltage − V O 4.0 2.0 1.0 0.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 VCC = 3 V IO = 1 µA TA = 25°C 3.0 2.0 1.0 0.0 0.0 1.0 VI − Input Voltage − V 2.0 POST OFFICE BOX 655303 4.0 VI − Input Voltage − V Figure 3. Data Output Voltage vs Data Input Voltage 8 3.0 • DALLAS, TEXAS 75265 5.0 6.0 SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE 4.0 100 µA 8 mA 16 mA 24 mA 3.0 2.5 2.0 1.5 2.3 2.5 2.7 2.9 3.1 3.3 3.5 V − Output Voltage High − V OH 3.5 VCC = 2.3 V to 3.6 V VI = 5.5 V TA = 85°C VCC = 2.3 V to 3.6 V VI = 5.5 V TA = 25°C 3.5 100 µA 8 mA 16 mA 24 mA 3.0 2.5 2.0 1.5 3.7 2.3 2.5 VCC − Supply Voltage − V 2.7 2.9 3.1 3.3 3.5 3.7 VCC − Supply Voltage − V OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE 4.0 V − Output Voltage High − V OH V − Output Voltage High − V OH 4.0 3.5 VCC = 2.3 V to 3.6 V VI = 5.5 V TA = –40°C 100 µA 8 mA 16 mA 24 mA 3.0 2.5 2.0 1.5 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 VCC − Supply Voltage − V Figure 4. VOH Values POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PACKAGE OPTION ADDENDUM www.ti.com 24-May-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74CB3T3383DBQRE4 ACTIVE SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 74CB3T3383DBQRG4 ACTIVE SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 74CB3T3383DGVRE4 ACTIVE TVSOP DGV 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74CB3T3383DGVRG4 ACTIVE TVSOP DGV 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3383DBQR ACTIVE SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN74CB3T3383DGVR ACTIVE TVSOP DGV 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3383DW ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3383DWE4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3383DWG4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3383DWR ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3383DWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3383DWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3383PW ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3383PWE4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3383PWG4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3383PWR ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3383PWRE4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3383PWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 24-May-2007 package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Jul-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 16-Jul-2007 Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74CB3T3383DBQR DBQ 24 MLA 330 16 6.5 9.0 2.1 8 16 Q1 SN74CB3T3383DGVR DGV 24 MLA 330 12 7.0 5.6 1.6 8 12 Q1 SN74CB3T3383DWR DW 24 TAI 330 24 10.75 15.7 2.7 12 24 Q1 SN74CB3T3383PWR PW 24 MLA 330 16 6.95 8.3 1.6 8 16 Q1 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) SN74CB3T3383DBQR DBQ 24 MLA 346.0 346.0 33.0 SN74CB3T3383DGVR DGV 24 MLA 346.0 346.0 29.0 SN74CB3T3383DWR DW 24 TAI 346.0 346.0 41.0 SN74CB3T3383PWR PW 24 MLA 346.0 346.0 33.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Jul-2007 Pack Materials-Page 3 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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