www.ti.com SN74CB3T3245 8-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER SCDS136 – OCTOBER 2003 – REVISED MARCH 2005 FEATURES • • • • • • • • • Standard '245-Type Pinout Output Voltage Translation Tracks VCC Supports Mixed-Mode Signal Operation on All Data I/O Ports – 5-V Input Down to 3.3-V Output Level Shift With 3.3-V VCC – 5-V/3.3-V Input Down to 2.5-V Output Level Shift With 2.5-V VCC 5-V-Tolerant I/Os With Device Powered Up or Powered Down Bidirectional Data Flow With Near-Zero Propagation Delay Low ON-State Resistance (ron) Characteristics (ron = 5 Ω Typ) Low Input/Output Capacitance Minimizes Loading (Cio(OFF) = 5 pF Typ) Data and Control Inputs Provide Undershoot Clamp Diodes Low Power Consumption (ICC = 40 µA Max) • • • • • • • • VCC Operating Range From 2.3 V to 3.6 V Data I/Os Support 0- to 5-V Signaling Levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V) Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Performance Tested Per JESD 22 – 2000-V Human-Body Model (A114-B, Class II) – 1000-V Charged-Device Model (C101) Supports Digital Applications: Level Translation, PCI Interface, USB Interface, Memory Interleaving, Bus Isolation Ideal for Low-Power Portable Equipment DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW) NC A1 A2 A3 A4 A5 A6 A7 A8 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC OE B1 B2 B3 B4 B5 B6 B7 B8 NC − No internal connection DESCRIPTION/ORDERING INFORMATION The SN74CB3T3245 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC. The SN74CB3T3245 supports systems using 5-V TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2005, Texas Instruments Incorporated SN74CB3T3245 8-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER www.ti.com SCDS136 – OCTOBER 2003 – REVISED MARCH 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) VCC 5.5 V VCC IN VCC − 1 V OUT VCC VCC − 1 V CB3T 0V 0V Input Voltages Output Voltages NOTE A: If the input high-voltage (VIH) level is greater than or equal to (VCC − 1 V) and less than or equal to 5.5 V, then the output high-voltage (VOH) level will be equal to approximately the VCC voltage level. Figure 1. Typical DC Voltage Translation Characteristics The SN74CB3T3245 is an 8-bit bus switch with a single ouput-enable (OE) input and a standard '245 pinout. When OE is low, the 8-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the 8-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION PACKAGE (1) TA SOIC – DW –40°C to 85°C SSOP (QSOP) – DBQ TSSOP – PW TVSOP – DGV (1) ORDERABLE PART NUMBER Tube SN74CB3T3245DW Tape and reel SN74CB3T3245DWR Tape and reel SN74CB3T3245DBQR Tube SN74CB3T3245PW Tape and reel SN74CB3T3245PWR Tape and reel SN74CB3T3245DGVR CB3T3245 CB3T3245 KS245 KS245 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE 2 TOP-SIDE MARKING INPUT OE INPUT/OUTPUT A FUNCTION L B A port = B port H Z Disconnect SN74CB3T3245 8-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER www.ti.com SCDS136 – OCTOBER 2003 – REVISED MARCH 2005 LOGIC DIAGRAM (POSITIVE LOGIC) 2 A1 A8 18 B1 SW 9 11 SW B8 19 OE SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW) A B VG(1) Control Circuit EN(2) 1) Gate Voltage (VG) is approximately equal to VCC + VT when the switch is ON and VI > (VCC + VT). 2) EN is the internal enable signal applied to the switch. 3 SN74CB3T3245 8-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER www.ti.com SCDS136 – OCTOBER 2003 – REVISED MARCH 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range (2) –0.5 7 V VIN Control input voltage range (2) (3) –0.5 7 V VI/O Switch I/O voltage range (2) (3) (4) IIK Control input clamp current VIN < 0 –50 mA II/OK I/O port clamp current VI/O < 0 –50 mA ±128 mA ±100 mA II/O ON-state switch –0.5 current (5) Continuous current through VCC or GND θJA Package thermal impedance (6) Tstg Storage temperature range DBQ package 68 DGV package 92 DW package 58 PW package (1) (2) (3) (4) (5) (6) 7 UNIT V °C/W 83 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground unless otherwise specified. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. VI and VO are used to denote specific conditions for VI/O. II and IO are used to denote specific conditions for II/O. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) VCC Supply voltage VIH High-level control input voltage VIL Low-level control input voltage VI/O Data input/output voltage TA Operating free-air temperature (1) 4 MIN MAX 2.3 3.6 UNIT VCC = 2.3 V to 2.7 V 1.7 5.5 VCC = 2.7 V to 3.6 V 2 5.5 VCC = 2.3 V to 2.7 V 0 0.7 VCC = 2.7 V to 3.6 V 0 0.8 0 5.5 V –40 85 °C V V V All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. SN74CB3T3245 8-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER www.ti.com SCDS136 – OCTOBER 2003 – REVISED MARCH 2005 Electrical Characteristics (1) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VCC = 3 V, II = –18 mA VOH See Figure 3 and Figure 4 IIN Control inputs MIN TYP (2) VCC = 3.6 V, VIN = 3.6 V to 5.5 V or GND MAX UNIT –1.2 V ±10 µA VI = VCC – 0.7 V to 5.5 V ±20 II VCC = 3.6 V, Switch ON, VIN = VCC or GND VI = 0.7 V to VCC – 0.7 V –40 IOZ (3) VCC = 3.6 V, VO = 0 to 5.5 V, VI = 0, Switch OFF, VIN = VCC or GND Ioff VCC = 0, VO = 0 to 5.5 V, VI = 0, ICC VCC = 3.6 V, II/O = 0, Switch ON or OFF, VIN = VCC or GND ±5 VI = 0 to 0.7 V 40 VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND Control inputs VCC = 3.3 V, VIN = VCC or GND ron (5) VCC = 3 V, VI = 0 (1) (2) (3) (4) (5) 300 VCC = 3.3 V, VI/O = 5.5 V, 3.3 V, or GND, Switch OFF, VIN = VCC or GND VCC = 2.3 V, TYP at VCC = 2.5 V, VI = 0 µA 40 Control inputs VCC = 3.3 V, Switch ON, VIN = VCC or GND µA 10 VI = 5.5 V Cin Cio(ON) ±10 VI = VCC or GND ∆ICC (4) Cio(OFF) µA VI/O = 5.5 V or 3.3 V µA µA 4 pF 5 pF 5 pF VI/O = GND 13 IO = 24 mA 5 8.5 IO = 16 mA 5 8.5 IO = 64 mA 5 7 IO = 32 mA 5 7 Ω VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. Measured by the voltage drop between A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals. Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) (1) VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V FROM (INPUT) TO (OUTPUT) tpd (1) A or B B or A 0.25 ns ten OE A or B 1 10.5 1 8 ns tdis OE A or B 1 5.5 1 7.5 ns PARAMETER MIN MAX MIN 0.15 UNIT MAX The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). 5 SN74CB3T3245 8-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER www.ti.com SCDS136 – OCTOBER 2003 – REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION VCC Input Generator VIN 50 Ω 50 Ω VG1 TEST CIRCUIT DUT 2 × VCC Input Generator S1 RL VO VI 50 Ω 50 Ω VG2 CL (see Note A) RL TEST VCC S1 RL VI CL tpd(s) 2.5 V ± 0.2 V 3.3 V ± 0.3 V Open Open 500 Ω 500 Ω 3.6 V or GND 5.5 V or GND 30 pF 50 pF tPLZ/tPZL 2.5 V ± 0.2 V 3.3 V ± 0.3 V 2 × VCC 2 × VCC 500 Ω 500 Ω GND GND 30 pF 50 pF 0.15 V 0.3 V tPHZ/tPZH 2.5 V ± 0.2 V 3.3 V ± 0.3 V Open Open 500 Ω 500 Ω 3.6 V 5.5 V 30 pF 50 pF 0.15 V 0.3 V V∆ VCC Output Control (VIN) VCC/2 VCC VCC/2 VCC/2 0V tPLH VOH Output VCC/2 VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (tpd(s)) Output Waveform 1 S1 at 2 × VCC (see Note B) tPLZ VCC VCC/2 VOL + V∆ VOL tPZH tPHL VCC/2 0V tPZL Output Control (VIN) Open GND Output Waveform 2 S1 at Open (see Note B) tPHZ VOH VCC/2 VOH − V∆ 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices. Figure 2. Test Circuit and Voltage Waveforms 6 SN74CB3T3245 8-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER www.ti.com SCDS136 – OCTOBER 2003 – REVISED MARCH 2005 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE vs INPUT VOLTAGE OUTPUT VOLTAGE vs INPUT VOLTAGE 4.0 VCC = 2.3 V IO = 1 µA TA = 25°C 3.0 V − Output Voltage − V O V − Output Voltage − V O 4.0 2.0 1.0 0.0 VCC = 3 V IO = 1 µA TA = 25°C 3.0 2.0 1.0 0.0 0.0 1.0 2.0 3.0 4.0 VI − Input Voltage − V 5.0 6.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 VI − Input Voltage − V Figure 3. Data Output Voltage vs Data Input Voltage 7 SN74CB3T3245 8-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER www.ti.com SCDS136 – OCTOBER 2003 – REVISED MARCH 2005 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE VCC = 2.3 V to 3.6 V VI = 5.5 V TA = 85°C 3.5 100 µA 8 mA 16 mA 24 mA 3.0 2.5 2.0 VOH − Output Voltage High − V 4.0 4.0 VOH − Output Voltage High − V OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE 1.5 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.5 VCC = 2.3 V to 3.6 V VI = 5.5 V TA = 25°C 2.5 2.0 2.5 VCC − Supply Voltage − V 100 µA 2.7 2.9 3.1 3.3 VCC − Supply Voltage − V OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE 8 mA 16 mA 24 mA VOH − Output Voltage High − V 4.0 3.5 VCC = 2.3 V to 3.6 V VI = 5.5 V TA = –40°C 100 µA 8 mA 16 mA 24 mA 3.0 2.5 2.0 1.5 2.3 2.5 2.7 2.9 3.1 3.3 VCC − Supply Voltage − V Figure 4. VOH Values 8 8 mA 16 mA 24 mA 3.0 1.5 2.3 3.7 100 µA 3.5 3.7 3.5 3.7 PACKAGE OPTION ADDENDUM www.ti.com 24-May-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74CB3T3245DBQRE4 ACTIVE SSOP/ QSOP DBQ 20 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 74CB3T3245DBQRG4 ACTIVE SSOP/ QSOP DBQ 20 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 74CB3T3245DGVRE4 ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74CB3T3245DGVRG4 ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3245DBQR ACTIVE SSOP/ QSOP DBQ 20 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN74CB3T3245DGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3245DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3245DWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3245DWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3245DWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3245DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3245DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3245PW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3245PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3245PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3245PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3245PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3245PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 24-May-2007 package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Jun-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 16-Jun-2007 Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74CB3T3245DBQR DBQ 20 MLA 330 16 6.5 9.0 2.1 8 16 Q1 SN74CB3T3245DGVR DGV 20 MLA 330 12 7.0 5.6 1.6 8 12 Q1 SN74CB3T3245DWR DW 20 MLA 330 24 10.8 13.0 2.7 12 24 Q1 SN74CB3T3245PWR PW 20 MLA 330 16 6.95 7.1 1.6 8 16 Q1 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) SN74CB3T3245DBQR DBQ 20 MLA 0.0 0.0 0.0 SN74CB3T3245DGVR DGV 20 MLA 342.9 336.6 20.64 SN74CB3T3245DWR DW 20 MLA 333.2 333.2 31.75 SN74CB3T3245PWR PW 20 MLA 342.9 336.6 28.58 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Jun-2007 Pack Materials-Page 3 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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