SCDS018O − MAY 1995 − REVISED JANUARY 2004 D TTL-Compatible Input Levels 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 2OE S0 2B4 2B3 2B2 2B1 2A S1 1B4 1B3 1B2 1B1 1A VCC 16 2 1 16 15 2OE 14 S0 2 3 13 2B4 12 2B3 4 5 11 2B2 10 2B1 6 7 8 9 2A 1 GND 1OE S1 1B4 1B3 1B2 1B1 1A GND 1OE RGY PACKAGE (TOP VIEW) D, DB, DBQ, OR PW PACKAGE (TOP VIEW) description/ordering information The SN74CBT3253 is a dual 1-of-4 high-speed TTL-compatible FET multiplexer/demultiplexer. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. 1OE, 2OE, S0, and S1 select the appropriate B output for the A-input data. ORDERING INFORMATION QFN − RGY TOP-SIDE MARKING Tape and reel SN74CBT3253RGYR Tube SN74CBT3253D Tape and reel SN74CBT3253DR SSOP − DB Tape and reel SN74CBT3253DBR CU253 SSOP (QSOP) − DBQ Tape and reel SN74CBT3253DBQR CU253 Tube SN74CBT3253PW Tape and reel SN74CBT3253PWR SOIC − D −40°C −40 C to 85 85°C C ORDERABLE PART NUMBER PACKAGE† TA TSSOP − PW CU253 CBT3253 CU253 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUTS FUNCTION 1OE 2OE S1 S0 X H X X H X X X Disconnect 1A and 2A L L L L 1A to 1B1 and 2A to 2B1 L L L H 1A to 1B2 and 2A to 2B2 L L H L 1A to 1B3 and 2A to 2B3 L L H H 1A to 1B4 and 2A to 2B4 Disconnect 1A and 2A Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCDS018O − MAY 1995 − REVISED JANUARY 2004 logic diagram (positive logic) 1A 6 7 1B1 5 1B2 4 1B3 3 1B4 2A 10 9 2B1 11 2B2 12 2B3 13 2B4 14 S0 2 S1 1 1OE 15 2OE absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W (see Note 2): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W (see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W (see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 3. The package thermal impedance is calculated in accordance with JESD 51-5. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCDS018O − MAY 1995 − REVISED JANUARY 2004 recommended operating conditions (see Note 4) MIN MAX 5.5 VCC VIH Supply voltage 4 High-level control input voltage 2 VIL TA Low-level control input voltage Operating free-air temperature −40 UNIT V V 0.8 V 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK II TEST CONDITIONS VCC = 4.5 V, VCC = 5 V, II = −18 mA VI = 5.5 V or GND IO = 0, One input at 3.4 V, ICC ∆ICC‡ Control inputs VCC = 5.5 V, VCC = 5.5 V, Ci Control inputs VI = 3 V or 0 MIN VI = VCC or GND Other inputs at VCC or GND B port ron§ MAX UNIT −1.2 V ±1 µA 3 µA 2.5 mA 3.5 A port Cio(OFF) TYP† pF 10 VO = 3 V or 0, OE = VCC VCC = 4.5 V pF 4 II = 64 mA II = 30 mA 5 VI = 0 5 7 7 VI = 2.4 V, II = 15 mA 10 15 Ω † All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. ‡ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. § Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined by the lower voltage of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) VCC = 4 V VCC = 5 V ± 0.5 V MIN MIN FROM (INPUT) TO (OUTPUT) tpd¶ A or B B or A 0.35 tpd S A or B 6.6 7.1 PARAMETER S ten OE A or B S tdis MAX UNIT MAX 0.25 ns 1.6 6.2 ns 1.3 6.3 7.3 1.4 6.4 7.9 1.1 7.4 7.3 2.3 7 A or B OE ns ns ¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCDS018O − MAY 1995 − REVISED JANUARY 2004 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test S1 7V Open TEST tpd tPLZ/tPZL tPHZ/tPZH GND CL = 50 pF (see Note A) 500 Ω 3V Output Control (low-level enabling) LOAD CIRCUIT 1.5 V 3V 1.5 V 1.5 V 0V tPLH tPLZ Output 1.5 V 1.5 V Output Waveform 1 S1 at 7 V (see Note B) 3.5 V 1.5 V VOH VOL Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOL + 0.3 V VOL tPHZ tPZH tPHL 1.5 V 0V tPZL Input S1 Open 7V Open 1.5 V VOH VOH − 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74CBT3253D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) TBD Lead/Ball Finish CU NIPDAU Level-1-260C-UNLIM SN74CBT3253DBLE OBSOLETE SSOP DB 16 SN74CBT3253DBQR ACTIVE SSOP/ QSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR SN74CBT3253DBQRE4 ACTIVE SSOP/ QSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR SN74CBT3253DBQRG4 ACTIVE SSOP/ QSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR SN74CBT3253DBR ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3253DBRE4 ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3253DE4 ACTIVE SOIC D 16 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3253DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3253DRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3253PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3253PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3253PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3253PWLE OBSOLETE TSSOP PW 16 TBD Call TI SN74CBT3253PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3253PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3253PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3253RGYR ACTIVE QFN RGY 16 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR SN74CBT3253RGYRG4 ACTIVE QFN RGY 16 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR 40 Call TI MSL Peak Temp (3) Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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