SN74CBTLV16800 LOW-VOLTAGE 20-BIT FET BUS SWITCH WITH PRECHARGED OUTPUTS www.ti.com SCDS045J – DECEMBER 1997 – REVISED MARCH 2005 FEATURES • • • • • • • DGG, DGV, OR DL PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus™ Family 5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation B-Port Outputs Are Precharged by Bias Voltage to Minimize Signal Distortion During Live Insertion Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) BIASV 1A1 1A2 1A3 1A4 1A5 1A6 GND 1A7 1A8 1A9 1A10 2A1 2A2 VCC 2A3 GND 2A4 2A5 2A6 2A7 2A8 2A9 2A10 DESCRIPTION/ORDERING INFORMATION The SN74CBTLV16800 provides 20 bits of high-speed bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The device also precharges the B port to a user-selectable bias voltage (BIASV) to minimize live-insertion noise. The device is organized as dual 10-bit bus switches with separate output-enable (OE) inputs. It can be used as two 10-bit bus switches or one 20-bit bus switch. When OE is low, the associated 10-bit bus switch is on, and port A is connected to port B. When OE is high, the switch is open, the high-impedance state exists between the two ports, and port B is precharged to BIASV through the equivalent of a 10-kΩ resistor. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 2OE 1B1 1B2 1B3 1B4 1B5 GND 1B6 1B7 1B8 1B9 1B10 2B1 2B2 2B3 GND 2B4 2B5 2B6 2B7 2B8 2B9 2B10 <br/> This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION PACKAGE (1) TA (1) TOP-SIDE MARKING SN74CBTLV16800DL Tape and reel SN74CBTLV16800DLR TSSOP – DGG Tape and reel SN74CBTLV16800GR CBTLV16800 TVSOP – DGV Tape and reel SN74CBTLV16800VR CN800 SSOP – DL –40°C to 85°C ORDERABLE PART NUMBER Tube CBTLV16800 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1997–2005, Texas Instruments Incorporated SN74CBTLV16800 LOW-VOLTAGE 20-BIT FET BUS SWITCH WITH PRECHARGED OUTPUTS www.ti.com SCDS045J – DECEMBER 1997 – REVISED MARCH 2005 FUNCTION TABLE (EACH 10-BIT BUS SWITCH) INPUT OE FUNCTION L A port = B port H A port = Z B port = BIASV LOGIC DIAGRAM (POSITIVE LOGIC) 1 2 BIASV 46 1A1 SW 12 1B1 36 SW 1A10 1B10 48 1OE 35 13 SW 2A1 24 2B1 25 SW 2A10 2B10 47 2OE SIMPLIFIED SCHEMATIC, EACH FET SWITCH A B (OE) 2 SN74CBTLV16800 LOW-VOLTAGE 20-BIT FET BUS SWITCH WITH PRECHARGED OUTPUTS www.ti.com SCDS045J – DECEMBER 1997 – REVISED MARCH 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 4.6 V BIASV Bias voltage range –0.5 4.6 V VI Input voltage range (2) –0.5 Continuous channel current IIK Input clamp current θJA Package thermal impedance (3) Tstg (1) (2) (3) VI < 0 4.6 V 128 mA –50 mA DGG package 70 DGV package 58 DL package 63 Storage temperature range –65 UNIT 150 °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) MIN MAX UNIT VCC Supply voltage 2.3 3.6 V BIASV Bias voltage 1.3 VCC V VIH High-level control input voltage VIL Low-level control input voltage TA Operating free-air temperature (1) VCC = 2.3 V to 2.7 V 1.7 VCC = 2.7 V to 3.6 V 2 V VCC = 2.3 V to 2.7 V 0.7 VCC = 2.7 V to 3.6 V 0.8 –40 85 V °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 3 SN74CBTLV16800 LOW-VOLTAGE 20-BIT FET BUS SWITCH WITH PRECHARGED OUTPUTS www.ti.com SCDS045J – DECEMBER 1997 – REVISED MARCH 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER MIN TYP (1) TEST CONDITIONS VIK VCC = 3 V, II = –18 mA II VCC = 3.6 V, VI = VCC or GND VCC = 0, VI or VO = 0 to 3.6 V VCC = 3 V, BIASV = 2.4 V, VO= 0, VCC = 3.6 V, IO = 0, VI = VCC or GND Control inputs VCC = 3.6 V, One input at 3 V, Other inputs at VCC or GND Control inputs VI = 3 V or 0 Ioff A port IO ICC ∆ICC (2) Ci Cio(OFF) VO = 3 V or 0, Switch off, VCC = 2.3 V, TYP at VCC = 2.5 V VI = 0 ron (3) VCC = 3 V VI = 1.7 V, VI = 0 VI = 2.4 V, (1) (2) (3) MAX V ±1 µA 10 OE = VCC 0.25 BIASV = Open UNIT –1.2 µA mA 10 µA 300 µA 4.5 pF 6.5 pF II = 64 mA 5 II = 24 mA 5 9 9 II = 15 mA 25 35 II = 64 mA 5 7 II = 24 mA 5 7 II = 15 mA 8 15 Ω All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND. Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER TEST CONDITIONS tpd (1) (1) 4 tPZH BIASV = GND tPZL BIASV = 3 V tPHZ BIASV = GND tPLZ BIASV = 3 V FROM (INPUT) TO (OUTPUT) A or B B or A OE A or B OE A or B VCC = 2.5 V ± 0.2 V MIN MAX VCC = 3.3 V ± 0.3 V MIN 0.15 UNIT MAX 0.25 2.9 7.7 2.2 5.5 2.8 6.4 2.1 5.3 1.4 6.8 2.6 7.6 1.3 4.2 1.5 5.1 The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). ns ns ns SN74CBTLV16800 LOW-VOLTAGE 20-BIT FET BUS SWITCH WITH PRECHARGED OUTPUTS www.ti.com SCDS045J – DECEMBER 1997 – REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 RL From Output Under Test Open GND CL (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND RL LOAD CIRCUIT VCC CL RL V∆ 2.5 V ± 0.2 V 3.3 V ± 0.3 V 30 pF 50 pF 500 Ω 500 Ω 0.15 V 0.3 V VCC Timing Input VCC/2 0V tw tsu VCC VCC/2 Input VCC/2 th VCC VCC/2 Data Input VCC/2 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC/2 Input VCC/2 0V tPHL tPLH VOH VCC/2 Output VCC/2 VOL tPHL Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH VOH Output VCC/2 VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VCC Output Control Output Waveform 2 S1 at GND (see Note B) VCC/2 VCC/2 0V tPZL tPLZ VCC VCC/2 tPZH VOL + V∆ VOL tPHZ VCC/2 VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 5 PACKAGE OPTION ADDENDUM www.ti.com 27-Sep-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74CBTLV16800DLG4 ACTIVE SSOP DL 48 74CBTLV16800DLRG4 ACTIVE SSOP DL 74CBTLV16800GRE4 ACTIVE TSSOP 74CBTLV16800GRG4 ACTIVE 74CBTLV16800VRE4 25 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74CBTLV16800VRG4 ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBTLV16800DL ACTIVE SSOP DL 48 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBTLV16800DLR ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBTLV16800GR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBTLV16800VR ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 25 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74CBTLV16800DLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 SN74CBTLV16800GR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1 SN74CBTLV16800VR TVSOP DGV 48 2000 330.0 24.4 6.8 10.1 1.6 12.0 24.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74CBTLV16800DLR SSOP DL 48 1000 346.0 346.0 49.0 SN74CBTLV16800GR TSSOP DGG 48 2000 346.0 346.0 41.0 SN74CBTLV16800VR TVSOP DGV 48 2000 346.0 346.0 41.0 Pack Materials-Page 2 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. 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