SN54LVT162245A,, SN74LVT162245A 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS www.ti.com FEATURES • • • • • • • • • • Members of the Texas Instruments Widebus™ Family A-Port Outputs Have Equivalent 22-Ω Series Resistors, So No External Resistors Are Required Supprt Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Ioff and Power-Up 3-State Support Hot Insertion Distributed VCC and GND Pins Minimize High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) SCBS714D – FEBRUARY 2000 – REVISED NOVEMBER 2006 SN54LVT162245A . . . WD PACKAGE SN74LVT162245A . . . DGG OR DL PACKAGE (TOP VIEW) 1DIR 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCC 2B5 2B6 GND 2B7 2B8 2DIR 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OE DESCRIPTION/ORDERING INFORMATION The 'LVT162245A devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ. The A-port outputs, which are designed to source or sink up to 12 mA, include equivalent 22-Ω series resistors to reduce overshoot and undershoot. When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2006, Texas Instruments Incorporated SN54LVT162245A,, SN74LVT162245A 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS www.ti.com SCBS714D – FEBRUARY 2000 – REVISED NOVEMBER 2006 ORDERING INFORMATION PACKAGE (1) TA FBGA – GRD FBGA – ZRD (Pb-free) Reel of 1000 Tube of 25 SSOP – DL –40°C to 85°C Reel of 1000 TSSOP – DGG VFBGA – GQL VFBGA – ZQL (Pb-free) –55°C to 125°C (1) (2) CFP – WD Reel of 2000 Reel of 1000 Tube ORDERABLE PART NUMBER SN74LVT162245AGRDR TOP-SIDE MARKING LZ245A SN74LVT162245AZRDR SN74LVT162245ADL SN74LVT162245ADLG4 LVT162245A SN74LVT162245ADLR 74LVT162245ADLRG4 SN74LVT162245ADGGR LVT162245A 74LVT162245ADGGRE4 SN74LVT162245AGQLR LZ245A SN74LVT162245AZQLR SNJ54LVT162245AWD (2) SNJ54LVT162245AWD Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Product preview GQL OR ZQL PACKAGE (TOP VIEW) TERMINAL ASSIGNMENTS (1) (56-Ball GQL/ZQL Package) 1 2 3 4 5 6 A B C D E F G H J K 1 2 3 4 5 6 A 1DIR NC NC NC NC 1OE B 1B2 1B1 GND GND 1A1 1A2 C 1B4 1B3 VCC VCC 1A3 1A4 D 1B6 1B5 GND GND 1A5 1A6 E 1B8 1B7 1A7 1A8 F 2B1 2B2 2A2 2A1 G 2B3 2B4 GND GND 2A4 2A3 H 2B5 2B6 VCC VCC 2A6 2A5 J 2B7 2B8 GND GND 2A8 2A7 K 2DIR NC NC NC NC 2OE xxx (1) xxx NC – No internal connection GRD OR ZRD PACKAGE (TOP VIEW) 1 2 3 4 5 6 TERMINAL ASSIGNMENTS (1) (54-Ball GRD/ZRD Package) A B 1 2 3 4 5 6 A 1B1 NC 1DIR 1OE NC 1A1 B 1B3 1B2 NC NC 1A2 1A3 C 1B5 1B4 VCC VCC 1A4 1A5 C D 1B7 1B6 GND GND 1A6 1A7 D E 2B1 1B8 GND GND 1A8 2A1 F 2B3 2B2 GND GND 2A2 2A3 G 2B5 2B4 VCC VCC 2A4 2A5 H 2B7 2B6 NC NC 2A6 2A7 J 2B8 NC 2DIR 2OE NC 2A8 E F G H J (1) 2 NC – No internal connection Submit Documentation Feedback SN54LVT162245A,, SN74LVT162245A 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS www.ti.com SCBS714D – FEBRUARY 2000 – REVISED NOVEMBER 2006 FUNCTION TABLE (1) (EACH 8-BIT SECTION) CONTROL INPUTS (1) OUTPUT CIRCUITS OPERATION OE DIR A PORT B PORT L L Enabled Hi-Z B data to A bus L H Hi-Z Enabled A data to B bus H X Hi-Z Hi-Z Isolation Input circuits of the data I/Os always are active. LOGIC DIAGRAM (POSITIVE LOGIC) 1DIR 1 2DIR 48 1A1 25 1OE 47 2A1 2 24 2OE 36 13 1B1 2B1 To Seven Other Channels To Seven Other Channels Submit Documentation Feedback 3 SN54LVT162245A,, SN74LVT162245A 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS www.ti.com SCBS714D – FEBRUARY 2000 – REVISED NOVEMBER 2006 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 4.6 V VI Input voltage range (2) –0.5 7 V –0.5 7 V –0.5 VCC + 0.5 V VO Voltage range applied to any output in the high-impedance or power-off VO Voltage range applied to any output in the high state (2) IO Current into any output in the low state IO Current into any output in the high state (3) state (2) SN54LVT162245A (B port) 96 SN74LVT162245A (B port) 128 A port 30 SN54LVT162245A (B port) 48 SN74LVT162245A (B port) 64 A port 30 UNIT mA mA IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA θJA Package thermal impedance (4) Tstg Storage temperature range DGG package 70 DL package 63 GQL/ZQL package 42 GRD/ZRD package (1) (2) (3) (4) °C/W 36 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This current flows only when the output is in the high state and VO > VCC. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) SN54LVT162245A (2) MAX MIN MAX 2.7 3.6 2.7 3.6 UNIT VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage 0.8 0.8 V VI Input voltage 5.5 5.5 V IOH High-level output current A port –12 –12 B port –24 –32 IOL Low-level output current A port 12 12 B port 48 64 ∆t/∆v Input transition rise or fall rate 2 Outputs enabled 200 TA –55 (2) Operating free-air temperature 2 10 ∆t/∆VCC Power-up ramp rate (1) 4 SN74LVT162245A MIN V 10 –40 mA mA ns/V µs/V 200 125 V 85 °C All unused or driven (floating) data inputs (I/Os) of the device must be held at logic HIGH or LOW (preferably VCCI or GND) to ensure proper device operation and minimize power. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Product preview Submit Documentation Feedback SN54LVT162245A,, SN74LVT162245A 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS www.ti.com SCBS714D – FEBRUARY 2000 – REVISED NOVEMBER 2006 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK A port VOH B port MIN TYP (2) SN54LVT162245A MAX MIN TYP (2) VCC = 2.7 V, II = –18 mA VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC – 0.2 VCC = 3 V, IOH = –12 mA 2 2 VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC – 0.2 VCC – 0.2 VCC = 2.7 V, IOH = –8 mA 2.4 2.4 VCC = 3 V A port SN54LVT162245A (1) TEST CONDITIONS IOH = –24 mA –1.2 –1.2 2 IOH = –32 mA 2 IOL = 100 µA 0.2 0.2 IOL = 12 mA 0.8 0.8 IOL = 100 µA 0.2 0.2 IOL = 24 mA 0.5 0.5 IOL = 16 mA 0.4 0.4 IOL = 32 mA 0.5 0.5 IOL = 48 mA 0.55 B port VCC = 3 V IOL = 64 mA II A or B port (3) VI = VCC or GND ±1 ±1 VCC = 0 or 3.6 V, VI = 5.5 V 10 10 VI = 5.5 V 20 20 5 5 VI = VCC VI = 0 –10 Ioff VCC = 0, IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don't care IOZPD VCC = 1.5 to 0 V, VO = 0.5 V to 3 V, OE = don't care ICC VCC = 3.6 V, IO = 0, VI = VCC or GND V 0.55 VCC = 3.6 V, VCC = 3.6 V V V VCC = 3 V, VOL UNIT VCC – 0.2 VCC = 2.7 V to 3.6 V, VCC = 2.7 V Control inputs MAX –10 ±100 µA ±100 (4) ±100 µA ±100 (4) ±100 µA 0.19 0.19 VI or VO = 0 to 4.5 V Outputs high Outputs low Outputs disabled µA 5 5 0.19 0.19 0.3 0.2 mA ∆ICC (5) VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = 3 V or 0 4 4 pF Cio VO = 3 V or 0 10 10 pF (1) (2) (3) (4) (5) mA Product preview All typical values are at VCC = 3.3 V, TA = 25°C. Unused pins at VCC or GND On products compliant to MIL-PRF-38535, this parameter is not production tested. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. Submit Documentation Feedback 5 SN54LVT162245A,, SN74LVT162245A 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS www.ti.com SCBS714D – FEBRUARY 2000 – REVISED NOVEMBER 2006 Switching Characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54LVT162245A (1) PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ (1) (2) 6 FROM (INPUT) TO (OUTPUT) A B B A OE B OE A OE B OE A VCC = 3.3 V ± 0.3 V SN74LVT162245A VCC = 3.3 V ± 0.3 V VCC = 2.7 V MIN MAX VCC = 2.7 V MIN TYP (2) MAX MIN MAX 1 3.5 4 1 2.3 3.3 3.7 1 3.5 3.9 1 2.2 3.3 3.5 1 4.3 5.3 1 2.8 4 4.6 1 4.2 4.5 1 2.5 3.4 3.6 1 4.8 5.9 1 2.8 4.6 5.4 1 4.8 5.5 1 3 4.6 5.2 1 5.5 7.2 1 3.3 5.3 6.3 1 5.4 6.4 1 3.3 5.1 5.8 1.5 5.5 5.8 1.5 3.8 5.2 5.5 1.5 5.5 5.8 1.5 3.5 5.1 5.4 1.5 5.8 6.5 1.5 4 5.6 5.9 1.2 6.3 6.3 1.5 3.8 5.5 5.5 tsk(LH) 0.5 tsk(HL) 0.5 Product preview All typical values are at VCC = 3.3 V, TA = 25°C. Submit Documentation Feedback UNIT MIN MAX ns ns ns ns ns ns ns SN54LVT162245A,, SN74LVT162245A 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS www.ti.com SCBS714D – FEBRUARY 2000 – REVISED NOVEMBER 2006 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test 6V Open S1 GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 2.7 V 1.5 V Input 1.5 V th 2.7 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V Input 1.5 V 0V tPLH tPHL VOH 1.5 V Output 1.5 V VOL tPHL Output Waveform 1 S1 at 6 V (see Note B) 1.5 V 1.5 V 1.5 V VOL tPZL tPLZ 3V 1.5 V Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V tPZH tPLH VOH Output 2.7 V Output Control VOL + 0.3 V VOL tPHZ 1.5 V VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms Submit Documentation Feedback 7 PACKAGE OPTION ADDENDUM www.ti.com 27-Sep-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74LVT162245ADGGRE4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVT162245ADGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVT162245ADLRG4 ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT162245ADGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT162245ADL ACTIVE SSOP DL 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT162245ADLG4 ACTIVE SSOP DL 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT162245ADLR ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT162245AGQLR NRND BGA MI CROSTA R JUNI OR GQL 56 1000 TBD SNPB Level-1-240C-UNLIM SN74LVT162245AGRDR ACTIVE BGA MI CROSTA R JUNI OR GRD 54 1000 TBD SNPB Level-1-240C-UNLIM SN74LVT162245AZQLR ACTIVE BGA MI CROSTA R JUNI OR ZQL 56 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM SN74LVT162245AZRDR ACTIVE BGA MI CROSTA R JUNI OR ZRD 54 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 27-Sep-2007 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN74LVT162245ADGGR TSSOP SN74LVT162245ADLR SSOP SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1.8 12.0 24.0 Q1 DGG 48 2000 330.0 24.4 8.6 15.8 DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 SN74LVT162245AGQLR BGA MI CROSTA R JUNI OR GQL 56 1000 330.0 16.4 4.8 7.3 1.45 8.0 16.0 Q1 SN74LVT162245AGRDR BGA MI CROSTA R JUNI OR GRD 54 1000 330.0 16.4 5.8 8.3 1.55 8.0 16.0 Q1 SN74LVT162245AZQLR BGA MI CROSTA R JUNI OR ZQL 56 1000 330.0 16.4 4.8 7.3 1.45 8.0 16.0 Q1 SN74LVT162245AZRDR BGA MI CROSTA R JUNI OR ZRD 54 1000 330.0 16.4 5.8 8.3 1.55 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVT162245ADGGR TSSOP DGG 48 2000 346.0 346.0 41.0 SN74LVT162245ADLR SSOP DL 48 1000 346.0 346.0 49.0 SN74LVT162245AGQLR BGA MICROSTAR JUNIOR GQL 56 1000 346.0 346.0 33.0 SN74LVT162245AGRDR BGA MICROSTAR JUNIOR GRD 54 1000 346.0 346.0 33.0 SN74LVT162245AZQLR BGA MICROSTAR JUNIOR ZQL 56 1000 346.0 346.0 33.0 SN74LVT162245AZRDR BGA MICROSTAR JUNIOR ZRD 54 1000 346.0 346.0 33.0 Pack Materials-Page 2 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. 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