SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP (Output Ground Bounce) D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Voltage Operation on All Ports SN54LV00A . . . J OR W PACKAGE SN74LV00A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y 2A 2B 2Y 14 1B 1A NC VCC 4B 1 2 13 4B 3 12 4A 4 11 4Y 5 10 3B 9 3A 6 7 8 SN54LV00A . . . FK PACKAGE (TOP VIEW) 1Y NC 2A NC 2B 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3B 2Y GND NC 3Y 3A 14 2 VCC 1 SN74LV00A . . . RGY PACKAGE (TOP VIEW) 3Y 1A 1B 1Y 2A 2B 2Y GND D 1A D Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) GND D D Ioff Supports Partial-Power-Down Mode NC − No internal connection description/ordering information These quadruple 2-input positive-NAND gates are designed for 2-V to 5.5-V VCC operation. The ’LV00A devices perform the Boolean function Y = A • B or Y = A + B in positive logic. ORDERING INFORMATION QFN − RGY SN74LV00ARGYR Tube of 50 SN74LV00AD Reel of 2500 SN74LV00ADR SOP − NS Reel of 2000 SN74LV00ANSR 74LV00A SSOP − DB Reel of 2000 SN74LV00ADBR LV00A Tube of 90 SN74LV00APW Reel of 2000 SN74LV00APWR Reel of 250 SN74LV00APWT TVSOP − DGV Reel of 2000 SN74LV00ADGVR LV00A CDIP − J Tube of 25 SNJ54LV00AJ SNJ54LV00AJ CFP − W Tube of 150 SNJ54LV00AW SNJ54LV00AW LCCC - FK Tube of 55 SNJ54LV00AFK SNJ54LV00AFK TSSOP − PW −55°C to 125°C † TOP-SIDE MARKING Reel of 1000 SOIC − D −40°C 40 C to 85°C 85 C ORDERABLE PART NUMBER PACKAGE† TA LV00A LV00A LV00A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2005, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 description/ordering information (continued) These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. FUNCTION TABLE (each gate) INPUTS OUTPUT Y A B H H L L X H X L H logic diagram, each gate (positive logic) A Y B absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W (see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W (see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W (see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 recommended operating conditions (see Note 5) SN54LV00A VCC MIN MAX 2 5.5 Supply voltage VCC = 2 V VIH High level input voltage High-level 1.5 Low level input voltage Low-level VI Input voltage VO Output voltage VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7 Input transition rise or fall rate TA Operating free-air temperature V V 0.5 0.5 VCC × 0.3 VCC × 0.3 VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 0 5.5 0 VCC 0 VCC = 3 V to 3.6 V VCC V −50 μA −2 −2 −6 −6 −12 50 50 VCC = 2.3 V to 2.7 V 2 2 VCC = 3 V to 3.6 V 6 6 VCC = 4.5 V to 5.5 V 12 12 VCC = 2.3 V to 2.7 V 200 200 VCC = 3 V to 3.6 V 100 100 20 −55 V −50 −12 VCC = 4.5 V to 5.5 V V VCC × 0.3 0 VCC = 2 V Δt/Δv UNIT VCC = 2.3 V to 2.7 V VCC = 2.3 V to 2.7 V Low level output current Low-level 5.5 VCC × 0.7 VCC = 4.5 V to 5.5 V IOL 2 VCC = 3 V to 3.6 V VCC = 2 V High level output current High-level MAX VCC = 2.3 V to 2.7 V VCC = 4.5 V to 5.5 V IOH MIN 1.5 VCC = 2 V VIL SN74LV00A 125 mA μA mA ns/V 20 −40 °C 85 NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LV00A PARAMETER VOH TEST CONDITIONS MIN TYP SN74LV00A MAX MIN IOH = −50 μA 2 V to 5.5 V IOH = −2 mA 2.3 V 2 2 IOH = −6 mA 3V 2.48 2.48 4.5 V 3.8 IOH = −12 mA VOL VCC VCC−0.1 TYP MAX VCC−0.1 V 3.8 IOL = 50 μA 2 V to 5.5 V 0.1 0.1 IOL = 2 mA 2.3 V 0.4 0.4 IOL = 6 mA 3V 0.44 0.44 4.5 V IOL = 12 mA II VI = 5.5 V or GND ICC VI = VCC or GND, Ioff VI or VO = 0 to 5.5 V Ci VI = VCC or GND IO = 0 UNIT V 0.55 0.55 0 to 5.5 V ±1 ±1 μA 5.5 V 20 20 μA 0 5 5 μA 3.3 V 3.3 3.3 5V 3.3 3.3 pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 switching characteristics over recommended operating VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tpdd A Y LOAD CAPACITANCE free-air TA = 25°C MIN temperature SN54LV00A range, SN74LV00A TYP MAX MIN MAX MIN MAX CL = 15 pF 7.1* 12.9* 1* 16* 1 15 CL = 50 pF 9.6 16.6 1 21 1 20 UNIT ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tpdd A Y LOAD CAPACITANCE free-air TA = 25°C MIN TYP temperature SN54LV00A range, SN74LV00A MAX MIN MAX MIN MAX CL = 15 pF 5* 7.9* 1* 10.5* 1 9.5 CL = 50 pF 6.9 11.4 1 14 1 13 UNIT ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tpdd A Y LOAD CAPACITANCE free-air TA = 25°C MIN temperature SN54LV00A range, SN74LV00A TYP MAX MIN MAX MIN MAX CL = 15 pF 3.6* 5.5* 1* 7.5* 1 6.5 CL = 50 pF 4.9 7.5 1 9.5 1 8.5 UNIT ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 6) SN74LV00A PARAMETER MIN TYP MAX UNIT VOL(P) Quiet output, maximum dynamic VOL 0.2 0.8 V VOL(V) Quiet output, minimum dynamic VOL −0.1 −0.8 V VOH(V) Quiet output, minimum dynamic VOH VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage 3.1 V 2.31 V 0.99 V VCC TYP UNIT 3.3 V 9.5 5V 11 NOTE 6: Characteristics are for surface-mount packages only. operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF, pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 10 MHz pF SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test Test Point RL = 1 kΩ From Output Under Test CL (see Note A) S1 Open TEST GND S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain CL (see Note A) Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC tPLH tPHL 50% VCC tPHL 50% VCC VOL VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 0V Output Waveform 1 S1 at VCC (see Note B) tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC 50% VCC tPZL VOH In-Phase Output Out-of-Phase Output 0V VCC Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd . H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 21-Dec-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LV00AD ACTIVE SOIC D 14 SN74LV00ADBLE OBSOLETE SSOP DB 14 SN74LV00ADBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV00ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV00ADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV00ADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV00ADGVR ACTIVE TVSOP DGV 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV00ADGVRE4 ACTIVE TVSOP DGV 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV00ADGVRG4 ACTIVE TVSOP DGV 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV00ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV00ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV00ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV00ANSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV00ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV00APW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV00APWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV00APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV00APWLE OBSOLETE TSSOP PW 14 SN74LV00APWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV00APWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV00APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV00APWT ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV00APWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV00APWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV00ARGYR ACTIVE VQFN RGY 14 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN74LV00ARGYRG4 ACTIVE VQFN RGY 14 3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR 50 Green (RoHS & no Sb/Br) TBD TBD Addendum-Page 1 Lead/Ball Finish CU NIPDAU Call TI Call TI MSL Peak Temp (3) Level-1-260C-UNLIM Call TI Call TI PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 21-Dec-2009 Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 21-Dec-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LV00ADBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74LV00ADGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74LV00ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LV00ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74LV00APWR TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 SN74LV00ARGYR VQFN RGY 14 3000 180.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 21-Dec-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV00ADBR SSOP DB 14 2000 346.0 346.0 33.0 SN74LV00ADGVR TVSOP DGV 14 2000 346.0 346.0 29.0 SN74LV00ADR SOIC D 14 2500 346.0 346.0 33.0 SN74LV00ANSR SO NS 14 2000 346.0 346.0 33.0 SN74LV00APWR TSSOP PW 14 2000 346.0 346.0 29.0 SN74LV00ARGYR VQFN RGY 14 3000 190.5 212.7 31.8 Pack Materials-Page 2 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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