SCES124L − DECEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP (Output Ground Bounce) 2 14 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y 1A 1Y 2OE 2A 2Y 14 1A 1OE NC VCC 4OE 1 2 13 4OE 3 12 4A 4 11 4Y 5 10 3OE 9 3A 6 7 8 SN54LV125A . . . FK PACKAGE (TOP VIEW) 1Y NC 2OE NC 2A 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3OE 2Y GND NC 3Y 3A 1 VCC 1OE 1A 1Y 2OE 2A 2Y GND Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) SN74LV125A . . . RGY PACKAGE (TOP VIEW) 3Y SN54LV125A . . . J OR W PACKAGE SN74LV125A . . . D, DB, DGV, N, NS, OR PW PACKAGE (TOP VIEW) D 1OE D D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Voltage Operation on All Ports GND D D Ioff Supports Partial-Power-Down Mode NC − No internal connection description/ordering information The ‘LV125A quadruple bus buffer gates are designed for 2-V to 5.5-V VCC operation. These devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. ORDERING INFORMATION Tube of 25 SN74LV125AN SN74LV125AN QFN − RGY Reel of 1000 SN74LV125ARGYR LV125A Tube of 50 SN74LV125AD Reel of 2500 SN74LV125ADR SOP − NS Reel of 2000 SN74LV125ANSR 74LV125A SSOP − DB Reel of 2000 SN74LV125ADBR LV125A Tube of 90 SN74LV125APW Reel of 2000 SN74LV125APWR Reel of 250 SN74LV125APWT TVSOP − DGV Reel of 2000 SN74LV125ADGVR LV125A CDIP − J Tube of 25 SNJ54LV125AJ SNJ54LV125AJ CFP − W Tube of 150 SNJ54LV125AW SNJ54LV125AW LCCC − FK Tube of 55 SNJ54LV125AFK TSSOP − PW −55°C −55 C to 125 125°C C TOP-SIDE MARKING PDIP − N SOIC − D −40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA LV125A LV125A SNJ54LV125AFK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2005, Texas Instruments Incorporated !"#$%&' #"'(' ) '*"+%("' #$++&' ( "* ,$-.#("' !(&/ +"!$# #"'*"+% " ,&#*#("' ,&+ & &+% "* &0( '+$%&' ('!(+! 1(++('2/ +"!$#"' ,+"#&'3 !"& '" '&#&(+.2 '#.$!& &'3 "* (.. ,(+(%&&+/ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCES124L − DECEMBER 1997 − REVISED APRIL 2005 description/ordering information (continued) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. FUNCTION TABLE (each buffer) INPUTS OE A OUTPUT Y L H H L L L H X Z logic diagram (positive logic) 1OE 1A 1 2 3OE 3 1Y 3A 9 3Y 4OE 5 6 2Y 4A 12 Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages. 2 8 13 4 2OE 2A 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 4Y SCES124L − DECEMBER 1997 − REVISED APRIL 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W (see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W (see Note 3): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W (see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W (see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCES124L − DECEMBER 1997 − REVISED APRIL 2005 recommended operating conditions (see Note 5) SN54LV125A VCC VIH Supply voltage High-level input voltage VIL Low-level input voltage VI Input voltage VO Output voltage IOH IOL ∆t/∆v High-level output current Low-level output current Input transition rise or fall rate VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V SN74LV125A MIN MAX 2 5.5 1.5 MIN MAX 2 5.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 0.5 0 High or low state 0 3-state 0 VCC × 0.3 5.5 VCC 5.5 V 0.5 VCC × 0.3 VCC × 0.3 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V V 1.5 VCC × 0.7 VCC × 0.7 VCC = 2 V VCC = 2.3 V to 2.7 V UNIT VCC × 0.3 VCC × 0.3 0 0 0 VCC × 0.3 5.5 V V VCC 5.5 V µA VCC = 2 V VCC = 2.3 V to 2.7 V −50 −50 −2 −2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V −8 −8 −16 −16 VCC = 2 V VCC = 2.3 V to 2.7 V 50 50 2 2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 8 8 16 16 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 200 200 100 100 VCC = 4.5 V to 5.5 V 20 20 mA µA mA ns/V TA Operating free-air temperature −55 125 −40 85 °C NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. ) '*"+%("' #"'#&+' ,+"!$# ' & *"+%(4& "+ !&3' ,(& "* !&4&.",%&'/ )(+(#&+# !(( ('! "&+ ,&#*#("' (+& !&3' 3"(./ &0( '+$%&' +&&+4& & +3 " #('3& "+ !#"''$& && ,+"!$# 1"$ '"#&/ 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCES124L − DECEMBER 1997 − REVISED APRIL 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LV125A PARAMETER VOH VOL TEST CONDITIONS IOH = −50 µA IOH = −2 mA MIN 2 V to 5.5 V IOH = −8 mA IOH = −16 mA IOL = 50 µA IOL = 2 mA IOL = 8 mA IOL = 16 mA VI = 5.5 V or GND VO = VCC or GND ICC Ioff VI = VCC or GND, IO = 0 VI or VO = 0 to 5.5 V VI = VCC or GND FROM (INPUT) TO (OUTPUT) tpd A Y ten tdis OE Y OE Y tpd A Y ten tdis OE Y OE Y 2.48 4.5 V 3.8 Y ten tdis OE Y OE Y tpd A ten tdis OE OE Y V 3.8 0.1 2.3 V 0.4 0.4 3V 0.44 0.44 4.5 V 0.55 0.55 0 to 5.5 V ±1 ±1 µA 5.5 V ±5 ±5 µA 5.5 V 20 20 µA 5 µA 0 5 3.3 V 1.6 1.6 5V 1.6 1.6 LOAD CAPACITANCE LOAD CAPACITANCE free-air TA = 25°C MIN TYP MAX MIN temperature SN54LV125A range, SN74LV125A MAX MIN MAX 13* 1* 15.5* 1 15.5 7* 13* 1* 15.5* 1 15.5 5.1* 14.*7 1* 17* 1 17 8.7 16.5 1 18.5 1 18.5 8.8 16.5 1 18.5 1 18.5 7.3 18.2 1 20.5 1 20.5 2 temperature SN54LV125A MAX MIN MAX 8* 1* 9.5* 1 9.5 4.8* 8* 1* 9.5* 1 9.5 4.1* 9.7* 1* 11.5* 1 11.5 Y 6.1 11.5 1 13 1 13 Y 6.2 11.5 1 13 1 13 5.5 13.2 1 15 1 15 CL = 15 pF CL = 50 pF tsk(o) * On products compliant to MIL-PRF-38535, this parameter is not production tested. 1.5 ns ns range, SN74LV125A MIN 4.8* UNIT 2 free-air TA = 25°C TYP MAX V pF MIN switching characteristics over recommended operating VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) A UNIT 0.1 CL = 50 pF tpd MAX 2 V to 5.5 V CL = 15 pF TO (OUTPUT) TYP 2.48 6.8* FROM (INPUT) MIN 3V tsk(o) * On products compliant to MIL-PRF-38535, this parameter is not production tested. PARAMETER MAX VCC−0.1 2 switching characteristics over recommended operating VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER SN74LV125A TYP VCC−0.1 2 2.3 V II IOZ Ci VCC UNIT ns ns 1.5 ) '*"+%("' #"'#&+' ,+"!$# ' & *"+%(4& "+ !&3' ,(& "* !&4&.",%&'/ )(+(#&+# !(( ('! "&+ ,&#*#("' (+& !&3' 3"(./ &0( '+$%&' +&&+4& & +3 " #('3& "+ !#"''$& && ,+"!$# 1"$ '"#&/ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SCES124L − DECEMBER 1997 − REVISED APRIL 2005 switching characteristics over recommended operating VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd A Y ten tdis OE Y OE tpd A ten tdis OE Y OE Y PARAMETER LOAD CAPACITANCE MIN free-air TA = 25°C TYP MAX temperature SN54LV125A range, SN74LV125A MIN MAX MIN MAX 3.4* 5.5* 1* 6.5* 1 6.5 3.4* 5.1* 1* 6* 1 6 Y 3.2* 6.8* 1* 8* 1 8 Y 4.3 7.5 1 8.5 1 8.5 4.4 7.1 1 8 1 8 4 8.8 1 10 1 10 CL = 15 pF CL = 50 pF tsk(o) * On products compliant to MIL-PRF-38535, this parameter is not production tested. 1 UNIT ns ns 1 noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 6) SN74LV125A PARAMETER MIN TYP MAX UNIT VOL(P) Quiet output, maximum dynamic VOL 0.4 0.8 V VOL(V) Quiet output, minimum dynamic VOL −0.3 −0.8 V VOH(V) Quiet output, minimum dynamic VOH VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage 3 V 2.31 V 0.99 V VCC 3.3 V TYP UNIT 5V 17.6 NOTE 6: Characteristics are for surface-mount packages only. operating characteristics, TA = 25°C PARAMETER Cpd 6 Power dissipation capacitance TEST CONDITIONS Outputs enabled POST OFFICE BOX 655303 CL = 50 pF, • DALLAS, TEXAS 75265 f = 10 MHz 15.5 pF SCES124L − DECEMBER 1997 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point VCC Open S1 TEST GND S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain CL (see Note A) CL (see Note A) Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC Input 50% VCC tPLH In-Phase Output 50% VCC VOH 50% VCC VOL VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 0V Output Waveform 1 S1 at VCC (see Note B) tPLH 50% VCC 50% VCC tPLZ tPZL tPHL tPHL Out-of-Phase Output 0V VCC Output Control ≈VCC 50% VCC tPHZ tPZH Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 21-Dec-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LV125AD ACTIVE SOIC D 14 SN74LV125ADBLE OBSOLETE SSOP DB 14 SN74LV125ADBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ADBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ADGVR ACTIVE TVSOP DGV 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ADGVRE4 ACTIVE TVSOP DGV 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ADGVRG4 ACTIVE TVSOP DGV 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125AN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74LV125ANE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74LV125ANSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125APW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125APWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125APWLE OBSOLETE TSSOP PW 14 TBD Call TI SN74LV125APWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125APWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125APWT ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125APWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM 50 Green (RoHS & no Sb/Br) TBD Addendum-Page 1 Lead/Ball Finish CU NIPDAU Call TI MSL Peak Temp (3) Level-1-260C-UNLIM Call TI Call TI PACKAGE OPTION ADDENDUM www.ti.com 21-Dec-2009 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LV125APWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ARGYR ACTIVE VQFN RGY 14 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN74LV125ARGYRG4 ACTIVE VQFN RGY 14 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 6-Aug-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LV125ADBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74LV125ADGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74LV125ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LV125ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74LV125APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV125APWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV125ARGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Aug-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV125ADBR SSOP DB 14 2000 346.0 346.0 33.0 SN74LV125ADGVR TVSOP DGV 14 2000 346.0 346.0 29.0 SN74LV125ADR SOIC D 14 2500 346.0 346.0 33.0 SN74LV125ANSR SO NS 14 2000 346.0 346.0 33.0 SN74LV125APWR TSSOP PW 14 2000 346.0 346.0 29.0 SN74LV125APWT TSSOP PW 14 250 346.0 346.0 29.0 SN74LV125ARGYR VQFN RGY 14 3000 346.0 346.0 29.0 Pack Materials-Page 2 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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