SCBS706F − AUGUST 1997 − REVISED OCTOBER 2003 D Support Mixed-Mode Signal Operation D D D D Bus Hold on Data Inputs Eliminates the (5-V Input and Output Voltages With 3.3-V VCC ) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Ioff and Power-Up 3-State Support Hot Insertion D D Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) SN54LVTH652 . . . JT OR W PACKAGE SN74LVTH652 . . . DB, DGV, DW, NS, OR PW PACKAGE (TOP VIEW) 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 OEAB SAB CLKAB NC VCC CLKBA SBA 1 VCC CLKBA SBA OEBA B1 B2 B3 B4 B5 B6 B7 B8 A1 A2 A3 NC A4 A5 A6 4 5 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 19 11 12 13 14 15 16 17 18 OEBA B1 B2 NC B3 B4 B5 A7 A8 GND NC B8 B7 B6 CLKAB SAB OEAB A1 A2 A3 A4 A5 A6 A7 A8 GND SN54LVTH652 . . . FK PACKAGE (TOP VIEW) NC − No internal connection description/ordering information These bus transceivers and registers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. ORDERING INFORMATION SN74LVTH652DW Tape and reel SN74LVTH652DWR SOP − NS Tape and reel SN74LVTH652NSR LVTH652 SSOP − DB Tape and reel SN74LVTH652DBR LXH652 Tube SN74LVTH652PW Tape and reel SN74LVTH652PWR TVSOP − DGV Tape and reel SN74LVTH652DGVR LXH652 CDIP − JT Tube SNJ54LVTH652JT SNJ54LVTH652JT CFP − W Tube SNJ54LVTH652W SNJ54LVTH652W LCCC − FK Tube SNJ54LVTH652FK TSSOP − PW −55°C −55 C to 125 125°C C TOP-SIDE MARKING Tube SOIC − DW −40°C −40 C to 85 85°C C ORDERABLE PART NUMBER PACKAGE† TA LVTH652 LXH652 SNJ54LVTH652FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated !"#$%&' #"'(' ')"*%("' #$**&' ( ") +$,-#("' !(& *"!$# #"')"*% " +&#)#("' +&* & &*% ") &.( '*$%&' ('!(*! /(**('0 *"!$#"' +*"#&'1 !"& '" '&#&(*-0 '#-$!& &'1 ") (-+(*(%&&* POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCBS706F − AUGUST 1997 − REVISED OCTOBER 2003 description/ordering information (continued) The ’LVTH652 devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between real-time and stored data. A low input selects real-time data and a high input selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ’LVTH652 devices. Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control pins. When SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input; therefore, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. FUNCTION TABLE DATA I/O† INPUTS OPERATION OR FUNCTION OEAB OEBA CLKAB CLKBA SAB SBA A1−A8 B1−B8 L H H or L H or L X X Input Input Isolation L H ↑ ↑ X X Input H ↑ H or L X Input H H ↑ ↑ X X‡ Input Unspecified‡ Store A and B data X X Input Output Store A in both registers L X H or L ↑ X Unspecified‡ Input Hold A, store B L L ↑ ↑ X X X‡ Output Input Store B in both registers L L X X X L Output Input Real-time B data to A bus L L X H or L X H Output Input Stored B data to A bus H H X X L X Input Output Real-time A data to B bus H H H or L X H X Input Output Stored A data to B bus Output Stored A data to B bus and stored B data to A bus H L H or L H or L H H Output Store A, hold B † The data-output functions can be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions always are enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs. ‡ Select control = L; clocks can occur simultaneously. Select control = H; clocks must be staggered to load both registers. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 21 OEAB OEBA L L 1 23 2 CLKAB CLKBA SAB X X X BUS B BUS A BUS A BUS B SCBS706F − AUGUST 1997 − REVISED OCTOBER 2003 22 SBA L 3 21 OEAB OEBA H H 21 OEBA H X H 23 2 1 CLKAB CLKBA SAB ↑ X ↑ X ↑ ↑ X X X 2 SAB L 22 SBA X BUS B BUS A BUS A 3 OEAB X L L 23 CLKBA X REAL-TIME TRANSFER BUS A TO BUS B BUS B REAL-TIME TRANSFER BUS B TO BUS A 1 CLKAB X 22 3 21 1 23 2 22 SBA OEAB H OEBA L CLKAB CLKBA SAB SBA H or L H or L H H X X X TRANSFER STORED DATA TO A AND/OR B STORAGE FROM A, B, OR A AND B Pin numbers shown are for the DB, DGV, DW, JT, NS, PW, and W packages. Figure 1. Bus-Management Functions POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCBS706F − AUGUST 1997 − REVISED OCTOBER 2003 logic diagram (positive logic) OEBA OEAB CLKBA SBA CLKAB SAB 21 3 23 22 1 2 One of Eight Channels 1D C1 A1 4 20 1D C1 To Seven Other Channels Pin numbers shown are for the DB, DGV, DW, JT, NS, PW, and W packages. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 B1 SCBS706F − AUGUST 1997 − REVISED OCTOBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Current into any output in the low state, IO: SN54LVTH652 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74LVTH652) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2): SN54LVTH652 . . . . . . . . . . . . . . . . . . . . . . . . 8 mA SN74LVTH652 . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4) SN54LVTH652 SN74LVTH652 MIN MAX MIN MAX 2.7 3.6 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 5.5 5.5 V IOH IOL High-level output current −24 −32 mA Low-level output current 48 64 mA ∆t /∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature −55 High-level input voltage 2 2 0.8 Outputs enabled V 0.8 10 10 −40 V ns/V µs/V 200 125 V 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. ')"*%("' #"'#&*' +*"!$# ' & )"*%(2& "* !&1' +(& ") !&2&-"+%&' (*(#&*# !(( ('! "&* +&#)#("' (*& !&1' 1"(- &.( '*$%&' *&&*2& & *1 " #('1& "* !#"''$& && +*"!$# /"$ '"#& POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SCBS706F − AUGUST 1997 − REVISED OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VCC = 2.7 V, VCC = 2.7 V to 3.6 V, II = −18 mA IOH = −100 µA VCC = 2.7 V, IOH = −8 mA IOH = −24 mA VCC = 3 V VOL VCC = 3 V Ioff II(hold) A or B ports SN74LVTH652 TYP† MAX MIN −1.2 VCC−0.2 2.4 −1.2 2 0.2 0.2 IOL = 24 mA IOL = 16 mA 0.5 0.5 0.4 0.4 IOL = 32 mA IOL = 48 mA 0.5 0.5 0.55 ±1 ±1 10 20 20 VCC = 3.6 V VI = VCC VI = 0 1 1 VCC = 0, VI or VO = 0 to 4.5 V VI = 0.8 V −5 VI = 2 V VI = 0 to 3.6 V VCC = 3.6 V§ V 0.55 10 VCC = 3 V V V 2 VI = 5.5 V VI = 5.5 V VCC = 3.6 V, VCC = 0 or 3.6 V, UNIT VCC−0.2 2.4 IOL = 64 mA VI = VCC or GND II A or B ports‡ MIN IOH = −32 mA IOL = 100 µA VCC = 2.7 V Control inputs SN54LVTH652 TYP† MAX TEST CONDITIONS µA −5 ±100 75 75 −75 −75 µA µA ±500 IOZPU VCC = 0 to 1.5 V, VO = 0.5 to 3 V, OE/OE = don’t care ±100∗ ±100 µA IOZPD VCC = 1.5 V to 0, VO = 0.5 to 3 V, OE/OE = don’t care ±100∗ ±100 µA 0.19 0.19 ICC VCC = 3.6 V, IO = 0, VI = VCC or GND 5 5 0.19 0.19 0.2 0.2 Outputs high Outputs low Outputs disabled ∆ICC¶ VCC = 3 V to 3.6 V, One input at VCC − 0.6 V, Other inputs at VCC or GND Ci VI = 3 V or 0 VO = 3 V or 0 4 4 mA mA pF Cio 9 9 pF ∗ On products compliant to MIL-PRF-38535, this parameter is not production tested. † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ Unused terminals at VCC or GND § This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. ')"*%("' #"'#&*' +*"!$# ' & )"*%(2& "* !&1' +(& ") !&2&-"+%&' (*(#&*# !(( ('! "&* +&#)#("' (*& !&1' 1"(- &.( '*$%&' *&&*2& & *1 " #('1& "* !#"''$& && +*"!$# /"$ '"#& 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCBS706F − AUGUST 1997 − REVISED OCTOBER 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) SN54LVTH652 VCC = 3.3 V ± 0.3 V MIN fclock tw Clock frequency MAX SN74LVTH652 VCC = 2.7 V MIN MAX 150 Pulse duration, CLK high or low VCC = 3.3 V ± 0.3 V MIN 150 MAX VCC = 2.7 V MIN 150 3.3 3.3 3.3 Data high 1.3 1.6 1.2 1.5 Data low 1.9 2.6 1.6 2.2 1.2 1.2 0.8 0.8 tsu Setup time, A or B before CLKAB↑ or CLKBA↑ th Hold time, A or B after CLKAB↑ or CLKBA↑ MAX 150 3.3 UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 2) SN54LVTH652 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.3 V MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ MAX 150 CLKBA or CLKAB A or B A or B B or A SBA or SAB‡ A or B OEBA A OEBA A OEAB B OEAB B SN74LVTH652 VCC = 2.7 V MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN VCC = 2.7 V TYP† MAX 150 MIN MAX 150 MHz 1.7 5 5.9 1.8 3.1 4.7 5.6 1.7 5 5.9 1.8 3.1 4.7 5.6 1.2 3.7 4.3 1.3 2.3 3.5 4.1 1.2 3.7 4.3 1.3 2.4 3.5 4.1 1.4 5.2 6.3 1.5 3.1 4.9 6 1.4 5.2 6.3 1.5 3.4 4.9 6 1 5.4 6.7 1.1 2.9 5.2 6.5 1 5.4 6.7 1.1 3.1 5.2 6.5 2.2 5.9 6.5 2.3 3.5 5.5 6.1 2.2 5.9 6.3 2.3 3.7 5.5 5.9 1.2 4.9 5.9 1.3 3 4.7 5.7 1.2 4.9 5.9 1.3 3.3 4.7 5.7 1.4 5.8 7 1.5 3.6 5.6 6.7 tPLZ 1.4 5.9 6.6 1.5 3.7 5.6 † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ These parameters are measured with the internal output state of the storage register opposite that of the bus input. UNIT 6.3 ns ns ns ns ns ns ns ')"*%("' #"'#&*' +*"!$# ' & )"*%(2& "* !&1' +(& ") !&2&-"+%&' (*(#&*# !(( ('! "&* +&#)#("' (*& !&1' 1"(- &.( '*$%&' *&&*2& & *1 " #('1& "* !#"''$& && +*"!$# /"$ '"#& POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SCBS706F − AUGUST 1997 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT 1.5 V Timing Input 0V tw tsu 2.7 V Input 1.5 V 1.5 V th 2.7 V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V Input 1.5 V 0V tPHL tPLH VOH 1.5 V Output 1.5 V VOL tPLH tPHL VOH Output 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 2.7 V Output Control Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) 1.5 V 1.5 V 0V tPLZ tPZL 3V 1.5 V VOL + 0.3 V VOL tPHZ tPZH 1.5 V VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LVTH652DBLE OBSOLETE SSOP DB 24 SN74LVTH652DBR ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH652DBRE4 ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH652DBRG4 ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH652DGVR ACTIVE TVSOP DGV 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH652DGVRE4 ACTIVE TVSOP DGV 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH652DGVRG4 ACTIVE TVSOP DGV 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH652DW ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH652DWE4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH652DWG4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH652DWR ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH652DWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH652DWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH652NSR ACTIVE SO NS 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH652NSRE4 ACTIVE SO NS 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH652NSRG4 ACTIVE SO NS 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH652PW ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH652PWE4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH652PWG4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH652PWLE OBSOLETE TSSOP PW 24 SN74LVTH652PWR ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH652PWRE4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH652PWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TBD TBD (1) Lead/Ball Finish Call TI Call TI MSL Peak Temp (3) Call TI Call TI The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2007 PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2008 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVTH652DBR DB 24 SITE 41 330 16 8.2 8.8 2.5 12 16 Q1 SN74LVTH652DGVR DGV 24 SITE 41 330 12 7.0 5.6 1.6 8 12 Q1 SN74LVTH652DWR DW 24 SITE 60 330 24 10.75 15.7 2.7 12 24 Q1 SN74LVTH652NSR NS 24 SITE 41 330 24 8.2 15.4 2.5 12 24 Q1 SN74LVTH652PWR PW 24 SITE 41 330 16 6.95 8.3 1.6 8 16 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 12-Feb-2008 Package Pins Site Length (mm) Width (mm) Height (mm) SN74LVTH652DBR DB 24 SITE 41 346.0 346.0 33.0 SN74LVTH652DGVR DGV 24 SITE 41 346.0 346.0 29.0 SN74LVTH652DWR DW 24 SITE 60 346.0 346.0 41.0 SN74LVTH652NSR NS 24 SITE 41 346.0 346.0 41.0 SN74LVTH652PWR PW 24 SITE 41 346.0 346.0 33.0 Pack Materials-Page 2 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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