SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 D D D D D D D D D D D Choice of Memory Organizations – SN74V263 – 8192 × 18/16384 × 9 – SN74V273 – 16384 × 18/32768 × 9 – SN74V283 – 32768 × 18/65536 × 9 – SN74V293 – 65536 × 18/131072 × 9 166-MHz Operation 6-ns Read/Write Cycle Time User-Selectable Input and Output Port Bus Sizing – ×9 in to ×9 out – ×9 in to ×18 out – ×18 in to ×9 out – ×18 in to ×18 out Big-Endian/Little-Endian User-Selectable Byte Representation 5-V-Tolerant Inputs Fixed, Low First-Word Latency Zero-Latency Retransmit Master Reset Clears Entire FIFO Partial Reset Clears Data, but Retains Programmable Settings Empty, Full, and Half-Full Flags Signal FIFO Status D D D D D D D D D D Programmable Almost-Empty and Almost-Full Flags; Each Flag Can Default to One of Eight Preselected Offsets Selectable Synchronous/Asynchronous Timing Modes for Almost-Empty and Almost-Full Flags Program Programmable Flags by Either Serial or Parallel Means Select Standard Timing (Using EF and FF Flags) or First-Word Fall-Through (FWFT) Timing (Using OR and IR Flags) Output Enable Puts Data Outputs in High-Impedance State Easily Expandable in Depth and Width Independent Read and Write Clocks Permit Reading and Writing Simultaneously High-Performance Submicron CMOS Technology Glueless Interface With ’C6x DSPs Available in 80-Pin Thin Quad Flat Pack (TQFP) and 100-Pin Ball Grid Array (BGA) Packages description The SN74V263, SN74V273, SN74V283, and SN74V293 are exceptionally deep, high-speed, CMOS first-in first-out (FIFO) memories with clocked read and write controls and a flexible bus-matching ×9/×18 data flow. There is flexible ×9/×18 bus matching on both read and write ports. The period required by the retransmit operation is fixed and short. The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short. These FIFOs are particularly appropriate for network, video, telecommunications, data communications, and other applications that need to buffer large amounts of data and match buses of unequal sizes. Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bit or 9-bit width, as determined by the state of external control pins’ input width (IW) and output width (OW) during the master-reset cycle. The input port is controlled by write-clock (WCLK) and write-enable (WEN) inputs. Data is written into the FIFO on every rising edge of WCLK when WEN is asserted. The output port is controlled by read-clock (RCLK) and read-enable (REN) inputs. Data is read from the FIFO on every rising edge of RCLK when REN is asserted. An output-enable (OE) input is provided for 3-state control of the outputs. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 RM RCLK REN WCLK PRS MRS LD FWFT/SI FF/IR PAF OW FSEL0 HF FSEL1 BE IP VCC PAE PFM EF/OR PZA PACKAGE (TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 60 2 59 3 58 4 57 5 56 6 55 7 54 8 53 9 52 10 51 11 50 12 49 13 48 14 47 15 46 16 45 17 44 18 43 19 42 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 D7 D6 GND D5 D4 D3 D2 D1 D0 GND Q0 Q1 GND Q2 Q3 VCC Q4 Q5 GND Q6 WEN SEN DNC VCC DNC IW GND D17 VCC D16 D15 D14 D13 GND D12 D11 D10 D9 D8 VCC DNC = Do not connect 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 RT OE VCC Q17 Q16 GND GND Q15 Q14 VCC Q13 Q12 GND Q11 GND Q10 VCC Q9 Q8 Q7 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 GGM PACKAGE (TOP VIEW) 1 2 3 4 5 A WCLK PRS LD GND VCC B SEN WEN MRS FF/IR FSEL0 C DNC DNC VCC FWFT/ SI D GND IW D17 E VCC D16 F VCC G 6 BE FSEL1 7 8 9 10 VCC PFM RCLK RT PAE RM REN OE OW HF IP EF/OR VCC Q17 NC PAF GND GND Q16 GND GND D15 GND NC NC GND Q15 Q14 VCC D14 D13 GND NC NC NC VCC Q13 Q12 NC D12 D11 VCC NC Q2 GND GND GND Q11 H D10 D9 D5 D1 Q0 GND VCC VCC Q9 Q10 J D8 D7 GND D3 GND Q1 Q3 Q5 Q7 Q8 K VCC D6 D4 D2 D0 GND VCC Q4 GND Q6 DNC = Do not connect description (continued) The frequencies of both the RCLK and the WCLK signals can vary from 0 to fMAX, with complete independence. There are no restrictions on the frequency of one clock input with respect to the other. There are two possible timing modes of operation with these devices: first-word fall-through (FWFT) mode and standard mode. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. REN need not be asserted for accessing the first word. However, subsequent words written to the FIFO do require a low on REN for access. The state of the FWFT/SI input during master reset determines the timing mode in use. In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN and enabling a rising RCLK edge, shifts the word from internal memory to the data output lines. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 functional block diagram D0–Dn (×9 or ×18) LD SEN WCLK Input Register WEN Offset Register Write-Control Logic Write Pointer BE IP RAM Array 8192 × 18 or 16384 × 9 16384 × 18 or 32768 × 9 32768 × 18 or 65536 × 9 65536 × 18 or 131072 × 9 Control Logic FF/IR PAF EF/OR PAE HF FWFT/SI PFM FSEL0 FSEL1 Flag Logic Read Pointer Read-Control Logic IW OW MRS PRS Bus Configuration RT RM Output Register Reset Logic RCLK OE REN Q0–Qn (×9 or ×18) description (continued) For applications requiring more data-storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e., the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required. These FIFOs have five flag pins: empty flag or output ready (EF/OR), full flag or input ready (FF/IR), half-full flag (HF), programmable almost-empty flag (PAE), and programmable almost-full flag (PAF). The IR and OR functions are selected in FWFT mode. The EF and FF functions are selected in standard mode. HF, PAE, and PAF always are available for use, regardless of timing mode. PAE and PAF can be programmed independently to switch at any point in memory. Programmable offsets determine the flag-switching threshold and can be loaded by parallel or serial methods. Eight default offset settings also are provided, so that PAE can be set to switch at a predefined number of locations from the empty boundary. The PAF threshold also can be set at similar predefined values from the full boundary. The default offset values are set during master reset by the state of FSEL0, FSEL1, and LD. For serial programming, SEN, together with LD, loads the offset registers via the serial input (SI) on each rising edge of WCLK. For parallel programming, WEN, together with LD, loads the offset registers via Dn on each rising edge of WCLK. REN, together with LD, can read the offsets in parallel from Qn on each rising edge of RCLK, regardless of whether serial or parallel offset loading has been selected. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 description (continued) Also, the timing modes of PAE and PAF outputs can be selected. Timing modes can be set to be either asynchronous or synchronous for PAE and PAF. If the asynchronous PAE/PAF configuration is selected, PAE is asserted low on the low-to-high transition of RCLK. PAE is reset to high on the low-to-high transition of WCLK. Similarly, PAF is asserted low on the low-to-high transition of WCLK, and PAF is reset to high on the low-to-high transition of RCLK. If the synchronous PAE/PAF configuration is selected , PAE is asserted and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK only and not RCLK. The desired mode is configured during master reset by the state of the programmable-flag mode (PFM) pin. The retransmit function allows data to be reread from the FIFO more than once. A low on the RT input during a rising RCLK edge initiates a retransmit operation by setting the read pointer to the first location of the memory array. Zero-latency retransmit timing mode can be selected using the retransmit timing mode (RM). During master reset, a low on RM selects zero-latency retransmit. A high on RM during master reset selects normal latency. If zero-latency retransmit operation is selected, the first data word to be retransmitted is placed on the output register with respect to the same RCLK edge that initiated the retransmit, if RT is low. During master reset (MRS), the functions for all the operating modes are programmed. These include FWFT or standard timing, input bus width, output bus width, big endian or little endian, retransmit mode, programmable-flag operating and programming method, programmable-flag default offsets, and interspersed parity select. The read and write pointers are set to the first location of the FIFO. Then, based on the selected timing mode, EF is set low or OR is set high and FF is set high or IR is set low. Also, PAE is set low, PAF is set high, and HF is set high. The Q outputs are set low. Partial reset (PRS) also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable-flag programming method, default or programmed offset settings, input and output bus widths, big endian/little endian, interspersed parity select, and retransmit mode existing before partial reset is asserted remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS is useful for resetting a device in mid-operation when reprogramming programmable flags and other functions would be undesirable. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 Partial Reset (PRS) Master Reset (MRS) Write Clock (WCLK) Read Clock (RCLK) Write Enable (WEN) Read Enable (REN) Load (LD) Output Enable (OE) (×9 or ×18) Data In (D0–Dn) Serial Enable (SEN) First-Word Fall-Through or Serial Input (FWFT/SI) (×9 or ×18) Data Out (Q0–Qn) SN74V263 SN74V273 SN74V283 SN74V293 Full Flag/Input Ready (FF/IR) Retransmit (RT) Empty Flag/Output Ready (EF/OR) Programmable Almost-Empty Flag (PAE) Half-Full Flag (HF) Big Endian/Little Endian (BE) Programmable Almost-Full Flag (PAF) Interspersed/Noninterspersed Parity (IP) Input Width (IW) Output Width (OW) Figure 1. Single-Device-Configuration Signal Flow description (continued) A big-endian/little-endian data word format is provided. This function is useful when data is written into the FIFO in long-word (×18) format and read out of the FIFO in small-word (×9) format. If big-endian mode is selected, the most significant byte (MSB) (word) of the long word written into the FIFO is read out of the FIFO first, followed by the least significant byte (LSB). If little-endian format is selected, the LSB of the long word written into the FIFO is read out first, followed by the MSB. The mode desired is configured during master reset by the state of the big-endian/little-endian (BE) pin. The interspersed/noninterspersed parity (IP) bit function allows the user to select the parity bit in the word loaded into the parallel port (D0–Dn) when programming the flag offsets. If interspersed-parity mode is selected, the FIFO assumes that the parity bit is located in bit position D8 during the parallel programming of the flag offsets. If noninterspersed-parity mode is selected, D8 is assumed to be a valid bit and D16 and D17 are ignored. IP mode is selected during master reset by the state of the IP input pin. This mode is relevant only when the input width is set to ×18 mode. The SN74V263, SN74V273, SN74V283, and SN74V293 are fabricated using TI’s high-speed submicron CMOS technology. For more information on this device family, see the following application reports: D D 6 Interfacing TI High-Speed External FIFOs With TI DSP Via DSPs’ External Memory Interface (EMIF) (literature number SPRA534) Interfacing TI High-Speed External FIFOs With TI DSP Via DSPs’ Expansion Bus (XBus) (literature number SPRA547) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 Table 1. Bus-Matching Configuration Modes IW OW WRITE PORT WIDTH READ PORT WIDTH L L ×18 ×18 L H ×18 ×9 H L ×9 ×18 H H ×9 ×9 Terminal Functions TERMINAL NAME I/O DESCRIPTION BE I Big endian/little endian. During master reset, a low on BE selects big-endian operation. A high on BE during master reset selects little-endian format. D0–D17 I Data inputs. Data inputs for an 18- or 9-bit bus. When in 18-bit mode, D0–D17 are used. When in 9-bit mode, D0–D8 are used and the unused inputs (D9–D17) should be tied low. EF/OR O Empty flag/output ready. In FWFT mode, the OR function is selected. OR indicates whether there is valid data available at the outputs. In the standard mode, the EF function is selected. EF indicates whether the FIFO memory is empty. FF/IR O Full flag/input ready. In FWFT mode, the IR function is selected. IR indicates whether there is space available for writing to the FIFO memory. In standard mode, the FF function is selected. FF indicates whether the FIFO memory is full. FSEL0 I Flag-select bit 0. During master reset, FSEL0, along with FSEL1 and LD, selects the default offset values for PAE and PAF. Up to eight possible settings are available. FSEL1 I Flag-select bit 1. During master reset, FSEL1, along with FSEL0 and LD, selects the default offset values for PAE and PAF. Up to eight possible settings are available. FWFT/SI I First-word fall-through/serial in. During master reset, FWFT/SI selects FWFT or standard mode. After master reset, FWFT/SI functions as a serial input for loading offset registers. HF O Half-full flag. HF indicates whether the FIFO memory is more or less than half full. IP I Interspersed parity. During master reset, a low on IP selects noninterspersed-parity mode. A high on IP selects interspersed-parity mode. IW I Input width. IW selects the bus width of the write port. During master reset, when IW is low, the write port is configured with a ×18 bus width. If IW is high, the write port is a ×9 bus width. I Load. This is a dual-purpose pin. During master reset, the state of the LD input, along with FSEL0 and FSEL1, determines one of eight default offset values for the PAE and PAF flags, along with the method by which these offset registers can be programmed, parallel or serial (see Table 2). After master reset, LD enables writing to and reading from the offset registers. MRS I Master reset. MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During master reset, the FIFO is configured for either FWFT or standard mode, bus-matching configurations, one of eight programmable-flag default settings, serial or parallel programming of the offset settings, big-endian/little-endian format, zero- or normal-latency retransmit, interspersed parity, and synchronous versus asynchronous programmable-flag timing modes. OE I Output enable. OE controls the output impedance of Qn. OW I Output width. OW selects the bus width of the read port. During master reset, when OW is low, the read port is configured with a ×18 bus width. If OW is high, the read port is a ×9 bus width. PAE O Programmable almost-empty flag. PAE goes low if the number of words in the FIFO memory is less than or equal to offset n, which is stored in the empty offset register. PAE goes high if the number of words in the FIFO memory is greater than offset n. Add one if PAE is in FWFT mode. PAF O Programmable almost-full flag. PAF goes high if the number of free locations in the FIFO memory is more than offset m, which is stored in the full offset register. PAF goes low if the number of free locations in the FIFO memory is less than or equal to m. LD POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 Terminal Functions (Continued) TERMINAL NAME I/O DESCRIPTION I Programmable-flag mode. During master reset, a low on PFM selects asynchronous programmable-flag timing mode. A high on PFM selects synchronous programmable-flag timing mode. PRS I Partial reset. PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During partial reset, the existing mode (standard or FWFT), programming method (serial or parallel), and programmable-flag settings, input and output bus widths, big/little endian, interspersed parity select, and retransmit mode are all retained. Q0–Q17 O Data outputs. Data outputs for a 18- or 9-bit bus. When in 18-bit mode, Q0–Q17 are used and when in 9-bit mode, Q0–Q8 are used, and the unused outputs, Q9–Q17 should not be connected. Outputs are not 5-V tolerant regardless of the state of OE. RCLK I Read clock. When enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets from the programmable registers. REN I Read enable. REN enables RCLK for reading data from the FIFO memory and offset registers. RM I Retransmit latency mode. During master reset, a low on RM selects zero-latency retransmit timing mode. A high on RM selects normal-latency mode. RT I Retransmit. RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to low (OR to high in FWFT mode) and does not disturb the write pointer, programming method, existing timing mode, or programmable flag settings. RT is useful to reread data starting from the first physical location of the FIFO. SEN I Serial enable. SEN enables serial loading of programmable flag offsets. WCLK I Write clock. When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into the programmable registers for parallel programming and, when enabled by SEN, the rising edge of WCLK writes one bit of data into the programmable register for serial programming. WEN I Write enable. WEN enables WCLK for writing data into the FIFO memory and offset registers. PFM detailed description inputs data in (D0–Dn) Data inputs for 18-bit-wide data (D0–D17) or data inputs for 9-bit wide data (D0–D8). controls master reset (MRS) A master reset is accomplished when the MRS input is taken to a low state. This operation sets the internal read and write pointers to the first location of the RAM array. PAE goes low, PAF goes high, and HF goes high. If FWFT/SI is high, the FWFT mode, along with IR and OR, is selected. OR goes high and IR goes low. If FWFT/SI is low during master reset, the standard mode, along with EF and FF, is selected. EF goes low and FF goes high. All control settings, such as OW, IW, BE, RM, PFM, and IP, are defined during the master reset cycle. During a master reset, the output register is initialized to all zeroes. A master reset is required after power up, before a write operation can take place. MRS is asynchronous. See Figure 5 for timing information. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 partial reset (PRS) A partial reset is accomplished when the PRS input is taken to a low state. As in the case of the master reset, the internal read and write pointers are set to the first location of the RAM array, PAE goes low, PAF goes high, and HF goes high. Whichever mode is active at the time of partial reset remains selected (FWFT or standard mode). If FWFT mode is active, OR goes high and IR goes low. If the standard mode is active, FF goes high and EF goes low. Following partial reset, all values held in the offset registers remain unchanged. The programming method (parallel or serial) active at the time of partial reset also is retained. The output register is initialized to all zeroes. PRS is asynchronous. A partial reset is useful for resetting the device during operation, when reprogramming programmable-flag offset settings might not be convenient. See Figure 6 for timing information. retransmit (RT) The retransmit operation allows previously read data to be accessed again. There are two modes of retransmit operation: normal latency and zero latency. There are two stages to retransmit. The first stage is a setup procedure that resets the read pointer to the first location of memory. The second stage is the actual retransmit, which consists of reading out the memory contents, starting at the beginning of the memory. Retransmit setup is initiated by holding RT low during a rising RCLK edge. REN and WEN must be high before RCLK rises when RT is low. When zero latency is used, REN need not be high before RCLK rises while RT is low. If FWFT mode is selected, the FIFO marks the beginning of the retransmit setup by setting OR high. During this period, the internal read pointer is set to the first location of the RAM array. When OR goes low, retransmit setup is complete; at the same time, the contents of the first location appear on the outputs. Because FWFT mode is selected, the first word appears on the outputs and no low on REN is necessary. Reading all subsequent words requires a low on REN to enable the rising edge of RCLK. See Figure 12 for timing information. If standard mode is selected, the FIFO marks the beginning of the retransmit setup by setting EF low. The change in level is noticeable only if EF was high before setup. During this period, the internal read pointer is initialized to the first location of the RAM array. When EF goes high, retransmit setup is complete and read operations can begin, starting with the first location in memory. Since standard mode is selected, every word read, including the first word following retransmit setup, requires a low on REN to enable the rising edge of RCLK. See Figure 11 for timing information. In retransmit operation, the zero-latency mode can be selected using the retransmit latency mode (RM) pin during a master reset. This can be applied to the standard mode and the FWFT mode. retransmit latency mode (RM) A zero-latency retransmit timing mode can be selected using RM. During master reset, a low on RM selects zero-latency retransmit. A high on RM during master reset selects normal latency. If zero-latency retransmit operation is selected, the first data word to be retransmitted is placed on the output register with respect to the same RCLK edge that initiated the retransmit based on RT being low. See Figures 13 and 14 for timing information. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 first-word fall-through/serial in (FWFT/SI) FWFT/SI is a dual-purpose pin. During master reset, the state of the FWFT/SI input determines whether the device operates in FWFT mode or standard mode. If, at the time of master reset, FWFT/SI is high, FWFT mode is selected. This mode uses OR to indicate whether there is valid data at the data outputs (Qn). It also uses IR to indicate whether the FIFO memory has any free space for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to Qn after three RCLK rising edges; REN = low is not necessary. Subsequent words must be accessed using REN and RCLK. If, at the time of master reset, FWFT/SI is low, standard mode is selected. This mode uses EF to indicate whether there are any words present in the FIFO memory. It also uses the FF to indicate whether the FIFO memory has any free space for writing. In standard mode, every word read from the FIFO, including the first, must be requested using REN and RCLK. After master reset, FWFT/SI acts as a serial input for loading PAE and PAF offsets into the programmable registers. The serial input function can be used only when the serial loading method is selected during master reset. Serial programming using the FWFT/SI pin functions the same way in both FWFT and standard modes. write clock (WCLK) A write cycle is initiated on the rising edge of the WCLK input. Data setup and hold times must be met, with respect to the low-to-high transition of WCLK. It is permissible to stop WCLK. Note that while WCLK is idle, the FF/IR, PAF, and HF flags are not updated. (WCLK is capable only of updating the HF flag to low.) The write and read clocks can be either independent or coincident. write enable (WEN) When WEN is low, data can be loaded into the FIFO RAM array on the rising edge of every WCLK cycle if the device is not full. Data is stored in the RAM array sequentially and independently of any ongoing read operation. When WEN is high, no new data is written in the RAM array on each WCLK cycle. To prevent data overflow in the FWFT mode, IR goes high, inhibiting further write operations. After completion of a valid read cycle, IR goes low, allowing a write to occur. The IR flag is updated by two WCLK cycles + tsk after the valid RCLK cycle. To prevent data overflow in the standard mode, FF goes low, inhibiting further write operations. After completion of a valid read cycle, FF goes high, allowing a write to occur. The FF is updated by two WCLK cycles + tsk after the RCLK cycle. WEN is ignored when the FIFO is full in either FWFT or standard modes. read clock (RCLK) A read cycle is initiated on the rising edge of the RCLK input. Data can be read on the outputs, on the rising edge of the RCLK input. It is permissible to stop RCLK. While RCLK is idle, the EF/OR, PAE and HF flags are not updated. RCLK is capable only of updating the HF flag to high. The write and read clocks can be independent or coincident. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 read enable (REN) When REN is low, data is loaded from the RAM array into the output register on the rising edge of every RCLK cycle, if the device is not empty. When REN is high, the output register holds the previous data and no new data is loaded into the output register. The data outputs Q0–Qn maintain the previous data value. In the FWFT mode, the first word written to an empty FIFO automatically goes to the outputs Qn on the third valid low-to-high transition of RCLK + tsk after the first write. REN does not need to be asserted low. To access all other words, a read must be executed using REN. The RCLK low-to-high transition after the last word has been read from the FIFO, OR goes high with a true read (RCLK with REN = low), inhibiting further read operations. REN is ignored when the FIFO is empty. In the standard mode, every word accessed at Qn, including the first word written to an empty FIFO, must be requested using REN. When the last word has been read from the FIFO, EF goes low, inhibiting further read operations. REN is ignored when the FIFO is empty. Once a write is performed, EF goes high, allowing a read to occur. The EF flag is updated by two RCLK cycles + tsk after the valid WCLK cycle. serial enable (SEN) The SEN input is an enable used only for serial programming of the offset registers. The serial programming method must be selected during master reset. SEN always is used with LD. When these lines are both low, data at the SI input can be loaded into the program register, with one bit for each low-to-high transition of WCLK. When SEN is high, the programmable registers retain the previous settings and no offsets are loaded. SEN functions the same way in FWFT and standard modes. output enable (OE) When OE is asserted (low), the parallel output buffers receive data from the output register. When OE is high, the output data bus (Qn) goes into the high-impedance state. load (LD) LD is a dual-purpose pin. During master reset, the state of the LD input, along with FSEL0 and FSEL1, determines one of eight default offset values for the PAE and PAF flags, along with the method by which these offset registers can be programmed, parallel or serial (see Table 2). After master reset, LD enables write operations to and read operations from the offset registers. Only the offset loading method currently selected can be used to write to the registers. Offset registers can be read only in parallel. After master reset, LD is used to activate the programming process of the flag offset values PAE and PAF. Pulling LD low begins a serial loading, or a parallel load, or a read of these offset values. input width (IW)/output width (OW) bus matching IW and OW define the input and output bus widths. During master reset, the state of these pins is used to configure the device bus sizes (see Table 1 for control settings). All flags operate based on the word/byte size boundary, as defined by the selection of the widest input or output bus width. big endian/little endian (BE) During master reset, a low on BE selects big-endian operation. A high on BE during master reset selects little-endian format. This function is useful when data is written into the FIFO in word format (×18) and read out of the FIFO in word format (×18) or byte format (×9). If big-endian mode is selected, the MSB of the word written into the FIFO is read out of the FIFO first, followed by the LSB. If little-endian format is selected, the LSB of the word written into the FIFO is read out first, followed by the MSB. The desired mode is configured during master reset by the state of the BE. See Figure 4 for the byte arrangement. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 programmable-flag mode (PFM) During master reset, a low on PFM selects asynchronous programmable-flag timing mode. A high on PFM selects synchronous programmable-flag timing mode. If asynchronous PAF/PAE configuration is selected (PFM low during MRS), PAE is asserted low on the low-to-high transition of RCLK. PAE is reset to high on the low-to-high transition of WCLK. Similarly, PAF is asserted low on the low-to-high transition of WCLK, and PAF is reset to high on the low-to-high transition of RCLK. If the synchronous PAE/PAF configuration is selected (PFM high during MRS), PAE is asserted and updated on the rising edge of RCLK only, and not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK only, and not RCLK. The mode desired is configured during master reset by the state of PFM. interspersed parity (IP) During master reset, a low on IP selects noninterspersed-parity mode. A high selects interspersed-parity mode. The IP bit function allows the user to select the parity bit in the word loaded into the parallel port (D0–Dn) when programming the flag offsets. If interspersed-parity mode is selected, the FIFO assumes that the parity bit is located in bit positions D8 and D17 during the parallel programming of the flag offsets and, therefore, ignores D8 when loading the offset register in parallel mode. This also is applied to the output register when reading the value of the offset register. If interspersed parity is selected, output Q8 is invalid. If noninterspersed-parity mode is selected, D16 and D17 are the parity bits and are ignored during parallel programming of the offsets (D8 becomes a valid bit). Additionally, output Q8 becomes a valid bit when performing a read of the offset register. Interspersed-parity mode is selected during master reset by state of IP. outputs full flag/input ready (FF/IR) FI/IR is a dual-purpose pin. In FWFT mode, the IR function is selected. IR goes low when memory space is available for writing in data. When there is no longer any free space left, IR goes high, inhibiting further write operations. If no reads are performed after a reset (either MRS or PRS), IR goes high after D writes to the FIFO. If ×18 input or ×18 output bus width is selected, D = 8193 for the SN74V263, D = 16385 for the SN74V273, D = 32769 for the SN74V283, and D = 65537 for the SN74V293. If both ×9 input and ×9 output bus widths are selected, D = 16385 for the SN74V263, D = 32769 for the SN74V273, D = 65537 for the SN74V283, and D = 131073 for the SN74V293. See Figure 9 for timing information. In standard mode, the FF function is selected. When the FIFO is full, FF goes low, inhibiting further write operations. When FF is high, the FIFO is not full. If no reads are performed after a reset (either MRS or PRS), FF goes low after D writes to the FIFO. If ×18 input or ×18 output bus width is selected, D = 8192 for the SN74V263, D = 16384 for the SN74V273, D = 32768 for the SN74V283, and D = 65536 for the SN74V293. If both ×9 input and ×9 output bus widths are selected, D = 16384 for the SN74V263, D = 32768 for the SN74V273, D = 65536 for the SN74V283, and D = 131072 for the SN74V293. See Figure 7 for timing information. The IR status not only measures the contents of the FIFO memory, but also counts the presence of a word in the output register. Thus, in FWFT mode, the total number of writes necessary to deassert IR is one greater than needed to assert FF in standard mode. FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are double register-buffered outputs. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 empty flag/output ready (EF/OR) EF/OR is a dual-purpose pin. In FWFT mode, the OR function is selected. OR goes low at the same time that the first word written to an empty FIFO appears valid on the outputs. OR stays low after the RCLK low-to-high transition that shifts the last word from the FIFO memory to the outputs. OR goes high only with a true read (RCLK with REN = low). The previous data stays at the outputs, indicating the last word was read. Further data reads are inhibited until OR goes low again. See Figure 10 for timing information. In the standard mode, the EF function is selected. When the FIFO is empty, EF goes low, inhibiting further read operations. When EF is high, the FIFO is not empty. See Figure 8 for timing information. EF/OR is synchronous and updated on the rising edge of RCLK. In FWFT mode, OR is a triple register-buffered output. In standard mode, EF is a double register-buffered output. programmable almost-full flag (PAF) PAF goes low when the FIFO reaches the almost-full condition. In FWFT mode, if ×18 input or ×18 output bus width is selected, PAF goes low after (8193 – m) writes for the SN74V263, (16385 – m) writes for the SN74V273, (32769 – m) writes for the SN74V283, and (65537 – m) writes for the SN74V293. If both ×9 input and ×9 output bus widths are selected, PAF goes low after (16385 – m) writes for the SN74V263, (32769 – m) writes for the SN74V273, (65537 – m) writes for the SN74V283, and (131073 – m) writes for the SN74V293. The offset m is the full offset value. The default setting for this value is shown in Table 2. In standard mode, if no reads are performed after MRS, PAF goes low after (D – m) words are written to the FIFO. If ×18 input or ×18 output bus width is selected, (D – m) = (8192 – m) writes for the SN74V263, (16384 – m) writes for the SN74V273, (32768 – m) writes for the SN74V283, and (65536 – m) writes for the SN74V293. If both ×9 input and ×9 output bus widths are selected, (D – m) = (16384 – m) writes for the SN74V263, (32768 – m) writes for the SN74V273, (65536 – m) writes for the SN74V283, and (131072 – m) writes for the SN74V293. The offset m is the full offset value. The default setting for this value is shown in Table 2. See Figure 18 for timing information. If asynchronous PAF configuration is selected, the PAF is asserted low on the low-to-high transition of WCLK. PAF is reset to high on the low-to-high transition of RCLK. If synchronous PAF configuration is selected, the PAF is updated on the rising edge of WCLK (see Figure 20). programmable almost-empty flag (PAE) PAE goes low when the FIFO reaches the almost-empty condition. In FWFT mode, PAE goes low when there are n + 1 words, or fewer, in the FIFO. The default setting for this value is shown in Table 2. In standard mode, PAE goes low when there are n words, or fewer, in the FIFO. The offset n is the empty offset value. The default setting for this value is shown in Table 2. See Figure 19 for timing information. If asynchronous PAE configuration is selected, PAE is asserted low on the low-to-high transition of the read clock (RCLK). PAE is reset to high on the low-to-high transition of the write clock (WCLK). If synchronous PAE configuration is selected, PAE is updated on the rising edge of RCLK. See Figure 21 for timing information. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 half-full flag (HF) The HF output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO beyond half-full sets HF low. The flag remains low until the difference between the write and read pointers becomes less than or equal to half of the total depth of the device. The rising RCLK edge that accomplishes this condition sets HF high. In FWFT mode, if no reads are performed after reset (MRS or PRS), HF goes low after [(D – 1)/2] + 2 writes to the FIFO. If ×18 input or ×18 output bus width is selected, D = 8193 for the SN74V263, D = 16385 for the SN74V273, D = 32769 for the SN74V283, and D = 65537 for the SN74V293. If both ×9 input and ×9 output bus widths are selected, D = 16385 for the SN74V263, D = 32769 for the SN74V273, D = 65537 for the SN74V283, and D = 131073 for the SN74V293. In standard mode, if no reads are performed after reset (MRS or PRS), HF goes low after (D/2) + 1 writes to the FIFO. If ×18 input or ×18 output bus width is selected, D = 8192 for the SN74V263, D = 16384 for the SN74V273, D = 32768 for the SN74V283, and D = 65536 for the SN74V293. If both ×9 input and ×9 output bus widths are selected, D = 16384 for the SN74V263, D = 32768 for the SN74V273, D = 65536 for the SN74V283, and D = 131072 for the SN74V293. See Figure 22 for timing information. Because HF is updated by both RCLK and WCLK, it is considered asynchronous. data outputs (Q0–Qn) Q0–Q17 are data outputs for 18-bit-wide data or Q0–Q8 are data outputs for 9-bit-wide data. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Terminal voltage range with respect to GND, VTERM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.5 V Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions MIN TYP MAX UNIT VCC GND Supply voltage (see Note 1) 3.15 3.3 3.45 V Supply voltage 0 0 0 V VIH VIL High-level input voltage (see Note 2) 2 5.5 V Low-level input voltage TA Operating free-air temperature NOTES: 1. VCC = 3.3 V ± 0.15 V, JESD8-A compliant 2. Outputs are not 5-V tolerant. 0 0.8 V 70 °C electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX 2.4 UNIT VOH VOL IOH = –2 mA IOL = 8 mA II IOZ VI = 0.4 V to VCC OE ≥ VIH, µA ×9 input to ×9 output, VO = 0.4 V to VCC See Notes 3, 4, and 5 ±10 ICC1 ICC2 30 mA ×18 input to ×18 output, See Notes 3, 4, and 5 35 mA ICC3 CIN Standby, See Notes 3 and 6 15 mA VI = 0, VO = 0, TA = 25°C, TA = 25°C, 10 pF f = 1 MHz V 0.4 V ±1 µA COUT f = 1 MHz, Output deselected (OE ≥ VIH) 10 pF NOTES: 3. Tested with outputs open (IOUT = 0) 4. RCLK and WCLK switch at 20 MHz and data inputs switch at 10 MHz. 5. For ×18 bus widths, typical ICC2 = 5 + fS + 0.02 × CL × fS (in mA); for ×9 bus widths, typical ICC1 = 5 + 0.775 fS + 0.02 × CL × fS (in mA). These equations are valid under the following conditions: VCC = 3.3 V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF). 6. All inputs = (VCC – 0.2 V) or (GND + 0.2 V), except RCLK and WCLK, which switch at 20 MHz. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figure 2 through Figure 22)† SN74V263-6 SN74V273-6 SN74V283-6 SN74V293-6 MIN MAX SN74V263-7.5 SN74V273-7.5 SN74V283-7.5 SN74V293-7.5 MIN 166 MAX SN74V263-10 SN74V273-10 SN74V283-10 SN74V293-10 MIN MAX MIN MAX Clock cycle frequency tCLK tCLKH Clock cycle time 6 7.5 10 15 ns Clock high time 2.5 3.5 4.5 6 ns tCLKL tDS Clock low time 2.5 3.5 4.5 6 ns Data setup time 1.5 2.5 3.5 4 ns tDH tENS Data hold time 0.5 0.5 0.5 1 ns Enable setup time 1.5 2.5 3.5 4 ns tENH tLDS Enable hold time 0.5 0.5 0.5 1 ns 2 3.5 3.5 4 ns tLDH tRS Load hold time 0 0.5 0.5 1 ns Reset pulse duration‡ 10 10 10 15 ns tRSS tRSR Reset setup time 15 15 15 15 ns Reset recovery time 10 10 10 15 tRSF tRTS Reset to flag and output time Retransmit setup time 2 3.5 3.5 4 ns tOLZ tOE Output enable to output in low impedance 0 0 0 0 ns Output enable to output valid 2 4.5 2 6 2 6 2 8 ns tOHZ tWFF Output enable to output in high impedance 2 4.5 2 6 2 6 2 8 ns Write clock to FF or IR 4.5 5 6.5 10 ns tREF Read clock to EF or OR 4.5 5 6.5 10 ns tPAFA Clock to asynchronous programmable almost-full flag 8.5 12.5 16 20 ns tPAFS Write clock to synchronous programmable almost-full flag 4.5 5 6.5 10 ns tPAEA Clock to asynchronous programmable almost-empty flag 8.5 12.5 16 20 ns tPAES Read clock to synchronous programmable almost-empty flag 4.5 5 6.5 10 ns tHF Clock to half-full flag 7 12.5 16 20 ns tsk1 Skew time between read clock and write clock for EF/OR and FF/IR 4 5 7 9 ns tsk2 Skew time between read clock and write clock for PAE and PAF 4 7 10 14 ns 2 Load setup time 4.5 2 15 POST OFFICE BOX 655303 2 15 † All ac timings apply to both FWFT mode and standard modes. ‡ Pulse durations less than minimum values are not allowed. 16 5 100 UNIT fclock tA Data access time 133 SN74V263-15 SN74V273-15 SN74V283-15 SN74V293-15 • DALLAS, TEXAS 75265 6.5 66.7 2 15 10 MHz ns ns 15 ns SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 PARAMETER MEASUREMENT INFORMATION VCC/2 AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load for tCLK = 10 ns, 15 ns Output Load for tCLK = 7.5 ns 50 Ω GND to 3.0 V 3 ns (see Note A) 1.5 V 1.5 V See A See B and C ZO = 50 Ω I/O B. AC TEST LOAD FOR 6- AND 7.5-SPEED GRADE 3.3 V From Output Under Test 510 Ω 30 pF (see Note B) Typical ∆t CD – ns 6 330 Ω 5 4 3 2 1 0 0 20 40 60 80 100 120 140 160 180 200 Capacitance – pF A. OUTPUT LOAD CIRCUIT FOR 10- AND 15-SPEED GRADES C. LUMPED CAPACITIVE LOAD, TYPICAL DERATING NOTES: A. For 133-MHz and 166-MHz operation, input rise/fall times are 1.5 ns. B. Includes probe and jig capacitance Figure 2. Load Circuits POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 functional description timing modes: FWFT mode vs standard mode The SN74V263, SN74V273, SN74V283, and SN74V293 support two different timing modes of operation: FWFT or standard. The selection of the mode is determined during master reset by the state of FWFT/SI. If, at the time of master reset, FWFT/SI is high, then FWFT mode is selected. This mode uses OR to indicate whether there is valid data at the data outputs (Qn). It also uses IR to indicate whether the FIFO has any free space for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to Qn after three RCLK rising edges; REN = low is not necessary. Subsequent words must be accessed using REN and RCLK. If, at the time of master reset, FWFT/SI is low, then standard mode is selected. This mode uses EF to indicate whether there are any words present in the FIFO. It also uses the FF function to indicate whether the FIFO has any free space for writing. In standard mode, every word read from the FIFO, including the first, must be requested, using REN and RCLK. Various signals (both input and output) operate differently, depending on which timing mode is in effect. FWFT mode In FWFT mode, status flags IR, PAF, HF, PAE, and OR operate as outlined in Table 4. To write data into the FIFO, WEN must be low. Data presented to the DATA IN lines is clocked into the FIFO on subsequent transitions of WCLK. After the first write is performed, the OR flag goes low after three low-to-high transitions on RCLK. Subsequent writes continue to fill up the FIFO. PAE goes high after n + 2 words have been loaded into the FIFO, where n is the empty offset value. The default setting for these values is in the footnote of Table 2. This parameter also is user programmable (see the programmable-flag offset loading section). If one continues to write data into the FIFO and assumes no read operations are taking place, HF switches to low after the [(D – 1)/2 + 2] words were written into the FIFO. If ×18 input or ×18 output bus width is selected, [(D – 1)/2 + 2] = 4098th word for the SN74V263, 8194th word for SN74V273, 16386th word for the SN74V283, and 32770th word for the SN74V293. If both ×9 input and ×9 output bus widths are selected, [(D – 1)/2 + 2] = 8194th word for the SN74V263, 16386th word for SN74V273, 32770th word for the SN74V283, and 65,538th word for the SN74V293. Continuing to write data into the FIFO causes PAF to go low. Again, if no reads are performed, the PAF goes low after (D – m) writes to the FIFO. If ×18 input or ×18 output bus width is selected, (D – m) = (8193 – m) writes for the SN74V263, (16385 – m) writes for the SN74V273, (32769 – m) writes for the SN74V283, and (65537 – m) writes for the SN74V293. If both ×9 input and ×9 output bus widths are selected, (D – m) = (16385 – m) writes for the SN74V263, (32769 – m) writes for the SN74V273, (65537 – m) writes for the SN74V283, and (131073 – m) writes for the SN74V293. The offset m is the full offset value. The default settings for these values are given in the footnote of Table 2. When the FIFO is full, the IR flag goes high, inhibiting further write operations. If no reads are performed after a reset, IR goes high after D writes to the FIFO. If ×18 input or ×18 output bus width is selected, D = 8193 writes for the SN74V263, D = 16385 writes for the SN74V273, D = 32769 writes for the SN74V283, and D = 65537 writes for the SN74V293. If both ×9 input and ×9 output bus widths are selected, D = 16385 writes for the SN74V263, D = 32769 writes for the SN74V273, D = 65537 writes for the SN74V283, and D = 131073 writes for the SN74V293. Note that the additional word in FWFT mode is due to the capacity of the memory plus output register. If the FIFO is full, the first read operation cause the IR flag to go low after two low-to-high transitions of WCLK. Subsequent read operations causes the PAF and HF to go high at the conditions shown in Table 4. If further read operations occur without write operations, PAE goes low when there are n + 1 words in the FIFO, where n is the empty offset value. Continuing read operations causes the FIFO to become empty. When the last word has been read from the FIFO, OR goes high, inhibiting further read operations. REN is ignored when the FIFO is empty. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 FWFT mode (continued) When configured in FWFT mode, the OR flag output is triple register buffered, and the IR flag output is double register buffered. Timing diagrams for FWFT mode can be found in Figures 9, 10, and 12. standard mode In this mode, status flags FF, PAF, HF, PAE, and EF operate as outlined in Table 3. To write data into to the FIFO, WEN must be low. Data presented to the DATA IN lines is clocked into the FIFO on subsequent transitions of WCLK. After the first write is performed, EF goes high after two low-to-high transitions on RCLK. Subsequent writes continue to fill up the FIFO. PAE goes high after n + 1 words have been loaded into the FIFO, where n is the empty offset value. The default setting for these values is in the footnote of Table 2. This parameter also is user programmable (see the programmable-flag offset loading section). If one continues to write data into the FIFO and assumes no read operations are taking place, HF switches to low after (D/2 + 1) words are written into the FIFO. If ×18 input or ×18 output bus width is selected, (D/2 + 1) = 4097th word for the SN74V263, 8193th word for the SN74V273, 16385th word for the SN74V283, and 32769th word for the SN74V293. If both ×9 input and ×9 output bus widths are selected, (D/2 + 1) = 8193rd word for the SN74V263, 16385th word for the SN74V273, 32769th word for the SN74V283, and 65537th word for the SN74V293. Continuing to write data into the FIFO causes PAF to go low. Again, if no reads are performed, PAF goes low after (D – m) writes to the FIFO. If ×8 input or ×18 output bus width is selected, (D – m) = (8192 – m) writes for the SN74V263, (16384 – m) writes for the SN74V273, (32768 – m) writes for the SN74V283, and (65536 – m) writes for the SN74V293. If both ×9 input and ×9 output bus widths are selected, (D – m) = (16384 – m) writes for the SN74V263, (32768 – m) writes for the SN74V273, (65536 – m) writes for the SN74V283, and (131072 – m) writes for the SN74V293. Offset m is the full offset value. The default setting for these values is in the footnote of Table 2. This parameter also is user programmable (see the programmable-flag offset loading section). When the FIFO is full, FF goes low, inhibiting further write operations. If no reads are performed after a reset, FF goes low after D writes to the FIFO. If the ×18 input or ×18 output bus width is selected, D = 8192 writes for the SN74V263, D = 16384 writes for the SN74V273, D = 32768 writes for the SN74V283, and D = 65536 writes for the SN74V293. If both ×9 input and ×9 output bus widths are selected, D = 16384 writes for the SN74V263, D = 32768 writes for the SN74V273, D = 65536 writes for the SN74V283, and D = 131072 writes for the SN74V293. If the FIFO is full, the first read operation causes FF to go high after two low-to-high transitions on WCLK. Subsequent read operations cause PAF and HF to go high at the conditions shown in Table 3. If further read operations occur without write operations, PAE goes low when there are n words in the FIFO, where n is the empty offset value. Continuing read operations causes the FIFO to become empty. When the last word has been read from the FIFO, EF goes low, inhibiting further read operations. REN is ignored when the FIFO is empty. When configured in standard mode, the EF and FF outputs are double register-buffered outputs. See Figures 7, 8, and 11 for timing diagrams for standard mode. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 Table 2. Default Programmable Flag Offsets OFFSETS (n, m)† OFFSETS (n, m)† LD FSEL0 FSEL1 SN74V263 SN74V273 LD FSEL0 SN74V283 FSEL1 ALL OTHER MODES ×9 TO ×9 MODE SN74V293 16383 H L L 1,023 L L H 511 16383 L L H 511 L H L 255 8191 8191 L H L 255 L H H 63 4,095 4,095 L L L 127 H L H 31 2,047 2,047 L H H 63 H L L 1,023 1,023 1,023 H L H 31 H H L 15 511 511 H H L 15 H H H 7 255 255 H H H 7 L L L 127 127 127 † n = empty offset for PAE, m = full offset for PAF programming flag offsets Full and empty flag offset values are user programmable. The SN74V263, SN74V273, SN74V283, and SN74V293 have internal registers for these offsets. Eight default offset values are selectable during master reset. These offset values are shown in Table 2. Offset values also can be programmed into the FIFO by serial or parallel loading. The loading method is selected using LD. During master reset, the state of the LD input determines whether serial or parallel flag offset programming is enabled. A high on LD during master reset selects serial loading of offset values. A low on LD during master reset selects parallel loading of offset values. In addition to loading offset values into the FIFO, it also is possible to read the current offset values. Offset values can be read via the parallel output ports Q0–Qn, regardless of the programming mode selected (serial or parallel). It is not possible to read the offset values in serial fashion. Figure 3 summarizes the control pins and sequence for both serial and parallel programming modes. A more detailed description is given in the following paragraphs. The offset registers can be programmed (and reprogrammed) any time after master reset, regardless of whether serial or parallel programming has been selected. Valid programming ranges are from 0 to D – 1. synchronous vs asynchronous programmable-flag timing selection The SN74V263, SN74V273, SN74V283, and SN74V293 can be configured during the master reset cycle with either synchronous or asynchronous timing for PAF and PAE flags by use of the PFM pin. If synchronous PAF/PAE configuration is selected (PFM high during MRS), PAF is asserted and updated on the rising edge of WCLK only and not RCLK. Similarly, PAE is asserted and updated on the rising edge of RCLK only and not WCLK (see Figure 18 for synchronous PAF timing and Figure 19 for synchronous PAE timing). If asynchronous PAF/PAE configuration is selected (PFM low during MRS), PAF is asserted low on the low-to-high transition of WCLK and PAF is reset to high on the low-to-high transition of RCLK. Similarly, PAE is asserted low on the low-to-high transition of RCLK. PAE is reset to high on the low-to-high transition of WCLK (see Figure 20 for asynchronous PAF timing and Figure 21 for asynchronous PAE timing). 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 Table 3. Status Flags for Standard Mode IW = OW = ×9 IW ≠ OW OR IW = OW = ×18 Number of Words in FIFO SN74V263 SN74V273 SN74V283 SN74V263 SN74V273 SN74V283 SN74V293 0 0 0 0 SN74V293 FF PAF HF PAE EF 0 H H H L L 1 to n 1 to n 1 to n 1 to n 1 to n H H H L H (n + 1) to 4096 (n + 1) to 8192 (n + 1) to 16384 (n + 1) to 32768 (n + 1) to 65536 H H H H H H H L H H 4097 to [8192 – (m + 1)] 8193 to [16384 – (m + 1)] 16385 to [32768 – (m + 1)] 32769 to [65536 – (m + 1)] 65537 to [131072 – (m + 1)] (8192 – m) to 8191 (16384 – m) to 16383 (32768 – m) to 32767 (65536 – m) to 65535 (131072 – m) to 131071 H L L H H 8192 16384 32768 65536 131072 L L L H H NOTE 1: See Table 2 for values for n, m. Table 4. Status Flags for FWFT Mode IW = OW = ×9 IW ≠ OW OR IW = OW = ×18 Number N mber of Words in FIFO SN74V263 SN74V263 SN74V273 SN74V283 SN74V273 SN74V283 SN74V293 SN74V293 IR PAF HF PAE OR 0 0 0 0 0 L H H L H 1 to (n + 1) 1 to (n + 1) 1 to (n + 1) 1 to (n + 1) 1 to (n + 1) L H H L L (n + 2) to 4097 (n + 2) to 8193 (n + 2) to 16385 (n + 2) to 32769 (n + 2) to 65537 L H H H L 4098 to [8193 – (m + 1)] 8194 to [16385 – (m + 1)] 16386 to [32769 – (m + 1)] 32770 to [65537 – (m + 1)] 65538 to [131073 – (m + 1)] L H L H L (8193 – m) to 8192 (16385 – m) to 16384 (32769 – m) to 32768 (65537 – m) to 65536 (131073 – m) to 131072 L L L H L 8193 16385 32769 65537 131073 H L L H L NOTES: 1. See Table 2 for values for n, m. 2. Number of words in FIFO = FIFO depth + output register POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 1st Parallel Offset Write/Read Cycle 1st Parallel Offset Write/Read Cycle D/Q8 D/Q0 D/Q8 1 X D/Q0 EMPTY OFFSET REGISTER X 8 7 6 5 4 3 EMPTY OFFSET REGISTER 2 2nd Parallel Offset Write/Read Cycle 8 D/Q0 15 14 13 12 11 10 9 X D/Q0 6 5 16 14 13 14 13 12 11 10 9 D/Q0 4 3 2 1 X X X X X X X X 17 4th Parallel Offset Write/Read Cycle D/Q0 D/Q8 9 X D/Q0 FULL OFFSET REGISTER 15 1 EMPTY OFFSET REGISTER D/Q8 16 15 D/Q8 4th Parallel Offset Write/Read Cycle X 2 D/Q0 FULL OFFSET REGISTER 7 3 3rd Parallel Offset Write/Read Cycle D/Q8 8 4 EMPTY OFFSET REGISTER 3rd Parallel Offset Write/Read Cycle X 5 D/Q8 EMPTY OFFSET REGISTER 16 6 2nd Parallel Offset Write/Read Cycle D/Q8 X 7 12 FULL OFFSET REGISTER 11 10 SN74V263/SN74V273/SN74V283/SN74V293 ×9 Bus Width (see Note A) 8 7 6 5 4 3 2 1 5th Parallel Offset Write/Read Cycle D/Q8 D/Q0 X = don’t care FULL OFFSET REGISTER X 16 15 14 13 12 11 10 9 6th Parallel Offset Write/Read Cycle D/Q8 D/Q0 FULL OFFSET REGISTER X X X X X X X X 17 SN74V293 ×9 Bus Width (see Note A) ×9 TO ×9 MODE ALL OTHER MODES Number of bits used: 14 bits for the SN74V263 15 bits for the SN74V273 16 bits for the SN74V283 17 bits for the SN74V293 Note: All unused bits of the LSB and MSB are don’t care Number of bits used: 13 bits for the SN74V263 14 bits for the SN74V273 15 bits for the SN74V283 16 bits for the SN74V293 Note: All unused bits of the LSB and MSB are don’t care NOTE A: When programming the SN74V293 with an input bus width of ×9 and output bus width of ×18, four write cycles are required. When reading the SN74V293 with an output bus width of ×9 and input bus width of ×18, four read cycles are required. A total of six program/read cycles are required for ×9 bus width if both the input and output bus widths are set to ×9. Figure 3. Programmable Flag Offset Programming Sequence 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 1st Parallel Offset Write/Read Cycle D/Q17 Data Inputs/Outputs D/Q0 EMPTY OFFSET REGISTER X X 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Noninterspersed Parity 16 15 14 13 12 11 10 9 X 8 7 6 5 4 3 2 1 Interspersed Parity D/Q8 Number of Bits Used 2nd Parallel Offset Write/Read Cycle D/Q17 Data Inputs/Outputs D/Q0 FULL OFFSET REGISTER X X 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16 15 14 13 12 11 10 9 X 8 7 6 5 4 3 2 1 D/Q8 SN74V263/SN74V273/SN74V283/SN74V293 ×18 Bus Width LD 0 0 WEN 0 1 REN 1 0 SEN 1 1 WCLK ↑ X SN74V263, SN74V273, SN74V283, SN74V293 RCLK X Parallel write to registers: Empty offset (LSB) Empty offset (MSB) Full offset (LSB) Full offset (MSB) ↑ Parallel read from registers: Empty offset (LSB) Empty offset (MSB) Full offset (LSB) Full offset (MSB) ×9 TO ×9 MODE ALL OTHER MODES Serial shift into registers: 28 bits for the SN74V263 30 bits for the SN74V273 32 bits for the SN74V283 34 bits for the SN74V293 1 bit for each rising WCLK edge, starting with empty offset (LSB) and ending with full offset (MSB) Serial shift into registers: 26 bits for the SN74V263 28 bits for the SN74V273 30 bits for the SN74V283 32 bits for the SN74V293 1 bit for each rising WCLK edge, starting with empty offset (LSB) and ending with full offset (MSB) 0 1 1 0 ↑ X X 1 1 1 X X 1 0 X X ↑ X Write memory 1 X 0 X X ↑ Read memory 1 1 1 X X X No operation No operation NOTES: B. The programming method can be selected only at master reset. C. Parallel reading of the offset registers is always permitted, regardless of which programming method has been selected. D. The programming sequence applies to FWFT and standard modes. Figure 3. Programmable Flag Offset Programming Sequence (Continued) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 serial programming mode If the serial programming mode has been selected as described previously, programming of PAE and PAF values can be achieved by using a combination of the LD, SEN, WCLK, and SI inputs. Programming PAE and PAF proceeds as follows; when LD and SEN are set low, data on the SI input are written, one bit for each WCLK rising edge, starting with the empty offset LSB and ending with the full offset MSB. If ×9 to ×9 mode is selected, a total of 28 bits for the SN74V263, 30 bits for the SN74V273, 32 bits for the SN74V283, and 34 bits for the SN74V293. For any other mode of operation (including ×18 bus width on either the input or output), minus 2 bits from the previous values. So, a total of 26 bits for the SN74V263, 28 bits for the SN74V273, 30 bits for the SN74V283, and 32 bits for the SN74V293. See Figure 15 for timing information. Using the serial method, individual registers cannot be programmed selectively. PAE and PAF can show a valid status only after the complete set of bits for all offset registers has been entered. The registers can be reprogrammed as long as the complete set of new offset bits is entered. When LD is low and SEN is high, no serial write to the registers can occur. Write operations to the FIFO are allowed before and during the serial programming sequence. In this case, the programming of all offset bits does not have to occur at once. A select number of bits can be written to the SI input and then, by bringing LD and SEN high, data can be written to FIFO memory via Dn by toggling WEN. When WEN is brought high with LD and SEN restored to a low, the next offset bit in sequence is written to the registers via SI. If an interruption of serial programming is desired, it is sufficient either to set LD low and deactivate SEN or to set SEN low and deactivate LD. Once LD and SEN are restored to a low level, serial offset programming continues. From the time serial programming has begun, neither programmable flag is valid until the full set of bits required to fill all the offset registers is written. Measuring from the rising WCLK edge that achieves the previous criteria, PAF is valid after two more rising WCLK edges + tPAF, PAE is valid after the next two rising RCLK edges + tPAE + tsk2 in synchronous timing mode. It is not possible to read the flag offset values in a serial mode. parallel programming mode If the parallel programming mode has been selected as described previously, programming of PAE and PAF values can be achieved by using a combination of the LD, WCLK , WEN and Dn inputs. If the FIFO is configured for an input bus width and output bus width both set to ×9, the total number of write operations required to program the offset registers is four for the SN74V263, SN74V273, and SN74V283, or six for the SN74V293. Refer to Figure 3 for a diagram of the data input lines D0–Dn used during parallel programming. If the FIFO is configured for an input-to-output bus width of ×9 to ×18, ×18 to ×9, or ×18 to ×18, the following number of write operations are required. For an input bus width of ×18, a total of two write operations is required to program the offset registers for the SN74V263, SN74V273, SN74V283, and SN74V293. For an input bus width of ×9, a total of four write operations is required to program the offset registers for the SN74V263, SN74V273, SN74V283, and SN74V283 (see Figure 3). For example, programming PAE and PAF on the SN74V293 configured for ×18 bus width proceeds as follows: when LD and WEN are set low, data on inputs Dn are written into the LSB of the empty offset register on the first low-to-high transition of WCLK. On the second low-to-high transition of WCLK, data are written into the MSB of the empty offset register. On the third low-to-high transition of WCLK, data are written into the LSB of the full offset register. On the fourth low-to-high transition of WCLK, data are written into the MSB of the full offset register. On the fifth low-to-high transition of WCLK, data are written again to the empty offset register. Note that, for ×9 bus width, one additional write cycle is required for the empty offset register and full offset register. See Figure 16 for timing information. 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 parallel programming mode (continued) Writing offsets in parallel employs a dedicated write offset register pointer. Reading offsets employs a dedicated read offset register pointer. The two pointers operate independently; however, a read and a write should not be performed simultaneously to the offset registers. A master reset initializes both pointers to the empty offset (LSB) register. A partial reset has no effect on the position of these pointers (see Figure 3 for a diagram of the data input lines D0–Dn used during parallel programming). Write operations to the FIFO are allowed before and during the parallel programming sequence. In this case, the programming of all offset registers need not occur at one time. One, two, or more offset registers can be written. Then, by bringing LD high, write operations can be redirected to the FIFO memory. When LD is set low again and WEN is low, the next offset register in sequence is written to. As an alternative to holding WEN low and switching LD, parallel programming also can be interrupted by setting LD low and switching WEN. Note that the status of a programmable-flag (PAE or PAF) output is invalid during the programming process. From the time parallel programming has begun, a programmable-flag output is not valid until the appropriate offset word has been written to the register(s) pertaining to that flag. Measuring from the rising WCLK edge that achieves the previous criteria, PAF is valid after two more rising WCLK edges + tPAF, and PAE is valid after the next two rising RCLK edges + tPAE + tsk2 in synchronous timing mode. Reading the offset registers employs a dedicated read offset register pointer. The contents of the offset registers can be read on the Q0–Qn pins when LD is set low and REN is set low. If the FIFO is configured for both an input bus width and output bus width set to ×9, the total number of read operations required to read the offset registers is four for the SN74V263, SN74V273, and SN74V283, or six for the SN74V293 (see Figure 3 for a diagram of the data input lines D0–Dn used during parallel programming). If the FIFO is configured for an input-to-output bus width of ×9 to ×18, ×18 to ×9, or ×18 to ×18, the following number of read operations are required. For an output bus width of ×18, a total of two read operations is required to read the offset registers for the SN74V263, SN74V273, SN74V283, and SN74V293. For an output bus width of ×9, a total of four read operations is required to read the offset registers for the SN74V263, SN74V273, SN74V283, and SN74V293 (see Figure 3 ). For example, reading PAE and PAF on the SN74V293 configured for ×18 bus width proceeds as follows. Data are read via Qn from the empty offset register on the first and second low-to-high transition of RCLK. On the third and fourth low-to-high transitions of RCLK, data are read from the full offset register. The fifth and sixth transition of RCLK reads again from the empty offset register. Note that for a ×9 bus width, one additional read cycle is required for both the empty offset register and full offset register. See Figure 17 for timing information. It is permissible to interrupt the offset register read sequence with reads or writes to the FIFO. The interruption is accomplished by deasserting REN, LD, or both together. When REN and LD are restored to a low level, reading of the offset registers continues where it left off. It should be noted (and care should be taken from the fact) that when a parallel read of the flag offsets is performed, the data word that was present on the output lines Qn is overwritten. Parallel reading of the offset registers always is permitted, regardless of which timing mode (FWFT or standard) has been selected. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 retransmit operation The retransmit operation allows data that has already been read to be accessed again. There are two modes of retransmit operation: normal latency and zero latency. There are two stages to retransmit. The first stage is a setup procedure that resets the read pointer to the first location of memory. The second stage is the actual retransmit, which consists of reading out the memory contents, starting at the beginning of memory. Retransmit setup is initiated by holding RT low during a rising RCLK edge. REN and WEN must be high before RCLK goes high while RT is low. When zero latency is utilized, REN need not be high before bringing RT low. At least two words, but no more than D – 2 words, should have been written into the FIFO and read from the FIFO between reset (master or partial) and the time of retransmit setup. If ×18 input or ×8 output bus width is selected, D = 8192 for the SN74V263, D = 16384 for the SN74V273, D = 32768 for the SN74V283, and D = 65536 for the SN74V293. If both ×9 input and ×9 output bus widths are selected, D = 16384 for the SN74V263, D = 32768 for the SN74V273, D = 65536 for the SN74V283, and D = 131072 for the SN74V293. In FWFT mode, if ×18 input or ×18 output bus width is selected, D = 8193 for the SN74V263, D = 16385 for the SN74V273, D = 32769 for the SN74V283, and D = 65537 for the SN74V293. If both ×9 input and ×9 output bus widths are selected, D = 16385 for the SN74V263, D = 32769 for the SN74V273, D = 65537 for the SN74V283, and D = 131073 for the SN74V293. In normal retransmit mode, if FWFT mode is selected, the FIFO marks the beginning of the retransmit setup by setting OR high. During this period, the internal read pointer is set to the first location of the RAM array. When OR goes low, retransmit setup is complete. At the same time, contents of the first location appear on the outputs. Since FWFT mode is selected, the first word appears on the outputs; no low on REN is necessary. Reading all subsequent words requires a low on REN to enable the rising edge of RCLK. See Figure 12 for timing information. If standard mode is selected, the FIFO marks the beginning of the retransmit setup by setting EF low. The change in level is noticeable only if EF was high before setup. During this period, the internal read pointer is initialized to the first location of the RAM array. When EF goes high, retransmit setup is complete and read operations can begin, starting with the first location in memory. Since standard mode is selected, every word read, including the first word following retransmit setup, requires a low on REN to enable the rising edge of RCLK. See Figure 11 for timing information. For either FWFT mode or standard mode, updating of the PAE, HF, and PAF flags begins with the rising edge of RCLK that the RT is set up on. PAE is synchronized to RCLK, thus, on the second rising edge of RCLK after RT is set up, the PAE flag is updated. HF is asynchronous, thus, the rising edge of RCLK that RT is set up on updates HF. PAF is synchronized to WCLK, thus, the second rising edge of WCLK that occurs tsk after the rising edge of RCLK that RT is set up on updates PAF. RT is synchronized to RCLK. The retransmit function has the option of two modes of operation, either normal latency or zero latency. Figures 11 and 12 show to normal latency. Figures 13 and 14 show the zero-latency retransmit operation. Zero latency means, basically, that the first data word to be retransmitted is placed in the output register with respect to the RCLK pulse that initiated the retransmit. 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT: BE IW OW L L L BE IW OW H L L D17–D9 D8–D0 A B Q17–Q9 Q8–Q0 A B Write to FIFO Read from FIFO (a) ×18 INPUT TO ×18 OUTPUT – BIG ENDIAN Q17–Q9 Q8–Q0 B A Read from FIFO (b) ×18 INPUT TO ×18 OUTPUT – LITTLE ENDIAN Q17–Q9 Q8–Q0 X A BE IW OW Q17–Q9 Q8–Q0 L L H X B 1st: Read from FIFO 2nd: Read from FIFO (c) ×18 INPUT TO ×9 OUTPUT – BIG ENDIAN Q17–Q9 Q8–Q0 X B BE IW OW Q17–Q9 Q8–Q0 H L H X A 1st: Read from FIFO 2nd: Read from FIFO (d) ×18 INPUT TO ×9 OUTPUT – LITTLE ENDIAN BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT: BE IW OW L H L BE IW OW H H L D17–D9 D8–D0 X A D17–D9 D8–D0 X B Q17–Q9 Q8–Q0 A B 1st: Write to FIFO 2nd: Write to FIFO Read from FIFO (a) ×9 INPUT TO ×18 OUTPUT – BIG ENDIAN Q17–Q9 Q8–Q0 B A Read from FIFO (a) ×9 INPUT TO ×18 OUTPUT – LITTLE ENDIAN Figure 4. Bus-Matching Byte Arrangement POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 MRS tRSS tRSR tRSS tRSR tRSS tRSR tRSS tRSR REN WEN FWFT/SI LD tRSS FSEL0, FSEL1 tRSS OW, IW tRSS BE tRSS RM tRSS PFM tRSS IP tRSS RT tRSS SEN tRSF EF/OR If FWFT = High, OR = High If FWFT = Low, EF = Low tRSF FF/IR If FWFT = Low, FF = High If FWFT = High, IR = Low tRSF PAE tRSF PAF, HF tRSF OE = High Q0–Qn OE = Low Figure 5. Master Reset Timing 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 tRS PRS tRSS tRSR tRSS tRSR REN WEN tRSS RT tRSS SEN tRSF If FWFT = High, OR = High EF/OR If FWFT = Low, EF = Low tRSF If FWFT = Low, FF = High FF/IR If FWFT = High, IR = Low tRSF PAE tRSF PAF, HF tRSF OE = High Q0–Qn OE = Low Figure 6. Partial Reset Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 tCLK No Write tCLKH WCLK No Write tCLKH 2 1 tsk1 (see Note A) D0–Dn 1 tDS tDH 2 tsk1 (see Note A) Dx tDS tDH Dx + 1 tWFF tWFF tWFF tWFF FF WEN RCLK tENS tENS tENH tENH REN tA Q0–Qn Data In Output Register tA Data Read Next Data Read NOTES: A. tsk1 is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that FF goes high (after one WCLK cycle + tWFF). If the time between the rising edge of the RCLK and the rising edge of the WCLK is less than tsk1, the FF deassertion can be delayed one additional WCLK cycle. B. LD = high, EF = high Figure 7. Write-Cycle and Full-Flag Timing (Standard Mode) 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 tCLKH RCLK 1 tENS tCLK tCLKL 2 tENS tENH No Operation REN tENH tENS tENH No Operation tref tref tref EF tA tA Last Word Q0–Qn Last Word tOLZ tOHZ tA D0 D1 tOLZ tOE OE tsk1 (see Note A) WCLK tENS tENH tENS tENH WEN tDS D0–Dn tDH D0 tDS tDH D1 NOTES: A. tsk1 is the minimum time between a rising WCLK edge and a rising RCLK edge to ensure that EF goes high (after one RCLK cycle + tref). If the time between the rising edge of WCLK and the rising edge of RCLK is less than tsk1, EF deassertion can be delayed one additional RCLK cycle. B. LD = high C. First-data-word latency: tsk1 + 1*TRCLK + tREF Figure 8. Read-Cycle, Empty-Flag, and First-Data-Word-Latency Timing (Standard Mode) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31 ÎÎ ÎÎÎÎÎÎ Î Î Î Î ÎÎÎÎÎÎ Î Î Î Î Î Î ÎÎÎ ÎÎ ÎÎÎÎÎÎ Î Î Î Î ÎÎÎÎÎÎ Î Î Î Î Î Î ÎÎÎ tDH tDS D0–D17 W1 W2 tDS W3 W[n+2] W4 tsk1 (see Note A) RCLK 1 2 W[n+3] tDS W[n+4] W D – 1+ 1 2 W D – 1+ 2 2 W tDS D – 1+ 3 2 W[D-m-2] W[D-m-1] W[D-m] tENH W[D-m+1] W[D-m+2] W[D] W[D+1] tsk2 (see Note B) 3 1 2 REN tA Q0–Q17 W1 Data in Output Register OR × POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 tREF × WEN × 2 × 1 SN74V263, SN74V273, SN74V283, SN74V293 8192 18, 16384 18, 32768 18, 65536 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES 1 tENS SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 32 WCLK tPAES PAE tHF HF tPAFS PAF tWFF IR NOTES: A. tsk1 is the minimum time between a rising WCLK edge and a rising RCLK edge to ensure that OR goes low after two RCLK cycles + tREF. If the time between the rising edge of WLCK and the rising edge of RCLK is less than tsk1, OR deassertion might be delayed one additional RCLK cycle. B. tsk2 is the minimum time between a rising WCLK edge and a rising RCLK edge to ensure that PAE goes high after one RCLK cycle + tPAES. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tsk2, PAE deassertion might be delayed one additional RCLK cycle. C. LD = high, OE = low D. n = PAE offset, m = PAF offset, D = maximum FIFO depth E. If ×18 input or ×18 output bus width is selected, D = 8193 for the SN74V263, D = 16385 for the SN74V273, D = 32769 for the SN74V283, and D = 65537 for the SN74V293. If both ×9 input and ×9 output bus widths are selected, D = 16385 for the SN74V263, D = 32769 for the SN74V273, D = 65537 for the SN74V283, and D = 131073 for the SN74V293. F. First-data-word latency: tsk1 + 2* TRCLK + tREF Figure 9. Write-Cycle and First-Data-Word-Latency Timing (FWFT Mode) WCLK 1 tENH 2 tsk2 (see Note B) tsk1 (see Note A) tENS WEN ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tDH tDS D0–D17 WD RCLK 1 2 tENS tENS REN OE tA tOHZ Q0–Q17 W1 tA tA tA tA tA W1 W2 W3 Wm+2 W[m+3] W[m+4] W D – 1+ 1 2 W D – 1+ 2 2 W[D-n-1] W[D-n] W[D-n+1] W[D-n+2] W[D-1] WD tREF tWFF IR NOTES: A. tsk1 is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that IR goes low after one WCLK cycle + tWFF. If the time between the rising edge of RLCK and the rising edge of WCLK is less than tsk1, IR assertion might be delayed an additional WCLK cycle. B. tsk2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to go high after one WCLK cycle + tPAFS. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tsk2, PAF deassertion may be delayed an additional WCLK cycle. C. LD = high D. n = PAE offset, m = PAF offset, D = maximum FIFO depth E. If ×18 input or ×18 output bus width is selected, D = 8193 for the SN74V263, D = 16385 for the SN74V273, D = 32769 for the SN74V283, and D = 65537 for the SN74V293. If both ×9 input and ×9 output bus widths are selected, D = 16385 for the SN74V263, D = 32769 for the SN74V273, D = 65537 for the SN74V283, and D = 131073 for the SN74V293. 33 Figure 10. Read Timing (First-Word Fall-Through Mode) × tWFF SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 tPAFS PAF × tHF HF × tPAES PAE × OR SN74V263, SN74V273, SN74V283, SN74V293 8192 18, 16384 18, 32768 18, 65536 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 tOE SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 1 RCLK 2 tRTS tENH tENS tENH tENS REN tA Q0–Qn tA Wx Wx + 1 W1 (see Note C) tsk2 1 WCLK tA W2 (see Note C) 2 tRTS WEN tENS tENH RT tREF tREF EF tPAES PAE tHF HF tPAFS PAF Retransmit setup is complete after EF returns high; only then can a read operation begin. OE = low W1 = first word written to the FIFO after master reset, W2 = second word written to the FIFO after master reset No more than (D – 2) words may be written to the FIFO between reset (master or partial) and retransmit setup. Therefore, FF is high throughout the retransmit setup procedure. If ×18 input or ×18 output bus width is selected, D = 8192 for the SN74V263, D = 16384 for the SN74V273, D = 32768 for the SN74V283, and D = 65536 for the SN74V293. If both ×9 input and ×9 output bus widths are selected, D = 16384 for the SN74V263, D = 32768 for the SN74V273, D = 65536 for the SN74V283, and D = 131072 for the SN74V293. E. There must be at least two words written to and two words read from the FIFO before a retransmit operation can be invoked. F. RM is set high during MRS. NOTES: A. B. C. D. Figure 11. Retransmit Timing (Standard Mode) 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 tENS 3 2 1 RCLK tRTS tENH tENS tENH 4 REN tA Q0–Qn Wx Wx + 1 tA W1 (see Note D) tA tA W2 (see Note D) W3 (see Note D) W4 tsk2 1 WCLK 2 tRTS WEN tENS tENH RT tREF tREF OR tPAES PAE tHF HF tPAFS PAF NOTES: G. Retransmit setup is complete after OR returns low. H. No more than (D – 2) words can be written to the FIFO between reset (master or partial) and retransmit setup. Therefore, IR is low throughout the retransmit setup procedure. If ×18 input or ×18 output bus width is selected, D = 8193 for the SN74V263, D = 16385 for the SN74V273, D = 32769 for the SN74V283, and D = 65537 for the SN74V293 If both ×9 input and ×9 output bus widths are selected, D = 16385 for the SN74V263, D = 32769 for the SN74V273, D = 65537 for the SN74V283, and D = 131073 for the SN74V293. I. OE = low J. W1, W2, W3 = first, second, and third words written to the FIFO after master reset K. There must be at least two words written to the FIFO before a retransmit operation can be invoked. L. RM is set high during MRS. Figure 12. Retransmit Timing (FWFT Mode) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 35 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 RCLK 2 1 3 tENS tENH REN tA Q0–Qn Wx tA Wx + 1 W1 tA tA W2 (see Note C) W3 (see Note C) tA W4 tsk2 1 WCLK 2 tRTS WEN tENH tENS RT EF (see Note A) tPAES PAE tHF HF tPAFS PAF NOTES: A. If the FIFO is empty at the point of retransmit, EF is updated based on RCLK (retransmit clock cycle). Valid data also appears on the output. B. OE = low, enables data to be read on outputs Q0–Qn C. W2 = second word written to the FIFO after master reset, W3 = third word written to the FIFO after master reset D. No more than (D – 2) words may be written to the FIFO between reset (master or partial) and retransmit setup. Therefore, FF is high throughout the retransmit setup procedure. If ×18 input or ×18 output bus width is selected, D = 8192 for the SN74V263, D = 16384 for the SN74V273, D = 32768 for the SN74V283, and D = 65536 for the SN74V293. If both ×9 input and ×9 output bus widths are selected, D = 16384 for the SN74V263, D = 32768 for the SN74V273, D = 65536 for the SN74V283, and D = 131072 for the SN74V293. E. There must be at least two words written to and read from the FIFO before a retransmit operation can be invoked. F. RM is set low during MRS. Figure 13. Zero-Latency Retransmit Timing (Standard Mode) 36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 1 RCLK 2 4 3 5 tENH tENS REN tA Q0–Qn Wx Wx + 1 tA W1 tA W2 (see Note D) W3 (see Note D) tA W4 (see Note D) tA W5 tsk2 1 WCLK 2 tRTS WEN tENS tENH RT OR tPAES PAE tHF HF tPAFS PAF NOTES: A. If the part is empty at the point of retransmit, OR is updated based on RCLK (retransmit clock cycle). Valid data also appears on the output. B. No more than (D – 2) words may be written to the FIFO between reset (master or partial) and retransmit setup. Therefore, IR is low throughout the retransmit setup procedure. If ×18 input or ×18 output bus width is selected, D = 8193 for the SN74V263, D = 16385 for the SN74V273, D = 32769 for the SN74V283, and D = 65537 for the SN74V293. If both ×9 input and ×9 output bus widths are selected, D = 16385 for the SN74V263, D = 32769 for the SN74V273, D = 65537 for the SN74V283, and D = 131073 for the SN74V293. C. OE = low D. W1, W2, W3 = first, second, and third words written to the FIFO after master reset. E. There must be at least two words written to the FIFO before a retransmit operation can be invoked. F. RM is set low during MRS. Figure 14. Zero-Latency Retransmit Timing (FWFT Mode) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 37 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 WCLK tENS tENH tENH tLDH tLDH SEN tLDS LD tDS SI tDH Bit 0 Bit x (see Note A) Bit 0 Bit x (see Note A) Empty Offset Full Offset NOTES: A. ×9 to ×9 mode: x = 13 for the SN74V263, x = 14 for the SN74V273, x = 15 for the SN74V283, and x = 16 for the SN74V293 B. All other modes: x = 12 for the SN74V263, x = 13 for the SN74V273, x = 14 for the SN74V283, and x = 15 for the SN74V293 Figure 15. Serial Loading of Programmable Flag Registers (FWFT and Standard Modes) tCLK tCLKH tCLKL WCLK tLDS tLDH tLDH LD tENS tENH tENH WEN tDS tDS tDS tDH tDH tDS tDH tDH D0–D16 PAE Offset (LSB) PAE Offset (MSB) PAF Offset (LSB) PAF Offset (MSB) NOTE A: This diagram is based on programming the SN74V293 ×18 bus width. Add one additional cycle to both the PAE offset and PAF offset for ×9 bus width. Figure 16. Parallel Loading of Programmable Flag Registers (FWFT and Standard Modes) 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 tCLK tCLKH tCLKL RCLK tLDS tLDH tLDH tENH tENH LD tENS REN tA Q0–Q16 Data In Output Register tA PAE Offset (LSB) tA PAE Offset (MSB) tA PAF Offset (LSB) PAF Offset (MSB) NOTES: A. OE = low B. This diagram is based on programming the SN74V293 ×18 bus width. Add one additional cycle to both the PAE offset and PAF offset for ×9 bus width. Figure 17. Parallel Read of Programmable Flag Registers (FWFT and Standard Modes) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 39 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 tCLKH tCLKL WCLK 1 tENS 1 2 2 tENH WEN tPAFS PAF tPAES D – m Words in FIFO (see Notes A and B) D – (m + 1) Words in FIFO (see Notes A and B) tsk2 (see Note C) D – (m + 1) Words in FIFO (see Notes A and B) RCLK tENS tENH REN NOTES: A. m = PAF offset B. D = maximum FIFO depth In FWFT mode: If ×18 input or ×18 output bus width is selected, D = 8193 for the SN74V263, D = 16385 for the SN74V273, D = 32769 for the SN74V283, and D = 65537 for the SN74V293. If both ×9 input and ×9 output bus widths are selected, D = 16385 for the SN74V263, D = 32769 for the SN74V273, D = 65537 for the SN74V283, and D = 131073 for the SN74V293. In standard mode: If ×18 input or ×18 output bus width is selected, D = 8192 for the SN74V263, D = 16384 for the SN74V273, D = 32768 for the SN74V283, and D = 65536 for the SN74V293. If both ×9 Input and ×9 output bus widths are selected, D = 16384 for the SN74V263, D = 32768 for the SN74V273, D = 65536 for the SN74V283, and D = 131072 for the SN74V293. C. tsk2 is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that PAF goes high (after one WCLK cycle + tPAFS). If the time between the rising edge of RCLK and the rising edge of WCLK is less than tsk2, the PAF deassertion time may be delayed one additional WCLK cycle. D. PAF is asserted and updated on the rising edge of WCLK only. E. Select this mode by setting PFM high during master reset. Figure 18. Synchronous Programmable Almost-Full Flag Timing (FWFT and Standard Modes) 40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 tCLKH tCLKL WCLK tENS tENH WEN n Words in FIFO (see Note B) n + 1 Words in FIFO (see Note C) n Words in FIFO (see Note B) n + 1 Words in FIFO (see Note C) PAE n Words in FIFO (see Note B) n + 1 Words in FIFO (see Note C) tsk2 (see Note D) tPAES 1 RCLK tPAES 2 1 tENS 2 tENH REN NOTES: A. B. C. D. n = PAE offset For standard mode For FWFT mode tsk2 is the minimum time between a rising WCLK edge and a rising RCLK edge to ensure that PAE goes high (after one RCLK cycle + tPAES). If the time between the rising edge of WCLK and the rising edge of RCLK is less than tsk2, the PAE deassertion can be delayed one additional RCLK cycle. E. PAE is asserted and updated on the rising edge of RCLK only. F. Select this mode by setting PFM high during master reset. Figure 19. Synchronous Programmable Almost-Empty Flag Timing (FWFT and Standard Modes) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 41 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 tCLKH tCLKL WCLK tENS tENH WEN tPAFA PAF D – (m + 1) Words in FIFO D – m Words in FIFO D – (m + 1) Words in FIFO tPAFA RCLK tENS REN NOTES: A. m = PAF offset B. D = maximum FIFO depth In FWFT mode: If ×18 input or ×18 output bus width is selected, D = 8193 for the SN74V263, D = 16385 for the SN74V273, D = 32769 for the SN74V283, and D = 65537 for the SN74V293. If both ×9 input and ×9 output bus widths are selected, D = 16385 for the SN74V263, D = 32769 for the SN74V273, D = 65537 for the SN74V283, and D = 131073 for the SN74V293. In standard mode: If ×18 input or ×18 output bus width is selected, D = 8192 for the SN74V263, D = 16384 for the SN74V273, D = 32768 for the SN74V283, and D = 65536 for the SN74V293. If both ×9 input and ×9 output bus widths are selected, D = 16384 for the SN74V263, D = 32768 for the SN74V273, D = 65536 for the SN74V283, and D = 131072 for the SN74V293. C. PAF is asserted to low on WCLK transition and reset to high on RCLK transition. D. Select this mode by setting PFM low during master reset. Figure 20. Asynchronous Programmable Almost-Full Flag Timing (FWFT and Standard Modes) 42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 tCLKH tCLKL WCLK tENS tENH WEN PAE n Words in FIFO (see Note B) n+1 Words in FIFO (see Note C) tPAEA n + 1 Words in FIFO (see Note B) n + 2 Words in FIFO (see Note C) tPAEA n Words in FIFO (see Note B) n + 1 Words in FIFO (see Note C) RCLK tENS REN NOTES: A. B. C. D. E. n = PAE offset For standard mode For FWFT mode PAE is asserted low on RCLK transition and reset to high on WCLK transition. Select this mode by setting PFM low during master reset. Figure 21. Asynchronous Programmable Almost-Empty Flag Timing (FWFT and Standard Modes) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 43 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 tCLKH tCLKL WCLK tENS tENH WEN tHF HF D + 1 Words in FIFO (see Note A) 2 D+1 + 1 Words in FIFO (see Note B) 2 D/2 Words in FIFO (see Note A) D/2 Words in FIFO (see Note A) D+1 Words in FIFO (see Note B) 2 tHF D + 1 Words in FIFO (see Note B) 2 RCLK tENS REN NOTES: A. In standard mode: D = maximum FIFO depth. If ×18 input or ×18 output bus width is selected, D = 8192 for the SN74V263, D = 16384 for the SN74V273, D = 32768 for the SN74V283, and D = 65536 for the SN74V293. If both ×9 input and ×9 output bus widths are selected, D = 16384 for the SN74V263, D = 32768 for the SN74V273, D = 65536 for the SN74V283, and D = 131072 for the SN74V293. B. In FWFT mode: D = maximum FIFO depth. If ×18 input or ×18 output bus width is selected, D = 8193 for the SN74V263, D = 16385 for the SN74V273, D = 32769 for the SN74V283, and D = 65537 for the SN74V293. If both ×9 input and ×9 output bus widths are selected, D = 16385 for the SN74V263, D = 32769 for the SN74V273, D = 65537 for the SN74V283, and D = 131073 for the SN74V293. Figure 22. Half-Full Flag Timing (FWFT and Standard Modes) 44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 optional configurations width expansion configuration Word width can be increased by connecting the control signals of multiple devices. Status flags can be detected from any one device. The exceptions are the the IR and OR functions in FWFT mode and EF and FF functions in standard mode. Because of variations in skew between RCLK and WCLK, it is possible for EF/FF deassertion and IR/OR assertion to vary by one cycle between FIFOs. In standard mode, such problems can be avoided by creating composite flags, that is, ANDing EF of every FIFO and separately ANDing FF of every FIFO. In FWFT mode, composite flags can be created by ORing OR of every FIFO and separately ORing IR of every FIFO. Figure 23 demonstrates a width expansion using two SN74V263, SN74V273, SN74V283, and SN74V293 devices. If ×18 input or ×18 output bus width is selected, D0–D17 from each device form a 36-bit-wide input bus, and Q0–Q17 from each device form a 36-bit-wide output bus. If both ×9 input and ×9 output bus widths are selected, D0–D8 from each device form an 18-bit-wide input bus, and Q0–Q8 from each device form an 18-bit-wide output bus. Any word width can be attained by adding additional SN74V263, SN74V273, SN74V283, and SN74V293 devices. Partial Reset (PRS) Master Reset (MRS) First-Word Fall-Through or Serial Input (FWFT/SI) Retransmit (RT) (Dm + 1) – Dn Data In m+n D0–Dm m n Read Clock (RCLK) Write Clock (WCLK) Read Enable (REN) Write Enable (WEN) Output Enable (OE) Load (LD) Full Flag/Input Ready 1 (FF/IR) Gate Full Flag/Input Ready 2 (FF/IR) SN74V263 SN74V273 SN74V283 SN74V293 SN74V263 SN74V273 SN74V283 SN74V293 Programmable (PAE) Empty Flag/Output Ready 1 (EF/OR) Empty Flag/Output Ready 2 Gate (EF/OR) Programmable (see Note A) Almost-Full Flag (PAF) Half-Full Flag (HF) FIFO 1 (Qm + 1) – Qn m+n n m FIFO 2 (see Note A) Data Out Q0–Qm NOTES: A. Use an OR gate in FWFT mode and an AND gate in standard mode. B. Do not connect any output control signals together directly. C. FIFO 1 and FIFO 2 must be the same depth, but can be different word widths. Figure 23. Width-Expansion Block Diagam (For the ×18 Input or ×18 Output Bus Width: 8192 × 36, 16384 × 36, 32768 × 36, and 65536 × 36) (For Both ×9 Input and ×9 Output Bus Widths: 16284 × 18, 32768 × 18, 65536 × 18, and 131072 × 18) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 45 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 depth-expansion configuration (FWFT mode only) The SN74V263 can be adapted easily to applications requiring depths greater than 8192 when the ×18 input or ×18 output bus width is selected, 16384 for the SN74V273, 32768 for the SN74V283, and 65536 for the SN74V293. When both ×9 input and ×9 output bus widths are selected, depths greater than 16384 can be adapted for the SN74V263, 32768 for the SN74V273, 65536 for the SN74V283, and 131072 for the SN74V293. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next), with no external logic necessary. The resulting configuration provides a total depth equivalent to the sum of the dpths associated with each single FIFO. Figure 24 shows a depth expansion using two SN74V263, SN74V273, SN74V283, and SN74V293 devices. Care should be taken to select FWFT mode during master reset for all FIFOs in the depth-expansion configuration. The first word written to an empty configuration passes from one FIFO to the next (ripple down) until it finally appears at the outputs of the last FIFO in the chain. No read operation is necessary, but the RCLK of each FIFO must be free running. Each time the data word appears at the outputs of one FIFO, that device’s OR line goes low, enabling a write to the next FIFO in line. FWFT/SI Transfer Clock Write Clock Write Enable Input Ready Data In n FWFT/SI WCLK WEN IR Dn FWFT/SI WCLK RCLK OR SN74V263 SN74V273 REN SN74V283 OE SN74V293 Qn WEN IR GND n SN74V263 SN74V273 SN74V283 SN74V293 Dn Read Clock RCLK Read Enable REN Output Ready OR Output Enable OE Qn n Data Out Figure 24. Depth-Expansion Block Diagram (For the ×18 Input or ×18 Output Bus Width: 16384 × 18, 32768 × 18, 65536 × 18, and 131072 × 18) (For Both ×9 Input and ×9 Output Bus Width: 32768 × 9, 65536 × 9, 131072 × 9, and 262144 × 9) For an empty expansion configuration, the amount of time it takes for OR of the last FIFO in the chain to go low (i.e., valid data to appear on the last FIFO’s outputs) after a word has been written to the first FIFO is the sum of the delays for each FIFO: (N – 1) × (4 × transfer clock) + 3 × TRCLK where N is the number of FIFOs in the expansion and TRCLK is the RCLK period. Note that extra cycles should be added for the possibility that the tsk1 specification is not met between WCLK and transfer clock, or RCLK and transfer clock, for the OR flag. The ripple-down delay is noticeable only for the first word written to an empty depth-expansion configuration. There is no delay evident for subsequent words written to the configuration. The first free location created by reading from a full-depth-expansion configuration bubbles up from the last FIFO to the previous one until it finally moves into the first FIFO of the chain. Each time a free location is created in one FIFO of the chain, that FIFO’s IR line goes low, enabling the preceding FIFO to write a word to fill it. For a full-expansion configuration, the amount of time it takes for IR of the first FIFO in the chain to go low after a word has been read from the last FIFO is the sum of the delays for each individual FIFO: (N – 1) × (3 × transfer clock) + 2TWCLK where N is the number of FIFOs in the expansion and TWCLK is the WCLK period. Note that additional cycles should be added for the possibility that the tsk1 specification is not met between RCLK and transfer clock, or WCLK and transfer clock, for the IR flag. 46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 depth-expansion configuration (FWFT mode only) (continued) The transfer clock line should be tied to either WCLK or RCLK, whichever is faster. Both these actions result in data moving as quickly as possible to the end of the chain and free locations moving to the beginning of the chain. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 47 PACKAGE OPTION ADDENDUM www.ti.com 4-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) SN74V263-10GGM SN74V263-10PZA SN74V263-15GGM SN74V263-15PZA Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) Package Type Package Drawing ACTIVE BGA GGM 100 184 None Call TI Level-3-220C-168 HR ACTIVE LQFP PZA 80 90 None Call TI Level-3-220C-168 HR ACTIVE BGA GGM 100 184 None Call TI Level-3-220C-168 HR ACTIVE LQFP PZA 80 90 None Call TI Level-3-220C-168 HR SN74V263-6GGM ACTIVE BGA GGM 100 184 None Call TI Level-3-220C-168 HR SN74V263-6PZA ACTIVE LQFP PZA 80 90 None Call TI Level-3-220C-168 HR SN74V263-7GGM ACTIVE BGA GGM 100 184 None Call TI Level-3-220C-168 HR SN74V263-7PZA ACTIVE LQFP PZA 80 90 None Call TI Level-3-220C-168 HR SN74V273-10GGM ACTIVE BGA GGM 100 184 None Call TI Level-3-220C-168 HR SN74V273-10PZA ACTIVE LQFP PZA 80 90 None Call TI Level-3-220C-168 HR SN74V273-15GGM ACTIVE BGA GGM 100 184 None Call TI Level-3-220C-168 HR SN74V273-15PZA ACTIVE LQFP PZA 80 90 None Call TI Level-3-220C-168 HR SN74V273-6GGM ACTIVE BGA GGM 100 184 None Call TI Level-3-220C-168 HR SN74V273-6PZA ACTIVE LQFP PZA 80 90 None Call TI Level-3-220C-168 HR SN74V273-7GGM ACTIVE BGA GGM 100 184 None Call TI Level-3-220C-168 HR SN74V273-7PZA ACTIVE LQFP PZA 80 90 None Call TI Level-3-220C-168 HR SN74V283-10GGM ACTIVE BGA GGM 100 184 None Call TI Level-3-220C-168 HR SN74V283-10PZA ACTIVE LQFP PZA 80 90 None Call TI Level-3-220C-168 HR SN74V283-15GGM ACTIVE BGA GGM 100 184 None Call TI Level-3-220C-168 HR SN74V283-15PZA ACTIVE LQFP PZA 80 90 None Call TI Level-3-220C-168 HR SN74V283-6GGM ACTIVE BGA GGM 100 184 None Call TI Level-3-220C-168 HR SN74V283-6PZA ACTIVE LQFP PZA 80 90 None Call TI Level-3-220C-168 HR SN74V283-7GGM ACTIVE BGA GGM 100 184 None Call TI Level-3-220C-168 HR SN74V283-7PZA ACTIVE LQFP PZA 80 90 None Call TI Level-3-220C-168 HR SN74V293-10GGM ACTIVE BGA GGM 100 184 None Call TI Level-3-220C-168 HR SN74V293-10PZA ACTIVE LQFP PZA 80 90 None Call TI Level-3-220C-168 HR SN74V293-15GGM ACTIVE BGA GGM 100 184 None Call TI Level-3-220C-168 HR SN74V293-15PZA ACTIVE LQFP PZA 80 90 None Call TI Level-3-220C-168 HR SN74V293-6GGM ACTIVE BGA GGM 100 184 None Call TI Level-3-220C-168 HR SN74V293-6PZA ACTIVE LQFP PZA 80 90 None Call TI Level-3-220C-168 HR SN74V293-7GGM ACTIVE BGA GGM 100 184 None Call TI Level-3-220C-168 HR SN74V293-7PZA ACTIVE LQFP PZA 80 90 None Call TI Level-3-220C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 4-Mar-2005 at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MPBG028B FEBRUARY 1997 – REVISED MAY 2002 GGM (S–PBGA–N100) PLASTIC BALL GRID ARRAY 10,10 SQ 9,90 7,20 TYP 0,80 0,40 K 0,80 J H G F E 0,40 D C B A A1 Corner 1 2 3 4 5 6 7 8 9 10 Bottom View 0,95 0,85 1,40 MAX Seating Plane 0,55 0,45 0,08 0,45 0,35 0,10 4145257–3/C 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice C. MicroStar BGA configuration. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MPQF099 – AUGUST 2000 PZA (S-PQFP-G80) PLASTIC QUAD FLATPACK 0,38 0,22 0,65 60 0,13 M 41 61 40 80 21 0,13 NOM 1 20 12,00 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 0,05 MIN 1,45 1,35 0,25 0° – 7° 0,75 0,45 Seating Plane 0,10 1,60 MAX 4201045/A 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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