TI SN74ABT3614

SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
D
D
D
D
D
D
D
D
Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
Two Independent 64 × 36 Clocked FIFOs
Buffering Data in Opposite Directions
Mailbox-Bypass Register for Each FIFO
Dynamic Port-B Bus Sizing of 36 Bits (Long
Word), 18 Bits (Word), and 9 Bits (Byte)
Selection of Big- or Little-Endian Format for
Word and Byte Bus Sizes
Three Modes of Byte-Order Swapping on
Port B
Programmable Almost-Full and
Almost-Empty Flags
Microprocessor Interface Control Logic
D
D
D
D
D
D
D
D
EFA, FFA, AEA, and AFA Flags
Synchronized by CLKA
EFB, FFB, AEB, and AFB Flags
Synchronized by CLKB
Passive Parity Checking on Each Port
Parity Generation Can Be Selected for Each
Port
Low-Power Advanced BiCMOS Technology
Supports Clock Frequencies up to 67 MHz
Fast Access Times of 10 ns
Package Options Include 120-Pin Thin
Quad Flat (PCB) and 132-Pin Quad Flat
(PQ) Packages
description
The SN74ABT3614 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory. It supports clock
frequencies up to 67 MHz and has read-access times as fast as 10 ns. Two independent 64 × 36 dual-port SRAM
FIFOs in this device buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions
and two programmable flags, almost full (AF) and almost empty (AE) to indicate when a selected number of
words is stored in memory. FIFO data on port B can be input and output in 36-bit, 18-bit, and 9-bit formats, with
a choice of big- or little-endian configurations. Three modes of byte-order swapping are possible with any
bus-size selection. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers.
Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each
port and can be ignored if not desired. Parity generation can be selected for data read from each port.
The SN74ABT3614 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple bidirectional interface between
microprocessors and/or buses controlled by a synchronous interface.
The full flag and almost-full flag of a FIFO are two-stage synchronized to the port clock that writes data to its
array. The empty flag and almost-empty flag of a FIFO are two-stage synchronized to the port clock that reads
data from its array.
The SN74ABT3614 is characterized for operation from 0°C to 70°C.
For more information on this device family, see the following application reports:
•
•
•
•
•
FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control
(literature number SCAA007)
Advanced Bus-Matching/Byte-Swapping Features for Internetworking FIFO Applications (literature
number SCAA014)
Parity-Generate and Parity-Check Features for High-Bandwidth-Computing FIFO Applications
(literature number SCAA015)
Internetworking the SN74ABT3614 (literature number SCAA015)
Metastability Performance of Clocked FIFOs (literature number SCZA004)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
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AFA
FFA
CSA
ENA
CLKA
W/RA
VCC
PGA
PEFA
MBF2
MBA
FS1
FS0
ODD/EVEN
RST
GND
BE
SW1
SW0
SIZ1
SIZ0
MBF1
PEFB
PGB
VCC
W/RB
CLKB
ENB
CSB
FFB
A23
A22
A21
GND
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
GND
A9
A8
A7
VCC
A6
A5
A4
A3
GND
A2
A1
A0
EFA
AEA
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A24
A25
A26
VCC
A27
A28
A29
GND
A30
A31
A32
A33
A34
A35
GND
B35
B34
B33
B32
B31
B30
GND
B29
B28
B27
VCC
B26
B25
B24
B23
PCB PACKAGE
(TOP VIEW)
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
B22
B21
GND
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
GND
B9
B8
B7
VCC
B6
B5
B4
B3
GND
B2
B1
B0
EFB
AEB
AFB
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
AFA
FFA
CSA
ENA
CLKA
W/RA
VCC
PGA
PEFA
GND
MBF2
MBA
FS1
FS0
ODD/EVEN
RST
GND
BE
SW1
SW0
SIZ1
SIZ0
MBF1
GND
PEFB
PGB
VCC
W/RB
CLKB
ENB
CSB
FFB
AFB
PQ PACKAGE†
(TOP VIEW)
17 16 15 14 13 12 11 10 9
GND
AEA
EFA
A0
A1
A2
GND
A3
A4
A5
A6
VCC
A7
A8
A9
GND
A10
A11
VCC
A12
A13
A14
GND
A15
A16
A17
A18
A19
A20
GND
A21
A22
A23
8
7
6
5
4
3
2
18
1 132 130 128
126 124
122 120 118
129
131
125 123
121
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127
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114
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GND
AEB
EFB
B0
B1
B2
GND
B3
B4
B5
B6
VCC
B7
B8
B9
GND
B10
B11
VCC
B12
B13
B14
GND
B15
B16
B17
B18
B19
B20
GND
B21
B22
B23
VCC
A24
A25
A26
GND
A27
A28
A29
VCC
A30
A31
A32
GND
A33
A34
A35
GND
B35
B34
B33
GND
B32
B31
B30
VCC
B29
B28
B27
GND
B26
B25
B24
VCC
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
NC – No internal connection
† Uses Yamaichi socket IC51-1324-828
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
functional block diagram
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
MBF1
ODD/
EVEN
Write
Pointer
Output Register
Device
Control
Bus Matching and
Byte Swapping
RST
PGB
Parity
Generation
Input Register
Mail1
Register
64 × 36
SRAM
PEFB
Parity
Gen/Check
36
Read
Pointer
Status-Flag
Logic
FFA
AFA
EFB
AEB
FIFO1
36
Programmable-Flag
Offset Register
FS0
FS1
A0 – A35
B0 – B35
FIFO2
Status-Flag
Logic
PGA
PEFA
Parity
Gen/Check
36
Write
Pointer
64 × 36
SRAM
Input Register
Parity
Generation
Output Register
Read
Pointer
FFB
AFB
Bus Matching and
Byte Swapping
EFA
AEA
Mail2
Register
MBF2
Port-B
Control
Logic
4
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• DALLAS, TEXAS 75265
CLKB
CSB
W/RB
ENB
BE
SIZ0
SIZ1
SW0
SW1
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
Terminal Functions
TERMINAL
NAME
I/O
A0 – A35
I/O
AEA
O
(port A)
Port-A almost-empty flag. Programmable flag synchronized to CLKA. AEA is low when the number of 36-bit words
in FIFO2 is less than or equal to the value in offset register X.
AEB
O
(port B)
Port-B almost-empty flag. Programmable flag synchronized to CLKB. AEB is low when the number of 36-bit words
in FIFO1 is less than or equal to the value in offset register X.
AFA
O
(port A)
Port-A almost-full flag. Programmable flag synchronized to CLKA. AFA is low when the number of 36-bit empty
locations in FIFO1 is less than or equal to the value in offset register X.
AFB
O
(port B)
Port-B almost-full flag. Programmable flag synchronized to CLKB. AFB is low when the number of 36-bit empty
locations in FIFO2 is less than or equal to the value in offset register X.
B0 – B35
I/O
BE
I
Big-endian select. Selects the bytes on port B used during byte or word data transfer. A low on BE selects the
most-significant bytes on B0 – B35 for use, and a high selects the least-significant bytes.
CLKA
I
Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
or coincident to CLKB. EFA, FFA, AFA, and AEA are synchronized to the low-to-high transition of CLKA.
CLKB
I
Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous
or coincident to CLKA. Port-B byte swapping and data-port-sizing operations are also synchronous to the low-to-high
transition of CLKB. EFB, FFB, AFB, and AEB are synchronized to the low-to-high transition of CLKB.
CSA
I
Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The
A0 – A35 outputs are in the high-impedance state when CSA is high.
CSB
I
Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The
B0 – B35 outputs are in the high-impedance state when CSB is high.
EFA
O
(port A)
Port-A empty flag. EFA is synchronized to the low-to-high transition of CLKA. When EFA is low, FIFO2 is empty and
reads from its memory are disabled. Data can be read from FIFO2 to the output register when EFA is high. EFA is forced
low when the device is reset and is set high by the second low-to-high transition of CLKA after data is loaded into empty
FIFO2 memory.
EFB
O
(port B)
Port-B empty flag. EFB is synchronized to the low-to-high transition of CLKB. When EFB is low, FIFO1 is empty and
reads from its memory are disabled. Data can be read from FIFO1 to the output register when EFB is high. EFB is
forced low when the device is reset and is set high by the second low-to-high transition of CLKB after data is loaded
into empty FIFO1 memory.
ENA
I
Port-A enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A.
ENB
I
Port-B enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.
FFA
O
(port A)
Port-A full flag. FFA is synchronized to the low-to-high transition of CLKA. When FFA is low, FIFO1 is full and writes
to its memory are disabled. FFA is forced low when the device is reset and is set high by the second low-to-high
transition of CLKA after reset.
FFB
O
(port B)
Port-B full flag. FFB is synchronized to the low-to-high transition of CLKB. When FFB is low, FIFO2 is full and writes
to its memory are disabled. FFB is forced low when the device is reset and is set high by the second low-to-high
transition of CLKB after reset.
FS1, FS0
I
Flag offset selects. The low-to-high transition of RST latches the values of FS0 and FS1, which selects one of four
preset values for the AE flag and AF flag offset.
MBA
I
Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When the
A0 – A35 outputs are active, a high level on MBA selects data from the mail2 register for output and a low level selects
FIFO2 output register data for output.
MBF1
O
Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. Writes
to the mail1 register are inhibited while MBF1 is low. MBF1 is set high by a low-to-high transition of CLKB when a port-B
read is selected and both SIZ1 and SIZ0 are high. MBF1 is set high when the device is reset.
MBF2
O
Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. Writes
to the mail2 register are inhibited while MBF2 is low. MBF2 is set high by a low-to-high transition of CLKA when a port-A
read is selected and MBA is high. MBF2 is set high when the device is reset.
DESCRIPTION
Port-A data. The 36-bit bidirectional data port for side A.
Port-B data. The 36-bit bidirectional data port for side B.
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• DALLAS, TEXAS 75265
5
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
Terminal Functions (Continued)
TERMINAL
NAME
I/O
DESCRIPTION
ODD/
EVEN
I
Odd/even parity select. Odd parity is checked on each port when ODD/EVEN is high and even parity is checked when
ODD/EVEN is low. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled
for a read operation.
O
(port A)
Port-A parity-error flag. When any byte applied to terminals A0 – A35 fails parity, PEFA is low. Bytes are organized as
A0 – A8, A9 – A17, A18 – A26, and A27 – A35, with the most-significant bit of each byte serving as the parity bit. The
type of parity checked is determined by the state of the ODD/EVEN input.
The parity trees used to check the A0 – A35 inputs are shared by the mail2 register to generate parity if parity generation
is selected by PGA; therefore, if a mail2 read with parity generation is set up by having W/RA low, MBA high, and PGA
high, the PEFA flag is forced high, regardless of the state of the A0 – A35 inputs.
PEFB
O
(port B)
Port-B parity-error flag. When any valid byte applied to terminals B0 – B35 fails parity, PEFB is low. Bytes are organized
as B0 – B8, B9 – B17, B18 – B26, and B27 – B35, with the most-significant bit of each byte serving as the parity bit. A
byte is valid when it is used by the bus size selected for port B. The type of parity checked is determined by the state
of the ODD/EVEN input.
The parity trees used to check the B0 – B35 inputs are shared by the mail1 register to generate parity if parity generation
is selected by PGB; therefore, if a mail1 read with parity generation is set up by having W/RB low, SIZ1 and SIZ0 high,
and PGB high, the PEFB flag is forced high, regardless of the state of the B0 – B35 inputs.
PGA
I
Port-A parity generation. Parity is generated for data reads from port A when PGA is high. The type of parity generated
is selected by the state of the ODD/EVEN input. Bytes are organized as A0 – A8, A9 – A17, A18 – A26, and A27 – A35.
The generated parity bits are output in the most-significant bit of each byte.
PGB
I
Port-B parity generation. Parity is generated for data reads from port B when PGB is high. The type of parity generated
is selected by the state of the ODD/EVEN input. Bytes are organized as B0 – B8, B9 – B17, B18 – B26, and B27 – B35.
The generated parity bits are output in the most-significant bit of each byte.
RST
I
Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur
while RST is low. This sets the AFA, AFB, MBF1, and MBF2 flags high and the EFA, EFB, AEA, AEB, FFA, and FFB
flags low. The low-to-high transition of RST latches the status of the FS1 and FS0 inputs to select AF flag and AE flag
offset.
SIZ0, SIZ1
I
(port B)
Port-B bus-size selects. The low-to-high transition of CLKB latches the states of SIZ0, SIZ1, and BE, and the following
low-to-high transition of CLKB implements the latched states as a port-B bus size. Port-B bus sizes can be long word,
word, or byte. A high on both SIZ0 and SIZ1 accesses the mailbox registers for a port-B 36-bit write or read.
SW0, SW1
I
(port B)
Port-B byte-swap selects. At the beginning of each long word transfer, one of four modes of byte-order swapping is
selected by SW0 and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order
swapping is possible with any bus-size selection.
W/RA
I
Port-A write/read select. W/RA high selects a write operation and a low selects a read operation on port A for a
low-to-high transition of CLKA. The A0 – A35 outputs are in the high-impedance state when W/RA is high.
W/RB
I
Port-B write/read select. W/RB high selects a write operation and a low selects a read operation on port B for a
low-to-high transition of CLKB. The B0 – B35 outputs are in the high-impedance state when W/RB is high.
PEFA
detailed description
reset
The SN74ABT3614 is reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and four
port-B clock (CLKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A device
reset initializes the internal read and write pointers of each FIFO and forces the full flags (FFA, FFB) low, the
empty flags (EFA, EFB) low, the almost-empty flags (AEA, AEB) low, and the almost-full flags (AFA, AFB) high.
A reset also forces the mailbox flags (MBF1, MBF2) high. After a reset, FFA is set high after two low-to-high
transitions of CLKA and FFB is set high after two low-to-high transitions of CLKB. The device must be reset after
power up before data is written to its memory.
A low-to-high transition on RST loads the almost-full and almost-empty offset register (X) with the value selected
by the flag-select (FS0, FS1) inputs. The values that can be loaded into the register are shown in Table 1.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
reset (continued)
Table 1. Flag Programming
FS1
FS0
RST
AF AND AE FLAG
OFFSET REGISTER (X)
H
H
↑
16
H
L
↑
12
L
H
↑
8
L
L
↑
4
FIFO write/read operation
The state of the port-A data (A0 – A35) outputs is controlled by the port-A chip select (CSA) and the port-A
write/read select (W/RA). The A0 – A35 outputs are in the high-impedance state when either CSA or W/RA is
high. The A0 – A35 outputs are active when both CSA and W/RA are low. Data is loaded into FIFO1 from the
A0– A35 inputs on a low-to-high transition of CLKA when CSA is low, W/RA is high, ENA is high, MBA is low,
and FFA is high. Data is read from FIFO2 to the A0 – A35 outputs by a low-to-high transition of CLKA when CSA
is low, W/RA is low, ENA is high, MBA is low, and EFA is high (see Table 2).
Table 2. Port-A Enable Function Table
CSA
W/RA
ENA
MBA
CLKA
A0 – A35 OUTPUTS
PORT FUNCTION
H
X
X
X
X
In high-impedance state
None
L
H
L
X
X
In high-impedance state
None
L
H
H
L
↑
In high-impedance state
FIFO1 write
L
H
H
H
↑
In high-impedance state
Mail1 write
L
L
L
L
X
Active, FIFO2 output register
None
L
L
H
L
↑
Active, FIFO2 output register
FIFO2 read
L
L
L
H
X
Active, mail2 register
None
L
L
H
H
↑
Active, mail2 register
Mail2 read (set MBF2 high)
The state of the port-B data (B0 – B35) outputs is controlled by the port-B chip select (CSB) and the port-B
write/read select (W/RB). The B0 – B35 outputs are in the high-impedance state when either CSB or W/RB is
high. The B0 – B35 outputs are active when both CSB and W/RB are low. Data is loaded into FIFO2 from the
B0– B35 inputs on a low-to-high transition of CLKB when CSB is low, W/RB is high, ENB is high, FFB is high,
and either SIZ0 or SIZ1 is low. Data is read from FIFO1 to the B0 – B35 outputs by a low-to-high transition of
CLKB when CSB is low, W/RB is low, ENB is high, EFB is high, and either SIZ0 or SIZ1 is low (see Table 3).
The setup- and hold-time constraints to the port clocks for the port-chip selects (CSA, CSB) and write/read
selects (W/RA, W/RB) are only for enabling write and read operations and are not related to high-impedance
control of the data outputs. If a port enable is low during a clock cycle, the port-chip select and write/read select
can change states during the setup- and hold-time window of the cycle.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
FIFO writer/read operation (continued)
Table 3. Port-B Enable Function Table
CSB
W/RB
ENB
SIZ1, SIZ0
CLKB
B0 – B35 OUTPUTS
PORT FUNCTION
H
X
X
X
X
In high-impedance state
None
L
H
L
X
X
In high-impedance state
None
L
H
H
One, both low
↑
In high-impedance state
FIFO2 write
L
H
H
Both high
↑
In high-impedance state
Mail2 write
L
L
L
One, both low
X
Active, FIFO1 output register
None
L
L
H
One, both low
↑
Active, FIFO1 output register
FIFO1 read
L
L
L
Both high
X
Active, mail1 register
None
L
L
H
Both high
↑
Active, mail1 register
Mail1 read (set MBF1 high)
synchronized FIFO flags
Each FIFO flag is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability
by reducing the probability of metastable events on the output when CLKA and CLKB operate asynchronously
to one another. EFA, AEA, FFA, and AFA are synchronized to CLKA. EFB, AEB, FFB, and AFB are synchronized
to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2.
Table 4. FIFO1 Flag Operation
NUMBER OF 36-BIT
WORDS IN FIFO1†
SYNCHRONIZED
TO CLKB
SYNCHRONIZED
TO CLKA
EFB
AEB
AFA
FFA
0
L
L
H
H
1 to X
H
L
H
H
(X + 1) to [64 – (X + 1)]
H
H
H
H
(64 – X) to 63
H
H
L
H
64
H
H
L
L
† X is the value in the AE flag and AF flag offset register.
Table 5. FIFO2 Flag Operation
NUMBER OF 36-BIT
WORDS IN FIFO2†
SYNCHRONIZED
TO CLKA
SYNCHRONIZED
TO CLKB
EFA
AEA
AFB
FFB
0
L
L
H
H
1 to X
H
L
H
H
(X + 1) to [64 – (X + 1)]
H
H
H
H
(64 – X) to 63
H
H
L
H
64
H
H
L
† X is the value in the AE flag and AF flag offset register.
8
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SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
empty flags (EFA, EFB)
The FIFO empty flag is synchronized to the port clock that reads data from its array. When the empty flag is high,
new data can be read to the FIFO output register. When the empty flag is low, the FIFO is empty and attempted
FIFO reads are ignored. When reading FIFO1 with a byte or word size on port B, EFB is set low when the fourth
byte or second word of the last long word is read.
The FIFO read pointer is incremented each time a new word is clocked to the output register. A word written
to a FIFO can be read to the FIFO output register in a minimum of three cycles of the empty-flag synchronizing
clock; therefore, an empty flag is low if a word in memory is the next data to be sent to the FIFO output register
and two cycles of the port clock that reads data from the FIFO have not elapsed since the time the word was
written. The FIFO empty flag is set high by the second low-to-high transition of the synchronizing clock and the
new data word can be read to the FIFO output register in the following cycle.
A low-to-high transition on an empty-flag synchronizing clock begins the first synchronization cycle of a write
if the clock transition occurs at time tsk1, or greater, after the write. Otherwise, the subsequent clock cycle can
be the first synchronization cycle (see Figures 13 and 14).
full flags (FFA, FFB)
The FIFO full flag is synchronized to the port clock that writes data to its array. When the full flag is high, a
memory location is free in the SRAM to receive new data. No memory locations are free when the full flag is
low and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, the write pointer is incremented. From the time a word is read from a FIFO,
the previous memory location is ready to be written in a minimum of three cycles of the full-flag synchronizing
clock. A full flag is low if less than two cycles of the full-flag synchronizing clock have elapsed since the next
memory write location has been read. The second low-to-high transition on the full-flag synchronizing clock after
the read sets the full flag high and data can be written in the following clock cycle.
A low-to-high transition on a full-flag synchronizing clock begins the first synchronization cycle of a read if the
clock transition occurs at time tsk1, or greater, after the read. Otherwise, the subsequent clock cycle can be the
first synchronization cycle (see Figures 15 and 16).
almost-empty flags (AEA, AEB)
The FIFO almost-empty flag is synchronized to the port clock that reads data from its array. The almost-empty
state is defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with
one of four preset values during a device reset (see reset ). An AE flag is low when the FIFO contains X or fewer
long words in memory and is high when the FIFO contains (X + 1) or more long words.
Two low-to-high transitions of the AE-flag synchronizing clock are required after a FIFO write for the AE flag to
reflect the new level of fill; therefore, the AE flag of a FIFO containing (X + 1) or more long words remains low
if two cycles of the synchronizing clock have not elapsed since the write that filled the memory to the (X + 1)
level. An AE flag is set high by the second low-to-high transition of the synchronizing clock after the FIFO write
that fills memory to the (X + 1) level. A low-to-high transition of an AE flag synchronizing clock begins the first
synchronization cycle if it occurs at time tsk2, or greater, after the write that fills the FIFO to (X + 1) long words.
Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figures 17 and
18).
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SCBS126H – JUNE 1992 – REVISED APRIL 2000
almost-full flags (AFA, AFB)
The FIFO almost-full flag is synchronized to the port clock that writes data to its array. The almost-full state is
defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with one of
four preset values during a device reset (see reset ). An almost-full flag is low when the FIFO contains (64 – X)
or more long words in memory and is high when the FIFO contains [64 – (X + 1)] or fewer long words.
Two low-to-high transitions of the AF-flag synchronizing clock are required after a FIFO read for the AF flag to
reflect the new level of fill; therefore, the AF flag of a FIFO containing [64 – (X + 1)] or fewer words remains low
if two cycles of the synchronizing clock have not elapsed since the read that reduced the number of long words
in memory to [64 – (X + 1)]. An AF flag is set high by the second low-to-high transition of the synchronizing clock
after the FIFO read that reduces the number of long words in memory to [64 – (X + 1)]. A low-to-high transition
of an AF-flag synchronizing clock begins the first synchronization cycle if it occurs at time tsk2, or greater, after
the read that reduces the number of long words in memory to [64 – (X + 1)]. Otherwise, the subsequent
synchronizing clock cycle can be the first synchronization cycle (see Figures 19 and 20).
mailbox registers
Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B
without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO
for a port data-transfer operation. A low-to-high transition on CLKA writes A0 – A35 data to the mail1 register
when a port-A write is selected by CSA, W/RA, and ENA, and MBA is high. A low-to-high transition on CLKB
writes B0 – B35 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB and both SIZ0
and SIZ1 are high. Writing data to a mail register sets the corresponding flag (MBF1 or MBF2) low. Attempted
writes to a mail register are ignored while the mail flag is low.
When the port-A data outputs (A0 – A35) are active, the data on the bus comes from the FIFO2 output register
when MBA is low and from the mail2 register when MBA is high. When the port-B data outputs (B0 – B35) are
active, the data on the bus comes from the FIFO1 output register when either one or both SIZ1 and SIZ0 are
low and from the mail2 register when both SIZ1 and SIZ0 are high. The mail1 register flag (MBF1) is set high
by a rising CLKB edge when a port-B read is selected by CSB, W/RB, and ENB and both SIZ1 and SIZ0 are
high. The mail2 register flag (MBF2) is set high by a rising CLKA edge when a port-A read is selected by CSA,
W/RA, and ENA and MBA is high. The data in the mail register remains intact after it is read and changes only
when new data is written to the register.
dynamic bus sizing
The port-B bus can be configured in a 36-bit long word, 18-bit word, or 9-bit byte format for data read from FIFO1
or written to FIFO2. Word- and byte-size bus selections can utilize the most-significant bytes of the bus (big
endian) or least-significant bytes of the bus (little endian). Port-B bus size can be changed dynamically and
synchronous to CLKB to communicate with peripherals of various bus widths.
The levels applied to the port-B bus-size select (SIZ0, SIZ1) inputs and the big-endian select (BE) input are
stored on each CLKB low-to-high transition. The stored port-B bus-size selection is implemented by the next
rising edge on CLKB according to Figure 1.
Only 36-bit long-word data is written to or read from the two FIFO memories on the SN74ABT3614.
Bus-matching operations are done after data is read from the FIFO1 RAM and before data is written to the FIFO2
RAM. Port-B bus sizing does not apply to mail-register operations.
10
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dynamic bus sizing (continued)
A35
BYTE ORDER ON PORT A:
A27 A26
A
B35
BE
SIZ1
SIZ0
X
L
L
A18
A17
B
B27 B26
A
A9
A8
C
B18
B17
B
A0
Write to FIFO1/Read From FIFO2
D
B9
B8
C
B0
Read From FIFO1/Write to FIFO2
D
(a) LONG WORD SIZE
B35
BE
SIZ1
SIZ0
L
L
H
B27 B26
A
B35
B18
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
B17
B
B27 B26
C
B18
B9
B17
D
B9
B8
B0
B8
1st: Read From FIFO1/Write to FIFO2
B0
2nd: Read From FIFO1/Write to FIFO2
(b) WORD SIZE – BIG ENDIAN
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
B35
BE
SIZ1
SIZ0
H
L
H
B27 B26
B35
B27 B26
B18
B18
B17
B9
B8
C
B17
B0
1st: Read From FIFO1/Write to FIFO2
D
B9
B8
A
B0
2nd: Read From FIFO1/Write to FIFO2
B
(c) WORD SIZE – LITTLE ENDIAN
B35
BE
SIZ1
SIZ0
L
H
L
B27 B26
B18
A
B35
B27 B26
B18
B17
B
B35
B27 B26
B18
B17
C
B35
B27 B26
B18
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
B17
B17
D
B9
B9
B9
B9
B8
B8
B8
B8
B0
1st: Read From FIFO1/Write to FIFO2
B0
2nd: Read From FIFO1/Write to FIFO2
B0
3rd: Read From FIFO1/Write to FIFO2
B0
4th: Read From FIFO1/Write to FIFO2
(d) BYTE SIZE – BIG ENDIAN
Figure 1. Dynamic Bus Sizing
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
dynamic bus sizing (continued)
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
B35
BE
SIZ1
SIZ0
H
H
L
B35
B35
B35
B27 B26
B27 B26
B27 B26
B27 B26
B18
B18
B18
B18
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
B17
B17
B17
B17
B9
B9
B9
B9
B8
B0
1st: Read From FIFO1/Write to FIFO2
D
B8
B0
2nd: Read From FIFO1/Write to FIFO2
C
B8
B0
3rd: Read From FIFO1/Write to FIFO2
B
B8
B0
A
4th: Read From FIFO1/Write to FIFO2
(e) BYTE SIZE – LITTLE ENDIAN
Figure 1. Dynamic Bus Sizing (continued)
bus-matching FIFO1 reads
Data is read from the FIFO1 RAM in 36-bit long-word increments. If a long-word bus size is implemented, the
entire long word immediately shifts to the FIFO1 output register. If byte or word size is implemented on port B,
only the first one or two bytes appear on the selected portion of the FIFO1 output register with the rest of the
long word stored in auxiliary registers. In this case, subsequent FIFO1 reads with the same bus-size
implementation output the rest of the long word to the FIFO1 output register in the order shown by Figure 1.
Each FIFO1 read with a new bus-size implementation automatically unloads data from the FIFO1 RAM to its
output register and auxiliary registers. Therefore, implementing a new port-B bus size and performing a FIFO1
read before all bytes or words stored in the auxiliary registers have been read results in a loss of the unread
long-word data.
When reading data from FIFO1 in byte or word format, the unused B0 – B35 outputs remain inactive but static
with the unused FIFO1 output register bits holding the last data value to decrease power consumption.
bus-matching FIFO2 writes
Data is written to the FIFO2 RAM in 36-bit long-word increments. FIFO2 writes with a long-word bus size
immediately store each long word in FIFO2 RAM. Data written to FIFO2 with a byte or word bus size stores the
initial bytes or words in auxiliary registers. The CLKB rising edge that writes the fourth byte or the second word
of long word to FIFO2 also stores the entire long word in FIFO2 RAM. The bytes are arranged in the manner
shown in Figure 1.
Each FIFO2 write with a new bus-size implementation resets the state machine that controls the data flow from
the auxiliary registers to the FIFO2 RAM. Therefore, implementing a new bus size and performing a FIFO2 write
before bytes or words stored in the auxiliary registers have been loaded to FIFO2 RAM results in a loss of data.
12
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port-B mail-register access
In addition to selecting port-B bus sizes for FIFO reads and writes, the port-B bus size select (SIZ0, SIZ1) inputs
also access the mail registers. When both SIZ0 and SIZ1 are high, the mail1 register is accessed for a port-B
long-word read and the mail2 register is accessed for a port-B long-word write. The mail register is accessed
immediately. Any bus-sizing operation that is underway is unaffected by the mail-register access. After the
mail-register access is complete, the previous FIFO access can resume in the next CLKB cycle. The logic
diagram in Figure 2 shows that the previous bus-size selection is preserved when the mail registers are
accessed from port B. A port-B bus size is implemented on each rising CLKB edge according to the states of
SIZ0_Q, SIZ1_Q, and BE_Q.
CLKB
MUX
G1
1
SIZ0_Q
D
Q
SIZ0
SIZ1
SIZ1_Q
BE_Q
1
BE
Figure 2. Logic Diagram for SIZ0, SIZ1, and BE Register
byte swapping
The byte-order arrangement of data read from FIFO1 or data written to FIFO2 can be changed synchronous
to the rising edge of CLKB. Byte-order swapping is not available for mail-register data. Four modes of byte-order
swapping (including no swap) can be done with any data-port-size selection. The order of the bytes is
rearranged within the long word, but the bit order within the bytes remains constant.
Byte arrangement is chosen by the port-B swap select (SW0, SW1) inputs on a CLKB rising edge that reads
a new long word from FIFO1 or writes a new long word to FIFO2. The byte order chosen on the first byte or first
word of a new long-word read from FIFO1 or written to FIFO2 is maintained until the entire long word is
transferred, regardless of the SW0 and SW1 states during subsequent writes or reads. Figure 3 is an example
of the byte-order swapping available for long words. Performing a byte swap and bus size simultaneously for
a FIFO1 read first rearranges the bytes as shown in Figure 3, then outputs the bytes as shown in Figure 1.
Simultaneous bus-sizing and byte-swapping operations for FIFO2 writes load the data according to Figure 1,
then swap the bytes as shown in Figure 3 when the long word is loaded to FIFO2 RAM.
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
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SCBS126H – JUNE 1992 – REVISED APRIL 2000
byte swapping (continued)
A35
SW1
SW0
L
L
A27 A26
A18
A17
A9
A8
A0
A
B
C
D
A
B
C
D
B35
B27 B26
B18
B17
B9
B8
B0
A18
A17
A9
A8
A0
(a) NO SWAP
A35
SW1
SW0
L
H
A27 A26
A
B
C
D
D
C
B
A
B35
B27 B26
B18
B17
B9
B8
B0
A18
A17
A9
A8
A0
(b) BYTE SWAP
A35
SW1
SW0
H
L
A27 A26
A
B
C
D
C
D
A
B
B35
B27 B26
B18
B17
B9
B8
B0
A17
A9
A8
A0
(c) WORD SWAP
A35
SW1
SW0
H
H
B35
A27 A26
A18
A
B
C
D
B
A
D
C
B27 B26
B18
B17
B9
B8
(d) BYTE-WORD SWAP
Figure 3. Byte Swapping (Long-Word Size Example)
14
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
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SCBS126H – JUNE 1992 – REVISED APRIL 2000
parity checking
The port-A data inputs (A0 – A35) and port-B data inputs (B0 – B35) each have four parity trees to check the parity
of incoming (or outgoing) data. A parity failure on one or more bytes of the port-A data bus is reported by a low
level on the port-A parity error flag (PEFA). A parity failure on one or more bytes of the port-B data inputs that
are valid for the bus-size implementation is reported by a low level on the port-B parity-error flag (PEFB). Oddor even-parity checking can be selected, and the parity-error flags can be ignored if this feature is not desired.
Parity status is checked on each input bus according to the level of the odd/even parity (ODD/EVEN) select
input. A parity error on one or more valid bytes of a port is reported by a low level on the corresponding
port-parity-error flag (PEFA, PEFB) output. Port-A bytes are arranged as A0 – A8, A9 – A17, A18 – A26, and
A27– A35. Port-B bytes are arranged as B0 – B8, B9 – B17, B18 – B26, and B27 – B35, and its valid bytes are
those used in a port-B bus-size implementation. When odd/even parity is selected, a port parity-error flag
(PEFA, PEFB) is low if any valid byte on the port has an odd/even number of low levels applied to the bits.
The four parity trees used to check the A0 – A35 inputs are shared by the mail2 register when parity generation
is selected for port-A reads (PGA = high). When a port-A read from the mail2 register with parity generation is
selected with CSA low, ENA high, W/RA low, MBA high, and PGA high, the port-A parity-error flag (PEFA) is
held high, regardless of the levels applied to the A0 – A35 inputs. Likewise, the parity trees used to check
the B0 – B35 inputs are shared by the mail1 register when parity generation is selected for port-B reads
(PGB = high). When a port-B read from the mail1 register with parity generation is selected with CSB low, ENB
high, and W/RB low, both SIZ0 and SIZ1 high, and PGB high, the port-B parity-error flag (PEFB) is held high,
regardless of the levels applied to the B0 – B35 inputs.
parity generation
A high level on the port-A parity-generate select (PGA) or port-B parity-generate select (PGB) enables the
SN74ABT3614 to generate parity bits for port reads from a FIFO or mailbox register. Port-A bytes are arranged
as A0 – A8, A9 – A17, A18 – A26, and A27 – A35, with the most-significant bit of each byte used as the parity bit.
Port-B bytes are arranged as B0 – B8, B9 – B17, B18 – B26, and B27 – B35, with the most-significant bit of each
byte used as the parity bit. A write to a FIFO or mail register stores the levels applied to all nine inputs of a byte,
regardless of the state of the parity-generate select (PGA, PGB) inputs. When data is read from a port with parity
generation selected, the lower eight bits of each byte are used to generate a parity bit according to the level on
the ODD/EVEN select. The generated parity bits are substituted for the levels originally written to the
most-significant bits of each byte as the word is read to the data outputs.
Parity bits for FIFO data are generated after the data is read from SRAM and before the data is written to the
output register. The port-A parity-generate select (PGA) and odd/even parity select (ODD/EVEN) have setupand hold-time constraints to the port-A clock (CLKA) and the port-B parity generate select (PGB) and
ODD/EVEN have setup- and hold-time constraints to the port-B clock (CLKB). These timing constraints apply
only for a rising clock edge used to read a new long word to the FIFO output register.
The circuit used to generate parity for the mail1 data is shared by the port-B bus (B0 – B35) to check parity. The
circuit used to generate parity for the mail2 data is shared by the port-A bus (A0 – A35) to check parity. The
shared parity trees of a port are used to generate parity bits for the data in a mail register when the port chip
select (CSA, CSB) is low, enable (ENA, ENB) is high, write/read select (W/RA, W/RB) input is low, the mail
register is selected (MBA is high for port A; both SIZ0 and SIZ1 are high for port B), and port parity-generate
select (PGA, PGB) is high. Generating parity for mail register data does not change the contents of the register.
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
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SCBS126H – JUNE 1992 – REVISED APRIL 2000
CLKA
th(RS)
CLKB
tsu(RS)
th(FS)
tsu(FS)
RST
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
FS1, FS0
0,1
tpd(C-FF)
tpd(C-FF)
FFA
tpd(C-EF)
EFA
tpd(C-FF)
tpd(C-FF)
FFB
tpd(C-EF)
EFB
MBF1,
MBF2
tpd(R-F)
tpd(C-AE)
AEA
tpd(C-AF)
AFA
tpd(C-AE)
AEB
tpd(C-AF)
AFB
Figure 4. Device Reset Loading the X Register With the Value of Eight
16
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
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SCBS126H – JUNE 1992 – REVISED APRIL 2000
tc
tw(CLKH)
tw(CLKL)
CLKA
FFA
CSA
W/RA
MBA
ENA
High
ÌÌÌ
ÌÌÌ
ÎÎÎÎÎÎÎ ÌÌÌ
ÏÏÏÏÏÏ
ÎÎÎÎÎÎÎ
ÌÌÌ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÌÌÌ
ÎÎÎÎÎÎ
ÏÏÏÏÏÏÏ
ÌÌÌ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÌÌÌÌÌÌÌ ÏÏÏÏÏÏ ÎÎÎÎÎÎ
ÌÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌ
ÌÌ
ÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌ
Ì
tsu(EN)
th(EN)
tsu(EN)
th(EN)
tsu(EN)
th(EN)
tsu(EN)
th(EN)
tsu(D)
A0 – A35
ODD/
EVEN
th(EN)
tsu(EN)
th(D)
W1†
W2†
tpd(D-PE)
PEFA
th(EN)
tsu(EN)
No Operation
tpd(D-PE)
Valid
Valid
† Written to FIFO1
Figure 5. Port-A Write-Cycle Timing for FIFO1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
CLKB
FFB
High
tsu(EN)
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÌÌÌÌÌÌ ÏÏÏÏÏÏÏ ÎÎÎÎ
ÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌ
ÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌ
CSB
tsu(EN)
W/RB
tsu(EN)
th(EN)
tsu(SW)
th(SW)
th(EN)
tsu(EN)
ENB
SW1,
SW0
tsu(SZ)
th(SZ)
BE
tsu(SZ)
SIZ1,
SIZ0
th(SZ)
(0, 0)
(0, 0)
tsu(D)
Not (1, 1)†
th(D)
B0 – B35
ODD/
EVEN
tpd(C-PE)
tpd(D-PE)
PEFB
Valid
Valid
† SIZ0 = H and SIZ1 = H writes data to the mail2 register.
DATA SWAP TABLE FOR LONG-WORD WRITES TO FIFO2
SWAP MODE
DATA WRITTEN TO FIFO2
DATA READ FROM FIFO2
SW1
SW0
B35 – B27
B26 – B18
B17 – B9
B8 – B0
A35 – A27
A26 – A18
A17 – A9
A8 – A0
L
L
A
B
C
D
A
B
C
D
L
H
D
C
B
A
A
B
C
D
H
L
C
D
A
B
A
B
C
D
H
H
B
A
D
C
A
B
C
D
Figure 6. Port-B Long-Word Write-Cycle Timing for FIFO2
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
CLKB
High
FFB
tsu(EN)
th(EN)
CSB
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÌÌÌÌÌÌ ÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎ
ÌÌÌÌÌÌ
ÏÏÏÏÏ
ÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌ
ÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌ
tsu(EN)
W/RB
tsu(EN)
th(EN)
tsu(SW)
th(SW)
tsu(EN)
th(EN)
ENB
SW1, SW0
tsu(SZ)
th(SZ)
tsu(SZ)
th(SZ)
tsu(SZ)
th(SZ)
tsu(SZ)
th(SZ)
BE
(0, 1)
SIZ1, SIZ0
Little
Endian
Big
Endian
Not (1, 1)†
(0, 1)
tsu(D)
th(D)
tsu(D)
th(D)
B0 – B17
B18 – B35
ODD/EVEN
tpd(C-PE)
tpd(D-PE)
Valid
PEFB
Valid
† SIZ0 = H and SIZ1 = H writes data to the mail2 register.
NOTE A: PEFB indicates parity error for the following bytes: B35 – B27 and B26 – B18 for big-endian bus, and B17 – B9 and B8 – B0 for littleendian bus.
DATA SWAP TABLE FOR WORD WRITES TO FIFO2
SWAP MODE
SW1
DATA WRITTEN TO FIFO2
WRITE
NO.
NO
SW0
BIG ENDIAN
DATA READ FROM FIFO2
LITTLE ENDIAN
B35 – B27
B26 – B18
B17 – B9
B8 – B0
A35 – A27
A26 – A18
A17 – A9
A8 – A0
A
C
B
D
C
A
D
B
A
B
C
D
L
L
1
2
L
H
1
2
D
B
C
A
B
D
A
C
A
B
C
D
H
L
1
2
C
A
D
B
A
C
B
D
A
B
C
D
H
H
1
2
B
D
A
C
D
B
C
A
A
B
C
D
Figure 7. Port-B Word Write-Cycle Timing for FIFO2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
CLKB
FFB
High
tsu(EN)
th(EN)
CSB
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÏÏÏÏ
ÎÎÎÎÎÎÎ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÏÏÏÏ
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌÌÌÌÌ
ÌÌ ÌÌÌÌ ÌÌÌÌ ÌÌÌÌ ÌÌÌÌÌÌÌÌ
ÌÌ ÌÌÌÌ ÌÌÌÌ ÌÌÌÌ ÌÌÌ ÌÌÌ
ÌÌÌÌÌÌÌ ÌÌÌÌ ÌÌÌÌ ÌÌÌ ÌÌÌ
ÌÌÌÌÌÌÌ ÌÌÌÌ ÌÌÌÌ ÌÌÌ ÌÌÌ
ÌÌÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌ ÌÌÌ
ÌÌÌ ÌÌÌ
ÌÌÌ ÌÌ
ÌÌ
tsu(EN)
W/RB
ENB
SW1, SW0
tsu(SZ)
BE
Little
Endian
B0 – B8
Big
Endian
B27 – B35
ODD/EVEN
th(EN)
tsu(SW)
th(EN)
th(SZ)
tsu(SZ)
th(SZ)
th(SZ)
tsu(SZ)
tsu(SZ)
SIZ1, SIZ0
tsu(EN)
(1, 0)
th(EN)
th(SZ)
(1, 0)
(1, 0)
tsu(D)
th(D)
tsu(D)
th(D)
tpd(C-PE)
PEFB
tsu(EN)
tpd(D-PE)
(1, 0)
Not (1, 1)†
tpd(D-PE)
Valid
tpd(D-PE)
Valid
Valid
† SIZ0 = H and SIZ1 = H writes data to the mail2 register.
NOTE A: PEFB indicates parity error for the following bytes: B35 – B27 for big-endian bus and B17 – B9 for little-endian bus.
Figure 8. Port-B Byte Write-Cycle Timing for FIFO2
20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Valid
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
DATA SWAP TABLE FOR BYTE WRITES TO FIFO2
SWAP MODE
SW1
DATA WRITTEN
TO FIFO2
WRITE
NO.
SW0
BIG
ENDIAN
LITTLE
ENDIAN
DATA READ FROM FIFO2
B35 – B27
B8 – B0
A35 – A27
A26 – A18
A17 – A9
A8 – A0
A
B
C
D
D
C
B
A
A
B
C
D
L
L
1
2
3
4
L
H
1
2
3
4
D
C
B
A
A
B
C
D
A
B
C
D
L
1
2
3
4
C
D
A
B
B
A
D
C
A
B
C
D
H
1
2
3
4
B
A
D
C
C
D
A
B
A
B
C
D
H
H
Figure 8. Port-B Byte Write-Cycle Timing for FIFO2 (Continued)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
CLKB
EFB
High
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎ
ÌÌÌÌÌÌÌÌÌÌ
ÌÌ ÌÌÌÌÌÌ
ÌÌ
ÌÌ
ÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌ
CSB
W/RB
tsu(EN)
ENB
tsu(SW)
SW1,
SW0
tsu(SZ)
th(SZ)
BE
tsu(SZ)
SIZ1,
SIZ0
th(SZ)
Not (1, 1)†
(0, 0)
th(EN)
tsu(EN)
ten
B0 – B35
th(EN)
No Operation
th(SW)
Not (1, 1)†
(0, 0)
tsu(PG)
PGB,
ODD/
EVEN
ÎÎÎÎÎ
ÎÎÎÎÎ
ÌÌÌÌÌÌ ÏÏÏÏÏÏ ÎÎÎÎÎ
ÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌ
th(PG)
ta
Previous Data
tdis
W2‡
ta
W1‡
† SIZ0 = H and SIZ1 = H selects the mail1 register for output on B0 – B35.
‡ Data read from FIFO1
DATA SWAP TABLE FOR LONG-WORD READS FROM FIFO1
DATA WRITTEN TO FIFO1
SWAP MODE
DATA READ FROM FIFO1
A35 – A27
A26 – A18
A17 – A9
A8 – A0
SW1
SW0
B35 – B27
B26 – B18
B17 – B9
B8 – B0
A
B
C
D
L
L
A
B
C
D
A
B
C
D
L
H
D
C
B
A
A
B
C
D
H
L
C
D
A
B
A
B
C
D
H
H
B
A
D
C
Figure 9. Port-B Long-Word Read-Cycle Timing for FIFO1
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
CLKB
High
EFB
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎ
ÌÌÌÌÌÌÌÌÌÌ
ÌÌ ÌÌÌÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌ
CSB
W/RB
tsu(EN)
th(EN)
ENB
tsu(SW)
SW1,
SW0
tsu(SZ)
BE
th(SZ)
Not (1, 1)†
(0, 1)
(0, 1)
tsu(PG)
PGB,
ODD/
EVEN
B0 – B17
Not (1, 1)†
th(PG)
ten
Little
Endian‡
No Operation
th(SW)
th(SZ)
tsu(SZ)
SIZ1,
SIZ0
ÎÎÎÎ
ÎÎÎÎ
ÌÌÌÌÌ ÏÏÏÏÏ ÎÎÎÎÎ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ta
ta
Previous Data
Read 1
ta
Big
Endian‡
B18 – B35
tdis
Read 2
ta
Previous Data
tdis
Read 1
Read 2
† SIZ0 = H and SIZ1 = H selects the mail1 register for output on B0 – B35.
‡ Unused word B0 – B17 or B18 – B35 holds the last FIFO1-output-register data for word-size reads.
DATA SWAP TABLE FOR WORD READS FROM FIFO1
DATA WRITTEN TO FIFO1
A35 – A27
A26 – A18
A17 – A9
SWAP MODE
A8 – A0
SW1
DATA READ FROM FIFO1
READ
NO.
NO
SW0
BIG ENDIAN
LITTLE ENDIAN
B35 – B27
B26 – B18
B17 – B9
B8 – B0
A
C
B
D
C
A
D
B
A
B
C
D
L
L
1
2
A
B
C
D
L
H
1
2
D
B
C
A
B
D
A
C
A
B
C
D
H
L
1
2
C
A
D
B
A
C
B
D
A
B
C
D
H
H
1
2
B
D
A
C
D
B
C
A
Figure 10. Port-B Word Read-Cycle Timing for FIFO1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
CLKB
EFB
High
CSB
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÌÌÌÌÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ
W/RB
tsu(EN)
ENB
tsu(SW)
SW1, SW0
tsu(SZ)
th(SZ)
BE
tsu(SZ)
SIZ1, SIZ0
th(SZ)
(1, 0)
ÎÎÎÎÎ
ÎÎÎÎÎ
ÌÌÌÌÌÌÌÌÌÌÌÌ ÏÏÏ ÎÎÎÎÎ
ÌÌÌÌÌÌÌÌÌÌÌÌ ÏÏÏ ÎÎÎÎÎ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
th(EN)
(1, 0)
Not (1, 1)†
tsu(PG)
PGB,
ODD/EVEN
ten
No
Operation
th(SW)
(1, 0)
Not (1, 1)†
th(PG)
Not (1, 1)†
ta
B0 – B8
ta
Read 1
Previous Data
ta
B27 – B35
Not (1, 1)†
(1, 0)
ta
Read 2
ta
Read 1
ta
Read 3
ta
Read 2
ta
Read 3
Previous Data
† SIZ0 = H and SIZ1 = H selects the mail1 register for output on B0 – B35.
NOTE A: Unused bytes hold the last FIFO1-output-register data for byte-size reads.
Figure 11. Port-B Byte Read-Cycle Timing for FIFO1
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
tdis
Read 4
tdis
Read 4
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
DATA SWAP TABLE FOR BYTE READS FROM FIFO1
DATA WRITTEN TO FIFO1
A35 – A27
A26 – A18
A17 – A9
SWAP MODE
A8 – A0
SW1
DATA READ
FROM FIFO1
READ
NO.
SW0
BIG
ENDIAN
LITTLE
ENDIAN
B35 – B27
B8 – B0
A
B
C
D
D
C
B
A
A
B
C
D
L
L
1
2
3
4
A
B
C
D
L
H
1
2
3
4
D
C
B
A
A
B
C
D
L
1
2
3
4
C
D
A
B
B
A
D
C
H
1
2
3
4
B
A
D
C
C
D
A
B
A
B
A
C
B
D
C
H
D
H
Figure 11. Port-B Byte Read-Cycle Timing for FIFO1 (continued)
tc
tw(CLKH)
tw(CLKL)
CLKA
EFA
High
CSA
ÏÏÏÏ
ÎÎÎÎÎ
W/RA
MBA
tsu(EN)
tsu(EN)
tsu(EN)
ÎÎÎÎÎÎÎÎ ÌÌÌÌÌÌ ÏÏÏÏÏÏ ÎÎÎÎÎ
ÌÌ
ÌÌ
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌ
Ì
ÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ ÌÌÌÌÌÌ Ì
ÌÌÌÌÌÌÌÌÌÌÌÌÌ
th(EN)
th(EN)
th(EN)
ENA
tpd(M-DV)
ta
ten
A0 – A35
PGA,
ODD/EVEN
† Read from FIFO2
tsu(PG)
Previous Data
th(PG)
No
Operation
ta
W1†
tsu(PG)
tdis
W2†
th(PG)
Figure 12. Port-A Read-Cycle Timing for FIFO2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
tc
tw(CLKH)
tw(CLKL)
CLKA
CSA
W/RA
Low
High
tsu(EN)
ÏÏÏÏÏ
ÏÏÏÏÏ
ÎÎÎÎ
ÌÌÌÌÌ
ÌÌÌÌÌ
MBA
tsu(EN)
th(EN)
ENA
FFA
High
tsu(D)
A0 – A35
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
th(EN)
th(D)
W1
tsk1†
tc
tw(CLKH)
1
CLKB
tw(CLKL)
2
tpd(C-EF)
tpd(C-EF)
FIFO1 Empty
EFB
CSB
Low
W/RB
Low
SIZ1, SIZ0
Low
th(EN)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
tsu(EN)
ENB
ta
W1
B0 – B35
† tsk1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition high in the next CLKB cycle. If the time
between the rising CLKA edge and rising CLKB edge is less than tsk1, the transition of EFB high may occur one CLKB cycle later than shown.
NOTE A: Port-B size of the long word is selected for FIFO1 read by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, EFB is set low by the
last word or byte read from FIFO1, respectively.
Figure 13. EFB-Flag Timing and First Data Read When FIFO1 Is Empty
26
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SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
tc
tw(CLKH)
tw(CLKL)
CLKB
CSB
W/RB
Low
High
tsu(EN)
ÏÏÏÏÏÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÏÏÏÏÏ
ÎÎÎÎÏÏÏÏÏ
ÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
th(EN)
SIZ1, SIZ0
tsu(EN)
th(EN)
ENB
FFB
High
tsu(D)
B0 – B35
th(D)
W1
tc
tsk1†
tw(CLKL)
tw(CLKH)
1
CLKA
2
tpd(C-EF)
tpd(C-EF)
FIFO2 Empty
EFA
CSA
Low
W/RA
Low
MBA
Low
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
th(EN)
tsu(EN)
ENA
ta
A0 – A35
W1
† tsk1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition high in the next CLKA cycle. If the time
between the rising CLKB edge and rising CLKA edge is less than tsk1, the transition of EFA high may occur one CLKA cycle later than shown.
NOTE A: Port-B size of the long word is selected for FIFO2 write by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, tsk1 is referenced to
the rising CLKB edge that writes the last word or byte of the long word, respectively.
Figure 14. EFA-Flag Timing and First Data Read When FIFO2 Is Empty
POST OFFICE BOX 655303
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27
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
tc
tw(CLKH)
tw(CLKL)
CLKB
CSB
Low
W/RB
Low
SIZ1, SIZ0
Low
ÎÎÎÎ ÏÏÏ
ÎÎÎÎ ÏÏÏ
tsu(EN)
ENB
EFB
th(EN)
High
ta
B0 – B35 Previous Word in FIFO1 Output Register
Next Word From FIFO1
tsk1†
tc
tw(CLKH)
tw(CLKL)
1
CLKA
2
tpd(C-FF)
tpd(C-FF)
FIFO1 Full
FFA
CSA
Low
W/RA
High
MBA
ENA
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌ
tsu(EN)
th(EN)
tsu(EN)
th(EN)
tsu(D)
A0 – A35
th(D)
To FIFO1
† tsk1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition high in the next CLKA cycle. If the time
between the rising CLKB edge and rising CLKA edge is less than tsk1, FFA may transition high one CLKA cycle later than shown.
NOTE A: Port-B size of the long word is selected for the FIFO1 read by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, tsk1 is referenced
from the rising CLKB edge that reads the first word or byte of the long word, respectively.
Figure 15. FFA-Flag Timing and First Available Write When FIFO1 Is Full
28
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SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
tc
tw(CLKH)
tw(CLKL)
CLKA
CSA
Low
W/RA
Low
MBA
Low
ÎÎÎÎ
ÏÏÏ
ÎÎÎÎ ÏÏÏ
tsu(EN)
ENA
EFA
th(EN)
High
ta
A0 – A35 Previous Word in FIFO2 Output Register
Next Word From FIFO2
tsk1†
tc
tw(CLKH)
tw(CLKL)
1
CLKB
2
tpd(C-FF)
tpd(C-FF)
FIFO2 Full
FFB
CSB
Low
W/RB
High
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
tsu(EN)
SIZ1, SIZ0
tsu(EN)
ENB
tsu(D)
B0 – B35
ÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
th(EN)
th(EN)
th(D)
To FIFO2
† tsk1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition high in the next CLKB cycle. If the time
between the rising CLKA edge and rising CLKB edge is less than tsk1, FFB may transition high one CLKB cycle later than shown.
NOTE A: Port-B size of the long word is selected for FIFO2 write by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, FFB is set low by the
last word or byte write of the long word, respectively.
Figure 16. FFB-Flag Timing and First Available Write When FIFO2 Is Full
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29
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
CLKA
ÎÎÎÎÎ
ÏÏÏÏÏ
ÎÎÎÎÎÏÏÏÏÏ
th(EN)
tsu(EN)
ENA
tsk2†
CLKB
1
2
tpd(C-AE)
AEB
tpd(C-AE)
X Long Words in FIFO1
(X + 1) Long Words in FIFO1
th(EN)
ÎÎÎÎÎ ÏÏÏÏ
tsu(EN)
ENB
† tsk2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition high in the next CLKB cycle. If the time
between the rising CLKA edge and rising CLKB edge is less than tsk2, AEB may transition high one CLKB cycle later than shown.
NOTES: A. FIFO1 write (CSA = L, W/RA = H, MBA = L), FIFO1 read (CSB = L, W/RB = L, MBB = L)
B. Port-B size of the long word is selected for FIFO1 read by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, AEB is set low by
the first word or byte read of the long word, respectively.
Figure 17. Timing for AEB When FIFO1 Is Almost Empty
CLKB
ÎÎÎÎÎ
ÏÏÏÏÏ
ÎÎÎÎÎÏÏÏÏÏ
th(EN)
tsu(EN)
ENB
tsk2‡
CLKA
1
2
tpd(C-AE)
AEA
X Long Words in FIFO2
tpd(C-AE)
(X + 1) Long Words in FIFO2
ÎÎÎÎÎ
ÏÏÏÏ
ÎÎÎÎÎ ÏÏÏÏ
tsu(EN)
ENA
th(EN)
‡ tsk2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition high in the next CLKA cycle. If the time
between the rising CLKB edge and rising CLKA edge is less than tsk2, AEA may transition high one CLKA cycle later than shown.
NOTES: A. FIFO2 write (CSB = L, W/RB = H, MBB = L), FIFO2 read (CSA = L, W/RA = L, MBA = L)
B. Port-B size of the long word is selected for FIFO2 write by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, tsk2 is referenced
from the rising CLKB edge that writes the last word or byte of the long word, respectively.
Figure 18. Timing for AEA When FIFO2 Is Almost Empty
30
POST OFFICE BOX 655303
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SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
tsk2†
CLKA
1
ÎÎÎÎÎ
ÏÏÏÏÏ
ÎÎÎÎÎ ÏÏÏÏÏ
th(EN)
tsu(EN)
ENA
tpd(C-AF)
AFA
2
tpd(C-AF)
(64 – X) Long Words in FIFO1
[64 – (X + 1)] Long Words in FIFO1
CLKB
th(EN)
ÎÎÎÎÎÏÏÏÏÏ
tsu(EN)
ENB
† tsk2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition high in the next CLKA cycle. If the time
between the rising CLKA edge and rising CLKB edge is less than tsk2, AFA may transition high one CLKB cycle later than shown.
NOTES: A. FIFO1 write (CSA = L, W/RA = H, MBA = L), FIFO1 read (CSB = L, W/RB = L, MBB = L)
B. Port-B size of the long word is selected for FIFO1 read by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, tsk2 is referenced
from the first word or byte read of the long word, respectively.
Figure 19. Timing for AFA When FIFO1 Is Almost Full
tsk2‡
CLKB
1
ÎÎÎÎÎ
ÏÏÏÏÏ
ÎÎÎÎÎ ÏÏÏÏÏ
tsu(EN)
ENB
tpd(C-AF)
AFB
2
th(EN)
[64 – (X + 1)] Long Words in FIFO2
tpd(C-AF)
(64 – X) Long Words in FIFO2
CLKA
ÎÎÎÎÎ
ÏÏÏÏÏ
ÎÎÎÎÎÏÏÏÏÏ
tsu(EN)
ENA
th(EN)
‡ tsk2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition high in the next CLKB cycle. If the time
between the rising CLKB edge and rising CLKA edge is less than tsk2, AFB may transition high one CLKA cycle later than shown.
NOTES: A. FIFO2 write (CSB = L, W/RB= H, MBB = L), FIFO2 read (CSA = L, W/RA = L, MBA = L)
B. Port-B size of the long word is selected for FIFO2 write by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, AFB is set low by
the last word or byte write of the long word, respectively.
Figure 20. Timing for AFB When FIFO2 Is Almost Full
POST OFFICE BOX 655303
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31
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
CLKA
th(EN)
tsu(EN)
CSA
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÌÌÌÌÌÌÌÌ
W/RA
MBA
ENA
th(D)
tsu(D)
A0 – A35
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
W1
CLKB
tpd(C-MF)
tpd(C-MF)
MBF1
CSB
W/RB
SIZ1, SIZ0
ÏÏÏÏ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ENB
ten
B0 – B35
ÎÎÎÎÎÎ
th(EN)
ÎÎÎÎ ÏÏÏÏ
ÎÎÎÎ
ÏÏÏÏ
ÌÌÌÌ
ÌÌÌÌ
tsu(EN)
tpd(M-DV)
tpd(C-MR)
W1 (remains valid in mail1 register after read)
FIFO1 Output Register
NOTE A: Port-B parity generation off (PGB = L)
Figure 21. Timing for Mail1 Register and MBF1 Flag
32
tdis
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SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
CLKB
th(EN)
tsu(EN)
CSB
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÌÌÌÌÌÌÌ
W/RB
SIZ1, SIZ0
ENB
th(D)
tsu(D)
B0 – B35
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
th(SZ)
tsu(SZ)
W1
CLKA
tpd(C-MF)
tpd(C-MF)
MBF2
CSA
ÎÎÎÎÎ
ÎÎÎÎÎ
W/RA
MBA
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÎÎÎÎ ÏÏÏ
ÎÎÎÎ
ÏÏÏ
ÌÌÌ
ÌÌÌ
tsu(EN)
ENA
th(EN)
tpd(M-DV)
ten
A0 – A35
tpd(C-MR)
tdis
W1 (remains valid in mail2 register after read)
FIFO2 Output Register
NOTE A: Port-A parity generation off (PGA = L)
Figure 22. Timing for Mail2 Register and MBF2 Flag
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33
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
ODD/
EVEN
W/RA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
MBA
PGA
tpd(O-PE)
PEFA
Valid
tpd(O-PE)
Valid
tpd(E-PE)
tpd(E-PE)
Valid
Valid
Figure 23. ODD/EVEN, W/RA, MBA, and PGA to PEFA Timing
ODD/
EVEN
W/RB
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SIZ1,
SIZ0
PGB
tpd(O-PE)
PEFB
Valid
tpd(O-PE)
tpd(E-PE)
Valid
Valid
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
tpd(E-PE)
Figure 24. ODD/EVEN, W/RB, SIZ1, SIZ0, and PGB to PEFB Timing
34
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Valid
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
ODD/
EVEN
CSA
Low
W/RA
MBA
PGA
A8, A17,
A26, A35
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ten
tpd(E-PB)
tpd(M-DV)
tpd(O-PB)
Generated Parity
tpd(E-PB)
Generated Parity
Mail2 Data
Mail2
Data
Figure 25. Parity-Generation Timing When Reading From the Mail2 Register
ODD/
EVEN
CSB
W/RB
SIZ1,
SIZ0
PGB
B8, B17,
B26, B35
Low
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ten
tpd(E-PB)
tpd(M-DV)
tpd(O-PB)
Generated Parity
tpd(E-PB)
Generated Parity
Mail1 Data
Mail1
Data
Figure 26. Parity-Generation Timing When Reading From the Mail1 Register
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35
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 500 mA
Package thermal impedance, θJA (see Note 2): PCB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28°C/W
PQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
MIN
MAX
4.5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.8
V
High-level output current
–4
mA
IOL
TA
Low-level output current
8
mA
70
°C
High-level input voltage
2
Operating free-air temperature
0
V
V
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
VOL
VCC = 4.5 V,
VCC = 4.5 V,
IOH = – 4 mA
IOL = 8 mA
II
IOZ
VCC = 5.5 V,
VCC = 5.5 V,
VI = VCC or 0
VO = VCC or 0
ICC
VCC = 5.5 V,
IO = 0 mA,
MIN
TYP‡
2.4
VI = VCC or GND
0.5
V
± 50
µA
± 50
µA
Outputs high
30
Outputs low
130
mA
30
f = 1 MHz
4
pF
Co
f = 1 MHz
‡ All typical values are at VCC = 5 V, TA = 25°C.
8
pF
36
VI = 0,
VO = 0,
UNIT
V
Outputs disabled
Ci
MAX
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SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 4 through 27)
’ABT3614-15
MIN
fclock
tc
Clock frequency, CLKA or CLKB
tw(CLKH)
tw(CLKL)
tsu(D)
tsu(EN)
tsu(SZ)
tsu(SW)
tsu(PG)
tsu(RS)
tsu(FS)
MAX
’ABT3614-20
MIN
66.7
Clock cycle time, CLKA or CLKB
MAX
’ABT3614-30
MIN
50
MAX
33.4
UNIT
MHz
15
20
30
ns
Pulse duration, CLKA and CLKB high
6
8
12
ns
Pulse duration, CLKA and CLKB low
6
8
12
ns
Setup time, A0 – A35 before CLKA↑ and B0 – B35 before CLKB↑
4
5
6
ns
Setup time, CSA, W/RA, ENA, and MBA before CLKA↑; CSB,
W/RB, and ENB before CLKB↑
5
5
6
ns
Setup time, SIZ0, SIZ1, and BE before CLKB↑
4
5
6
ns
Setup time, SW0 and SW1 before CLKB↑
5
7
8
ns
4
5
6
ns
5
6
7
ns
Setup time, ODD/EVEN and PGA before CLKA↑; ODD/EVEN and
PGB before CLKB↑†
Setup time, RST low before CLKA↑ or CLKB↑‡
Setup time, FS0 and FS1 before RST high
5
6
7
ns
th(D)
Hold time, A0 – A35 after CLKA↑ and B0 – B35 after CLKB↑
1
1
1
ns
th(EN)
Hold time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB,
and ENB after CLKB↑
1
1
1
ns
Hold time, SIZ0, SIZ1, and BE after CLKB↑
2
2
2
ns
Hold time, SW0 and SW1 after CLKB↑
0
0
0
ns
0
0
0
ns
5
6
7
ns
Hold time, FS0 and FS1 after RST high
4
4
4
ns
tsk1§
Skew time between CLKA↑ and CLKB↑ for EFA, EFB, FFA, and
FFB
8
8
10
ns
tsk2§
Skew time between CLKA↑ and CLKB↑ for AEA, AEB, AFA, and
AFB
9
16
20
ns
th(SZ)
th(SW)
th(PG)
th(RS)
th(FS)
Hold time, ODD/EVEN and PGA after CLKA↑; ODD/EVEN and
PGB after CLKB↑†
Hold time, RST low after CLKA↑ or CLKB↑‡
† Applies only for a clock edge that does a FIFO read
‡ Requirement to count the clock edge as one of at least four needed to reset a FIFO
§ Skew time is not a timing constraint for proper device operation and is included only to illustrate the timing relationship between CLKA cycle and
CLKB cycle.
POST OFFICE BOX 655303
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37
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 30 pF (see Figures 4 through 27)
’ABT3614-15
PARAMETER
fmax
ta
MIN
MAX
66.7
’ABT3614-20
MIN
MAX
50
’ABT3614-30
MIN
MAX
33.4
UNIT
MHz
Access time, CLKA↑ to A0 – A35 and CLKB↑ to B0 – B35
2
10
2
12
2
15
ns
tpd(C-FF)
tpd(C-EF)
Propagation delay time, CLKA↑ to FFA and CLKB↑ to FFB
2
10
2
12
2
15
ns
Propagation delay time, CLKA↑ to EFA and CLKB↑ to EFB
2
10
2
12
2
15
ns
tpd(C-AE)
tpd(C-AF)
Propagation delay time, CLKA↑ to AEA and CLKB↑ to AEB
2
10
2
12
2
15
ns
Propagation delay time, CLKA↑ to AFA and CLKB↑ to AFB
2
10
2
12
2
15
ns
1
9
1
12
1
15
ns
3
11
3
13
3
15
ns
tpd(C-MR)
Propagation delay time, CLKA↑ to MBF1 low or MBF2 high and
CLKB↑ to MBF2 low or MBF1 high
Propagation delay time, CLKA↑ to B0 – B35† and CLKB↑ to
A0 – A35‡
tpd(C-PE)§
Propagation delay time, CLKB↑ to PEFB
2
11
2
12
2
13
ns
tpd(M-DV)
Propagation delay time, MBA to A0 – A35 valid and SIZ1, SIZ0 to
B0 – B35 valid
1
11
1
11.5
1
12
ns
tpd(D-PE)
Propagation delay time, A0-A35 valid to PEFA valid; B0-B35
valid to PEFB valid
3
10
3
11
3
13
ns
tpd(O-PE)
Propagation delay time, ODD/EVEN to PEFA and PEFB
3
11
3
12
3
14
ns
tpd(O-PB)¶
Propagation delay time, ODD/EVEN to parity bits (A8, A17, A26,
A35) and (B8, B17, B26, B35)
2
11
2
12
2
14
ns
tpd(E-PE)
Propagation delay time, CSA, ENA, W/RA, MBA, or PGA to
PEFA; CSB, ENB, W/RB, SIZ1, SIZ0, or PGB to PEFB
1
11
1
12
1
14
ns
tpd(E-PB)¶
Propagation delay time, MBA or PGA to parity bits (A8, A17,
A26, A35); SIZ1, SIZ0, or PGB to parity bits (B8, B17, B26, B35)
3
12
3
13
3
14
ns
tpd(R-F)
Propagation delay time, RST to (MBF1, MBF2) high
1
15
1
20
1
30
ns
ten
Enable time, CSA and W/RA low to A0 – A35 active and CSB low
and W/RB high to B0 – B35 active
2
10
2
12
2
14
ns
tdis
Disable time, CSA or W/RA high to A0 – A35 at high impedance
and CSB high or W/RB low to B0 – B35 at high impedance
1
8
1
9
1
11
ns
tpd(C-MF)
† Writing data to the mail1 register when the B0 – B35 outputs are active and SIZ1, SIZ0 are high
‡ Writing data to the mail2 register when the A0 – A35 outputs are active and MBA is high
§ Applies only when a new port-B bus size is implemented by the rising CLKB edge
¶ Applies only when reading data from a mail register
38
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
PARAMETER MEASUREMENT INFORMATION
5V
1.1 kΩ
From Output
Under Test
680 Ω
30 pF
(see Note A)
LOAD CIRCUIT
3V
Timing
Input
3V
High-Level
Input
1.5 V
1.5 V
1.5 V
GND
GND
th
tsu
Data,
Enable
Input
tw
3V
1.5 V
3V
1.5 V
Low-Level
Input
GND
1.5 V
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Enable
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
3V
1.5 V
1.5 V
GND
tPLZ
tPZL
Low-Level
Output
≈3V
1.5 V
VOL
3V
≈0V
tpd
tpd
VOH
1.5 V
1.5 V
GND
tPZH
High-Level
Output
1.5 V
Input
VOH
In-Phase
Output
1.5 V
1.5 V
VOL
tPHZ
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. Includes probe and jig capacitance
B. tPZL and tPZH are the same as ten.
C. tPLZ and tPHZ are the same as tdis.
Figure 27. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
39
SN74ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENCY
400
fdata = 1/2 fclock
TA = 25°C
CL = 0 pF
I CC(f) – Supply Current – mA
350
300
VCC = 5.5 V
VCC = 5 V
250
200
VCC = 4.5 V
150
100
50
0
0
10
20
30
40
50
60
fclock – Clock Frequency – MHz
Figure 28
40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
70
80
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