www.DataSheet4U.com DATA SHEET Y l ia OG t n L e if d NO INC n H o E C S PC HE8200A IS SP E s uDVD SinTgle ChNip DMPEGLAY/V l p C P r o c essor A I n N N u H S UN C E O R S S E U r M o F & Preliminary OCT. 07, 2003 Version 0.2 SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO. is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document. Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus. www.DataSheet4U.com Preliminary SPHE8200A Table of Contents PAGE Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & 1. GENERAL DESCRIPTION...................................................................................................................................................................... 4 2. FEATURE ............................................................................................................................................................................................... 5 3. BLOCK DIAGRAM.................................................................................................................................................................................. 6 4. SIGNAL DESCRIPTION.......................................................................................................................................................................... 7 4.1. PIN MAP ........................................................................................................................................................................................... 7 4.2. GROUP MAP ..................................................................................................................................................................................... 8 4.3. PIN DESCRIPTION .............................................................................................................................................................................. 9 5. FUNCTIONAL DESCRIPTIONS............................................................................................................................................................ 18 5.1. PLL AND CLOCKGEN ....................................................................................................................................................................... 18 5.2. POWER CONTROL ........................................................................................................................................................................... 18 5.3. EMBEDDED 32-BIT RISC CONTROLLER ............................................................................................................................................. 18 5.4. RISC INTERFACE ............................................................................................................................................................................ 19 5.5. ROM/FLASH/SRAM CONTROLLER.................................................................................................................................................... 20 5.6. RISC MEMORY INTERFACE .............................................................................................................................................................. 20 5.7. PERIPHERAL CONTROL INTERFACE ................................................................................................................................................... 20 5.8. CSS/CPPM SUPPORT ..................................................................................................................................................................... 20 5.9. MPEG VIDEO DECODER .................................................................................................................................................................. 20 5.10.GRAPHICS ENGINE BONDYPRO®...................................................................................................................................................... 21 5.11. VIDEO POST PROCESSING ............................................................................................................................................................... 21 5.12.AUDIO DSP .................................................................................................................................................................................... 21 5.13.AUDIO INTERFACE ........................................................................................................................................................................... 22 5.14.INTEGRATED AUDIO QUALITY ADC .................................................................................................................................................... 22 5.15.I/O PROCESSOR.............................................................................................................................................................................. 22 5.16.SDRAM CONTROLLER .................................................................................................................................................................... 22 5.17.SUB-PICTURE DECODER .................................................................................................................................................................. 22 5.18.ON SCREEN DISPLAY ....................................................................................................................................................................... 22 5.19.DISPLAY INTERFACE ......................................................................................................................................................................... 22 5.20.VIDEO DAC .................................................................................................................................................................................... 23 5.21.ATAPI INTERFACE ........................................................................................................................................................................... 23 5.22.GPIO ............................................................................................................................................................................................. 23 5.23.UART ............................................................................................................................................................................................ 23 6. ELECTRICAL SPECIFICATIONS ......................................................................................................................................................... 24 6.1. ABSOLUTE MAXIMUM RATINGS ......................................................................................................................................................... 24 6.2. DC OPERATING CONDITIONS............................................................................................................................................................ 24 6.3. CAPACITANCE.................................................................................................................................................................................. 24 6.4. AC CHARACTERISTICS..................................................................................................................................................................... 25 6.4.1. SDRAM interface timing diagrams ...................................................................................................................................... 25 6.4.2. ROM / flash interface timing diagrams................................................................................................................................. 26 6.4.3. Audio interface timing diagrams .......................................................................................................................................... 27 6.4.4. Video timing diagrams......................................................................................................................................................... 28 7. REGISTER LIST ................................................................................................................................................................................... 30 8. PACKAGE/PAD LOCATION ................................................................................................................................................................. 38 © Sunplus Technology Co., Ltd. Proprietary & Confidential 2 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A 8.1. OUTLINE DIMENSIONS ...................................................................................................................................................................... 38 9. DISCLAIMER........................................................................................................................................................................................ 39 10. REVISION HISTORY............................................................................................................................................................................. 40 Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & © Sunplus Technology Co., Ltd. Proprietary & Confidential 3 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A DVD SINGLE CHIP MPEG A/V PROCESSOR 1.GENERAL DESCRIPTION Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & SPHE8200A A/V decoder is a single-chip integrated DVD A/V SPHE8200A supports Dolby Digital, DTS, MPEGI/II Layer1/2 , decoder. PCM, LPCM, WMA audio playback. It performs real-time decoding and playback of ISO/IEC 11172 MPEG1 and 13818 MPEG2 stream for multiple bitstream sources. SPHE8200A also combines all the functions required for a high-performance progressive-scan DVD system. Built-in SPHE8200A supports DVD-Video, DVD-Audio, Super Video CD, de-interlacing hardware allows high quality DVD playback. The Video CD, CD-DA, HDCD, OKO, CD-ROM different disc formats. embedded digital audio decoder is able to support key control and audio sound effects for Karaoke. SPHE8200A is designed to maximize system performance with minimum cost. For typical DVD application it integrates DVD/CD In additional to that SPHE8200A includes a flexible 2D graphics servo controller, multi-channel multi-format TV-encoder and audio engine for high quality user interface and other applications. quality ADC, with high quality 5.1ch Audio, or low cost 2-ch AC3 Complex application could be built using this platform easily. system. Development tools of SPHE8200A include complete compiler tools, programming guide and system application libraries. Application utilizing the SPHE8200A is presented below: IR 6-ch video output VFD front panel DVD-loader SPHE8200A 2~10 ch RF Audio DAC Audio amplifier SDRAM ROM © Sunplus Technology Co., Ltd. Proprietary & Confidential 4 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A 2.FEATURE Single Chip Integrated DVD Servo and A/V Decoder — Support up to 4 SDRAM devices Integrated DVD/CD Servo Controller — Support 16M/64M/128M/256M SDRAM devices — Support 1x ~ 2x DVD format reading Graphics Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & — Support 1x ~ 16x CD format reading — Embedded 2D Graphics Accelerator Embedded 32-bit RISC Processor without external host — BitBlt, line, triangle drawing support controller Display Embedded Audio Processor supports multiple audio standards — De-interlacing of interlaced video source Embedded I/O processor supports programmable interface — Flexible vertical interpolation control — Flexible horizontal interpolation with optional CIF filter Embedded TV encoder with multi-channel built-in high-speed — Powerful cropping and panning effect video DAC supports various display standards — Support YUV422, 8-bit indexed color or 16-bit direct color Embedded audio ADC supports stereo analog audio input format Built-in system PLL and audio PLL generate all clock sources OSD required from single 27MHz input — Multiple OSD regions with different formats Support following disc format: — Support 4/16/256 indexed color — DVD Navigation 1.0 — Support 16/24-bit direct color — DVD audio — Support x2/x3/x4 horizontal scaling — SVCD (Chaoji VCD) Embedded TV encoder — OKO disc — Simultaneous multi-channel output — VCD 2.0/1.1/1.0 — Support 480i/480p/576i/576p format — CDDA / HDCD — Support 640x480 VGA / 800x600 SVGA format — CDROM (game, WMA and JPEG disc) — Support CVBS output CSS/CPPM hardware — Support SVideo, Component (YUV / YPbPr) or RGB output — Built-in CSS hardware — Macrovision 7.01 and Macrovision AGC v1.03 copy — Built-in CPPM C2_DCBC and C2_D/C2_D function protection Video Decoder Interface — Real time MPEG2 MP@ML decoding — 27MHz crystal driver — Real time MPEG1 D1 (720x480x30 /720x576x25) decoding — 16/32-bit SDRAM interface — Hardware accelerated JPEG decoding — 8/16-bit ROM/FLASH/SRAM interface — Advanced decoding and display control — UART ports Sub-picture Decoder — IR and VFD support — Advanced Sub-Picture Decoder for DVD SVCD and OKO — Video DAC analog output — Support hardware vertical scaling — Simultaneous 10-channel audio DAC output Audio Decoder — IEC958/SPDIF digital input / output — Flexible Programmable DSP Architecture — Analog audio input — Embedded high resolution audio quality ADC — External ADC digital input interface (optional) — Support CDDA, HDCD, and DVD-Audio — Optional ATAPI and I2S interface support — Support LPCM, PCM, and WMA playback — Optional Parallel Port interface support — Support MPEGI/II layer 1/2 and MPEG 2.5 playback (with Low power optional down-mixing) — Advanced low power design — Support Dolby Digital AC3 5.1ch / DTS 5.1ch playback (with — Selective standby mode optional down-mixing) — Programmable low speed operation — Support Key Shift of 2 channels Technology — Support equalization, reverb and special sound field — Advanced CMOS technology SDRAM controller — 216pin LQFP package — High Performance SDRAM controller — 3v (I/O) and 1.8v (kernel) power supplies — Support 16 or 32 bit operation — 5v I/O tolerance © Sunplus Technology Co., Ltd. Proprietary & Confidential 5 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A 3.BLOCK DIAGRAM Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & EPROM/SRAM SDRAM /16 or /32 EPROM/ SRAM interface SDRAM controller Video postprocessing Video encoder Video output © Sunplus Technology Co., Ltd. Proprietary & Confidential Video DAC RISC PLLv PLLa icache dcache Power control Graphics Engine Intr. control loader inf. ECC loader RF input I/O processor IR/VFD/(I2C) Timer DMA Engine OSD decoder Audio DSP icache Servo Sub-picture decoder mem MPEG video decoder CSS/ CPPM 6 GPIO UART UART / smartcard ADC Audio Analog In DAC digital out Audio Interface IEC 958 I/O ADC digital in OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A 4.SIGNAL DESCRIPTION 4.1. Pin Map 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VSS_ADA VDD_ADA VM AIN_R/AI_DATA ATO/AI_LRCK AIN/AIN_L/AI_BCK VFD_DATA/TDM_CLK VFD_STB/TDM_FSX VFD_CLK/TDM_DX IR_IN/TDM_DR VSS_O6 M_A12/GPIO GPIO GPIO GPIO VDD_O6 GPIO GPIO GPIO GPIO VSS_K5 GPIO M_DQM2/GPIO M_DQM3/GPIO GPIO VDD_K5 R_A26/GPIO R_A25/GPIO R_A24/GPIO R_A23/GPIO VSS_O5 R_A22/GPIO R_A21/GPIO R_A20/GPIO VDD_O5 M_A3 M_A2 M_A1 VSS_K4 M_A0 M_A10 M_BA1/GPIO VDD_K4 M_DQM0 M_DQM1 M_A4 VSS_O4 M_A5 M_A6 M_A7 VDD_O4 M_A8 M_A9 M_A11/GPIO Y l ia OG t n L e if d NO INC n H o E C C E IS SPHE8200A s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 216 PIN LQFP 24x24mm2 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 M_CKE VSS_K3 M_CLKO VDD_O3 M_D8 M_D9 M_D10 M_D11 VSS_K3 M_D12 M_D13 M_D14 M_D15 VDD_K3 M_BA0 M_CS_B M_RAS_B M_CAS_B VSS_O2 M_WE_B M_D0 M_D1 M_D2 VDD_O2 M_D3 M_D4 M_D5 M_D6 M_D7 VSS_K2 CLKIN CLKOUT VDD_K2 VSS_PLLA VDD_PLLA VSS_PLLV VDD_PLLV R_CS3_B/GPIO R_CS2_B/GPIO R_CS1_B/GPIO R_WE_B/GPIO R_OE_B/GPIO R_A19/GPIO R_A18 R_A17 VSS_O1 R_A16 R_A7 R_A6 R_A5 R_A4 R_A3 R_A2 VDD_O1 DSRSET CNIN SLVL SVDD RFO SVSS RFRP RFRPLP TEXOLP TEXO ADVDD TEI FEI CSI SBAD VREF VRGD ADVSS SRV_SCLK SRV_SDATA SRV_SDEN SRV_DFCT T_PLCK VDD_K0 T_SLRF GPIO/TDM_DX/ttin0_4 GPIO/TDM_CLK/ttio1_4 GPIO/TDM_FSXR/ttio2_6 R_CS4_B/GPIO/TDM_DR/ttio3_7 VSS_K0 GPIO VDD_O0 RST_B R_A8 R_A9 VSS_O0 R_A10 R_A11 R_A12 R_A13 R_A14 VDD_K1 R_A15 R_D7 R_D6 R_D5 VSS_K1 R_D4 R_D3 R_D2 R_D1 R_D0 R_A0 R_A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 A_DATA4/GPIO A_IEC_RX/GPIO A_IEC_TX/GPIO A_DATA0/GPIO VDD_O7 A_DATA1/GPIO A_DATA2/GPIO A_DATA3/GPIO A_LRCK/GPIO VSS_K6/VSS_O7 A_BCK/GPIO A_XCK/GPIO UA0_RX/GPIO UA0_TX/GPIO VDD_K6 V_COMP V_BIAS V_FSADJ V_REFOUT TV_DAC0 VDD_TVA0 VSS_TVA0 TV_DAC1 TV_DAC2 VDD_TVA1 VSS_TVA1 TV_DAC3 TV_DAC4 VDD_TVA2 VSS_TVA2 TV_DAC5 PWM_VDD TRAY_OUT SC1_OUT SPDC_OUT SC_OUT DMEA FGIN PWM_VSS DAVSS TEO FEO DAVDD HGIN LGIN2 LGIN1 LPFNIN PDFLT1 FDFLT VREFO PLLVDD PDRSET FDRSET PLLVSS © Sunplus Technology Co., Ltd. Proprietary & Confidential 7 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A 4.2. Group Map Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & System Interface VSS_* VDD_* CLKIN RSTB TESTMODE ADC analog interface AIN_L/MIC AIN_R ATO VM ADC digital input AUI_BCK AUI_LRCK AUI_DATA Audio digita l output interface ROM Flash interface R_A[21:0] R_D[7:0] R_CS_B[3:0] R_WE_B R_OE_B R_WP_B IO_CHRDY SDRAM interface M_CLKO M_RAS_B M_CAS_B M_WE_B M_CS_B M_BA[1:0] M_A[11:0] M_D[31:0] M_DQ M[3:0] IR VFD UART GPIOs © Sunplus Technology Co., Ltd. Proprietary & Confidential AU_XCK AU_BCK AU_LRCK AU_DATA[3:0] AU_IEC_TXRV TEO FEO HGIN LGIN1 LGIN2 LPFNIN PDFLT1 FDFLT VREFO PDRSET FDRSET DRESET CNIN SLVL RFO RFRP RFRPLP TEXOLP TEXO TEI FEI CSI SBAO VREF VRGO SERVO TRAY_OUT SC1_OUT SPDC_OUT SC_OUT DMEA FGIN SRV_SCLK SRV_SDATA SRV_SDEN SRV_FDCT T_PLCK T_SLRF SERVO SPHE8200A (216pin) TDM_DX TDM_DR TDM_FSX TDM_CLK IR_IN VFD_CLK VFD_STB VFD_DATA U0_DI U0_DO Other GPIOs V_FSAD J V_COMP V_REFOUT V_REFIN V_DACO[5:0] 8 TDM Video output interface OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A 4.3. Pin Description Signal Pin State Description Supply Pins (51) Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & VSS_K* 30, 47, 79, 100, 124, S Ground pins for chip kernel logic S Ground pins for chip output 172 S Shared ground pin 24, 42, 76, 95, 120, S 1.8V power supply pins for chip kernel logic and input pre-driver S 3.3V power supply pins for output pins 142 VSS_O* 36, 63, 90, 107, 116, 132, 152 VSS_K6/O7 VDD_K* 137, 177 VDD_O* 32, 55, 85, 105, 112, 128, 147, 167, VSS_PLLV 73 S Ground pin for system PLL VDD_PLLV 72 S 1.8V power supply pin for system PLL VSS_PLLA 75 S Ground pin for audio PLL VDD_PLLA 74 S 3.3V power supply pin for audio PLL VDD_TVA* 183, 187, 191 S 3.3V power supply pin for TV DAC VSS_TVA* 184. 188. 192 S Ground pin for TV DAC VSS_ADA 162 S Ground pin for on-chip audio ADC VDD_ADA 161 S 3.3V power supply pin for on-chip audio ADC PWM_VSS 201 S Servo PWM ground (digital) PWM_VDD 194 S Servo PWM 3.3V power (digital) DA_VSS 202 S Servo DAC ground DA_VDD 205 S Servo DAC 3.3V power PLLVDD 213 S Servo PLL 3.3V power PLLVSS 216 S Servo PLL ground SVSS 6 S Servo analog ground SVDD 4 S Servo analog 3.3V power ADVSS 18 S Servo ADC ground ADVDD 11 S Servo ADC 3.3V power RST_B 33 I System reset (active low reset) System Control Pin ROM / SRAM / Flash Interface (33) R_A[8] 34 O ROM / SRAM / flash address bus bit [8] R_A[9] 35 O ROM / SRAM / flash address bus bit [9] R_A[10] 37 O ROM / SRAM / flash address bus bit [10] R_A[11] 38 O ROM / SRAM / flash address bus bit [11] R_A[12] 39 O ROM / SRAM / flash address bus bit [12] R_A[13] 40 O ROM / SRAM / flash address bus bit [13] R_A[14] 41 O ROM / SRAM / flash address bus bit [14] R_A[15] 43 O ROM / SRAM / flash address bus bit [15] R_D[7] 44 I/O ROM / SRAM / flash data bus [7] R_D[6] 45 I/O ROM / SRAM / flash data bus [6] © Sunplus Technology Co., Ltd. Proprietary & Confidential 9 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A Signal Pin State Description R_D[5] 46 I/O ROM / SRAM / flash data bus [5] R_D[4] 48 I/O ROM / SRAM / flash data bus [4] R_D[3] 49 I/O ROM / SRAM / flash data bus [3] R_D[2] 50 I/O ROM / SRAM / flash data bus [2] R_D[1] 51 I/O ROM / SRAM / flash data bus [1] R_D[0] 52 I/O ROM / SRAM / flash data bus [0] R_A[0] 53 O ROM / SRAM / flash address bus bit [0] R_A[1] 54 O ROM / SRAM / flash address bus bit [1] R_A[2] 56 O ROM / SRAM / flash address bus bit [2] R_A[3] 57 O ROM / SRAM / flash address bus bit [3] R_A[4] 58 O ROM / SRAM / flash address bus bit [4] R_A[5] 59 O ROM / SRAM / flash address bus bit [5] R_A[6] 60 O ROM / SRAM / flash address bus bit [6] Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & R_A[7] 61 O ROM / SRAM / flash address bus bit [7] R_A[16] 62 O ROM / SRAM / flash address bus bit [16] R_A[17] 64 O ROM / SRAM / flash address bus bit [17] R_A[18] 65 O ROM / SRAM / flash address bus bit [18] R_A19/GPIO 66 I/O ROM / SRAM / flash address bus bit 19 or GPIO Priority selection R_OE_B/GPIO 67 I/O R_A19 (default) sft_cfg2[4:2]=3’b010 UART0 TX (other) GPIO[32] ROM / SRAM / flash output enable or GPIO Priority selection R_WE_B/GPIO 68 I/O Function sft_cfg1[4]=1’b1 R_OE_B (default) sft_cfg4[2:0]=3’b100 DSP FL0 (other) GPIO[33] ROM / SRAM / flash write strobe or GPIO Priority selection © Sunplus Technology Co., Ltd. Proprietary & Confidential Function sft_cfg0[0]=1’b1 Function sft_cfg1[5]=1’b1 R_WE_B (default) sft_cfg4[5:3]=3’b100 DSP FL1 (other) GPIO[34] 10 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A Signal R_CS1_B/GPIO Pin State 69 I/O Description ROM / SRAM / flash chip select #1 (first device) or GPIO Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & Priority selection R_CS2_B/GPIO 70 I/O Function sft_cfg1[0]=1’b1 R_CS1_B (default) (other) GPIO[13] ROM / SRAM / flash chip select #2 or GPIO Priority selection R_CS3_B/GPIO 71 I/O Function sft_cfg1[1]=1’b1 R_CS2_B (default) sft_cfg4[8:6]=3’b100 DSP FL2 (other) GPIO[35] ROM / SRAM / flash chip select #3 or GPIO Priority selection Function sft_cfg1[2]=1’b1 R_CS3_B (default) sft_cfg4[11:9]=3’b100 DSP FLAGOUT (other) GPIO[36] Crystal / Clock Pins (2) CLKIN 78 I Clock input / crystal in (XTALI) CLKOUT 77 O Clock output / crystal out (XTALO) SDRAM Interface Pins (57) M_DD[7] 80 I/O SDRAM data bus [7] M_DD[6] 81 I/O SDRAM data bus [6] M_DD[5] 82 I/O SDRAM data bus [5] M_DD[4] 83 I/O SDRAM data bus [4] M_DD[3] 84 I/O SDRAM data bus [3] M_DD[2] 86 I/O SDRAM data bus [2] M_DD[1] 87 I/O SDRAM data bus [1] M_DD[0] 88 I/O SDRAM data bus [0] M_WE_B 89 O SDRAM write enable / row precharge M_CAS_B 91 O SDRAM column address strobe M_RAS_B 92 O SDRAM row address strobe / precharge M_CS_B 93 O SDRAM chip select M_BA0 94 O SDRAM bank select address [0] M_DD[15] 96 I/O SDRAM data bus [15] M_DD[14] 97 I/O SDRAM data bus [14] M_DD[13] 98 I/O SDRAM data bus [13] M_DD[12] 99 I/O SDRAM data bus [12] M_DD[11] 101 I/O SDRAM data bus [11] © Sunplus Technology Co., Ltd. Proprietary & Confidential 11 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A Signal Pin State Description M_DD[10] 102 I/O SDRAM data bus [10] M_DD[9] 103 I/O SDRAM data bus [9] M_DD[8] 104 I/O SDRAM data bus [8] M_CLKO 106 O SDRAM clock output Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & M_CKE 108 O SDRAM clock enable M_A[11]/GPIO 109 I/O SDRAM address bus [11] or GPIO Priority selection M_A[9] 110 Function sft_cfg6[4]=1’b1 M_A[11] (default) (other) GPIO[14] O SDRAM address bus [9] M_A[8] 111 O SDRAM address bus [8] M_A[7] 113 O SDRAM address bus [7] M_A[6] 114 O SDRAM address bus [6] M_A[5] 115 O SDRAM address bus [5] M_A[4] 117 O SDRAM address bus [4] M_DQM1 118 O SDRAM data input/output mask for M_DD[15:8] M_DQM0 119 O SDRAM data input/output mask for M_DD[7:0] M_BA1 121 O SDRAM bank select address [1] Priority selection Function sft_cfg6[6]=1’b1 M_BA1 (other) GPIO[15] M_A[10] 122 O SDRAM address bus [10] M_A[0] 123 O SDRAM address bus [0] M_A[1] 125 O SDRAM address bus [1] M_A[2] 126 O SDRAM address bus [2] M_A[3] 127 O SDRAM address bus [3] M_DD[31] 129 I/O SDRAM data bus bit 31 M_DD[30] 130 I/O SDRAM data bus bit 30 M_DD[29] 131 I/O SDRAM data bus bit 29 M_DD[28] 133 I/O SDRAM data bus bit 28 M_DD[27] 134 I/O SDRAM data bus bit 27 M_DD[26] 135 I/O SDRAM data bus bit 26 M_DD[25] 136 I/O SDRAM data bus bit 25 M_DD[24] 138 I/O SDRAM data bus bit 24 M_DQM3/GPIO 139 I/O SDRAM data input/output mask for M_DD[31:24] M_DQM2/GPIO 140 I/O SDRAM data input/output mask for M_DD[23:16] M_DD[23] 141 I/O SDRAM data bus bit 23 M_DD[22] 143 I/O SDRAM data bus bit 22 © Sunplus Technology Co., Ltd. Proprietary & Confidential 12 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A Signal Pin State Description M_DD[21] 144 I/O SDRAM data bus bit 21 M_DD[20] 145 I/O SDRAM data bus bit 20 M_DD[19] 146 I/O SDRAM data bus bit 19 M_DD[18] 148 I/O SDRAM data bus bit 18 M_DD[17] 149 I/O SDRAM data bus bit 17 M_DD[16] 150 I/O SDRAM data bus bit 16 M_A[12]/GPIO 151 I/O SDRAM address bus [12] or GPIO Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & Priority selection Function sft_cfg6[5]=1’b1 M_A[12] (default) (other) GPIO[18] Audio Interface (10) A_DATA[4] / GPIO 163 I/O Serial audio data output for channel 9/8 or GPIO Priority selection A_IEC_RX/GPIO 164 I/O sft_cfg3[5]=1’b1 A_DATA[4] (default) (other) GPIO[57] IEC-958 receive data Priority selection A_IEC_TX/GPIO 165 I/O 166 I/O A_IEC_RX (default) (other) GPIO[58] IEC-958 transmit data 168 I/O A_IEC_TX (default) (other) GPIO[19] Serial audio data output for channel 1/0 or GPIO Function sft_cfg3[7]=1’b1 A_DATA[0] (default) (other) GPIO[20] Serial audio data output for channel 3/2 or GPIO Priority selection © Sunplus Technology Co., Ltd. Proprietary & Confidential Function sft_cfg3[7]=1’b1 Priority selection A_DATA[1] / GPIO Function sft_cfg3[7]=1’b1 Priority selection A_DATA[0] / GPIO Function Function sft_cfg3[7]=1’b1 A_DATA[1] (default) (other) GPIO[21] 13 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A Signal Pin State A_DATA[2] / GPIO 169 I/O Description Serial audio data output for channel 5/4 or GPIO Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & Priority selection A_DATA[3] / GPIO 170 I/O sft_cfg3[3]=1’b1 A_DATA[2] (default) (other) GPIO[59] Serial audio data output for channel 7/6 or GPIO Priority selection A_LRCK/GPIO 171 I/O 173 I/O A_DATA[3] (default) (other) GPIO[60] PCM data output L/R strobe 174 I/O Function sft_cfg3[6]=1’b1 A_LRCK (default) (other) GPIO[61] PCM bit clock Priority selection A_XCK/GPIO Function sft_cfg3[4]=1’b1 Priority selection A_BCK/GPIO Function Function sft_cfg3[7]=1’b1 A_BCK (default) (other) GPIO[22] Audio over-sampling clock Priority selection Function sft_cfg3[7]=1’b1 A_XCK (default) (other) GPIO[23] GPIO (7) GPIO 31 I/O GPIO pin Priority selection © Sunplus Technology Co., Ltd. Proprietary & Confidential Function sft_cfg2[8:5]=4’b1110 UART1_TX sft_cfg1[6]=1’b1 ISA_CH_RDY sft_cfg5[2:0]=3’b011 DSP_IRQE sft_cfg5[8:6]=3’b011 RI_INT[12] sft_cfg5[11:9]=3’b011 RISC_INT[3] sft_cfg5[14:12]=3’b011 RISC_INTE[1] (other) GPIO[4] (default) 14 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A Signal IR_IN/TDM_DR Pin State 153 I/O Description GPIO (for IR) or TDM data receive Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & Priority selection VFD_CLK/TDM_D X 154 I/O Function sft_cfg4[14:13]=2’b10 TDM_DR (other) GPIO[53] (default) GPIO (for VFD clock) or TDM data transmit This pin must be pull-high to 3.3v. Priority selection VFD_STB/TDM_FS X 155 I/O Function sft_cfg4[14:13]=2’b10 TDM_DX (other) GPIO[54] (default) GPIO (for VFD strobe) or TDM frame sync This pin must be pull-high to 3.3v. Priority selection VFD_DATA/TDM_C 156 I/O LK Function sft_cfg4[14:13]=2’b10 TDM_FSXR (other) GPIO[55] (default) GPIO (for VFD data) or TDM clock This pin must be pull-high to 3.3v. Priority selection UA0_RX/GPIO 175 I/O Function sft_cfg4[14:13]=2’b10 TDM_CLK (other) GPIO[56] (default) UART #0 data receive or GPIO Priority selection UA0_TX/GPIO 176 I/O Function sft_cfg2[4:2]=3’b101 UART0_RX (default) (other) GPIO[62] UART #0 data transmit or GPIO Priority selection Function sft_cfg2[4:2]=3’b101 UART0_TX (default) (other) GPIO[63] Audio ADC pins (4) AIN/AIN_L AI_BCK © Sunplus Technology Co., Ltd. Proprietary & Confidential 157 A ADC input (left channel, with OP) (bonding option) Digital audio input interface bit clock 15 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A Signal ATO Pin State 158 A AI_LRCK Description ADC OP output. When not used, connect a 0.1uF to ground. (bonding option) Digital audio input interface L/R strobe Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & AIN_R 159 A AI_DATA VM ADC input (right channel) (bonding option) Digital audio input interface data 160 A ADC input voltage reference. When not used, connect a 0.1uF to ground. TV DAC (10) V_COMP 178 A Compensation pin. A 0.1pF ceramic capacitor must be used to bypass this pin to VSSA. The lead length must be kept as short as possible to avoid noise. V_BIAS 179 V_FSADJ 180 A Full-Scale adjustment control pin. The full-scale current of D/A converters can be adjusted by connecting a resistor (RSET) between this pin and ground. V_REFOUT 181 A Voltage reference output. It generates typical 1.2V voltage reference and may be used to drive V_REFIN pin directly. V_DAC[0] 182 A Video DAC output #0. This is a high-impedance current source output. These outputs can drive a 37.5 Ω load directly. V_DAC[1] 185 A Video DAC output #1. This is a high-impedance current source output. These outputs can drive a 37.5 Ω load directly. V_DAC[2] 186 A V_DAC[3] 189 A Video DAC output #2. This is a high-impedance current source output. These outputs can drive a 37.5 Ω load directly. Video DAC output #3. This is a high-impedance current source output. These outputs can drive a 37.5 Ω load directly. V_DAC[4] 190 A Video DAC output #4. This is a high-impedance current source output. These outputs can drive a 37.5 Ω load directly. V_DAC[5] 193 A Video DAC output #5. This is a high-impedance current source output. These outputs can drive a 37.5 Ω load directly. Servo Digital Interface (16) TRAY_OUT 195 (Servo digital pins) SC1_OUT 196 (Servo digital pins) SPDC_OUT 197 (Servo digital pins) SC_OUT 198 (Servo digital pins) DMEA 199 (Servo digital pins) FGIN 200 (Servo digital pins) SRV_SCLK 19 (Servo digital pins) SRV_SDATA 20 (Servo digital pins) SRV_SDEN 21 (Servo digital pins) SRV_DFCT 22 (Servo digital pins) T_PLCK 23 (Servo digital pins) T_SLRF 25 (Servo digital pins) TDM_DX/ttin0_4/G 26 I/O TDM output data or GPIO 27 I/O TDM master clock or GPIO PIO TDM_CLK/ttin1_5/ GPIO © Sunplus Technology Co., Ltd. Proprietary & Confidential 16 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A Signal TDM_FSXR/ttin2_6 Pin State 28 I/O Description TDM input/output frame signal or GPIO /GPIO Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & TDM_DR/ttin3_7/G 29 I/O TDM input data or GPIO PIO/R_CS4_B Servo Analog Interface (25) TEO 203 A (Servo analog pins) FEO 204 A (Servo analog pins) HGIN 206 A (Servo analog pins) LGIN2 207 A (Servo analog pins) LGIN1 208 A (Servo analog pins) LPFNIN 209 A (Servo analog pins) PDFLT1 210 A (Servo analog pins) FDFLT 211 A (Servo analog pins) VREFO 212 A (Servo analog pins) PDRSET 214 A (Servo analog pins) FDRSET 215 A (Servo analog pins) DRESET 1 A (Servo analog pins) CNIN 2 A (Servo analog pins) SLVL 3 A (Servo analog pins) RFO 5 A (Servo analog pins) RFRP 7 A (Servo analog pins) RFRPLP 8 A (Servo analog pins) TEXOLP 9 A (Servo analog pins) TEXO 10 A (Servo analog pins) TEI 12 A (Servo analog pins) FEI 13 A (Servo analog pins) CSI 14 A (Servo analog pins) SBAD 15 A (Servo analog pins) VREF 16 A (Servo analog pins) VRGD 17 A (Servo analog pins) Note: Please reference SPHE8200 servo datasheet for servo related information. © Sunplus Technology Co., Ltd. Proprietary & Confidential 17 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A 5.FUNCTIONAL DESCRIPTIONS SPHE8200 is a highly integrated system-on-chip design. It includes DVD/CD servo controller, RISC processor, MPEG1/2 CLKI 27MHz video decoder, programmable audio decoder, programmable PLLa CLK_PLLA 147.456MHz 135.4752MHz AUDCLK_GEN XCK ADCLK IECCLK Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & peripheral controller, audio ADC and multi-format TV-encoder on a single chip. 5.2. Power Control 5.1. PLL and ClockGen SPHE8200 provides various levels of power-control mechanism in SPHE8200 contains two PLLs to generate system clock (PLLv) order to achieve minimum power consumption. and audio reference clocks (PLLa). Both the PLLs reference a Automatic power-save: single external 27MHz clock or crystal to generate all the required clocks. Most hardware modules are automatically power-saved when System clock is then derived from division of the PLLv output. not operating. Module-level stop-operation: SPHE8200 provides a function to turn off specific module from operating. Without explicit wake-up, the hardware module will CLKI 27MHz PLLv Fractional multiples of CLKI CLK_PLL SYSCLK_GEN /2, /4 ~ /65536 remain static and consume very little power. SYSCLK System-level doze: For maximum power-saving, firmware could fine-tune system Option Video Clock In VIDCLK_GEN performance according to system task. VIDCLK 5.3. Embedded 32-bit RISC Controller SPHE8200 includes a powerful 32-bit RISC processor. This RISC Some pre-defined PLLv/SYSCLK frequencies are listed below: SYSCLK Frequency processor is utilized to manage decoding tasks as well as UI tasks. PLLV Frequency 101.25MHz 405MHz 108MHz 216MHz 114.75MHz 459MHz 121.5MHz 486MHz 128.25MHz 256.5MHz 135MHz 270MHz 141.75MHz 283.5MHz 148.5MHz 297MHz 155.25MHz 310.5MHz 162MHz 324MHz 168.75MHz 337.5MHz 175.5MHz 351MHz 182.25MHz 364.5MHz 189MHz 378MHz It can access to all the memory and devices, cooperate between processor systems. Audio decoder and I/O processor handshake with RISC processor through the mailbox registers. mailbo (16x16 Audio decoder mailbo (16x8) I/O processo RISC subsyste Figure 5-1: Communication between processors The RISC processor is equipped with instruction and data caches. These caches can accelerate accesses to the SDRAM or ROM cacheable regions. PLLa supports two center frequencies (for 48kHz family or 44.1kHz family) and generates required audio clocks from the audio system clock. © Sunplus Technology Co., Ltd. Proprietary & Confidential 18 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A edge-trigger and level-sensitive mode. BIU Processor Local Bus RISC32 core SMMU I-CACHE Peripheral Control bus Other modules ROM/Flash interface ROM FLASH SRAM Watchdog: Watchdog keeps monitoring RISC behavior and whenever firmware is in a deadlock, it can try to reset the system and Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & System Bus Interface D-RAM DMA keep the application functioning continuously. Timers System Bus D-CACHE DRAM There are 4-channel timers and 2 cascade counters for timed tasks. During A/V decoding, counters are utilized to synchronize audio and video. Figure 5-2: RISC subsystem Table: RISC processor configuration I-Cache 8kbyte (2-way set associated) D-Cache 4kbyte (direct-mapped) D-RAM/DMA 1kbyte scratch buffer to RISC interrupt Device interrupt controller The RISC sub-system is able to bootstrap from multiple sources. peripheral control bus RISC subsystem Specification RISC monitor monitor interrupt Watchdog watchdog reset Timers timer interrupt In typical application the RISC processor boots from external ROM device #1. Besides that, it also supports standalone booting Figure 5-3: RISC dedicated hardware without pre-loaded firmware. Table: Device interrupt controller sources 5.4. RISC interface Symbol RISC controllers interface to system via various interface control INT_WDOG modules. These interface modules are mapped to the processor Description Watchdog interrupt (if reset disabled) INT_HSYNC Interrupt when horizontal resync INT_VSYNC Interrupt when enter vertical resync INT_FLD_ACT Interrupt when enter active region INT_FLD_SYNC Interrupt when leave active region INT_HOST Host device interrupt INT_TIMER0 Timer 0 interrupt The RISC memory mapping of these controllers is shown in INT_TIMER1 Timer 1 interrupt following table: INT_TIMER2A Timer 2 scale interrupt Table: RISC memory mapping INT_TIMER2B Timer 2 count interrupt INT_TIMER3A Timer 3 scale interrupt memory map and firmware could operate on them via typical memory accesses. These controllers include: ROM/FLASH/SRAM (RFS) controller RISC Memory Interface controller (SDRAM) Peripheral control interface Memory range Description SDRAM (cached) INT_TIMER3B Timer 3 count interrupt a000_0000-a7ff_ffff SDRAM (uncached) INT_TIMERW Watchdog timer interrupt 8800_0000-8fbf_ffff ROM/FLASH/SRAM (cached) INT_UART0 UART0 interrupt a800_0000-afbf_ffff ROM/FLASH/SRAM (uncached) INT_UART1 UART1 interrupt affe_8000-affe_ffff Peripheral control registers INT_VDP0 Video decoder interrupt afff_0000-afff_03ff DMA buffer INT_DSP DSP interrupt INT_EXT0 External interrupt #0 In additional to that, SPHE8200 includes dedicated RISC INT_EXT1 External interrupt #1 peripherals to assist the system tasks: INT_EXT2 External interrupt #2 INT_EXT3 External interrupt #3 8000_0000-87ff_ffff Device interrupt controller: Device interrupt controller takes care of interrupt sources from INT_IOP IOP interrupt on-chip devices and off chip sources. For each interrupt source INT_AUD Audio hardware interrupt the firmware is able to configure the interrupt behavior between © Sunplus Technology Co., Ltd. Proprietary & Confidential 19 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A 5.5. ROM/Flash/SRAM controller 5.7. Peripheral Control Interface The SPHE8200 provides flexible connections to external ROM, RISC firmware controls on-chip devices (such as video decoder, Flash or SRAM (RFS). It can support up to 4 external RFS devices audio decoder..) by a dedicated peripheral control interface. by using different chip-selects (R_CS_B[3:0]). The firmware can Firmware controls the hardware behavior by writing to specific configure RFS memory anchor registers and map these devices hardware registers with this interface. Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & into locations of memory space. For each memory space it can be in flash mode or in ISA mode. 5.8. CSS/CPPM support In FLASH mode the access timing is decided by wait-state setting, while in ISA mode the SPHE8200 have built-in CSS and CPPM hardware support. For controller will reference external IO_CHRDY input. CSS the system supports accelerated DMA. For CPPM the system supports C2_D/C2_E and C2_DCBC functions. Prefetch buffer 5.9. MPEG Video Decoder The system incorporates a powerful MPEG video decoding Processor local bus Address translator External ROM interface Address sequencer datapath and provides real-time video decoding of MPEGI/II bitstream. The bitstream can come from Servo hardware, ATAPI, TDM or UART. This enables various applications to be built over SPHE8200 such as real-time broadcasting over Ethernet. Wait state generation The video decoder is a hardwired MPEG1/2 datapath. The system Figure 5-4: ROM/FLASH/SRAM controller architecture is as in the figure. RISC subsystem is in charge of de-multiplexing the data and buffering formatted video data into ROM/Flash mode video bitstream buffer resided in external SDRAM. Upon correct CSB wait wait ADDR[] Address (read) Address (write) reconstructed video frame for playback. oe_hold we_setup DATA[] Data (read) we_hold DATA (for write) RISC subsystem data is sampled at this point bitstream Figure 5-5: ROM/FLASH/SRAM mode timing ISA MODE memory bus wait ADDR[] OEB Video decoder iochrdy_hold Address (read) oe_setup wait iochrdy_hold all data CSB control bus reconstruct WEB bitstream oe_setup reference OEB timing video decoder will decode the bitstream and write back Address (write) oe_hold WEB we_setup External SDRAM we_hold IO_RDY DATA[] Data (read) DATA (for write) Figure 5-7: Interface between RISC and Video decoder data is sampled at this point Advanced video decoding and display control mechanism is Figure 5-6: ISA mode timing included to prevent tearing effect. 5.6. RISC Memory Interface RISC memory interface provides a fast-path between processor local bus and system memory bus. Local bus transactions are mapped to system memory bus tasks. © Sunplus Technology Co., Ltd. Proprietary & Confidential 20 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A Video contrast/bright/color enhancement Picture control During runtime video post-processing hardware will fetch video Q matrix sources from framebuffer and process the data as in the following figure. Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & Variable length decoder input FIFO Memory Interface Inverse quantization line buffer input buffer Inverse DCT Motion compensation output buffer from memory interface input buffer DCT buffer display information Vertical filtering d chroma resampl de-interlac CIF and horizonta expansio to display interface de-interlac buffer Decoding control 5.12. Audio DSP Figure 5-8: architecture of video decoding pipeline The SPHE8200 contains a high-performance 24-bit audio DSP optimized for embedded systems. The DSP processor can fetch 5.10. Graphics Engine BondyPro® operands For thin-client or set-top box applications, 2D graphics capabilities are key to system performance. This graphics engine is able to Upon receiving command from and perform During at the same time the ICACHE will store the LRU instructions. is combined with 2 parts: graphics command interpreter and datapath. memories execution the DSP fetches instruction from main-memory or IROM, perform fast BitBlt and 2D drawing functions. The graphics engine graphics from multiplication-and-accumulation (MAC) in one cycle. Data are loaded from and to main-memory by using the RISC, cycle-stealing interpreter will send micro-commands to graphics datapath, where DMA channels. There are 3 independent cycle-stealing DMA channels that allow DSP run without stalled by raster operations are executed. memory access. The DSP works closely with RISC processors by using mailbox Grap comma interpret registers or shared-memory protocol. When downloaded with Grap data different codec firmware the DSP could support multi-standard RISC subsyste audio and act as an accelerator for RISC in some case. Graph work Memo Interfa IROM Figure 5-9: BondyPro® architecture ICACHE 5.11. Video Post Processing data ROM DSP SPHE8200 includes powerful video-post-processing facilities to BIU data RAM provide high video quality. It perform following functions: YUV411, YUV420, YUV422 and 8-bit indexed color Memory interface data RAM SIF to CCIR601 interpolation MPEG1 CIF filter data ROM MPEG1/2 chroma vertical interpolation Up to 1/2x horizontal decimation Up to 1/512x vertical decimation audio interface controller Figure 5-10: Audio DSP architecture Up to 1024x horizontal expansion Up to 1024x vertical expansion Powerful de-interlacing hardware Pan and scan function De-flicker during interlaced display © Sunplus Technology Co., Ltd. Proprietary & Confidential 21 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A 5.13. Audio Interface For power-constrained applications SPHE8200 also implements The audio interface is in charge of servicing DSP and maintaining SDRAM power-down modes to save dynamic operating power. all audio-related tasks. It will buffer the DSP processed audio 5.17. Sub-picture Decoder playback data and format them to audio DAC required format. Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & For DVD and SVCD sub-picture content SPHE8200 includes an advanced multi-format sub-picture decoder. It could support Buffer control Memory Interface IEC-958 input digital input interface digital audio input ADC ctrl Audio work buffer real-time decode and display from raw sub-picture bitstream. IEC958 ADC Vertical interpolation is supported for PAL/NTSC translation or special effect. analog in 5.18. On Screen Display The on screen display (OSD) function of the SPHE8200 provides PCM playback digital audio output IEC958 IEC-958 output an overlay bitmap graphics on the final TV display. Applications can use this function to display specific information over the video display plane without operating on the video source. The SPHE8200 can display multiple OSD regions on a single Figure 5-11: Audio Interface architecture display frame, where every OSD regions can be in different size, location and color format. The OSD hardware supports 4, 16, SPHE8200 support following audio DAC format combinations: 256 indexed color or 16-bit direct color. 32k 44.1k 48k 64k 88.2k 96k 192k 256fs ok ok ok ok ok ok ok 384fs ok ok ok ok ok ok ok Data alignment in main memory before display. During display, OSD decoder would read these header and data and interpret to be a graphic data that overlay with video to be output to the display interface. 5.19. Display Interface Left adjust, I2S, normal format LRCK frame width 16b, 24b, 32b, 64b Data bits 16b, 18b, 20b, 24b Data sign extension zero-extended, sign-extended OSD regions are stored The display interface of SPHE8200 integrates the video content generated from video-post-processing, sub-picture-decoder and on-screen-display modules. It also performs content cropping, underflow and overflow detection, and overall bright/contrast adjustment. 5.14. Integrated Audio Quality ADC The embedded ADC is a 2-channel 64fs over-sampling ADC Video active of12-bit quality. If required it could operate under 128fs over-sampling. Sub-picture active OSD active (1.0 - sup_blend_factor) blank (black) Video processed source data 5.15. I/O Processor TV data output The SPHE8200 includes an 8-bit micro-controller to handle most sub-picture source data I/O jobs. IR, VFD and other slow devices can be interfaced using (1.0 - osd_blend_factor) (sup_blend_factor) this I/O processor. OSD source (osd_blend_factor) 5.16. SDRAM Controller Figure 5-12: Display pipeline SDRAM controller in SPHE8200 is very flexible and powerful. It was designed to meet different SDRAM timing requirement while achieving maximum performance. SDRAM tasks are optimized for maximum system performance. DRAM refreshing is issued automatically whenever required or SDRAM interface is idle for a given time. © Sunplus Technology Co., Ltd. Proprietary & Confidential 22 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A ATA/ATAPI compliant devices directly. The ATAPI/IDE interface is The video enhancement process is show in following figure: a standard ATA-5 host interface capable of PIO mode 2 to PIO mode 4 to external devices. By implementing this interface system OSD sub-picture could support IDE hard-disk drives, compact flash cards, ATAPI Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & Video post processing Display interface vid[] video source enhancement and bright/ contrast/color control TV-encoder dac[] DAC based DVDROM loaders or other ATA compliant devices. analog video DAC gain, linearity adjustment 5.22. GPIO In SPHE8200 almost every pin that related to selectable features can serve as general-purpose input-output control function. When Figure 5-13: Display pipeline a pin is programmed to this mode, the RISC can take full control 5.20. Video DAC over the direction and output level. SPHE8200 contains 6-channel 10-bit high-speed current-source DACs operating from 27MHz to 60MHz (for 480p/576p or SVGA 5.23. UART display). The DAC outputs can drive a 37.5Ohm load directly. Two UART channels are provided for debugging or communication purpose. The UART can support standard serial 5.21. ATAPI interface port baud-rate and formats. It also supports auto baud-rate SPHE8200 also supports ATAPI interface directly without glue detection and hardware flow-control (CTS/RTS pair). logic. Although the SPHE8200 has integrated DVD/CD servo logics, with this interface the application could support other © Sunplus Technology Co., Ltd. Proprietary & Confidential 23 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A 6.ELECTRICAL SPECIFICATIONS 6.1. Absolute Maximum Ratings Parameter Symbol Value Unit Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & Voltage on any pin relative to Vss VIN -0.3 to 5.5 V Voltage on VDDIO supply relative to VSS VDDIO -0.3 to 3.6 V Voltage on VDDK supply relative to VSS VDDK -0.3 to 1.98 V TSTG -55 to 150 °C TSOLDER 240 (for 5 Sec. Max.) °C IOS 50 mA Storage Temperature Soldering Temp. (Max. Time) Short circuit current Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied and exposure to absolute maximum rating conditions for extended periods may affect device reliability. 6.2. DC Operating Conditions Recommended Operating Conditions (Voltage referenced to VSS=0V, TA=-0 to 70°C) Symbol Min. Typ. Max. Units Voltage on VDDK supply relative to VSS Parameter VDDK 1.62 1.8 1.98 V Voltage on VDDIO supply relative to VSS VDDIO 3.0 3.30 3.6 V Input logic high voltage VIH 2.0 - 5.5 V Input logic low voltage VIL -0.3 - 0.8 V Output logic high voltage VOH 2.4 - - V Output logic low voltage VOL - - 0.4 V IL -10 - 10 uA Symbol Min. Typ. Max. Units CIN - 3.5 - pF Input leakage current 6.3. Capacitance (VDDIO=3.3V, TA=24°C, f=108MHz, VREF=1.4V+-200mV) Parameter Input pin capacitance Input pin capacitance COUT - 3.5 - pF Bidirectional pin capacitance CBIDIR - 3.5 - pF © Sunplus Technology Co., Ltd. Proprietary & Confidential 24 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A 6.4. AC Characteristics 6.4.1. SDRAM interface timing diagrams Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & tCH 0 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK tCL CKE tCC tRAS tRC CS tRP tSH RAS tCCD tRCD tSS CAS RAa ADDR CAa RBb CBb RAc CAc BA RAa A10/AP RBb RAc *Note 1 tRRD tCDL DQ CL=2 CAa0 CAa1 CAa2 CAa3 CAa0 CAa1 CAa2 DBb0 DBb1 DBb2 DBb3 DBb0 DBb1 DBb2 DBb3 CAc0 CAc1 CAc2 CAc0 CAc1 tSAC CL=3 CAa3 tSLZ DH WE DQM Row Active (A-Bank) 0 1 Read (A-Bank) 2 Row Active (B-Bank) 3 4 5 6 Write (B-Bank) Precharge (A-Bank) 7 8 9 10 11 12 Read (A-Bank) Row Active (A-Bank) 13 14 15 16 : Don't care 17 18 19 CLOCK HIGH CKE CS RAS CAS ADDR RAa CAa CAb BA A10/AP RAa tBDL DQ DAa0 DAa1 DAa2 DAa3 tRDL DAa4 DAb0 DAb1 DAb2 DAb3 DAb4 DAb5 WE DQM Row Active (A-Bank) © Sunplus Technology Co., Ltd. Proprietary & Confidential Write (A-Bank) Write (A-Bank) Burat Stop 25 Precharge (A-Bank) OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A (Recommended condition for DVD playback is listed in typical condition with f=121.5MHz) Parameter Symbol Min Typ Max Units Row active to row active delay tRRD 1 2 4 *1 System clock cycle RAS to CAS delay tRCD 1 2 4 *1 System clock cycle Row precharge time tRP 1 2 4 *1 System clock cycle Row active time tRAS 1 5 8 *1 System clock cycle Row cycle time tRC 1 8 32 *1 System clock cycle Last data in to new column address delay tCDL 1 1 4 *1 System clock cycle Column address to column address delay tCCD 1 1 1 CLK cycle time *2 tCC 6 8.2 1000 ns CLK to valid SDRAM output delay *2 tSAC - 6.0 6.5 ns SDRAM output data hold time *2 tOH 1 2 - ns CLK high pulse width *3 tCH - 3 - ns CLK low pulse width *3 tCL - 3 - ns CLK to SDRAM output Low-Z tSLZ - 1.0 (tCC) ns CLK to SDRAM output High-Z tSHZ - 6.0 (tSAC) ns Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & System clock cycle *1 Using maximum values may limit system performance. *2 Width of data window can be estimated from (tCC-tSAC+tOH). *3 Width of clock pulse depends on system clock cycle. 6.4.2. ROM / flash interface timing diagrams ROM Compatible Mode CSB tACCESS tACCESS ADDR[] Address (read) Address (write) OEB tWES WEB tDS tDH Data (read) DATA[] tWEH DATA (for write) Figure 6-1: ROM / flash interface ROM mode access timing Parameter Symbol Min Typ Max Units tACCESS 2 8 *1 31 System clock cycle tDS 5 - - Data hold time for read tDH 0 - - Address/data setup time before write strobe tWS 0 1 31 System clock cycle Address/data setup time after write strobe tWH 0 1 31 System clock cycle ROM / SRAM / flash access time Data setup time for read ns ns *1 Recommended value when f=121.5MHz © Sunplus Technology Co., Ltd. Proprietary & Confidential 26 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A ISA Compatible Mode CSB tACCESS tACCESS Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & Address (read) ADDR[] Address (write) OEB tWES WEB tOH tWAIT tWEH tWAIT tIH tIH tOH IO_RDY Data (write) Data (read) DATA[] Figure 6-2: ROM / flash interface ISA mode access timing Parameter Symbol Min Typ Max Units ISA access time *1 tACCESS 2 - 31 IO_RDY wait time tWAIT 0 - 1000 System clock cycle Output hold time tOH 1 - - Input hold time tIH 0 - - Address/data setup time before write strobe tWS 0 1 31 System clock cycle Address/data setup time after write strobe tWH 0 1 31 System clock cycle ns System clock cycle ns *1 After this period of time IO_RDY_B must be stable and indicates correct status of target device. 6.4.3. Audio interface timing diagrams Some audio interface configuration timing diagrams are shown below. 0 1 22 23 0 1 2 22 23 BCK LRCK left channel AUDATA[] 23 22 21 2 right channel 1 0 MSB 23 22 21 2 1 0 LSB MSB LSB Figure 6-3: Normal mode / 24bit data / 24bit frame / MSB first 0 1 8 9 30 31 0 1 30 31 1 0 0 BCK LRCK AUDATA[] left channel 23 22 right channel 21 2 1 MSB 0 2 LSB Figure 6-4: Right justified (normal) mode / 24bit data / 32bit frame / MSB first © Sunplus Technology Co., Ltd. Proprietary & Confidential 27 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A 0 1 2 22 23 24 31 0 1 2 31 0 BCK Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & LRCK left channel AUDATA[] 23 22 21 right channel 1 MSB 0 23 22 21 LSB Figure 6-5: Left justified mode / 24bit data / 32bit frame / MSB first 0 1 2 3 23 24 25 31 0 1 2 3 31 0 1 BCK LRCK D left channel AUDATA[] 23 22 21 D 2 1 right channel 0 MSB 23 22 LSB Figure 6-6: I2S mode / 24bit data / 32bit frame 0 1 2 22 23 0 1 2 22 23 0 2 1 0 BCK LRCK left channel D AUDATA[] 23 22 21 D 2 1 right channel 0 MSB 23 22 21 LSB MSB LSB 2 Figure 6-7: I S mode / 24bit data / 24bit frame Parameter Symbol Min Typ Max Units BCK rising to LRCK / AUDATA transition tS - 0.5 - System clock cycle 6.4.4. Video timing diagrams Interlaced Modes SP active period SP active period active line period V blanking period (21) active line period Video line number 522 523 524 525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 0 2 4 6 8 10 12 SP line number 473 475 477 479 Video line number 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 SP line number 474 476 478 active line period 1 V blanking period (21) 3 5 7 9 11 active line period SP active period SP active period Figure 6-8: NTSC (480i) timing diagram © Sunplus Technology Co., Ltd. Proprietary & Confidential 28 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A SP active period SP active period active line period V blanking period (23.5) active line period Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & Video line number 619 620 621 622 623 624 625 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 0 2 4 6 8 SP line number 567 569 571 573 Video line number 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 SP line number 474 476 478 1 active line period V blanking period (24) 3 5 7 9 active line period SP active period SP active period Figure 6-9: PAL (576i) timing diagram Progressive Modes SP active period SP active period active line period 521 522 523 524 525 476 477 478 479 active line period 1 2 3 4 5 6 7 8 9 10 11 12 13 14 44 45 46 47 48 49 50 51 0 1 2 3 4 5 6 Figure 6-10: NTSC (480p) timing diagram SP active period SP active period active line period active line period 617 618 619 620 621 622 623 624 625 1 2 3 4 5 6 7 8 9 572 573 574 575 43 44 45 46 47 48 49 50 51 0 1 2 3 4 5 6 Figure 6-11: PAL (576p) timing diagram © Sunplus Technology Co., Ltd. Proprietary & Confidential 29 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A 7.REGISTER LIST Name Address Description GROUP 0 System Control Registers Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & sft_cfg0 0xbffe8044 Configure pin-mux 0 sft_cfg1 0xbffe8048 Configure pin-mux 1 sft_cfg2 0xbffe804c Configure pin-mux 2 sft_cfg3 0xbffe8050 Configure pin-mux 3 sft_cfg5 0xbffe8058 Configure pin-mux 5 sft_cfg6 0xbffe805c Configure pin-mux 6 0xbffe8044 sft_cfg0 Description Pin MUX control register #0 (General) Attribute: RW 15 14 Bit-field 13 12 RA26 11 10 RA25 9 8 RA24 7 6 RA23 5 4 RA22 3 2 RA21 1 RA20 0 RA19 Reset_2 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reset_3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 Reset_* 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 Reset_2: reset default when hardware-configuration is set to 2 Reset_3: reset default when hardware-configuration is set to 3 Reset_*: reset default for other hardware-configuration RA19 ROM address bus bit 19 (R_A19) select 0: R_A19 is not available and ignored 1: Enable (default) RA20 ROM address bus bit 20 (R_A20) select 00: R_A20 is not available and ignored 01: R_A20 is available at pin 19 10: R_A20 is available at pin 129 11: Reserved RA21 ROM address bus bit 21 (R_A21) select 00: R_A21 is not available and ignored 01: R_A21 is available at pin 20 10: R_A21 is available at pin 130 11: Reserved RA22 ROM address bus bit 22 (R_A22) select 00: R_A22 is not available and ignored 01: R_A22 is available at pin 21 10: R_A22 is available at pin 131 11: reserved © Sunplus Technology Co., Ltd. Proprietary & Confidential 30 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A RA23 ROM address bus bit 23 (R_A23) select 00: R_A23 is not available and ignored 01: R_A23 is available only at 256 pin package Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & 10: R_A23 is available at pin 133 11: reserved RA24 ROM address bus bit 24 (R_A24) select 00: R_A24 is not available and ignored 01: R_A24 is available only at 256 pin package 10: R_A24 is available at pin 134 11: reserved RA25 ROM address bus bit 25 (R_A25) select 00: R_A25 is not available and ignored 01: R_A25 is available only at 256 pin package 10: R_A25 is available at pin 135 11: reserved RA26 ROM address bus bit 26 (R_A26) select 00: R_A26 is not available and ignored 01: R_A26 is available only at 256 pin package 10: R_A26 is available at pin 136 11: reserved 0xbffe8048 sft_cfg1 Description Pin MUX control register #1 (General) Attribute: RW 15 Bit-field Reset CS1 14 LPT 0 13 12 BOOT 0 0 11 10 pcmcia_WAIT 0 0 9 8 7 pcmcia_IORW 0 0 0 0 6 5 4 3 2 1 0 CHRDY WE OE CS4 CS3 CS2 CS1 0 1 1 1 1 1 1 CS1 (ROM/FLASH chip select 1) function control 1: Enable Chip Select 1 (default) 0: Disable (CS1 becomes GPIO) CS2 CS2 (ROM/FLASH chip select 2) function control 1: Enable Chip Select 2 (default) 0: Disabled (CS2 becomes GPIO) CS3 CS3 (ROM/FLASH chip select 3) function control 1: Enable Chip Select 3 (default) 0: Disabled (CS3 becomes GPIO) CS4 CS4 (ROM/FLASH chip select 4) function control © Sunplus Technology Co., Ltd. Proprietary & Confidential 31 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A 1: Enable Chip Select 4 (default) 0: Disabled (CS4 becomes GPIO) OE OEB (ROM/FLASH output enable) function control Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & 1: Enable OE function (default) 0: Disabled (OEB becomes GPIO) WE WEB (FLASH/SRAM write enable) function control 1: Enable WEB function (default) 0: Disabled (WEB becomes GPIO) CHRDY IOCHRDY (ISA_IOCHRDY) function control 1: Enable IOCHRDY input (i.e. output always tri-stated) 0: Disabled (default) pcmcia_IORW PCMCIA IOR/IOW select 000: Disabled (default) 001: IOR from pin 19, IOW from pin 20 010: IOR from pin 135, IOW from pin 136 011: IOR from pin 58, IOW from pin 59 100: Available only at 256 pin package 101 to 111: Reserved pcmcia_WAIT bit 12-10 : PCMCIA_WAIT_B select 000: Disabled (default) 001: PCMCIA_WAIT_B is from pin 21 010: PCMCIA_WAIT_B is from pin 61 011: PCMCIA_WAIT_B is from pin 129 100: PCMCIA_WAIT_B is from pin 138 101: Available only at 256 pin package 011 to 111: reserved BOOT RISC32 reset boot address 0: RISC32 boots from bfc0_0000 (internal ROM) (default) 1: RISC32 boots from 8000_0000 (SDRAM region) LPT LPT handshake signals (STROBE, ACK) select 00: Disabled (default) 01: LPT STROBE is from pin 62, LPT ACK is from pin 64 10: LPT STROBE is from pin 135, LPT ACK is from pin 136 11: Available only at 256 pin package © Sunplus Technology Co., Ltd. Proprietary & Confidential 32 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A 0xbffe804c sft_cfg2 Description Pin MUX control register #2 (General) Attribute: RW Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & 15 14 13 12 Bit-field SWAP BRS BRP BRE Reset 0 0 0 0 ATAPI 11 10 9 8 7 0 0 0 TV_LCD 0 0 6 5 4 0 1 UART1 0 3 2 UART0 0 1 1 0 IOP ATAPI 0 0 ATAPI interface 0: Disable (default) 1: Enabled IOP IOP reset system 0: Disable (default) 1: Enabled UART0 UART0 select 000: Disabled 001: UA0_RX is from pin 19, UA0_TXD is from pin 20 010: UA0_RX is from pin 65, UA0_TXD is from pin 66 011: UA0_RX is from pin 130, UA0_TXD is from pin 131 100: UA0_RX is from pin 144, UA0_TXD is from pin 145 101: UA0_RX is from pin 175, UA0_TXD is from pin 176 (default) 011,111: available only at 256 pin package UART1 UART1 function selection 0000: Disable (default) 0001-1111: Please refer to pin-description TV_LCD TV LCD function selection 000: Disable (default) 001-111: please refer to pin-description BRE Bootstrap enable bit 0: Disable (default) 1: Enable BRP Bootstrap RXD pull up enable (pin 175) 0: Internal pull up disable (default) 1: Internal pull up enable BRS Bootstrap UART select 0: Bootstrap from UART0 (default) 1: Bootstrap from UART1 SWAP SWAP UART0 and UART1 0: No swap (default) © Sunplus Technology Co., Ltd. Proprietary & Confidential 33 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A 1: Swap UART0 and UART1 signals 0xbffe8050 sft_cfg3 (Audio interface and TV interface control) Description Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & Pin MUX control register #3 (reference pin multiplex table for detailed information) Attribute: RW 15 Bit-field Reset EDAC 14 pc_SYNC 0 13 12 11 TELETEXT 0 0 0 10 9 8 0 0 SYNC 0 0 7 6 5 4 3 AUD LRCK AU4 AU3 AU2 1 1 1 1 1 2 1 0 EADC 0 0 0 External ADC select 000: Disabled (default) 001: BCK is from pin 19, LRCK is from pin 20, DATA is from pin 21 010: BCK is from pin 58, LRCK is from pin 59, DATA is from pin 60 011: BCK is from pin 34, LRCK is from pin 35, DATA is from pin 37 100: BCK is from pin 130, LRCK is from pin 131, DATA is from pin 133 101: BCK is from pin 141, LRCK is from pin 143, DATA is from pin 144 110: Available only at 256 pin package 111: reserved AU2 Audio DAC interface data #2 (AU_DATA[2]) function control 0: Disabled (AU_DATA[2] becomes GPIO) 1: Enable (default) AU3 Audio DAC interface data #3 (AU_DATA[3]) function control 0: Disabled (AU_DATA[3] becomes GPIO) 1: Enable (default) AU4 Audio DAC interface data #4 (AU_DATA[4]) function control 0: Disabled (AU_DATA[4] becomes GPIO) 1: Enable (default) LRCK Audio DAC interface LRCK function control 0: Disable 1: Enable (default) AUD Audio function 0: Disable 1: enable (default) SYNC H/V SYNC select 000: Disabled (default) 001: Reserved 010: Slave mode: HSYNC is from pin 146, VSYNC is from pin 148 011: Master mode: HSYNC is on pin 146, VSYNC is on pin 148 © Sunplus Technology Co., Ltd. Proprietary & Confidential 34 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A 100: Slave mode: HSYNC is from pin 34, VSYNC is from pin 35 101: Master mode: HSYNC is on pin 34, VSYNC is on pin 35 110, 111: available only at 256 pin package Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & TELETEXT TELETEXT select 00: Disable (default) 01: Teletext BIT is from pin 149, teletext REQ is from pin 150 10: Teletext BIT is from pin 37, teletext REQ is from pin 38 11: available only at 256 pin package pc_SYNC H/VSYNC PC select 00: Disabled (default) 01: HSYNC_PC is on pin 175, VSYNC_PC is on pin 176 10: HSYNC_PC is on pin 146, VSYNC_PC is on pin 148 11: HSYNC_PC is on pin 144, VSYNC_PC is on pin 145 0xbffe8058 sft_cfg5 Description Pin MUX control register #5 (RISC interrupt control) Attribute: RW 15 14 0 0 Bit-field Reset RISC_INT1 13 12 11 RISC_INTEXT 0 0 10 9 8 0 0 RISC_INT5_2 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RISC_INT1 0 RID INT1 bit 15 to bit 11 interrupt select 000: Disable (default) 001: INT1[11] is from pin 141, INT1[12] is from pin 143, INT1[13] is from pin 144, INT1[14] is from pin 145, INT1[15] is from pin 146 010: INT1[11] is from pin 129, INT1[12] is from pin 130, INT1[13] is from pin 131, INT1[14] is from pin 133, INT1[15] is from pin 134 011: INT1[11] is from pin 29, INT1[12] is from pin 31, INT1[13] is from pin 34, INT1[14] is from pin 35, INT1[15] is from pin 37 © Sunplus Technology Co., Ltd. Proprietary & Confidential 35 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A 100-110 : Available only at 256 pin package 111: Reserved RISC_INT5_2 RISC INT bit 5 to bit 2 interrupt select (level, active low) Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & 000: Disable (default) 001: INTRQ_N[2] is from pin 141, INTRQ_N[3] is from pin 143, INTRQ_N[4] is from pin 144, INTRQ_N[5] is from pin 145 010: INTRQ_N[2] is from pin 129, INTRQ_N[3] is from pin 130, INTRQ_N[4] is from pin 131, INTRQ_N[5] is from pin 133 011: INTRQ_N[2] is from pin 29, INTRQ_N[3] is from pin 31, INTRQ_N[4] is from pin 34, INTRQ_N[5] is from pin 35 100-110: Available only at 256 pin package 111: Reserved RISC_INTEXT RISC INTEXT_N bit 5 to bit 0 interrupt select (level, active low) 000: Disable (default) 001: INTRQ_N[0] is from pin 141, INTRQ_N[1] is from pin 143, INTRQ_N[2] is from pin 144, INTRQ_N[3] is from pin 145, INTRQ_N[4] is from pin 146 INTRQ_N[5] is from pin 148 010: INTRQ_N[0] is from pin 129, INTRQ_N[1] is from pin 130, INTRQ_N[2] is from pin 131, INTRQ_N[3] is from pin 133, INTRQ_N[4] is from pin 134, INTRQ_N[5] is from pin 135 011: INTRQ_N[0] is from pin 29, INTRQ_N[1] is from pin 31, INTRQ_N[2] is from pin 34, INTRQ_N[3] is from pin 35, INTRQ_N[4] is from pin 37, INTRQ_N[5] is from pin 38 © Sunplus Technology Co., Ltd. Proprietary & Confidential 36 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A 100-110: Available only at 256 pin package 111: Reserved Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & 0xbffe805c sft_cfg6 Description Pin MUX control register #6 (SDRAM interface control) Attribute: RW 15 14 13 12 11 10 9 Bit-field Reset SA11 0 0 0 0 1 1 8 7 6 5 4 SDQM3 SDQM2 SBA1 SA12 SA11 1 1 1 1 1 0 3 2 1 0 0 1 1 1 SDRAM address 11 enable 0: SDRAM address 11 is disabled 1: SDRAM address 11 is enabled (default) SA12 SDRAM address 12 enable 0: SDRAM address 12 is disabled 1: SDRAM address 12 is enabled (default) SBA1 SDRAM BA1 enable 0: SDRAM BA1 is disabled 1: SDRAM BA1 is enabled (default) SDQM2 SDRAM DQM2 enable 0: SDRAM DQM2 is disabled 1: SDRAM DQM2 is enabled (default) SDQM3 SDRAM DQM3 enable 0: SDRAM DQM3 is disabled 1: SDRAM DQM3 is enabled (default) © Sunplus Technology Co., Ltd. Proprietary & Confidential 37 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A 8.PACKAGE/PAD LOCATION 8.1. Outline Dimensions 216-pin LQFP Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & © Sunplus Technology Co., Ltd. Proprietary & Confidential 38 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A 9.DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, expressed, statutory implied or by description regarding the information in this publication or Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. Please note that application circuits illustrated in this document are for reference purposes only. © Sunplus Technology Co., Ltd. Proprietary & Confidential 39 OCT. 07, 2003 Preliminary Version: 0.2 www.DataSheet4U.com Preliminary SPHE8200A 10. REVISION HISTORY Date Revision # Description Page Y l ia OG t n L e if d NO INC n H o E C C E IS s u T ND LY l p C I A n N N u H S UN C E O R S S E U r M o F & JUN. 10, 2003 0.1 Original OCT. 07, 2003 0.2 Add Functional Description and Electrical Specification and Register List © Sunplus Technology Co., Ltd. Proprietary & Confidential 40 14 18-37 OCT. 07, 2003 Preliminary Version: 0.2