Real time clock module SERIAL-INTERFACE REAL TIME CLOCK MODULE RTC-4553 • Builtin crystal unit allows adjustment-free efficient operation. • The small package makes high-density mounting possible. (SOP 14-pin) • Automatic calendar function (year, month, day, day of the week, hour, minute, second). • Automatic leap year correction. (up to 2099) • Builtin 30 x 4-bit S-RAM. • High-speed access. • Reference pulse output. (1024 Hz, 1/10 Hz) • Low current consumption. (1 µA typical) • Similar mounting method to that used for universal type SMD IC. Specifications (characteristics) Absolute Max. rating Symbol Condition Supply voltage VDD VDD-GND Input voltage VIN Storage temperature TSTG Soldering conditions TSOL Unit __ __ __ SIN,SCK, WR, CS0, CS1 ____ -0.3 Stored without tape & reel -55 VDD+0.3 V SOUT, TPOUT +125 ˚C Twice at under 260˚C within 10 sec. or under 230˚C within 3 min. Symbol Operating voltage VDD Operating temperature TOPR L1 to L5 are test pin. Do not connect them to any terminals. Condition Min. Typ. Max. Unit 2.7 5.0 5.5 V -30 — +70 ˚C — Frequency characteristics Frequency tolerance Symbol ∆f/fo Range Condition Ta=25˚C, VDD=5V AA 5±5 A 5±10 B 5±20 Top Ta=-10 to 70˚C, VDD=5V Reference at 25˚C +10 -120 Frequency voltage characteristics fv Ta=Fix, VDD=2 to 5.5V Reference at 5V ±5 Aging fa Frequency temperature characteristics Unit External dimensions R4553 A E 6496 (Unit: mm) 10.1±0.2 ppm 3.1 Item No. Pin terminal 14 TPOUT 13 SOUT 12 CS1 11 CS0 10 L5 9 L4 8 VDD 1 2 3 4 5 6 7 Operating range Item No. Pin terminal 1 GND 2 WR 3 SIN SCK 4 L1 5 L2 6 L3 7 14 13 12 11 10 9 8 +6.0 5.0 VOUT Max. 7.4±0.2 Output voltage Terminal connection Min. 3.2±0.1 Item Actual size 0.05 min. Ta=25˚C, VDD=5V, first year 0.6 ppm/ year 0.15 DC characteristics VDD=5V±10% (GND=OV, Ta=-30˚C to +70˚C) Item Symbol Condition Min. Data holding voltage VDH — 2.0 Current consumption ___ Typ. Max. Unit 5.5 V — IDD1 SCK=500 kHz IDD2 SCK=DC VOH IOH=-400µA VDD-0.4 — VOL IOL=1.6mA — 0.4 IOZH VOUT=5.5V -2.0 2.0 IOZL VOUT=0V ___ 100 — 1.0 Output voltage Off leak current 4/5 VDD VIH Input voltage IIH Input current Oscillation start-up time 47 — — — VIL — 1/5 VDD -2.0 2.0 VIN=5.5V IIL VIN=0V Tosc Ta=25˚C — µA 3.0 3.0 V µA V µA s VDD=3V±10% (GND=OV, Ta=-30˚C to +70˚C) Item Symbol Condition Min. Data holding voltage VDH — 2.0 IDD1 Current consumption Output voltage Off leak current IDD2 ___ — SCK=300 kHz ___ Input current Oscillation start-up time Max. Unit 3.3 V 100 — SCK=DC 1.0 IOH=-400µA VDD-0.4 — VOL IOL=1.6mA — 0.4 IOZH VOUT=3.3V IOZL -2.0 2.0 VOUT=0V VIL 4/5 VDD — IIH VIN=3.3V IIL VIN=0V Tosc Ta=25˚C — µA 3.0 VOH VIH Input voltage Typ. V µA — V — 1/5 VDD -2.0 2.0 µA — 3.0 s Real time clock module Register table A3 A2 MODE 1 MODE 2 User RAM Domain 1 User RAM Domain 2 MODE 0 Address A0 A1 Counter control register Register symbol D3 D2 Register name D1 D0 1-second digit register D3 D1 D2 D0 D3 D2 D1 D0 RA60 0 0 0 0 0 S1 S8 S4 S2 S1 RA3 RA2 RA1 RA0 RA63 RA62 RA61 1 0 0 0 1 S10 0 S40 S20 S10 10-second digit register RA7 RA6 RA5 RA4 RA67 RA66 RA65 RA64 2 0 0 1 0 MI1 mi8 mi4 mi2 mi1 1-minute digit register RA11 RA10 RA9 RA8 RA71 RA70 RA69 RA68 3 0 0 1 1 MI10 0 mi40 mi20 mi10 10-minute digit register RA15 RA14 RA13 RA12 RA75 RA74 RA73 RA72 h4 h2 h1 1-hour digit register RA19 RA18 RA17 RA16 RA79 RA78 RA77 RA76 4 0 1 0 0 H1 h8 5 0 1 0 1 H10 PM/AM 0 h20 h10 10-hour digit register RA23 RA22 RA21 RA20 RA83 RA82 RA81 RA80 6 0 1 1 0 W 0 w4 w2 w1 Day of the week digit register RA27 RA26 RA25 RA24 RA87 RA86 RA85 RA84 RA88 7 0 1 1 1 D1 d8 d4 d2 d1 1-day digit register RA31 RA30 RA29 RA28 RA91 RA90 RA89 8 1 0 0 0 D10 0 0 d20 d10 10-day digit register RA35 RA34 RA33 RA32 RA95 RA94 RA93 RA92 9 1 0 0 1 MO1 mo8 mo4 mo2 mo1 1-month digit register RA39 RA38 RA37 RA36 RA99 RA98 RA97 RA96 A 1 0 1 0 MO10 0 0 0 mo10 10-month digit register RA43 RA42 RA41 RA40 RA103 RA102 RA101 RA100 1-year digit register RA47 RA46 RA45 RA44 RA107 RA106 RA105 RA104 10-year digit register RA51 RA50 RA49 RA48 RA111 RA110 RA109 RA108 RA114 RA113 RA112 RA118 RA117 RA116 B 1 0 1 1 Y1 y8 y4 y2 y1 C 1 1 0 0 Y10 y80 y40 y20 y10 D 1 1 0 1 C1 TPS 30ADJ CNTR 24/12 Control register 1 RA55 RA54 RA53 RA52 RA115 E 1 1 1 0 C2 BUSY PONC — ∗ Control register 2 RA59 RA58 RA57 RA56 RA119 C3 SYSR TEST MS1 MS0 Control register 3 1 F 1 1 1 Same as MODE 0 Same as MODE 0 Note: ∗ TEST bit should be “0”. Switching characteristics ___ Symbol Item SCK input frequency fSCK SCK “L” time tWSCKL SCK “H” time tWSCKH SCK pause time tPS ___ ___ ___ __ CS0 setup time __ (Ta=-30˚C to +70˚C, VDD=5V±10%, GND=OV) Condition Min. Typ. Max. Unit 500 kHz CS 0 — — — 90% 10% SCK tSCS t WCKL 0 1/f CLK tHCS SIN data setup time tSD 0.5 — ___ WR setup time 1.0 WR hold time tHWR 0.5 SOUT delay time tDSO __ CS0, and CS1 enable to SOUT output __ — — tDSZ2 CS1 enable to SOUT output tDPZ1 CS1 enable to SOUT high Z tDPZ2 90% t HD WR 150 — — 100 t SWR 90% 500 ns t DSZ1 t DSZ2 CS0 SCK Block diagram 32.768 kHz Day Sec. Min. Hou. of t PS Day Mon. Year Week Counter Output control t HWR 10% SOUT CL=100pF t HCS 10% tDSZ1 CS0 disenable to SOUT high Z SIN t WCKH t SD tSWR ___ µs 0.2 tHD SIN data Hold time TP OUT 90% 10% — 1.0 tSCS CS0 hold time OSC Timing chart SCK 10% Control register 1 Control register 2 Control register 3 RAM (120bit) 90% 10% SOUT t DSO S OUT Output control 90% CS1 SCK S IN CS 1 CS 0 Input control Shift register Control circuit 10% 90% TPOUT 90% 10% t DPZ1 10% t DPZ2 WR 48