256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit (x8) Many-Time Programmable Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 SST27SF256 / 512 / 010 / 0205.0V-Read 256Kb / 512Kb / 1Mb / 2Mb (x8) MTP flash memories Data Sheet FEATURES: • Organized as 32K x8 / 64K x8 / 128K x8 / 256K x8 • 4.5-5.5V Read Operation • Superior Reliability – Endurance: At least 1000 Cycles – Greater than 100 years Data Retention • Low Power Consumption – Active Current: 20 mA (typical) – Standby Current: 10 µA (typical) • Fast Read Access Time – 70 ns – 90 ns • Fast Byte-Program Operation – Byte-Program Time: 20 µs (typical) – Chip Program Time: 0.7 seconds (typical) for SST27SF256 1.4 seconds (typical) for SST27SF512 2.8 seconds (typical) for SST27SF010 5.6 seconds (typical) for SST27SF020 • Electrical Erase Using Programmer – Does not require UV source – Chip-Erase Time: 100 ms (typical) • TTL I/O Compatibility • JEDEC Standard Byte-wide EPROM Pinouts • Packages Available – 32-pin PLCC – 32-pin TSOP (8mm x 14mm) – 28-pin PDIP for SST27SF256/512 – 32-pin PDIP for SST27SF010/020 PRODUCT DESCRIPTION The SST27SF256/512/010/020 are a 32K x8 / 64K x8 / 128K x8 / 256K x8 CMOS, Many-Time Programmable (MTP) low cost flash, manufactured with SST’s proprietary, high performance SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. These MTP devices can be electrically erased and programmed at least 1000 times using an external programmer with a 12 volt power supply. They have to be erased prior to programming. These devices conform to JEDEC standard pinouts for byte-wide memories. Featuring high performance Byte-Program, the SST27SF256/512/010/020 provide a Byte-Program time of 20 µs. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with an endurance of at least 1000 cycles. Data retention is rated at greater than 100 years. The SST27SF256/512/010/020 are suited for applications that require infrequent writes and low power nonvolatile storage. These devices will improve flexibility, efficiency, and performance while matching the low cost in nonvolatile applications that currently use UV-EPROMs, OTPs, and mask ROMs. To meet surface mount and conventional through hole requirements, the SST27SF256/512 are offered in 32-pin PLCC, 32-pin TSOP, and 28-pin PDIP packages. The SST27SF010/020 are offered in 32-pin PDIP, 32-pin PLCC and 32-pin TSOP packages. See Figures 1, 2, and 3 for pinouts. ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 1 Device Operation The SST27SF256/512/010/020 are a low cost flash solution that can be used to replace existing UV-EPROM, OTP, and mask ROM sockets. These devices are functionally (read and program) and pin compatible with industry standard EPROM products. In addition to EPROM functionality, these devices also support electrical erase operation via an external programmer. They do not require a UV source to erase, and therefore the packages do not have a window. Read The Read operation of the SST27SF256/512/010/020 is controlled by CE# and OE#. Both CE# and OE# have to be low for the system to obtain data from the outputs. Once the address is stable, the address access time is equal to the delay from CE# to output (TCE). Data is available at the output after a delay of TOE from the falling edge of OE#, assuming that CE# pin has been low and the addresses have been stable for at least TCE - TOE. When the CE# pin is high, the chip is deselected and a typical standby current of 10 µA is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Byte-Program Operation The SST27SF256/512/010/020 are programmed by using an external programmer. The programming mode for SST27SF256/010/020 is activated by asserting 12V (±5%) The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MTP is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet Product Identification Mode on VPP pin, VDD = 5V (±5%), VIL on CE# pin, and VIH on OE# pin. The programming mode for SST27SF512 is activated by asserting 12V (±5%) on OE#/VPP pin, VDD = 5V (±5%), and VIL on CE# pin. These devices are programmed byte-by-byte with the desired data at the desired address using a single pulse (CE# pin low for SST27SF256/512 and PGM# pin low for SST27SF010/ 020) of 20 µs. Using the MTP programming algorithm, the Byte-Programming process continues byte-by-byte until the entire chip has been programmed. The Product Identification mode identifies the devices as the SST27SF256, SST27SF512, SST27SF010 and SST27SF020 and manufacturer as SST. This mode may be accessed by the hardware method. To activate this mode for SST27SF256/010/020, the programming equipment must force VH (12V±5%) on address A9 with VPP pin at VDD (5V±10%) or VSS. To activate this mode for SST27SF512, the programming equipment must force VH (12V±5%) on address A9 with OE#/VPP pin at VIL. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0. For details, see Tables 3, 4, and 5 for hardware operation. Chip-Erase Operation The only way to change a data from a “0” to “1” is by electrical erase that changes every bit in the device to “1”. Unlike traditional EPROMs, which use UV light to do the ChipErase, the SST27SF256/512/010/020 uses an electrical Chip-Erase operation. This saves a significant amount of time (about 30 minutes for each Erase operation). The entire chip can be erased in a single pulse of 100 ms (CE# pin low for SST27SF256/512 and PGM# pin for SST27SF010/020). In order to activate the Erase mode for SST27SF256/010/020, the 12V (±5%) is applied to VPP and A9 pins, VDD = 5V (±5%), VIL on CE# pin, and VIH on OE# pin. In order to activate Erase mode for SST27SF512, the 12V (±5%) is applied to OE#/VPP and A9 pins, VDD = 5V (±5%), and VIL on CE# pin. All other address and data pins are “don’t care”. The falling edge of CE# (PGM# for SST27SF010/020) will start the Chip-Erase operation. Once the chip has been erased, all bytes must be verified for FFH. Refer to Figures 13, 14, and 15 for the flowcharts. TABLE 1: PRODUCT IDENTIFICATION Address Data 0000H BFH SST27SF256 0001H A3H SST27SF512 0001H A4H SST27SF010 0001H A5H SST27SF020 0001H A6H Manufacturer’s ID Device ID T1.1 502 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 2 502 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet FUNCTIONAL BLOCK DIAGRAM OF THE SST27SF256 SuperFlash Memory X-Decoder A14 - A0 Address Buffer Y-Decoder CE# OE# VPP A9 I/O Buffers Control Logic DQ7 - DQ0 502 ILL B1.1 FUNCTIONAL BLOCK DIAGRAM OF THE SST27SF512 SuperFlash Memory X-Decoder A15 - A0 Address Buffer Y-Decoder CE# OE#/VPP A9 Control Logic I/O Buffers DQ7 - DQ0 502 ILL B2.1 FUNCTIONAL BLOCK DIAGRAM OF THE SST27SF010/020 SuperFlash Memory X-Decoder AMS - A0 Address Buffer Y-Decoder CE# OE# A9 VPP PGM# I/O Buffers Control Logic DQ7 - DQ0 502 ILL B3.2 AMS = A17 for SST27SF020, A16 for SST27SF010 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 3 502 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 A17 PGM# A13 A13 NC A14 A14 PGM# VDD VDD VDD VDD VPP A16 NC NC VPP A15 VPP A16 A15 A12 A12 A15 A12 A12 A7 A7 SST27SF256 SST27SF512 SST27SF010 SST27SF020 Data Sheet 4 3 2 1 32 31 30 29 SST27SF020 SST27SF010 SST27SF512 SST27SF256 SST27SF256 SST27SF512 SST27SF010 SST27SF020 A7 A7 A6 A6 5 A6 A6 A5 A5 A5 A5 A4 A4 A4 A3 A8 A14 A14 28 A9 A9 A13 A13 A4 7 27 A11 A11 A8 A8 A3 A3 8 26 NC NC A9 A9 A3 A2 A2 9 25 OE# A11 A11 A2 A2 A1 A1 10 24 A10 OE#/VPP A10 OE# OE# A1 A1 A0 A0 11 23 CE# CE# A10 A10 A0 A0 NC NC 12 22 DQ7 DQ7 CE# CE# DQ0 DQ0 DQ0 DQ0 13 21 14 15 16 17 18 19 20 DQ6 DQ6 DQ7 DQ7 VSS NC DQ3 DQ4 DQ5 VSS NC DQ3 DQ4 DQ5 VSS DQ3 DQ4 DQ5 DQ6 VSS DQ4 DQ5 DQ6 DQ2 DQ2 DQ2 DQ2 DQ3 DQ1 DQ1 DQ1 32-pin PLCC Top View DQ1 SST27SF020 SST27SF010 SST27SF512 SST27SF256 A8 6 502 ILL F02c.2 FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN PLCC ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 4 502 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet SST27SF020 SST27SF010 SST27SF512 SST27SF256 A11 A9 A8 A13 A14 A17 PGM# VDD VPP A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC PGM# VDD VPP A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC NC VDD NC NC A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC NC VDD VPP NC NC A12 A7 A6 A5 A4 SST27SF256 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Standard Pinout Top View Die Up SST27SF512 SST27SF010 SST27SF020 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE#/VPP A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 502 ILL F01.1 FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN TSOP (8MM X 14MM) SST27SF020 SST27SF010 SST27SF512 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS SST27SF256 VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS SST27SF256 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28-pin PDIP Top View 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 SST27SF512 VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS VDD A14 A13 A8 A9 A11 OE#/VPP A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS SST27SF010 SST27SF020 1 2 3 4 5 32-pin 6 PDIP 7 8 Top View 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD PGM# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VDD PGM# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 502 ILL F02a.1 502 ILL F02b.1 FIGURE 3: PIN ASSIGNMENTS FOR 28-PIN AND 32-PIN PDIP ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 5 502 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet TABLE 2: PIN DESCRIPTION Symbol Pin Name Functions AMS1-A0 Address Inputs To provide memory addresses DQ7-DQ0 Data Input/output To output data during Read cycles and receive input data during Program cycles The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low OE# Output Enable For SST27SF256/010/020, to gate the data output buffers during Read operation OE#/VPP Output Enable/VPP For SST27SF512, to gate the data output buffers during Read operation and high voltage pin during Chip-Erase and programming operation VPP Power Supply for Program or Erase For SST27SF256/010/020, high voltage pin during Chip-Erase and programming operation 12V (±5%) VDD Power Supply To provide 5.0V supply (±10%) VSS Ground NC No Connection Unconnected pins. T2.3 502 1. AMS = Most significant address AMS = A14 for SST27SF256, A15 for SST27SF512, A16 for SST27SF010, and A17 for SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 6 502 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet TABLE 3: OPERATION MODES SELECTION FOR SST27SF256 Mode CE# OE# Read VIL VIL VDD or VSS VPP Output Disable VIL VIH VDD or VSS Byte-Program VIL VIH VPPH Standby VIH X Chip-Erase VIL VIH Program/Erase Inhibit VIH X Product Identification VIL VIL A9 DQ Address AIN DOUT AIN X AIN High Z X DIN AIN VDD or VSS X High Z X VPPH VH High Z X VPPH X High Z X VDD or VSS VH Manufacturer’s ID (BFH) Device ID (A3H) A14 - A1 = VIL, A0 = VIL A14 - A1 = VIL, A0 = VIH T3.1 502 Note: X = VIL or VIH VPPH = 12V±5%, VH = 12V±5% TABLE 4: OPERATION MODES SELECTION FOR SST27SF512 Mode CE# OE#/VPP A9 DQ Address Read VIL VIL AIN DOUT AIN Output Disable VIL VIH X Program VIL VPPH AIN High Z X DIN AIN Standby VIH X X High Z X Chip-Erase VIL VPPH VH High Z X Program/Erase Inhibit VIH VPPH X High Z X Product Identification VIL VIL VH Manufacturer’s ID (BFH) Device ID (A4H) A15 - A1 = VIL, A0 = VIL A15 - A1 = VIL, A0 = VIH T4.1 502 Note: X = VIL or VIH VPPH = 12V±5%, VH = 12V±5% TABLE 5: OPERATION MODES SELECTION FOR SST27SF010/020 Mode CE# OE# PGM# A9 VPP DQ Address Read VIL VIL X AIN VDD or VSS DOUT AIN Output Disable VIL VIH X X VDD or VSS High Z AIN Program VIL VIH VIL AIN Standby VIH X X X Chip-Erase VIL VIH VIL Program/Erase Inhibit VIH X X Product Identification VIL VIL X VPPH DIN AIN VDD or VSS High Z X VH VPPH High Z X X VPPH High Z X VH VDD or VSS Manufacturer’s ID (BFH) Device ID1 AMS2 - A1 = VIL, A0 = VIL AMS2 - A1 = VIL, A0 = VIH T5.1 502 1. Device ID = A5H for SST27SF010 and A6H for SST27SF020 2. AMS = Most significant address AMS = A16 for SST27SF010 and A17 for SST27SF020 Note: X = VIL or VIH VPPH = 12V±5%, VH = 12V±5% ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 7 502 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD+1.0V Voltage on A9 and VPP Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 14.0V Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE Range Commercial AC CONDITIONS OF TEST Input Rise/Fall Time . . . . . . . . . . . 10 ns Ambient Temp VDD VPP 0°C to +70°C 5.0V±10% 12V±5% Output Load . . . . . . . . . . . . . . . . . CL = 100 pF for 90 ns Output Load . . . . . . . . . . . . . . . . . CL = 30 pF for 70 ns See Figures 11 and 12 TABLE 6: READ MODE DC OPERATING CHARACTERISTICS FOR SST27SF256/512/010/020 VDD = 5.0V±10%, VPP=VDD OR VSS (Ta = 0°C to +70°C (Commercial)) Limits Symbol Parameter IDD VDD Read Current Min Max Test Conditions Address input=VIL/VIH at f=1/TRC Min VDD=VDD Max 30 IPPR Units mA VPP Read Current CE#=OE#=VIL, all I/Os open Address input=VIL/VIH at f=1/TRC Min VDD=VDD Max, VPP=VDD 100 µA CE#=OE#=VIL, all I/Os open ISB1 Standby VDD Current (TTL input) 3 mA CE#=VIH, VDD=VDD Max ISB2 Standby VDD Current (CMOS input) 100 µA CE#=VDD-0.3 VDD=VDD Max ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage 0.8 V VDD=VDD Min VIH Input High Voltage VDD+0.5 V VDD=VDD Max VOL Output Low Voltage 0.2 V IOL=2.1 mA, VDD=VDD Min VOH Output High Voltage V IOH=-400 µA, VDD=VDD Min IH Supervoltage Current for A9 100 µA CE#=OE#=VIL, A9=VH Max 2.0 2.4 T6.3 502 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 8 502 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet TABLE 7: PROGRAM/ERASE DC OPERATING CHARACTERISTICS FOR SST27SF256 VDD=5.0V±10%, VPP=VPPH (Ta=25°C±5°C) Limits Symbol Parameter Min Max Units Test Conditions IDD VDD Erase or Program Current 30 mA CE#=VIL, OE#=VIH, VPP=12V±5%, VDD=VDD Max IPP VPP Erase or Program Current 1 mA CE#=VIL, OE#=VIH, VPP=12V±5%, VDD=VDD Max ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 1 VH Supervoltage for A9 IH Supervoltage Current for A9 VPPH High Voltage for VPP Pin µA VOUT=GND to VDD, VDD=VDD Max 11.4 12.6 V CE#=OE#=VIL, 100 µA CE#=OE#=VIL, A9=VH Max 11.4 12.6 V T7.1 502 TABLE 8: PROGRAM/ERASE DC OPERATING CHARACTERISTICS FOR SST27SF512 VDD=5.0V±10%, VPP=VPPH (Ta=25°C±5°C) Limits Symbol Parameter Min Max Units Test Conditions IDD VDD Erase or Program Current 30 mA CE#=VIL, OE#/VPP=12V±5%, VDD=VDD Max IPP VPP Erase or Program Current 1 mA CE#=VIL, OE#/VPP=12V±5%, VDD=VDD Max ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 1 µA VOUT=GND to VDD, VDD=VDD Max VH Supervoltage for A9 IH Supervoltage Current for A9 VPPH High Voltage for OE#/VPP Pin 11.4 12.6 V CE#=OE#/VPP=VIL, 100 µA CE#=OE#/VPP=VIL, A9=VH Max 11.4 12.6 V T8.1 502 TABLE 9: PROGRAM/ERASE DC OPERATING CHARACTERISTICS FOR SST27SF010/020 VDD=5.0V±10%, VPP=VPPH (Ta=25°C±5°C) Limits Symbol Parameter Min Max Units Test Conditions IDD VDD Erase or Program Current 30 mA CE#=PGM#=VIL, OE#=VIH, VPP=12V±5%, VDD=VDD Max IPP VPP Erase or Program Current 1 mA CE#=PGM#=VIL, OE#=VIH, VPP=12V±5%, VDD=VDD Max ILI Input Leakage Current 1 µA VIN =GND to VDD, VDD=VDD Max 1 ILO Output Leakage Current VH Supervoltage for A9 IH Supervoltage Current for A9 VPPH High Voltage for VPP Pin µA VOUT =GND to VDD, VDD=VDD Max 11.4 12.6 V CE#=OE#=VIL, 100 µA CE#=OE#=VIL, A9=VH Max 11.4 12.6 V T9.1 502 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 9 502 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet TABLE 10: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter Minimum Units TPU-READ1 Power-up to Read Operation 100 µs Power-up to Write Operation 100 µs TPU-WRITE 1 T10.1 502 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 11: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum CI/O1 I/O Pin Capacitance VI/O = 0V 12 pF Input Capacitance VIN = 0V 6 pF CIN 1 T11.0 502 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 12: RELIABILITY CHARACTERISTICS Symbol 1 Parameter Minimum Specification Units Test Method Endurance 1000 Cycles JEDEC Standard A117 TDR1 Data Retention 100 Years JEDEC Standard A103 ILTH1 Latch Up 100 mA NEND JEDEC Standard 78 T12.2 502 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. AC CHARACTERISTICS TABLE 13: READ CYCLE TIMING PARAMETERS VDD = 5.0V±10% (Ta = 0°C to +70°C (Commercial)) SST27SF256-70 SST27SF512-70 SST27SF010-70 SST27SF020-70 Min Symbol Parameter TRC Read Cycle Time TCE Chip Enable Access Time 70 90 ns TAA Address Access Time 70 90 ns TOE Output Enable Access Time 45 ns TCLZ1 CE# Low to Active Output 0 TOLZ1 TCHZ1 TOHZ1 TOH1 OE# Low to Active Output 0 70 Min ns 0 ns 30 25 0 Units ns 0 25 OE# High to High-Z Output Max 90 35 CE# High to High-Z Output Output Hold from Address Change Max SST27SF256-90 SST27SF512-90 SST27SF010-90 SST27SF020-90 30 0 ns ns ns T13.1 502 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 10 502 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet TABLE 14: PROGRAM/ERASE CYCLE TIMING PARAMETERS FOR SST27SF256 Symbol TAS TAH TPRT TVPS TVPH TPW TEW TDS TDH TVR TART TA9S TA9H Parameter Address Setup Time Address Hold Time VPP Pulse Rise Time VPP Setup Time VPP Hold Time CE# Program Pulse Width CE# Erase Pulse Width Data Setup Time Data Hold Time VPP and A9 Recovery Time A9 Rise Time to 12V during Erase A9 Setup Time during Erase A9 Hold Time during Erase Min 1 1 50 1 1 20 100 1 1 1 50 1 1 Max 30 500 Units µs µs ns µs µs µs ms µs µs µs ns µs µs T14.0 502 TABLE 15: PROGRAM/ERASE CYCLE TIMING PARAMETERS FOR SST27SF512 Symbol TAS TAH TPRT TVPS TVPH TPW TEW TDS TDH TVR TART TA9S TA9H Parameter Address Setup Time Address Hold Time OE#/VPP Pulse Rise Time OE#/VPP Setup Time OE#/VPP Hold Time CE# Program Pulse Width CE# Erase Pulse Width Data Setup Time Data Hold Time OE#/VPP and A9 Recovery Time A9 Rise Time to 12V during Erase A9 Setup Time during Erase A9 Hold Time during Erase Min 1 1 50 1 1 20 100 1 1 1 50 1 1 Max 30 500 Units µs µs ns µs µs µs ms µs µs µs ns µs µs T15.0 502 TABLE 16: PROGRAM/ERASE CYCLE TIMING PARAMETERS FOR SST27SF010/020 Symbol TCES TCEH TAS TAH TPRT TVPS TVPH TPW TEW TDS TDH TVR TART TA9S TA9H Parameter CE# Setup Time CE# Hold Time Address Setup Time Address Hold Time VPP Pulse Rise Time VPP Setup Time VPP Hold Time PGM# Program Pulse Width PGM# Erase Pulse Width Data Setup Time Data Hold Time A9 Recovery Time for Erase A9 Rise Time to 12V during Erase A9 Setup Time during Erase A9 Hold Time during Erase Min 1 1 1 1 50 1 1 20 100 1 1 1 50 1 1 Max 30 500 Units µs µs µs µs ns µs µs µs ms µs µs µs ns µs µs T16.0 502 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 11 502 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet TAA TRC ADDRESS TCE CE# TOE OE# TOHZ TOLZ HIGH-Z DQ7-0 TOH TCHZ DATA VALID DATA VALID TCLZ 502 ILL F03.0 FIGURE 4: READ CYCLE TIMING DIAGRAM FOR SST27SF256/512/010/020 ADDRESS (EXCEPT A9) CE# TEW OE# VIH DQ7-0 VPPH TVPS VDD VPP VSS TVPH TVR TPRT VPPH TA9S A9 TVR VIH VIL TART TA9H 502 ILL F04a.1 FIGURE 5: CHIP-ERASE TIMING DIAGRAM FOR SST27SF256 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 12 502 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet ADDRESS (EXCEPT A9) CE# TEW DQ7-0 VPPH TVPS OE#/VPP TVR VDD VSS TVPH TPRT VPPH TA9S A9 TVR VIH VIL TART TA9H 502 ILL F04b.1 FIGURE 6: READ CYCLE TIMING DIAGRAM FOR SST27SF512 ADDRESS (EXCEPT A9) CE# TCEH OE# VIH DQ7-0 VPPH VPP TVPS VDD VSS TVPH TPRT VPPH TA9S A9 TVR VIH VIL TART TA9H TEW PGM# TCES 502 ILL F04c.1 FIGURE 7: CHIP-ERASE TIMING DIAGRAM FOR SST27SF010/020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 13 502 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet ADDRESS ADDRESS VALID TAS TAH CE# TPW OE# VIH TDS DQ7-0 TDH DATA VALID HIGH-Z TVR VPPH TVPS VDD VPP VSS TPRT TVPH 502 ILL F05a.1 FIGURE 8: BYTE-PROGRAM TIMING DIAGRAM FOR SST27SF256 ADDRESS ADDRESS VALID TAH TAS TPW CE# TDS DQ7-0 TDH DATA VALID HIGH-Z TVR VPPH TVPS VDD OE#/VPP TPRT VSS TVPH 502 ILL F05b.2 FIGURE 9: BYTE-PROGRAM TIMING DIAGRAM FOR SST27SF512 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 14 502 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet ADDRESS ADDRESS VALID TAH TAS CE# OE# TCEH VIH TDS TDH DQ7-0 HIGH-Z DATA VALID VPPH TVPS VDD VPP TPRT TPW VSS TVPH PGM# 502 ILL F05c.1 TCES FIGURE 10: BYTE-PROGRAM TIMING DIAGRAM FOR SST27SF010/020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 15 502 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet VIHT VHT INPUT VHT REFERENCE POINTS OUTPUT VLT VLT VILT 502 ILL F06.0 AC test inputs are driven at VIHT (2.4 V) for a logic “1” and VILT (0.4 V) for a logic “0”. Measurement reference points for inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Input rise and fall times (10% ↔ 90%) are <10 ns. Note: VHT - VHIGH Test VLT - VLOW Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 11: AC INPUT/OUTPUT REFERENCE WAVEFORMS VDD TO TESTER RL HIGH TO DUT CL RL LOW 502 ILL F07.1 FIGURE 12: A TEST LOAD EXAMPLE ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 16 502 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet Start VPP = VPPH, A9 = VH Erase 100ms pulse (CE# = VIL) VPP = VDD or VSS A9 = VIL or VIH Wait for VPP and A9 Recovery Time Read Device (CE# = OE# = VIL) No Compare All bytes to FFH Yes Device Passed Device Failed 502 ILL F08a.2 FIGURE 13: CHIP-ERASE ALGORITHM FOR SST27SF256 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 17 502 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet Start A9 = VH OE#/VPP = VPPH Erase 100ms pulse (CE# = VIL) OE#/VPP = VDD or VSS A9 = VIL or VIH Wait for OE#/VPP and A9 Recovery Time Read Device (CE# = OE# = VIL) No Compare All bytes to FFH Yes Device Passed Device Failed 502 ILL F08b.2 FIGURE 14: CHIP-ERASE ALGORITHM FOR SST27SF512 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 18 502 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet Start A9 = VH, VPP = VPPH CE# = VIL, OE# = VIH Erase 100ms pulse (PGM# = VIL) PGM# = VIH A9 = VIL or VIH Wait A9 Recovery Time Read Device Compare all bytes to FFH No Yes Device Passed Device Failed 502 ILL F08c.1 FIGURE 15: CHIP-ERASE ALGORITHM FOR SST27SF010/020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 19 502 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet Start Erase* VPP = VPPH Address = First Location Program 20µs pulse (CE# = VIL) Increment Address VPP = VDD or VSS Last Address? No Yes Wait for VPP RecoveryTime Read Device (CE# = OE# = VIL) Compare all bytes to original data No Yes Device Passed Device Failed 502 ILL F09a.3 * See Figure 13 FIGURE 16: BYTE-PROGRAM ALGORITHM FOR SST27SF256 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 20 502 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet Start Erase* OE#/VPP = VPPH Address = First Location Program 20µs pulse (CE# = VIL) Increment Address OE#/VPP = VDD or VSS Last Address? No Yes Wait for OE#/VPP RecoveryTime Read Device (CE# = OE# = VIL) Compare all bytes to original data No Yes Device Passed Device Failed 502 ILL F09b.2 * See Figure 14 FIGURE 17: BYTE-PROGRAM ALGORITHM FOR SST27SF512 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 21 502 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet Start Erase* VPP = VPPH Address = First Location CE# = VIL, OE# = VIH Program 20µs pulse (PGM# = VIL) Increment Address Last Address? No Yes Read Device Compare all bytes to original data No Yes Device Passed Device Failed 502 ILL F09c.1 * See Figure 15 FIGURE 18: BYTE-PROGRAM ALGORITHM FOR SST27SF010/020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 22 502 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet Device SST27SFxxx Speed - XXX Suffix1 - XX Suffix2 - XX Package Modifier G = 28 pins H = 32 pins Numeric = Die modifier Package Type N = PLCC W = TSOP (die up) (8mm x 14mm) P = PDIP Operating Temperature C = Commercial = 0° to +70°C Minimum Endurance 3 = 1000 cycles Read Access Speed 70 = 70 ns 90 = 90 ns Device Density 256 = 256 Kilobit 512 = 512 Kilobit 010 = 1 Megabit 020 = 2 Megabit ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 23 502 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet Valid combinations for SST27SF256 SST27SF256-70-3C-NH SST27SF256-90-3C-NH SST27SF256-70-3C-WH SST27SF256-90-3C-WH SST27SF256-70-3C-PG SST27SF256-90-3C-PG Valid combinations for SST27SF512 SST27SF512-70-3C-NH SST27SF512-90-3C-NH SST27SF512-70-3C-WH SST27SF512-90-3C-WH SST27SF512-70-3C-PG SST27SF512-90-3C-PG Valid combinations for SST27SF010 SST27SF010-70-3C-NH SST27SF010-90-3C-NH SST27SF010-70-3C-WH SST27SF010-90-3C-WH SST27SF010-70-3C-PH SST27SF010-90-3C-PH Valid combinations for SST27SF020 SST27SF020-70-3C-NH SST27SF020-90-3C-NH Example: SST27SF020-70-3C-WH SST27SF020-90-3C-WH SST27SF020-70-3C-PH SST27SF020-90-3C-PH Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 24 502 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet PACKAGING DIAGRAMS TOP VIEW Optional Pin #1 Identifier SIDE VIEW .485 .495 .447 .453 .042 .048 2 1 .106 .112 32 .020 R. MAX. .023 x 30˚ .029 .030 R. .040 .042 .048 .585 .595 BOTTOM VIEW .547 .553 .013 .021 .400 BSC .026 .032 .490 .530 .050 BSC. .015 Min. .075 .095 .050 BSC. .026 .032 .125 .140 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 32.PLCC.NH-ILL.2 4. Coplanarity: 4 mils. 32-PIN PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH 1.05 0.95 Pin # 1 Identifier .50 BSC .270 .170 8.10 7.90 0.15 0.05 12.50 12.30 0.70 0.50 14.20 13.80 32.TSOP-WH-ILL.4 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads. 32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM SST PACKAGE CODE: WH ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 25 502 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet 28 CL .600 .625 1 Pin #1 Identifier .530 .550 1.445 1.455 .065 .075 7˚ 4 PLCS. .170 .200 Base Plane Seating Plane 0˚ 15˚ .015 .050 .070 .080 Note: .045 .065 .016 .022 .100 BSC .120 .150 .008 .012 .600 BSC 1. Complies with JEDEC publication 95 MO-015 AH dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. 28.pdipPG-ILL.2 28-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP) SST PACKAGE CODE: PG 32 CL .600 .625 1 Pin #1 Identifier .530 .550 1.645 1.655 .065 .075 7˚ 4 PLCS. .170 .200 Base Plane Seating Plane .015 .050 .070 .080 Note: .045 .065 .016 .022 .100 BSC .120 .150 0˚ 15˚ .008 .012 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. .600 BSC 32.pdipPH-ILL.2 32-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP) SST PACKAGE CODE: PH Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.ssti.com ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 26 502