Preliminary ST49C107A-04 ...the analog plus company TM Preprogrammed CPU Mother Board Frequency Generator June 1997-3 FEATURES Provides Reference Clock And Synthesized Clock Low Power Single 5V CMOS Technology 5 to 32 MHz Input Reference Frequency Up to 16 Frequencies Stored Internally Pin-to-Pin Compatible to Avasem AV9107 8/14 pin DIP or SOIC Package Programmable Analog Phase Locked Loop GENERAL DESCRIPTION The ST49C107A-04 is a mask programmable monolithic analog CMOS device designed to generate two simultaneous clocks. The output frequency can vary from 2 to 130MHz, with up to 16 single selectable preprogrammed frequencies stored in internal ROM. in order to reduce board space and number of oscillators. To provide high speed and low jitter clock, the parts utilize a high speed analog CMOS phase locked loop using 14.318 MHz system clock as the reference clock (note that reference clock can be changed to generate optional frequencies from a standard programmed device). The programmed clock outputs are selectable via four address lines. The ST49C107A-04 is designed to replace existing CPU mother board clocks generated from individual oscillators ORDERING INFORMATION Part No. Package Operating Temperature Range ST49C107ACF14-04 14 Lead 150 Mil JEDEC SOIC 0°C to 70°C BLOCK DIAGRAM XTAL XTAL OE1 OE2 Oscillator Circuit Programmable Counter B Output Buffer Phase Detector Charge Pump Loop Filter Programmable Counter A Voltage Controlled Oscillator 1X-CLOCK 2X-CLOCK Programmable Counter C Voltage Reference Circuit Rom Table Select Logic B=5....128 A=5....128 C = 1, 2, 4 A0-A3 Figure 1. Block Diagram Rev. P2.00 1996 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7017 1 ST49C107A-04 Preliminary PIN CONFIGURATION A1 A2 A3 AGND DGND PD* XTAL1 1 14 2 13 3 12 4 11 5 10 6 9 7 8 A0 1XCLK VCC 2XCLK OE2 OE1 XTAL2 14 Lead SOIC (Jedec, 0.150”) PIN DESCRIPTION Symbol Pin # Type Description 21 . A1 1 I Frequency Select Address Input A2 2 I Frequency Select Address Input 31. A3 3 I Frequency Select Address Input 41. AGND 4 O Analog Ground. DGND 5 O Digital Ground. PD 6 I Power-down (Active Low). Shuts off chip when low1. XTAL1 7 I Crystal Or External Clock Input. A crystal can be connected to this pin and XTAL2 pin to generate internal phase locked loop reference clock. For external 14.318 MHz clock, XTAL2 is left open or used as buffered clock output. XTAL2 8 O Crystal Output. OE1 9 I 1X-CLOCK Output Enable (Active High). 1X-CLOCK output is three stated when this pin is low1. OE2 10 I 2X-CLOCK Output Enable (Active High). 2X-CLOCK output is three stated when this pin is low1. 2XCLK 11 O Programmed Output Clock. VCC 12 I Positive Supply Voltage. Single +5 volts. 1XCLK 13 O 2X-CLOCK Divide-by-two Output. A0 14 I Frequency Select Address Input 11. Notes 1Have internal pull-up resistors on inputs. Rev. P2.00 2 ST49C107A-04 Preliminary DC ELECTRICAL CHARACTERISTICS Test Conditions: TA = 0°C to +70°C, VCC = 5.0V 10% Unless Otherwise Specified Symbol Parameter VIL Input Low Level VIH Input High Level VOL Output Low Level VOH Output High Level IIL Input Low Current Min. Typ. Max. Unit 0.8 V 2.0 V 0.4 V IOL = 8.0mA V IOH = 8.0mA µA Except Crystal Input 1 µA VIN=VCC 55 mA No Load. CLOCK=100MHz µA No Load 2.4 -10 IIH Input High Current ICC Operating Current 45 ISB Standby Current 25 RIN Input Pull-up Resistance 500 Conditions 900 1300 kΩ DC ELECTRICAL CHARACTERISTICS Test Conditions: TA = 0°C to +70°C, VCC = 5.0V 10% Unless Otherwise Specified Symbol Parameter Min. Typ. Max. Unit Conditions T1 1X, 2X-CLOCK Rise Time 1 2 ns CL=20pF 0.8V - 2.0V T2 1X, 2X-CLOCK Fall Time 1 2 ns CL=20pF 2.0V - 0.8V T4 Duty Cycle 40 50 60 % 1.4V Switch Point T5 Duty Cycle 45 50 55 % VCC/2 Switch Point T3 Jitter 1 Sigma 0.5 2 % T3 Jitter Absolute 3 5 % T Input Frequency 32 MHz T7 Buffered Clock Rise Time 20 ns T8 Buffered Clock Fall Time 20 ns 2 Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS Operating Temperature . . . . . . . . . . . . . 0°C to +70°C Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Volts Voltage at Any Pin . . . . . . . . . GND-0.3V to VCC +0.3V Storage Temperature . . . . . . . . . . . . -40°C to +150°C Package Dissipation . . . . . . . . . . . . . . . . . . . . . 500 mW Rev. P2.00 3 ST49C107A-04 Preliminary CLOCK OUTPUT TABLE FOR ST49C107A-04 (using 14.318 MHz input. All frequencies in MHz). EXTERNAL CLOCK CONNECTION To minimize the noise pickup, it is recommended to connect 0.047 (F capacitor to XTAL1, and keep the lead length of the capacitor to XTAL1 to a minimum to reduce noise susceptibility. Factor 2XCLOCK CLOCK 0 95/17 80.02 40.01 1 107/23 66.62 33.31 1 0 35/10 50.11 25.06 0 1 1 95/34 40.01 20.00 0 1 0 0 56/8 100.23 50.11 The ST49C107A-04 contains an analog phase locked loop circuit with digital closed loop dividers and a final output multiplexer to achieve the desired dividing ratios for the clock output. 0 1 0 1 107/46 33.31 16.66 0 1 1 0 38/17 32.01 16.00 0 1 1 1 35/20 25.06 12.47 1 0 0 0 76/17 64.02 32.01 The accuracy of the frequencies produced by the ST49C107A-04 depends on the input frequency and divider ratios. The formula for calculating the exact output frequency is as follows: 1 0 0 1 2 2X-Input 1X-Input 1 0 1 0 3 3X-Input 1.5X-Input 1 0 1 1 8 8X-Input 4X-Input 1 1 0 0 1/2 0.5X-Input 0.25X-Input 1 1 0 1 1/4 0.25XInput 0.125XInput 1 1 1 0 109/13 120.00 60.00 1 1 1 1 118/13 129.96 64.98 FREQUENCY SELECT CALCULATION CLKOUT = CLKIN * Factor For proper output frequency, the ST49C107A-04 can accept a reference frequency from 5 - 32MHz with max output frequency of 130MHz (2X – clock). 1X–CLOCK 2X–CLOCK CLOCK T5 T1 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 T2 T4 T3 BCLK T8 Figure 2. Timing Diagram Rev. P2.00 4 T7 ST49C107A-04 Preliminary 14 LEAD SMALL OUTLINE (150 MIL JEDEC SOIC) Rev. 1.00 D 14 8 E H 1 7 C A Seating Plane α e B A1 L INCHES SYMBOL MILLIMETERS MIN MAX MIN A 0.053 0.069 1.35 1.75 A1 0.004 0.010 0.10 0.25 B 0.013 0.020 0.33 0.51 C 0.007 0.010 0.19 0.25 D 0.337 0.344 8.55 8.75 E 0.150 0.157 3.80 4.00 e 0.050 BSC MAX 1.27 BSC H 0.228 0.244 5.80 6.20 L 0.016 0.050 0.40 1.27 α 0° 8° 0° Note: The control dimension is the millimeter column Rev. P2.00 5 8° ST49C107A-04 Preliminary Notes Rev. P2.00 6 Preliminary Notes Rev. P2.00 7 ST49C107A-04 ST49C107A-04 Preliminary NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1996 EXAR Corporation Datasheet June 1997 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. P2.00 8