PLL PL611S-15-XXXUC-R

(Preliminary)
PL611s-15
1.8V-3.3V PicoPLL TM 32K Programmable Clock
FEATURES
DESCRIPTION
• Advanced Programmable PLL design for lowfrequency (KHz) input applications.
• OTP selectable AC/DC Ref. Coupling.
• Accepts <1.0V reference signal input voltage
• Very low Jitter and Phase Noise (30-70ps Pk-Pk typical)
• Output frequency up to
o 133MHz @ 1.8V operation
o 166MHz @ 2.5V operation
o 200MHz @ 3.3V operation
• Offered in Tiny GREEN/RoHS compliant packages
o 6-pin DFN (2.0mmx1.3mmx0.6mm)
o 6-pin SC70 (2.3mmx2.25mmx1.0mm)
o 6-pin SOT23 (3.0mmx3.0mmx1.35mm)
• Input Frequency: 10KHz – 200MHz
• Single 1.8V, 2.5V, or 3.3V ± 10% power supply
• Operating temperature range from 0°C to 70°C
The PL611s-15 is a low-cost general purpose
frequency synthesizer and a member of PhaseLink’s
PicoPLL TM Factory Programmable ‘Quick Turn Clock
(QTC)’ family. Designed to fit in a small SOT23,
SC70, or DFN package for high performance
applications, the PL611s-15 accepts low frequency
(>10KHz) Reference input and generates up to
200MHz output with the best phase noise, jitter
performance, and power consumption for handheld
devices and notebook applications. Cascading
PL611s-15 with other PicoPLL ICs could result in
producing all required system clocks with specific
savings in board space, power consumption, and
cost.
PACKAGE PIN ASSIGNMENT
LF
GND
CLK0
DFN-6L
(2.0mmx1.3mmx0.6mm)
GNDA
2
VDD
3
6
LF
5
GND
4
CLK0
SC70-6L
(2.3mmx2.25mmx1.0mm)
VDD
1
GNDA
2
FIN
3
PL611s-15
6
5
4
1
PL611s-15
1
2
3
PL611s-15
FIN
GNDA
VDD
FIN
6
CLK0
5
GND
4
LF
SOT23-6L
(3.0mmx3.0mmx1.35mm)
BLOCK DIAGRAM
FIN
R-Counter
(7-bit)
M-Counter
(16-bit)
Phase
Detector
FVCO = FRef * (2* M/R)
Programmable Function
FOut = FVCO
P-Counter
(4-bit)
/2*P
Charge
Pump
VCO
CLK0
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 07/18/06 Page 1
(Preliminary)
PL611s-15
1.8V-3.3V PicoPLL TM 32K Programmable Clock
PACKAGE PIN ASSIGNMENT
SOT
Pin #
SC70
DFN
VDD
1
3
3
P
VDD connection.
GNDA
2
2
2
P
Ground connection for Analog Circuitry.
FIN
3
1
1
I
Reference input pin.
LF
4
6
6
I
Loop Filter input pin.
GND
5
5
5
P
GND connection
CLK0
6
4
4
O
Programmable Clock Output
Name
Type
Description
GUIDELINES FOR EXTERNAL COMPONENT SELECTION
For the optimum performance, accurate external loop filter components must be selected. A general guideline for
selecting these components based on the input frequency is shown in the below table. Please contact PhaseLink
for more accurate component selections.
Input frequency
3MHz ~ 200MHz
300KHz ~ 10MHz
30KHz ~ 1.0MHz
10KHz ~ 100KHz
Capacitor Value
4.7nF
4.7nF
4.7nF
47nF
Resistor Value
2.2KΩ
6.8KΩ
22KΩ
22KΩ
APPLICATION RECOMMENDATIONS FOR PL611s-15
PL611s-15 can accept a reference input >10KHz and produce a clock output in the MHz range, as shown in the
diagram ‘1’, below. However, to save costs in consumer product system designs and for greater area optimization,
it is possible to use the XOUT of the RTC crystal (32.768KHz) as the reference input to the PL611s-15, as shown
in diagram ‘2’, below.
XIN
1.8~3.3V
PL611s15
REFIN
C1
LF
LPGND
C2
XIN
32.768K
Hz
XOUT
ASIC
XOUT
MHZ CLK
(Any Frequency
1.8~3.3V
Diagram ‘1’
PL611s15
REFIN
LF
LPGND
MHZ CLK
(Any Frequency)
Diagram ‘2’
Note: An AC Coupling Cap may be required if RTC Clock amplitude is too small.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 07/18/06 Page 2
(Preliminary)
PL611s-15
1.8V-3.3V PicoPLL TM 32K Programmable Clock
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
V DD
- 0.5
4.6
V
Input Voltage Range
VI
- 0.5
V DD + 0.5
V
Output Voltage Range
VO
- 0.5
V DD + 0.5
V
Supply Voltage Range
10
Data Retention @ 85°C
Storage Temperature
TS
Ambient Operating Temperature
Year
-65
150
°C
-40
85
°C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied.
AC SPECIFICATIONS
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
10KHz
200
MHz
Input Frequency (FIN)
Reference Clock Input
Output Frequency
@ Vdd=3.3V
2.5
200
MHz
Output Frequency
@ Vdd=2.5V
2.5
166
MHz
Output Frequency
@ Vdd=1.8V
2.5
133
MHz
Settling Time
At power-up (after VDD increases over 1.62V)
2
ms
Input (FIN) Signal Amplitude
Internally AC coupled
VDD
Vpp
Output Rise Time
15pF Load, 10/90%VDD, High Drive, 3.3V
1
1.2
ns
Output Fall Time
15pF Load, 90/10%VDD, High Drive, 3.3V
1
1.2
ns
Duty Cycle
VDD/2
50
55
%
0.9
45
* Note: Jitter performance depends on the programming parameters.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 07/18/06 Page 3
(Preliminary)
PL611s-15
1.8V-3.3V PicoPLL TM 32K Programmable Clock
DC SPECIFICATIONS
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Supply Current, Dynamic, with
Loaded CMOS Outputs
I DD
@Vdd=3.3V,30MHz,
load=15pF
6.0
mA
Supply Current, Dynamic, with
Loaded CMOS Outputs
I DD
@Vdd=2.5V,30MHz,
load=15pF
3.9
mA
Supply Current, Dynamic with
Loaded CMOS Outputs
I DD
@Vdd=1.8V,30MHz,
load=5pF
2.1*
mA
Operating Voltage
V DD
Output Low Voltage
V OL
I OL = +4mA Standard Drive
Output High Voltage
V OH
I OH = -4mA Standard Drive
Output Current, Low drive
I OSD
V OL = 0.4V, V OH = 2.4V
4
mA
Output Current, Standard drive
I OSD
V OL = 0.4V, V OH = 2.4V
8
mA
Output Current, High drive
I OHD
V OL = 0.4V, V OH = 2.4V
16
mA
Short-circuit Current
1.62
3.3
3.63
V
0.4
V
V DD – 0.4
IS
V
±50
mA
* Note: Please see PL611s-16 datasheet if lower power is required.
PCB LAYOUT CONSIDERATIONS FOR PERFORMANCE OPTIMIZATION
The following guidelines are to assist you with a performance optimized PCB design:
- Keep all the PCB traces to PL611s-15 as short
as possible, as well as keeping all other traces
as far away from it as possible.
- When a reference input clock is generated from
a crystal (see diagram above), place the
PL611s-15 ‘FIN’ as close as possible to the
‘Xout’ crystal pin. This will reduce the crosstalk between the reference input and the other
signals.
- Place the Loop Filter (LF) components as close
to the package pin of PL611s-15 as possible.
- Place a 0.01µF~0.1µF decoupling capacitor
between VDD and GND, on the component
side of the PCB, close to the VDD pin. It is not
recommended to place this component on the
backside of the PCB. Going through vias will
reduce the signal integrity, causing additional
jitter and phase noise.
- It is highly recommended to keep the VDD and
GND traces as short as possible.
- When connecting long traces (> 1 inch) to a
CMOS output, it is important to design the
traces as a transmission line or ‘stripline’, to
avoid reflections or ringing. In this case, the
CMOS output needs to be matched to the trace
impedance. Usually ‘striplines’ are designed
for 50Ω impedance and CMOS outputs usually
have lower than 50Ω impedance so matching
can be achieved by adding a resistor in series
with the CMOS output pin to the ‘stripline’
trace.
- Please contact PhaseLink for the application
note on how to design outputs driving long
traces or the Gerber files for the PL611s-15
layout.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 07/18/06 Page 4
(Preliminary)
PL611s-15
1.8V-3.3V PicoPLL TM 32K Programmable Clock
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
SOT23-6 L
Symbol
A
A1
A2
b
c
D
E
H
L
e
Dimension in MM
Min.
Max.
1.05
1.35
0.05
0.15
1.00
1.20
0.30
0.50
0.08
0.20
2.80
3.00
1.50
1.70
2.60
3.0
0.35
0.55
0.95 BSC
Pin1 Dot
E
H
D
A2 A
A1
C
b
e
L
SC70-6L
Symbol
A
A1
A2
b
c
D
E
H
L
e
Dimension in MM
Min.
Max.
0.80
1.00
0.00
0.09
0.80
0.91
0.15
0.30
0.08
0.25
1.85
2.25
1.15
1.35
2.00
2.30
0.21
0.41
0.65BSC
Pin1 Dot
E
H
D
A2 A
A1
C
b
e
L
DFN-6L
D1
Symbol
A
A1
A3
b
e
D
E
D1
E1
L
Dimension in MM
Min.
Max.
0.50
0.60
0.00
0.05
0.152
0.152
0.15
0.25
0.40BSC
1.25
1.35
1.95
2.05
0.75
0.85
0.95
1.05
0.20
0.30
b
e
D
Pin 6 ID
Chamfer
E
E1
L
Pin1 Dot
A A1
A3
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 07/18/06 Page 5
(Preliminary)
PL611s-15
1.8V-3.3V PicoPLL TM 32K Programmable Clock
ORDERING INFORMATION (GREEN PACKAGE COMPLIANT)
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PL611s-XXX X X X
PART NUMBER
3 DIGIT ID Code *
(will be assigned at
programming time)
PACKAGE TYPE
T=SOT
U=SC70
G=DFN
†
NONE= TUBE
R=TAPE and REEL
TEMPERATURE
C=COMMERCIAL
I = INDUSTRIAL
Part Number
Order Number
Marking†
PL611s-XXX
PL611s-XXX
PL611s-XXX
PL611s-15-XXXGC-R
PL611s-15-XXXUC-R
PL611s-15-XXXTC-R
15XXX
15XXX
15XXX
Package Option
6-Pin SC70 (Tape and Reel)
6-Pin SC70 (Tape and Reel)
6-Pin SOT-23 (Tape and Reel)
Note: ‘XXX’ designates marking identifier that could be independent of the part number.
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 07/18/06 Page 6