STMICROELECTRONICS ST72T141K2M6

ST72141K
8-BIT MCU WITH ELECTRIC-MOTOR CONTROL,
ADC, 16-BIT TIMERS, SPI INTERFACE
■
■
■
■
■
■
■
Memories
– 8K Program memory
(ROM/OTP/EPROM)
– 256 Bytes RAM
Clock, Reset and Supply Management
– Enhanced reset system
– Low voltage supply supervisor
– 3 Power saving modes
14 I/O Ports
– 14 multifunctional bidirectional I/O lines with:
External interrupt capability (2 vectors), 13 alternate function lines, 3 high sink outputs
Motor Control peripheral
– 6 PWM output channels
– Emergency pin to force outputs to HiZ state
– 3 analog inputs for rotor position detection
with no need for additional sensors
– Comparator for current limitation
3 Timers
– Two 16-bit timers with: 2 input captures, 2 output compares, external clock input, PWM and
Pulse generator modes
– Watchdog timer for system integrity
Communications Interface
– SPI synchronous serial interface
Analog Peripheral
– 8-bit ADC with 8 input pins
SDIP32
SO34S
■
■
Instruction Set
– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
– True bit manipulation
Development Tools
– Full hardware/software development package
Device Summary
Features
ST72141K2
Program memory - bytes
RAM (stack) - bytes
8K
256 (64)
Motor control,
Watchdog, Two 16-bit timers,
SPI, ADC
4V to 5.5V
4 or 8 MHz (with 8 or 16 MHz oscillator)
-40°C to +85°C / -40°C to +125°C
SO34 / SDIP32
Peripherals
Operating Supply
CPU Frequency
Operating Temperature
Packages
Rev. 1.8
October 2001
1/132
1
Table of Contents
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 EXTERNAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5 EPROM PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2 RESET MANAGER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9
3.3 LOW CONSUMPTION OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4 MAIN CLOCK CONTROLLER (MCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.4 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
31
31
34
6.3.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.1 I/O PORT INTERRUPT SENSITIVITY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.3 CLOCK PRESCALER SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.4 MISCELLANEOUS REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.1 MOTOR CONTROLLER (MTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.1.1
8.1.2
8.1.3
8.1.4
2/132
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
....
Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
40
40
44
Table of Contents
8.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
66
66
67
75
8.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
75
76
76
76
76
78
8.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
78
78
78
90
90
90
91
96
8.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.4.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.4.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
8.4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
8.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
8.5 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.5.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.5.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.5.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
109
109
110
110
110
111
112
112
9.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1.7 Relative Mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
113
113
113
113
113
114
114
115
10 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
10.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
10.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
10.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
3/132
3
Table of Contents
10.4 GENERAL TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
10.5 I/O PORT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
10.6 SUPPLY, RESET AND CLOCK CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 121
10.6.1Supply Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.6.2RESET Sequence Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.6.3Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.7 MEMORY AND PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . .
121
121
121
122
11 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
11.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
11.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
12 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
132
4/132
1
ST72141K
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST72141K devices are members of the ST7
microcontroller family designed specifically for motor control applications and including A/D conversion and SPI interface capabilities. They include
an on-chip Moter Controller peripheral for control
of electric brushless moters with or without sensors. An example application, for 6-step control of
a Permanent Magnet DC motor, is shown in Figure
1.
The ST72141K devices are based on a common
industry-standard 8-bit core, featuring an enhanced instruction set.
Under software control, they can be placed in
WAIT, SLOW, or HALT mode, reducing power
consumption when the application is in idle or
standby state.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing
modes.
Figure 1. Example of a 6-step-controlled Motor
ST7
300V
MCO5-0
6
0
2
B
MCIB
I6
I1
MTC
I4
I3
A
MCIA
MCIC
I5
3
Net
Σ1
Σ2
4
Σ3
Σ4
Step
Σ5
C
I2
5
Σ6
Σ1
1
Σ2
Σ3
0
1
2
3
4
5
A
300V
150V
0
B
300V
150V
0
C
300V
150V
0
Figure 2. Device Block Diagram
Internal
CLOCK
OSC1
OSC
PORT A
DIV
OSC2
VDD
VSS
8-BIT ADC
POWER
SUPPLY
TIMER B
LVD
TIMER A
8-BIT CORE
ALU
8K-EPROM
ADDRESS AND DATA BUS
RESET
CONTROL
PA7:0
(8-BIT)
OC1A
MCO5:0
MCIA:C
MOTOR CTRL
MCES
MCCFI
PORT B
SPI
256b-RAM
PB5:0
(6-BIT)
WATCHDOG
5/132
4
ST72141K
1.2 PIN DESCRIPTION
Figure 3. 34-Pin SO Package Pinout
MCO5
1
34
MCIA
MCO4
MCO3
2
33
MCIB
3
32
MCIC
MCO2
4
31
MCCFI
MCO1
5
30
MCO0
6
29
VDD
VSS
MCES
7
28
VPP
MISO/PB5
8
27
OCMP1_A
9
26
NC
25
PA7/AIN7/OCMP2_A
24
PA6/AIN6/ICAP1_A
NC
MOSI/PB4
SCK/PB3
10
SS/ (HS) PB2
EXTCLK_B/ (HS) PB1
12
23
PA5/AIN5/ICAP2_A
13
22
EXTCLK_A/ (HS) PB0
14
21
PA4/AIN4/OCMP1_B
PA3/AIN3/OCMP2_B
OSC1
OSC2
15
20
16
19
PA2/AIN2/ICAP1_B
PA1/AIN1/ICAP2_B
RESET
17
18
PA0/AIN0
MCO5
1
32
MCIA
MCO4
MCO3
2
31
MCIB
3
30
MCO2
4
29
MCIC
MCCFI
MCO1
5
28
VDD
MCO0
6
27
MCES
MISO/PB5
7
26
VSS
VPP
8
25
MOSI/PB4
9
24
11
EI1
EI0
Figure 4. 32-Pin SDIP Package Pinout
SCK/PB3
SS/ (HS) PB2
10
EXTCLK_B/ (HS) PB1
12
11
EI0
23
OCMP1_A
PA7/AIN7/OCMP2_A
PA6/AIN6/ICAP1_A
22
PA5/AIN5/ICAP2_A
21
EXTCLK_A/ (HS) PB0
13
20
OSC1
OSC2
14
19
PA4/AIN4/OCMP1_B
PA3/AIN3/OCMP2_B
PA2/AIN2/ICAP1_B
15
18
PA1/AIN1/ICAP2_B
RESET
16
17
PA0/AIN0
EI1
6/132
5
ST72141K
PIN DESCRIPTION (Cont’d)
Legend / Abbreviations:
Type:
I = input, O = output, S = supply
Input level:
A = Dedicated analog input
In/Output level: C = CMOS 0.3VDD/0.7VDD,
CT= CMOS 0.3VDD/0.7VDD with input trigger
Output level:
HS = high sink (on N-buffer only),
R = 70Ω/100Ω ratio of logical levels.
Analog level if used as PWM filtered with an external capacitor
Port configuration capabilities:
– Input:
float = floating, wpu = weak pull-up, int = interrupt, ana = analog
– Output:
OD = open drain, T = true open drain, PP = push-pull
Note: the Reset configuration of each pin is shown in bold.
Table 1. Device Pin Description
Port / Control
PP
OD
Output
ana
int
wpu
Input
float
Input
Pin Name
Output
Level
Type
SO34
SDIP32
Pin n°
Main
Function
(after reset)
Alternate Function
1
1 MCO5
O
C
X
Motor Control Output Channel 5
2
2 MCO4
O
C
X
Motor Control Output Channel 4
3
3 MCO3
O
C
X
Motor Control Output Channel 3
4
4 MCO2
O
C
X
Motor Control Output Channel 2
5
5 MCO1
O
C
X
Motor Control Output Channel 1
6
6 MCO0
O
C
X
Motor Control Output Channel 0
7
7 MCES
I
8
8 PB5/MISO
I/O
CT
X
CT
X
Motor Control Emergency Stop Input
EI1
X
9 NC
X
Port B5
SPI Master In / Slave Out Data
Not Connected
I/O
CT
X
EI1
X
X
Port B4
SPI Master Out / Slave In Data
10 11 PB3/SCK
I/O
CT
X
EI1
X
X
Port B3
SPI Serial Clock
11 12 PB2/SS
I/O CT HS
X
EI1
T
Port B2
SPI Slave Select (active low)
12 13 PB1/EXTCLK_B
I/O CT HS
X
EI1
T
Port B1
Timer B Input Clock
13 14 PB0/EXTCLK_A
I/O CT HS
X
EI1
T
Port B0
Timer A Input Clock
9
10 PB4/MOSI
These pins connect a crystal or ceramic
resonator, or an external RC, or an external
source to the on-chip oscillator
14 15 OSC1
15 16 OSC2
16 17 RESET
I/O
C
17 18 PA0/AIN0
I/O
CT
X
X
EI0
X
X
X
Top priority non maskable interrupt (active low)
X
Port A0
18 19 PA1/ICAP2_B/AIN1
I/O
CT
X
EI0
X
X
X
Port A1
19 20 PA2/ICAP1_B/AIN2
I/O
CT
X
EI0
X
X
X
Port A2
ADC Analog Input 0
Timer B Input Capture 2 or
ADC Analog Input 1
Timer B Input Capture 1 or
ADC Analog Input 2
7/132
6
ST72141K
Port / Control
20 21 PA3/OCMP2_B/AIN3
I/O
CT
X
EI0
X
X
X
Port A3
21 22 PA4/OCMP1_B/AIN4
I/O
CT
X
EI0
X
X
X
Port A4
22 23 PA5/ICAP2_A/AIN5
I/O
CT
X
EI0
X
X
X
Port A5
23 24 PA6/ICAP1_A/AIN6
I/O
CT
X
EI0
X
X
X
Port A6
24 25 PA7/OCMP2_A/AIN7
I/O
CT
X
EI0
X
X
X
Port A7
26 NC
int
PP
Main
Function
(after reset)
OD
Output
ana
wpu
Input
float
Output
Type
SO34
SDIP32
Pin Name
Input
Level
Pin n°
Alternate Function
Timer B Output Compare 2 or
ADC Analog Input 3
Timer B Output Compare 1 or
ADC Analog Input 4
Timer A Input Capture 2 or
ADC Analog Input 5
Timer A Input Capture 1 or
ADC Analog Input 6
Timer A Output Compare 2 or
ADC Analog Input 7
Not Connected
25 27 OCMP1_A
O
26 28 VPP
I
Must be tied low during normal operating
mode,EPROM Programming voltage pin.
27 29 VSS
S
Ground
28 30 VDD
S
Main power supply
29 31 MCCFI
I
A
Motor Control Current Feedback Input
30 32 MCIC
I
A
Motor Control Input C
31 33 MCIB
I
A
Motor Control Input B
32 34 MCIA
I
A
Motor Control Input A
8/132
R
Timer A Output Compare 1
ST72141K
1.3 EXTERNAL CONNECTIONS
The following figure shows the recommended external connections for the device.
The VPP pin is only used for programming OTP
and EPROM devices and must be tied to ground in
user mode.
The 10 nF and 0.1 µF decoupling capacitors on
the power supply lines are a suggested EMC performance/cost tradeoff.
The external reset network is intended to protect
the device against parasitic resets, especially in
noisy environments.
Unused I/Os should be tied high to avoid any unnecessary power consumption on floating lines.
An alternative solution is to program the unused
ports as inputs with pull-up.
Figure 5. Recommended External Connections
VPP
VDD
10µF
VDD
+
0.1µF
VSS
Optional if Low Voltage
Detector (LVD) is used
VDD
VDD
4.7K
0.1µF
RESET
EXTERNAL RESET CIRCUIT
0.1µF
VSS
See
Clocks
Section
OSC1
OSC2
Or configure unused I/O ports
by software as input with pull-up
VDD
10K
Unused I/O
9/132
ST72141K
1.4 REGISTER & MEMORY MAP
As shown in Figure 6, the MCU is capable of addressing 64K bytes of memories and I/O registers.
The available memory locations consist of 128
bytes of register locations, 256 bytes of RAM and
8Kbytes of user program memory. The RAM
space includes up to 64 bytes for the stack from
0140h to 017Fh.
The highest address bytes contain the user reset
and interrupt vectors.
Figure 6. Memory Map
0080h
0000h
007Fh
0080h
HW Registers
(see Table 3)
Short Addressing
RAM
“Zero page”
(128 Bytes)
256 Bytes RAM
00FFh
0100h
017Fh
0180h
16-bit Addressing
RAM
(64 Bytes)
Reserved
DFFFh
E000h
013Fh
0140h
Program Memory
(8K Bytes)
FFDFh
FFE0h
FFFFh
Interrupt & Reset Vectors
(see Table 2)
017Fh
Stack or
16-bit Addressing
RAM
(64 Bytes)
Table 2. Interrupt Vector Map
Vector Address
FFE0-FFE1h
FFE2-FFE3h
FFE4-FFE5h
FFE6-FFE7h
FFE8-FFE9h
FFEA-FFEBh
FFEC-FFEDh
FFEE-FFEFh
FFF0-FFF1h
FFF2-FFF3h
FFF4-FFF5h
FFF6-FFF7h
FFF8-FFF9h
FFFA-FFFBh
FFFC-FFFDh
FFFE-FFFFh
10/132
Description
Not used
Not used
Not used
Not used
Not used
TIMER B interrupt vector
TIMER A interrupt vector
SPI interrupt vector
Motor control interrupt vector (events: E, O)
Motor control interrupt vector (events: C, D)
Motor control interrupt vector (events: R, Z)
External interrupt vector EI1: port B7..0
External interrupt vector EI0: port A7..0
Not used
TRAP (software) interrupt vector
RESET vector
Remarks
Internal Interrupt
External Interrupt
External Interrupt
CPU Interrupt
ST72141K
Table 3. Hardware Register Map
Address
Block
0000h
0001h
0002h
Port A
Register
Label
PADR
PADDR
PAOR
Register Name
Port A Data Register
Port A Data Direction Register
Port A Option Register
0003h
0004h
0005h
0006h
Port B
00h
00h
00h
R/W
R/W
R/W
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
00h
00h
00h
R/W
R/W
R/W.
Reserved Area (24 Byte)
0020h
0021h
0022h
0023h
SPI
0024h
0025h
WATCHDOG
MISCR
Miscellaneous Register
00h
R/W
SPIDR
SPICR
SPISR
SPI Data I/O Register
SPI Control Register
SPI Status Register
xxh
0xh
00h
R/W
R/W
Read Only
WDGCR
WDGSR
Watchdog Control Register
Watchdog Status Register
7Fh
x0h
R/W
Read Only
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
0026h
to
0030h
0040h
Remarks
Reserved Area (1 Byte)
0007h
to
001F
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
Reset
Status
Reserved Area (11 Bytes)
TIMER A
TACR2
TACR1
TASR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
A Control Register 2
A Control Register 1
A Status Register
A Input Capture 1 High Register
A Input Capture 1 Low Register
A Output Compare 1 High Register
A Output Compare 1 Low Register
A Counter High Register
A Counter Low Register
A Alternate Counter High Register
A Alternate Counter Low Register
A Input Capture 2 High Register
A Input Capture 2 Low Register
A Output Compare 2 High Register
A Output Compare 2 Low Register
Reserved Area (1 Byte)
11/132
ST72141K
Address
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
Block
TIMER B
Register
Label
TBCR2
TBCR1
TBSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
0050h
to
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
0072h
to
007Fh
12/132
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
B Control Register 2
B Control Register 1
B Status Register
B Input Capture 1 High Register
B Input Capture 1 Low Register
B Output Compare 1 High Register
B Output Compare 1 Low Register
B Counter High Register
B Counter Low Register
B Alternate Counter High Register
B Alternate Counter Low Register
B Input Capture 2 High Register
B Input Capture 2 Low Register
B Output Compare 2 High Register
B Output Compare 2 Low Register
Reset
Status
Remarks
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00h
00h
Read Only
R/W
Reserved Area (16 Bytes)
MOTOR
CONTROL
MTIM
MZPRV
MZREG
MCOMP
MDREG
MWGHT
MPRSR
MIMR
MISR
MCRA
MCRB
MPHST
MPAR
MPOL
006Eh
to
006Fh
0070h
0071h
Register Name
Timer Counter Register
Zn-1 Capture Register
Zn Capture Register
Cn+1Compare Register
D capture/Compare Register
Weight Register
Prescaler and Ratio Register
Interrupt Mask Register
Interrupt Status Register
Control Register A
Control Register B
Phase State Register
Output Parity Register
Output Polarity Register
Reserved Area (2 bytes)
ADC
ADCDR
ADCCSR
Data Register
Control/Status Register
Reserved Area (14 Bytes)
ST72141K
1.5 EPROM PROGRAM MEMORY
The program memory of the OTP and EPROM devices can be programmed with EPROM programming tools available from STMicroelectronics.
EPROM Erasure
EPROM devices are erased by exposure to high
intensity UV light admitted through the transparent
window. This exposure discharges the floating
gate to its initial state through induced photo current.
It is recommended that the EPROM devices be
kept out of direct sunlight, since the UV content of
sunlight can be sufficient to cause functional failure. Extended exposure to room level fluorescent
lighting may also cause erasure.
An opaque coating (paint, tape, label, etc...)
should be placed over the package window if the
product is to be operated under these lighting conditions. Covering the window also reduces IDD in
power-saving modes due to photo-diode leakage
currents.
13/132
ST72141K
2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
2.2 MAIN FEATURES
■
■
■
■
■
■
■
■
63 basic instructions
Fast 8-bit by 8-bit multiply
17 main addressing modes
Two 8-bit index registers
16-bit stack pointer
Low power modes
Maskable hardware interrupts
Non-maskable software interrupt
2.3 CPU REGISTERS
The 6 CPU registers shown in Figure 7 are not
present in the memory mapping and are accessed
by specific instructions.
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
Index Registers (X and Y)
In indexed addressing modes, these 8-bit registers
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from
the stack).
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
Figure 7. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
X INDEX REGISTER
RESET VALUE = XXh
7
0
Y INDEX REGISTER
RESET VALUE = XXh
15
PCH
8 7
PCL
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1 1 1 H I
0
N Z C
CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X
15
8 7
0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
14/132
ST72141K
CPU REGISTERS (Cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
Reset Value: 111x1xxx
7
1
0
1
1
H
I
N
Z
because the I bit is set by hardware at the start of
the routine and reset by the IRET instruction at the
end of the routine. If the I bit is cleared by software
in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the current interrupt routine.
C
The 8-bit Condition Code register contains the interrupt mask and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.
Bit 2 = N Negative.
This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic,
logical or data manipulation. It is a copy of the 7th
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instructions.
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 3 = I Interrupt mask.
This bit is set by hardware when entering in interrupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptable
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
15/132
ST72141K
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
Read/Write
Reset Value: 01 7Fh
15
0
8
0
0
0
0
0
0
7
0
1
0
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 8).
Since the stack is 128 bytes deep, the 9th most
significant bits are forced by hardware. Following
an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP6 to SP0 bits are set) which is the
stack higher address.
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD instruction.
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously
stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 8.
– When an interrupt is received, the SP is decremented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
Figure 8. Stack Manipulation Example
CALL
Subroutine
PUSH Y
Interrupt
Event
POP Y
RET
or RSP
IRET
@ 0100h
SP
SP
CC
A
X
X
X
PCH
PCH
PCH
PCL
PCL
PCL
PCH
PCH
PCH
PCH
PCH
PCL
PCL
PCL
PCL
PCL
SP
@ 017Fh
Stack Higher Address = 017Fh
Stack Lower Address = 0100h
16/132
SP
Y
CC
A
CC
A
SP
SP
ST72141K
3 SUPPLY, RESET AND CLOCK MANAGEMENT
The ST72141K includes a range of utility features
for securing the application in critical situations (for
example in case of a power brown-out), and reducing the number of external components. An
overview is shown in Figure 9.
Main Features
■ Main supply low voltage detection (LVD)
■ RESET Manager
■ Low consumption resonator oscillator
■ Main clock controller (MCC)
Figure 9. Clock, RESET, Option and Supply Management Overview
fMOTOR_CONTROL
fSPI
OSC2
OSCILLATOR
OSC1
RESET
VDD
fOSC
MAIN CLOCK
CONTROLLER
fCPU
(MCC)
RESET
FROM
WATCHDOG
PERIPHERAL
LOW VOLTAGE
DETECTOR
VSS
(LVD)
17/132
ST72141K
3.1 LOW VOLTAGE DETECTOR (LVD)
To allow the integration of power management
features in the application, the Low Voltage Detector function (LVD) generates a static reset when
the VDD supply voltage is below a VLVDf reference
value. This means that it secures the power-up as
well as the power-down keeping the ST7 in reset.
The V LVDf reference value for a voltage drop is
lower than the V LVDr reference value for power-on
in order to avoid a parasitic reset when the MCU
starts running and sinks current on the supply
(hysteresis).
The LVD Reset circuitry generates a reset when
VDD is below:
– VLVDr when VDD is rising
– VLVDf when VDD is falling
The LVD function is illustrated in Figure 10.
Provided the minimum VDD value (guaranteed for
the oscillator frequency) is below VLVDf, the MCU
can only be in two modes:
– under full software control
– in static safe reset
In these conditions, secure operation is always ensured for the application without the need for external reset hardware.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
Notes:
The LVD allows the device to be used without any
external RESET circuitry.
Figure 10. Low Voltage Detector vs Reset
VDD
HYSTERISIS
VLVDhyst
VLVDr
VLVDf
RESET
18/132
ST72141K
3.2 RESET MANAGER
The RESET block includes three RESET sources
as shown in Figure 11:
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.
A 4096 CPU clock cycle delay allows the oscillator
to stabilise and ensures that recovery has taken
place from the Reset state.
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 11. Reset Block Diagram
V DD
INTERNAL
RESET
RON
COUNTER
fCPU
RESET
WATCHDOG RESET
LVD RESET
19/132
ST72141K
RESET MANAGER (Cont’d)
External RESET pin
The RESET pin is both an input and an open-drain
output with integrated R ON weak pull-up resistor
(see Figure 11). This pull-up has no fixed value but
varies in accordance with the input voltage. It can
be pulled low by external circuitry to reset the device.
A RESET signal originating from an external
source must have a duration of at least tPULSE in
order to be recognized. Two RESET sequences
can be associated with this RESET source as
shown in Figure 12.
When the RESET is generated by a internal
source, during the two first phases of the RESET
sequence, the device RESET pin acts as an output that is pulled low.
Generic Power On RESET
The function of the POR circuit consists of waking
up the MCU by detecting (at around 2V) a dynamic
(rising edge) variation of the VDD Supply. At the
beginning of this sequence, the MCU is configured
in the RESET state. When the power supply voltage rises to a sufficient level, the oscillator starts to
operate, whereupon an internal 4096 CPU cycles
delay is initiated, in order to allow the oscillator to
fully stabilize before executing the first instruction.
The initialization sequence is executed immediately following the internal delay.
To ensure correct start-up, the user should take
care that the VDD Supply is stabilized at a sufficient level for the chosen frequency (see Electrical
Characteristics) before the reset signal is released. In addition, supply rising must start from
0V.
As a consequence, the POR does not allow to supervise static, slowly rising, or falling, or noisy (oscillating) VDD supplies.
An external RC network connected to the RESET
pin, or the LVD reset can be used instead to get
the best performance.
Figure 12. External RESET Sequences
VDD
VDD nominal
VLVDf
RESET
RUN
DELAY
tPULSE
INTERNAL RESET
4096 CLOCK CYCLES
FETCH
VECTOR
RUN
EXTERNAL RESET SOURCE
RESET PIN
WATCHDOG RESET
20/132
ST72141K
RESET MANAGER (Cont’d)
Internal Low Voltage Detection RESET (option)
Two different RESET sequences caused by the internal LVD circuitry can be distinguished:
- LVD Power-On RESET
- Voltage Drop RESET
In the second sequence, a “delay” phase is used
to keep the device in RESET state until VDD rises
up to VLVDr (see Figure 13).
Figure 13. LVD RESET Sequences
VDD
RESET
POWEROFF
LVD POWER-ON RESET
VDDnominal
VLVDr
INTERNAL RESET
FETCH
4096 CLOCK CYCLES VECTOR
RUN
EXTERNAL RESET SOURCE
RESET PIN
WATCHDOG RESET
VDD
VDDnominal
VLVDr
VLVDf
RESET
RUN
VOLTAGE DROP RESET
DELAY
INTERNAL RESET
FETCH
4096 CLOCK CYCLES VECTOR
RUN
EXTERNAL RESET SOURCE
RESET PIN
WATCHDOG RESET
21/132
ST72141K
RESET MANAGER (Cont’d)
Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow has the shortest reset
phase (see Figure 14).
Figure 14. Watchdog RESET Sequence
VDD
VDDnominal
VLVDf
RESET
RUN
INTERNAL RESET
4096 CLOCK CYCLES
FETCH
VECTOR
RUN
EXTERNAL RESET SOURCE
tWDGRST
RESET PIN
WATCHDOG RESET
WATCHDOG UNDERFLOW
22/132
ST72141K
3.3 LOW CONSUMPTION OSCILLATOR
The main clock of the ST7 can be generated by
two different sources:
■ an external source
■ a crystal or ceramic resonator oscillators
External Clock Source
In this mode, a square clock signal with ~50% duty
cycle has to drive the OSC2 pin while the OSC1
pin is tied to V SS (see Figure 15).
Crystal/Ceramic Oscillators
This oscillator (based on constant current source)
is optimized in terms of consumption and has the
advantage of producing a very accurate rate on
the main clock of the ST7.
When using this oscillator, the resonator and the
load capacitances have to be connected as shown
in Figure 16 and have to be mounted as close as
possible to the oscillator pins in order to minimize
output distortion and start-up stabilization time.
This oscillator is not stopped during the RESET
phase to avoid losing time in the oscillator start-up
phase.
Figure 15. External Clock
Figure 16. Crystal/Ceramic Resonator
ST7
OSC1
ST7
OSC2
EXTERNAL
SOURCE
OSC1
CL0
OSC2
LOAD
CAPACITANCES
CL1
23/132
ST72141K
3.4 MAIN CLOCK CONTROLLER (MCC)
The MCC block supplies the clock for the ST7
CPU and its internal peripherals. It allows the
SLOW power saving mode and the Motor Contral
and SPI peripheral clocks to be managed independently. The MCC functionality is controlled by
two bits of the MISCR register: SMS and XT16.
The XT16 bit acts on the clock of the motor control
and SPI peripherals while the SMS bit acts on the
CPU and the other peripherals.
Figure 17. Main Clock Controller (MCC) Block Diagram
OSC2
OSCILLATOR
OSC1
MCC
fOSC
DIV 2
DIV 16
XT16
24/132
fCPU
-
-
-
CPU CLOCK
TO CPU AND
PERIPHERALS
-
-
-
SMS
DIV 2
4MHz
MOTOR CONTROL
PERIPHERAL
DIV 2
4MHz
SPI
PERIPHERAL
MISCR
ST72141K
4 INTERRUPTS
The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as
listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt
processing flowchart is shown in Figure 18.
The maskable interrupts must be enabled by
clearing the I bit in order to be serviced. However,
disabled interrupts may be latched and processed
when they are enabled (see external interrupts
subsection).
Note: After reset, all interrupts are disabled.
When an interrupt has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
– The I bit of the CC register is set to prevent additional interrupts.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
the Interrupt Mapping Table for vector addresses).
The interrupt service routine should finish with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I bit will be cleared and the main program will
resume.
Priority Management
By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine.
In the case when several interrupts are simultaneously pending, an hardware priority defines which
one will be serviced first (see the Interrupt Mapping Table).
Interrupts and Low Power Mode
All interrupts allow the processor to leave the
WAIT low power mode. Only external and specifically mentioned interrupts allow the processor to
leave the HALT low power mode (refer to the “Exit
from HALT“ column in the Interrupt Mapping Table).
4.1 NON MASKABLE SOFTWARE INTERRUPT
This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit.
It will be serviced according to the flowchart on
Figure 18.
4.2 EXTERNAL INTERRUPTS
External interrupt vectors can be loaded into the
PC register if the corresponding external interrupt
occurred and if the I bit is cleared. These interrupts
allow the processor to leave the Halt low power
mode.
The external interrupt polarity is selected through
the miscellaneous register or interrupt register (if
available).
An external interrupt triggered on edge will be
latched and the interrupt request automatically
cleared upon entering the interrupt service routine.
If several input pins, connected to the same interrupt vector, are configured as interrupts, their signals are logically NANDed before entering the
edge/level detection block.
Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of a NANDed source
(as described on the I/O ports section), a low level
on an I/O pin configured as input with interrupt,
masks the interrupt request even in case of risingedge sensitivity.
4.3 PERIPHERAL INTERRUPTS
Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:
– The I bit of the CC register is cleared.
– The corresponding enable bit is set in the control
register.
If any of these two conditions is false, the interrupt
is latched and thus remains pending.
Clearing an interrupt request is done by:
– Writing “0” to the corresponding bit in the status
register or
– Access to the status register while the flag is set
followed by a read or write of an associated register.
Note: the clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being enabled) will therefore be lost if the clear sequence is
executed.
25/132
ST72141K
INTERRUPTS (Cont’d)
Figure 18. Interrupt Processing Flowchart
FROM RESET
I BIT SET?
N
N
Y
Y
FETCH NEXT INSTRUCTION
N
IRET?
Y
STACK PC, X, A, CC
SET I BIT
LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
26/132
INTERRUPT
PENDING?
ST72141K
INTERRUPTS (Cont’d)
Table 4. Interrupt Mapping
N°
Source
Block
RESET
TRAP
0
Reset
Software Interrupt
Register
Label
Priority
Order
N/A
Highest
Priority
Exit
from
HALT
EI0
2
EI1
3
External Interrupt Port A7..0 (C5..0*)
External Interrupt Port B7..0 (C5..0*)
FFFEh-FFFFh
no
FFFCh-FFFDh
FFFAh-FFFBh
yes
N/A
Motor Control Interrupt (events: R, Z)
MTC
5
Motor Control Interrupt (events: C, D)
Address
Vector
yes
Not used
1
4
Description
MISR
Motor Control Interrupt (events: E, O)
FFFAh-FFFBh
yes
FFF8h-FFF9h
no
FFF4h-FFF5h
no
FFF2h-FFF3h
no
FFF0h-FFF1h
6
SPI
SPI Peripheral Interrupts
SPISR
no
FFEEh-FFEFh
7
TIMER A
TIMER A Peripheral Interrupts
TASR
no
FFECh-FFEDh
8
TIMER B
TIMER B Peripheral Interrupts
TBSR
no
FFEAh-FFEBh
9
Not used
FFE8h-FFE9h
10
Not used
FFE6h-FFE7h
11
Not used
FFE4h-FFE5h
12
Not Used
FFE2h-FFE3h
13
Not Used
Lowest
Priority
FFE0h-FFE1h
27/132
ST72141K
5 POWER SAVING MODES
5.1 Introduction
To give a large measure of flexibility to the application in terms of power consumption, three main
power saving modes are implemented in the ST7
(see Figure 19).
After a RESET the normal operating mode is selected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided by 2 (f CPU).
From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the the oscillator status.
Figure 19. Power saving mode consumption / transitions
HALT
Low
POWER CONSUMPTION
28/132
SLOW WAIT
WAIT
SLOW
RUN
High
ST72141K
POWER SAVING MODES (Cont’d)
5.2 HALT Mode
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
ST7 HALT instruction (see Figure 21).
The MCU can exit HALT mode on reception of either an external interrupt or a reset (see Table 2).
When exiting HALT mode by means of a RESET
or an interrupt, the oscillator is immediately turned
on and the 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU
resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see Figure 20).
When entering HALT mode, the I bit in the CC
Register is forced to 0 to enable interrupts.
In the HALT mode the main oscillator is turned off
causing all internal processing to be stopped, including the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscillator).
Figure 20. HALT Mode timing overview
4096 CPU CYCLE
DELAY
HALT
RUN
RESET
OR
INTERRUPT
HALT
INSTRUCTION
RUN
FETCH
VECTOR
Figure 21. HALT modes flow-chart
N
WATCHDOG
ENABLE
HALT
OSCILLATOR
PERIPHERALS
CPU
I BIT
HALT INSTRUCTION
Y
OFF
OFF
OFF
0
N
4096 clock cycles delay
RESET
Y
N
EXTERNAL*
INTERRUPT
Y
Notes:
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
OFF
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
FETCH RESET VECTOR
OR SERVICE INTERRUPT**
* External interrupt or internal interrupts with Exit from Halt Mode capability
** Before servicing an interrupt, the CC register is pushed on the stack.
29/132
ST72141K
POWER SAVING MODES (Cont’d)
5.3 WAIT Mode
5.4 SLOW Mode
WAIT mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selected by calling the
“WFI” ST7 software instruction.
All peripherals remain active. During WAIT mode,
the I bit of the CC register are forced to 0, to enable all interrupts. All other registers and memory
remain unchanged. The MCU remains in WAIT
mode until an interrupt or Reset occurs, whereupon the Program Counter branches to the starting
address of the interrupt or Reset service routine.
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Refer to Figure 22.
This mode has two targets:
– To reduce power consumption by decreasing the
internal clock in the device,
– To adapt the internal clock frequency (fCPU) to
the available supply voltage.
SLOW mode is controlled by the SMS bit in the
MISCR register. This bit enables or disables Slow
mode selecting the internal slow frequency (fCPU).
In this mode, the oscillator frequency can be divided by 32 instead of 2 in normal operating mode.
The CPU and peripherals are clocked at this lower
frequency except the Motor Control and the SPI
peripherals which have their own clock selection
bit (XT16) in the MISCR register.
Figure 22. WAIT mode flow-chart
OSCILLATOR
PERIPHERALS
CPU
I BIT
WFI INSTRUCTION
N
RESET
if exit caused by a RESET, a 4096 CPU
clock cycle delay is inserted.
Y
N
ON
ON
OFF
0
INTERRUPT
Y
OSCILLATOR
PERIPHERALS
CPU
Note:
30/132
ON
OFF*
OFF
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
FETCH RESET VECTOR
OR SERVICE INTERRUPT**
* The peripheral clock is stopped only when exit caused by RESET and not by an interrupt.
** Before servicing an interrupt, the CC register is pushed on the stack.
ST72141K
6 I/O PORTS
6.1 INTRODUCTION
The I/O ports offer different functional modes:
– transfer of data through digital inputs and outputs
and for specific pins:
– external interrupt generation
– alternate signal input/output for the on-chip peripherals.
An I/O port contains up to 8 pins. Each pin can be
programmed independently as digital input (with or
without interrupt generation) or digital output.
6.2 FUNCTIONAL DESCRIPTION
Each port has 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
and one optional register:
– Option Register (OR)
Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The
same correspondence is used for the DR register.
The following description takes into account the
OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is
shown in Figure 23
6.2.1 Input Modes
The input configuration is selected by clearing the
corresponding DDR register bit.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
Different input modes can be selected by software
through the OR register.
Notes:
1. Writing the DR register modifies the latch value
but does not affect the pin status.
2. When switching from input to output mode, the
DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output.
External interrupt function
When an I/O is configured as Input with Interrupt,
an event on this I/O can generate an external interrupt request to the CPU.
Each pin can independently generate an interrupt
request. The interrupt sensitivity is independently
programmable using the sensitivity bits in the Miscellaneous register.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description
and interrupt section). If several input pins are selected simultaneously as interrupt source, these
are logically NANDed. For this reason if one of the
interrupt pins is tied low, it masks the other ones.
In case of a floating input with interrupt configuration, special care must be taken when changing
the configuration (see Figure 24).
The external interrupts are hardware interrupts,
which means that the request latch (not accessible
directly by the application) is automatically cleared
when the corresponding interrupt vector is
fetched. To clear an unwanted pending interrupt
by software, the sensitivity bits in the Miscellaneous register must be modified.
6.2.2 Output Modes
The output configuration is selected by setting the
corresponding DDR register bit. In this case, writing the DR register applies this digital value to the
I/O pin through the latch. Then reading the DR register returns the previously stored value.
Two different output modes can be selected by
software through the OR register: Output push-pull
and open-drain.
DR register value and output pin status:
DR
0
1
Push-pull
VSS
VDD
Open-drain
Vss
Floating
6.2.3 Alternate Functions
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically selected. This alternate function takes priority over the
standard I/O programming.
When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the
peripheral).
When the signal is going to an on-chip peripheral,
the I/O pin must be configured in input mode. In
this case, the pin state is also digitally readable by
addressing the DR register.
Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral
input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.
31/132
ST72141K
I/O PORTS (Cont’d)
Figure 23. I/O Port General Block Diagram
ALTERNATE
OUTPUT
REGISTER
ACCESS
1
VDD
0
P-BUFFER
(see table below)
ALTERNATE
ENABLE
PULL-UP
(see table below)
DR
VDD
DDR
PULL-UP
CONFIGURATION
DATA BUS
OR
PAD
If implemented
OR SEL
N-BUFFER
DIODES
(see table below)
DDR SEL
DR SEL
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
1
0
EXTERNAL
INTERRUPT
SOURCE (eix)
POLARITY
SELECTION
ALTERNATE
INPUT
FROM
OTHER
BITS
Table 5. I/O Port Mode Options
Configuration Mode
Input
Output
Floating with/without Interrupt
Pull-up with/without Interrupt
Push-pull
Open Drain (logic level)
True Open Drain
Legend: NI - not implemented
Off - implemented not activated
On - implemented and activated
32/132
Pull-Up
P-Buffer
Off
On
Off
Off
NI
On
Off
NI
Diodes
to VDD
On
to VSS
On
NI (see note)
Note: The diode to V DD is not implemented in the
true open drain pads. A local protection between
the pad and VSS is implemented to protect the device against positive stress.
ST72141K
I/O PORTS (Cont’d)
Table 6. I/O Port Configurations
Hardware Configuration
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
VDD
RPU
PULL-UP
CONFIGURATION
DR
REGISTER
PAD
W
DATA BUS
INPUT 1)
R
ALTERNATE INPUT
FROM
OTHER
PINS
INTERRUPT
CONFIGURATION
EXTERNAL INTERRUPT
SOURCE (eix)
POLARITY
SELECTION
PUSH-PULL OUTPUT 2)
OPEN-DRAIN OUTPUT 2)
ANALOG INPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
VDD
RPU
DR
REGISTER
PAD
ALTERNATE
ENABLE
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
R/W
DATA BUS
ALTERNATE
OUTPUT
DR REGISTER ACCESS
VDD
RPU
PAD
DR
REGISTER
ALTERNATE
ENABLE
R/W
DATA BUS
ALTERNATE
OUTPUT
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
33/132
ST72141K
I/O PORTS (Cont’d)
CAUTION: The alternate function must not be activated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts.
Analog alternate function
When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input.
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected analog pin.
WARNING: The analog input voltage level must
be within the limits stated in the absolute maximum ratings.
6.3 I/O PORT IMPLEMENTATION
The hardware implementation on each I/O port depends on the settings in the DDR and OR registers
34/132
and specific feature of the I/O port such as ADC Input or true open drain.
Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 24 Other transitions
are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
such as spurious interrupt generation.
Figure 24. Interrupt I/O Port State Transitions
01
00
10
11
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
XX
= DDR, OR
The I/O port register configurations are summarized as follows.
ST72141K
I/O PORTS (Cont’d)
Interrupt Ports
PA7:0, PB5:3 (with pull-up)
MODE
floating input
pull-up interrupt input
open drain output
push-pull output
DDR
OR
0
0
1
1
0
1
0
1
DDR
OR
0
0
1
0
1
X
True Open Drain Interrupt Ports
PB2:0 (without pull-up)
MODE
floating input
floating interrupt input
true open drain (high sink ports)
Table 7. Port Configuration
Input
Port
Port A
Port B
Output
Pin name
PA7:0
PB5:3
PB2:0
OR = 0
OR = 1
floating
floating
floating
pull-up interrupt
pull-up interrupt
floating interrupt
OR = 0
OR = 1
open drain
push-pull
open drain
push-pull
true open drain
35/132
ST72141K
I/O PORTS (Cont’d)
6.3.1 Register Description
OPTION REGISTER (OR)
Port x Option Register
PxOR with x = A or B.
Read /Write
Reset Value: 0000 0000 (00h)
DATA REGISTER (DR)
Port x Data Register
PxDR with x = A or B.
Read /Write
Reset Value: 0000 0000 (00h)
7
D7
D6
D5
D4
D3
D2
D1
0
7
D0
O7
Bit 7:0 = D[7:0] Data register 8 bits.
The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken into account
even if the pin is configured as an input; this allows
to always have the expected level on the pin when
toggling to output mode. Reading the DR register
returns either the DR register latch content (pin
configured as output) or the digital value applied to
the I/O pin (pin configured as input).
DATA DIRECTION REGISTER (DDR)
Port x Data Direction Register
PxDDR with x = A or B.
Read /Write
Reset Value: 0000 0000 (00h)
7
DD7
0
DD6
DD5
DD4
DD3
DD2
DD1
DD0
Bit 7:0 = DD[7:0] Data direction register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bits is set and
cleared by software.
0: Input mode
1: Output mode
36/132
0
O6
O5
O4
O3
O2
O1
O0
Bit 7:0 = O[7:0] Option register 8 bits.
For specific I/O pins, this register is not implemented. In this case the DDR register is enough to select the I/O pin configuration.
The OR register allows to distinguish: in input
mode if the pull-up with interrupt capability or the
basic pull-up configuration is selected, in output
mode if the push-pull or open drain configuration is
selected.
Each bit is set and cleared by software.
Input mode:
0: floating input
1: pull-up input with or without interrupt
Output mode:
0: output open drain (with P-Buffer unactivated)
1: output push-pull (when available)
ST72141K
I/O PORTS (Cont’d)
Table 8. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
Reset Value
of all IO port registers
0000h
PADR
0001h
PADDR
0002h
PAOR
0004h
PBDR
0005h
PBDDR
0006h
PBOR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
MSB
LSB
MSB
LSB
37/132
ST72141K
7 MISCELLANEOUS REGISTER
The miscellaneous register allows control over
several different features such as the external interrupts or the I/O alternate functions.
7.1 I/O Port Interrupt Sensitivity Description
The external interrupt sensitivity is controlled by
the ISxx bits of the Miscellaneous register. This
control allows to have two fully independent external interrupt source sensitivities as shown in Figure 25.
Each external interrupt source can be generated
on four different events on the pin:
■ Falling edge
■ Rising edge
■ Falling and rising edge
■ Falling edge and low level
To guaranty correct functionality, a modification of
the sensitivity in the MISCR register must be done
only when the I bit of the CC register is set to 1 (interrupt masked). See I/O port register and Miscellaneous register descriptions for more details on
the programming.
Figure 25. External Interrupt Sensitivity
MISCR
IS01
IS00
SENSITIVITY
EI0
INTERRUPT
SOURCE
PA7
CONTROL
PA0
MISCR
IS11
IS10
SENSITIVITY
EI1
INTERRUPT
SOURCE
PB7
CONTROL
PB0
38/132
7.2 I/O Port Alternate Functions
The MISCR register manages the SPI SS pin alternate function configuration. This makes it possible to use the PB2 I/O port function while the SPI is
active.
These functions are described in detail in Section
7.4 Miscellaneous Register Description.
7.3 Clock Prescaler Selection
The MISCR register is used to select the SLOW
mode (see Section 5.4 SLOW Mode for more details) and the SPI and Motor Control peripheral
clock prescaler.
ST72141K
MISCELLANEOUS REGISTER (Cont’d)
Bits 4:3 = IS1[1:0] EI1 sensitivity
The interrupt sensitivity defined using the IS1[1:0]
bits combination is applied to the EI1 external interrupts. These two bits can be written only when
the I bit of the CC register is set to 1 (interrupt
masked).
EI1: Port B
7.4 Miscellaneous Register Description
MISCELLANEOUS REGISTER (MISCR)
Read /Write
Reset Value: 0000 0000 (00h)
7
0
IS11 IS10
XT16 SSM
SSI
IS11
IS10
IS01
IS00
External Interrupt Sensitivity
SMS
Bit 7 = XT16 MTC and SPI clock selection
This bit is set and cleared by software. The maximum allowed frequency is 4MHz.
0: MTC and SPI clock supplied with fOSC/2
1: MTC and SPI clock supplied with fOSC/4
Bit 6 = SSM SS mode selection
This bit is set and cleared by software.
0: Normal mode - the level of the SPI SS signal is
the external SS pin.
1: I/O mode, the level of the SPI SS signal is read
from the SSI bit.
Bit 5 = SSI SS internal mode
This bit replaces the SS pin of the SPI when the
SSM bit is set to 1. (see SPI description). It is set
and cleared by software.
0
0
Falling edge & low level
0
1
Rising edge only
1
0
Falling edge only
1
1
Rising and falling edge
Bits 2:1 = IS0[1:0] EI0 sensitivity
The interrupt sensitivity defined using the IS0[1:0]
bits combination is applied to the EI1 external interrupts. These two bits can be written only when
the I bit of the CC register is set to 1 (interrupt
masked).
EI0: Port A
IS01 IS00
External Interrupt Sensitivity
0
0
Falling edge & low level
0
1
Rising edge only
1
0
Falling edge only
1
1
Rising and falling edge
Bit 0 = SMS Slow mode select
This bit is set and cleared by software.
0: Normal mode. fCPU = fOSC / 2
1: Slow mode. fCPU = fOSC / 32
See sections on low power consumption mode
and MCC for more details.
Table 9. Miscellaneous Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
0020h
MISCR
Reset Value
XT16
0
SSM
0
SSI
0
IS11
0
IS10
0
IS01
0
IS00
0
SMS
0
39/132
ST72141K
8 ON-CHIP PERIPHERALS
8.1 MOTOR CONTROLLER (MTC)
8.1.1 Introduction
The ST7 Motor Controller (MTC) can be seen as a
Pulse Width Modulator multiplexed on six output
channels, and a Back Electromotive Force
(BEMF) zero-crossing detector for sensorless control of Permanent Magnet Direct Current (PMDC)
brushless motors.
The MTC is particularly suited to driving synchronous motors and supports operating modes like:
– Commutation step control with motor voltage
regulation and current limitation
– Commutation step control with motor current
regulation, i.e. direct torque control
– Sensor or sensorless motor phase commutation
control
– BEMF zero-crossing detection with high sensitivity. The integrated phase voltage comparator is
directly referred to the full BEMF voltage without
any attenuation. A BEMF voltage down to
200 mV can be detected, providing high noise
immunity and self-commutated operation in a
large speed range.
– Realtime motor winding demagnetization detection for fine-tuning the phase voltage masking
time to be applied before BEMF monitoring.
– Automatic and programmable delay between
BEMF zero-crossing detection and motor phase
commutation.
8.1.2 Main Features
■ Two on-chip analog comparators, one for BEMF
zero-crossing detection with 100 mV hysteresis,
the other for current regulation or limitation
■ Four selectable reference voltages for the
hysteresis comparator (0.2 V, 0.6 V, 1.2 V,
2.5 V)
■ 8-bit timer (MTIM) with two compare registers
and two capture features
■ Measurement window generator for BEMF
zero-crossing detection
■ Auto-calibrated prescaler with 16 division steps
■ 8x8-bit multiplier
■ Phase input multiplexer
■ Sophisticated output management:
– The six output channels can be split into two
groups (odd & even).
– The PWM signal can be multiplexed on even,
odd or both groups, alternatively or simultaneously.
40/132
– The output polarity is programmable channel
by channel.
– An software enabled bit (active low) forces the
outputs in HiZ.
– An “emergency stop” input pin (active low)
asynchronously forces the outputs in HiZ.
Table 10. MTC Registers
Register
MTIM
MZPRV
MZREG
MCOMP
MDREG
MWGHT
MPRSR
MIMR
MISR
MCRA
MCRB
MPHST
MPAR
MPOL
Description
Timer Counter Register
Capture Zn-1 Register
Capture Zn Register
Compare Cn+1 Register
Demagnetization Register
An Weight Register
Prescaler & Sampling Register
Interrupt Mask Register
Interrupt Status Register
Control Register A
Control Register B
Phase State Register
Parity Register
Polarity Register
Page
67
67
67
67
67
67
67
68
68
69
70
71
71
71
8.1.3 Application Example
This example shows a six-step command sequence for a 3-phase permanent magnet DC
brushless motor (PMDC motor). Figure 27 shows
the phase steps and voltage, while Table 11
shows the relevant phase configurations.
To run this kind of motor efficiently, an autoswitching mode has to be used, i.e. the position of the rotor must self-generate the powered winding commutation. The BEMF zero crossing (Z event) on
the non-excited winding is used by the MTC as a
rotor position sensor. The delay between this
event and the commutation is computed by the
MTC and the commutation event Cn is automatically generated after this delay.
After the commutation occurs, the MTC waits until
the winding is completely demagnetized by the
free-wheeling diode: during this phase the winding
is tied to 0V or to the HV high voltage rail and no
BEMF can be read. At the end of this phase a new
BEMF zero-crossing detection is enabled.
The end of demagnetization event (D), is also detected by the MTC or simulated with a timer compare feature when no detection is possible.
ST72141K
MOTOR CONTROLLER (Cont’d)
The MTC manages these three events always in
the same order: Z generates C after a delay computed in realtime, then waits for D in order to enable the peripheral to detect another Z event.
The speed regulation is managed by the microcontroller, by means of an adjustable reference
current level in case of current control, or by direct
PWM duty-cycle adjustment in case of voltage
control.
All detections of Zn events are done during a short
measurement window while the high side switch is
turned off. For this reason the PWM signal is applied on the high side switches.
When the high side switch is off, the high side
winding is tied to 0V by the free-wheeling diode,
the low side winding voltage is also held at 0V by
the low side ON switch and the complete BEMF
voltage is present on the third winding: detection is
then possible.
Figure 26. Chronogram of Events (in Autoswitched Mode)
C event
Z event
DH event
DS event
Cn processing
Wait for Cn
Wait for Dn
Wait for Z
T
Zn
Z > Zn min
C > Cn min
Dn
Cn
t
Voltage on phase A
Voltage on phase B
Voltage on phase C
BEMF
sampling
P signal when sampled
(Output of the V
DD
analog MUX)
VREF
(Threshold value for VSS
Input comparator)
41/132
ST72141K
MOTOR CONTROLLER (Cont’d)
Figure 27. Example of Command Sequence for 6-step Mode (typical 3-phase PMDC Motor Control)
Σ2
Σ1
Step
Σ3
Σ4
Σ5
Σ6
Σ1
Σ2
Σ3
HV
Switch
0
T0
T2
T4
B
1
I1
2
I6
I4
3
I3
4
B
C
HV
HV/2
0
T3
T5
T1
HV
HV/2
0
HV
HV/2
0
Note: Control & sampling PWM influence is not represented on these simplified chronograms.
Σ1
Σ2
Σ3
Σ4
Σ5
Σ6
HV
C2
C4
D2
HV/2
Superimposed voltage
(BEMF induced by rotor)
- approx. HV/2 (PWM on)
- approx. 0V (PWM off)
0V
Z2
D 5 Z5
t
Demagnetization
Commutation delay
Wait for BEMF = 0
42/132
C
I5
Node
A
I2
A
5
PWM off pulses
ST72141K
MOTOR CONTROLLER (Cont’d)
Table 11. Step Configuration Summary
demagnetization
Step
Current direction
High side
Low side
Σ1
A to B
T0
T5
Σ2
A to C
T0
T1
Σ3
B to C
T2
T1
Σ4
B to A
T2
T3
Σ5
C to A
T4
T3
Σ6
C to B
T4
T5
OO[5:0] bits in MPHST register
100001
000011
000110
001100
011000
110000
Measurement done on:
MCIC
MCIB
MCIA
MCIC
MCIB
MCIA
IS[1:0] bits in MPHST register
10
01
00
10
01
00
Back EMF shape
CPB bit in MCRB register
(ZVD bit = 0)
Voltage on measured point at the
start of demagnetization
Falling
Rising
Falling
Rising
Falling
Rising
0
1
0
1
0
1
0V
HV
0V
HV
0V
HV
HDM-SDM bits in MCRB register
10
11
10
11
10
11
PWM side selection to accelerate
Odd Side Even Side Odd Side Even Side Odd Side Even Side
demagnetization
switch
Hardware or
Demagnetization
Hardware-software
BEMF BEMF Phase state
edge input
register
Configuration
Driver selection to accelerate demagnetization
T5
T0
T1
T2
T3
T4
For a detailed description of the MTC registers, see Section 8.1.7.
43/132
ST72141K
MOTOR CONTROLLER (Cont’d)
8.1.4 Functional Description
The MTC can be split into four main parts as
shown in the simplified block diagram in Figure 28.
– The BEMF ZERO-CROSSING DETECTOR with
a comparator and an input multiplexer.
– The DELAY MANAGER with an 8-bit timer
(MTIM) and an 8x8 bit multiplier.
– The PWM MANAGER, including a measurement
window generator, a mode selector and a current
comparator.
– The CHANNEL MANAGER with the PWM multiplexer, polarity programming capability and
emergency HiZ configuration input.
8.1.4.1 Input Detection Block
This block can operate in sensor mode or sensorless mode. The mode is selected via the SR bit in
the MCRA register. The block diagram is shown in
Figure 29.
Figure 28. Simplified MTC Block Diagram
DELAY MANAGER
DELAY
WEIGHT
MTIM
TIMER
CAPTURE Zn
BEMF ZERO-CROSSING
DETECTOR
BEMF=0
[Z]
MCIA
MCIB
MCIC
Internal VREF
=?
DELAY = WEIGHT x Zn
COMMUTE [C]
MCO5
(I)
CURRENT
VOLTAGE
(V)
(I)
MCO4
PHASE
MEASUREMENT
WINDOW
GENERATOR
MCO3
MCO2
MCO1
MCO0
(V)
MODE
NMCES
PWM (1)
MCCFI
(V)
OCP1A
(I)
PWM MANAGER
Note 1: The PWM signal is generated by the ST7 16-bit Timer
[Z] : Back EMF Zero-crossing event
Zn : Time elapsed between two consecutive Z events
[C] : Commutation event
Cn : Time delayed after Z event to generate C event
(I): Current mode
(V): Voltage mode
44/132
VDD
CHANNEL MANAGER
R1ext
(V)
R2ext
Cext
(I)
ST72141K
MOTOR CONTROLLER (Cont’d)
Input Pins
The MCIA, MCIB and MCIC input pins can be
used as analog pins in Sensorless mode or as digital pins in Sensor mode. In sensorless mode, the
analog inputs are used to measure the BEMF zero
crossing and to detect the end of demagnetization
if required. In Sensor mode, they are connected to
sensor outputs.
Due to the presence of diodes, these pins can permanently support an input current of 5 mA. In Sensorless mode, this feature enables the inputs to be
connected to each motor phase through a single
resistor.
Note: In high voltage applications, in Sensorless
mode and for certain motors and power topologies
(with parasitic capacitance or other), it may be required to add external pull-up Schottky 0.4 V (e.g.
BAT48) diodes on the MCIA, MCIB and MCIC
pins.
A multiplexer, programmed by the IS[1:0] bits in
MPHST register selects the input pins and connects them to the rotor position control logic in either Sensorless or Sensor mode.
Figure 29. Input Stage
External Input Block
Event Detection
Input Comparator Block
MPHST Register
Inputn Sel Reg
IS[1:0]
MCIA
A
00
MCIB
C
P
01
B
+
Sample
D Q
MCIC
-
10
C
CP
VREF
1
2
DS,H
C
MCRB Register
VR[1:0]
Freq (T=1.25 µs) for demagnetization and sensors
Sampling frequency
I
16-bit Timer PWM
MCRA Register
V0C1 bit
Notes:
Updated/Shifted on R
Reg
Regn
I
V
C
Z
DS,H
E
+/-
R
O
* = Preload register,
changes taken into
account at next C event.
V
MPAR Register
Updated with Regn+1 on C
Current Mode
Voltage Mode
events:
Commutation
BEFM Zero-crossing
End Of Demagnetization
Emergency Stop
Ratio Updated (+1 or -1)
Multiplier Overflow
1
Branch taken after C event
2
Branch taken after D event
CPBn bit*
REO bit
DS,H
C
MCRB Register MPAR Register
20 µs / D
or
Sample
ZVD bit
or
Z
or
2
20µs / C
1
SR bit
or
CPBn bit*
MCRA Register
HDMn bit*
DH
MCRB Register
45/132
ST72141K
MOTOR CONTROLLER (Cont’d)
Sensorless Mode
This mode is used to detect BEMF zero crossing
and end of demagnetization events.
The analog phase multiplexer connects the nonexcited motor winding to an analog 100mV hysteresis comparator referred to a selectable reference
voltage.
The VR[1:0] bits in the MCRB register select the
reference voltage from four internal values depending on the noise level and the application voltage supply.
BEMF detections are performed during the measurement window, when the excited windings are
free-wheeling through the low side switches and
diodes. At this stage the common star connection
voltage is near to ground voltage (instead of V DD/2
when the excited windings are powered) and the
complete BEMF voltage is present on the non-excited winding terminal, referred to the ground terminal.
The zero crossing sampling frequency is then defined, in current mode, by the measurement window generator frequency (SA[3:0] bits in the
MPRSR register) or, in voltage mode, by the 16-bit
Timer PWM frequency and duty cycle.
During a short period after a phase commutation
(C event), the winding is no longer excited but
needs a demagnetisation phase during which the
BEMF cannot be read. A demagnetization current
goes through the free-wheeling diodes and the
winding voltage is stuck at the high voltage or to
the ground terminal. For this reason an “end of demagnetization event” D must be detected on the
winding before the detector can sense a BEMF
zero crossing.
For the end-of-demagnetization detection, no special PWM configuration is needed, the comparator
sensing is done at a fixed 800kHz sampling frequency.
So, the three events: C (commutation), D (demagnetization) and Z (BEMF zero crossing) must always occur in this order.
The comparator output is processed by a detector
that automatically recognizes the D or Z event, depending on the CPB or ZVD edge and level configuration bits as described in Table 12.
A 20−µs filter after a C event disables a D event if
spurious spikes occur.
Another 20−µs filter after a D event disables a Z
event if spurious spikes occur.
Table 12. ZVD and CPB Edge Selection Bits
ZVD bit
CPB bit
Event generation vs input data sampled
20-µs filter
0
0
C
20-µs filter
0
20-µs filter
Z
20-µs filter
DH
Z
20-µs filter
0
C
20-µs filter
1
DH
1
C
1
20-µs filter
DH
20-µs filter
1
C
DH
Note: The ZVD bit is located in the MPAR register, the CPB bit is in the MCRB register.
46/132
Z
Z
ST72141K
MOTOR CONTROLLER (Cont’d)
Demagnetization (D) Event
At the end of the demagnetization phase, current
no longer goes through the free-wheeling diodes.
The voltage on the non-excited winding terminal
goes from one of the power rail voltages to the
common star connection voltage plus the BEMF
voltage. In some cases (if the BEMF voltage is
positive and the free-wheeling diodes are at
ground for example) this end of demagnetization
can be seen as a voltage edge on the selected
MCIx input and it is called a hardware demagnetization event D H. See Table 12.
If enabled by the HDM bit in the MCRB register,
the current value of the MTIM timer is captured in
register MDREG when this event occurs in order
to be able to simulate the demagnetization phase
for the next steps.
When enabled by the SDM bit in the MCRB register, demagnetization can also be simulated by
comparing the MTIM timer with the MDREG register. This kind of demagnetization is called software
demagnetization D S.
If the HDM and SDM bits are both set, the first
event that occurs, triggers a demagnetization
event. For this to work correctly, a D S event must
not precede a DH event because the latter could
be detected as a Z event.
Software demagnetization can also be always
used if the HDM bit is reset and the SDM bit is set.
This mode works as a programmable masking
time between the C and Z events. To drive the motor securely, the masking time must be always
greater than the real demagnetization time in order
to avoid a spurious Z event.
When an event occurs, (either DH or DS) the DI bit
in the MISR register is set and an interrupt request
is generated if the DIM bit of register MIMR is set.
Warning 1: Due to the alternate automatic capture
and compare of the MTIM timer with MDREG register by DH and DS events, the MDREG register
should be manipulated with special care.
Warning 2: To avoid a system stop, the value written to the MDREG register in Soft Demagnetization Mode (SDM = 1) should always be:
– Greater than the MCOMP value of the commutation before the related demagnetization
– Greater than the value in the MTIM counter at
that moment (when writing to the MDREG register).
Figure 30. D Event Generation Mechanism
MTIM [8-bit Up Counter]§
DS,H
C
Sample
8
DH
To Z event detection
2
20 µs / C
1
SR bit
or
DH
HDM n bit*
MCRB Register
SDM bit
Compare
20µs / C
CPBn bit*
MDREG [Dn]§
MCRA Register
MCRB Register
DS
DH
DS
F(x)
D = DH & HDM bit + DS & SDM bit
HDM bit
SDM bit
§ Register
updated on R event
* = Preload register, changes taken into account at next C event
D
To interrupt generator
47/132
ST72141K
MOTOR CONTROLLER (Cont’d)
Table 13. Demagnetisation (D) Event Generation (example for ZVD=0)
HDM
bit
CPB bit = 1
Meaning
CPB bit = 0
(Even Σ)
(Odd Σ)
D = DS = Output Compare [MDREG, MTIM registers]
Undershoot due to
motor parasite or first
sampling
Σ2
Weak / null
undershoot and
BEMF positive
Σ2
HVV
Σ5
HV
HVV
C
Software Mode
0
DS
C
DS
(SDM bit =1 and
HDM bit = 0)
DS
(*)
HV/2
C
HV/2
HV/2
(*)
(*)
0V
0V
0V
Z
Z
Z
D = DH
D = D H + DS
(Hardware detection only)
(Hardware detection or Output compare true)
Undershoot due to
Weak / null
motor parasite or first
undershoot and
sampling
BEMF positive
Σ2
Σ2
HV
Σ5
HV
HV
C
1
Hardware/Simulated Mode
DS
C
DS
(*)
(SDM bit = 1 and
HDM bit = 1)
HV/2
C
HV/2
HV/2
(*)
(*)
0V
DH
0V
Z
0V
Z
(*) Note: This is a zoom to the additional voltage induced by the rotor (Back EMF)
48/132
DH
Z
ST72141K
MOTOR CONTROLLER (Cont’d)
BEMF Zero Crossing (Z) Event
When both C and D events have occurred, the
PWM may be switched to another group of outputs
(depending on the OS[2:0] bits in the MCRB register) and the real BEMF zero crossing sampling can
start (see Figure 32).
A BEMF voltage is present on the non-powered
terminal but referred to common star connection of
the motor whose voltage is equal to V DD/2.
When a winding is free-wheeling (during PWM offtime) its terminal voltage changes to the other
power rail voltage, that means if the PWM is applied on the high side driver, free-wheeling will be
done through the high side diode and the terminal
will be 0V.
This is used to force the common star connection
to 0V in order to read the BEMF referred to the
ground terminal.
Consequently, BEMF reading (i.e. comparison
with a voltage close to 0V) can only be done when
the PWM is applied on the high side drivers.
For this reason the MTC outputs can be split in two
groups called ODD and EVEN and the BEMF
reading will be done only when PWM is applied on
one of these two groups. The REO bit in the MPAR
register is used to select the group to be used for
BEMF sensing (high side group)
Refer to Table 15 for an overview of when a BEMF
can be read depending on REO bit, PWM mode
and function mode of peripheral.
Depending on the edge and level selection (ZVD
and CPB) bits and when PWM is applied on the
correct group, a BEMF zero crossing detection
sets the ZI bit in the MISR register and generates
an interrupt if the ZIM bit is set.
The Z event also triggers some timer/multiplier operations, for more details see Section 8.1.4.2
Figure 31. Sampling and Zero Crossing Blocks
Sample
Output of hysteresis comparator
D Q
Freq. (T=1.25us) for Demagnetization and Sensor
CP
1
Sampling frequency
I
16-bit Timer PWM
V
Regn
E
R+/O
C
V0C1 bit
Updated/Shifted on R
Reg
C
Z
DS,H
DS,H
MCRA Register
Notes:
I
V
2
Updated with Regn+1 on C
Current Mode
Voltage Mode
events:
Commutation
BEFM Zero-crossing
End Of Demagnetization
Emergency Stop
Ratio Updated (+1 or -1)
Multiplier Overflow
1
Branch taken after C event
2
Branch taken after D event
MPAR Register
DS,H
C
REO bit
MCRB Register MPAR Register
CPBn bit*
20µs / D
or
Sample
ZVD bit
or
or
Z
2
1
To D detection
SR bit
MCRA Register
* = Preload register, changes taken into account at next C event.
49/132
ST72141K
MOTOR CONTROLLER (Cont’d)
Sensor Mode
In sensor mode, the rotor position information is
given to the peripheral by means of logical data on
the three inputs MCIA, MCIB and MCIC.
For each step one of these three inputs is selected
(IS[1:0] bits in register MPHST) in order to detect
the Z event.
In this case Demagnetization has no meaning and
the relevant features such as the special PWM
configuration, D S or DH management, 20-µs filter;
are not available (see Table 14).
For this configuration the rotor detection doesn’t
need a particular phase configuration to validate
the measurement and a Z event can be read from
any detection window. A fixed sampling frequency
(800 kHz) is used, that means the Z event and position sensoring is more precise than it is in sensorless mode.
The minimum off time for current control PWM is
also reduced to 1.25µs.
Procedure for reading sensor inputs in Direct
Access mode: In Direct Access mode, the peripheral clock is disabled as shown in Table 25. As the
data present on the selected input is synchronized
by a 800 kHz clock, the sensor can’t be read directly (the value is latched). To read the sensor
data the following steps have to be performed:
1. Select the appropriate MCIx input pin by means
of the IS[1:0] bits in the MPHST register
2. Switch from direct access mode to indirect
access mode in order to latch the sensor data
(DAC bit in MCRA register).
3. Switch back to direct access mode.
4. Read the comparator output (HST bit in the
MIMR register)
Table 14. Sensor mode selection
SR bit
Mode
OS2 bit use
0
Sensors not
used
Enabled
1
Sensors
used
Disabled
50/132
Event detection
sampling clock
D: Clock 1.25µs
20µs after C for D event
Z: SA&OT config.
20µs after D for Z event
“Before D” behaviour
& “after D” behaviour
Z: Clock 1.25µs
20µs after C for Z event
Only “after D” behaviour
Filtering
Behaviour of the output
PWM
ST72141K
MOTOR CONTROLLER (Cont’d)
Figure 32. Functional Diagram of Z Detection after D Event
DS or DH
Begin
20µs Filter turned on
Switch Sampling Clock[D] -> Sampling Clock[Z]
Side change on
Output PWM
?
No
Yes
Change the side according to OS[2:0]
Wait for next sampling clock edge
Read enable
by REO
?
No
Yes
Filter
off
?
No
Yes
Read enabled
End
51/132
ST72141K
MOTOR CONTROLLER (Cont’d)
Table 15. Modes permitting BEMF reading after Demagnetization (D event)
SR bit
V0C1 bit
(Sensor/ Demagnetization
Sensorless Mode)
(Voltage/
Current
Mode)
OS[2:0]
bits
(PWM
Output
Config.)
REO bit
Significant
(Read
PWM
BEMF on
Group
Even/Odd
group)
x00
Even
0
x01
Odd
1
x10
Even
0
x10
Odd
1
000
Even
0
001
Odd
1
100
Even
0
101
Odd
1
110
Even
0
110
Odd
1
x
x11
Even and
Odd
x
x
xxx
Odd or
Even
x
1
0
After D
event
0
1
Not Used
Other cases
52/132
BEMF reading permitted after D event
when:
Sensorless mode, Current Mode, PWM
output only on Even group and BEMF
read on Even group
Sensorless mode, Current Mode, PWM
output only on Odd group and BEMF read
on Odd group
Sensorless mode, Current Mode, PWM
output on alternate groups but BEMF
read only on Even group
Sensorless mode, Current Mode, PWM
output on alternate groups but BEMF
read only on Odd group
Sensorless mode, Voltage Mode, PWM
output only on Even group and BEMF
read on Even group
Sensorless mode, Voltage Mode, PWM
output only on Odd group and BEMF read
on Odd group
Sensorless mode, Voltage Mode, PWM
output only on Even group and BEMF
Read on Even group
Sensorless mode, Voltage Mode, PWM
output only on Odd group and BEMF Read
on Odd group
Sensorless mode, Voltage Mode, PWM
output on alternate groups but BEMF read
only on Even group
Sensorless mode, Voltage Mode, PWM
output on alternate groups but BEMF read
on Odd group
Sensorless mode, Current or Voltage
Mode, PWM output on both groups, BEMF
read on either group
Sensor Mode, in any PWM output configuration, BEMF read on either group
BEMF reading forbidden
ST72141K
MOTOR CONTROLLER (Cont’d)
8.1.4.2 Delay Manager
Figure 33. Overview of MTIM Timer
MCRA register
Tratio
SWA bit
ck
8-bit Up Counter MTIM§
Z
1
clr
C
0
8
Z
DH
MDREG [Dn]§
MZREG [Zn]§
Z
Compare
MZPRV [Zn-1]§
MCRB register
MCOMP [Cn+1]§
20µs/C
SDM bit
DS
Compare
C
C
DS,H
§
= Register updated on R event
This part of the MTC contains all the time-related
functions, its architecture is based on an 8-bit shift
left/shift right timer shown in Figure 33. The MTIM
timer includes:
– An auto-updated prescaler
– A capture/compare register for software demagnetization simulation (MDREG)
– Two cascaded capture register (MZREG and
MZPRV) for storing the times between two consecutive BEMF zero crossings (Z events)
– An 8x8 bit multiplier for auto computing the next
commutation time
– One compare register for phase commutation
generation (MCOMP)
The MTIM timer module can work in two main
modes. In switched mode the user must process
the step duration and commutation time by software, in autoswitched mode the commutation action is performed automatically depending on the
rotor position information and register contents.
Z
To interrupt generator
To interrupt generator
To interrupt generator
Table 16. Switched and Autoswitched Modes
SWA
bit
0
1
Commutation Type
MCOMP User
access
Switched mode
Autoswitched mode
Read/Write
Read only
Switched Mode
This feature allows the motor to be run step-bystep. This is useful when the rotor speed is still too
low to generate a BEMF. It can also run other
kinds of motor without BEMF generation such as
induction motors or switch reluctance motors. This
mode can also be used for autoswitching with all
computation for the next commutation time done
by software (hardware multiplier not used) and using the powerful interrupt set of the peripheral.
In this mode, the step time is directly written by
software in the commutation compare register
MCOMP. When the MTIM timer reaches this value
a commutation occurs (C event) and the MTIM
timer is reset.
53/132
ST72141K
MOTOR CONTROLLER (Cont’d)
At this time all registers with a preload function are
loaded (registers marked with (*) in Section 8.1.7).
The CI bit of MISR is set and if the CIM bit in the
MISR register is set an interrupt is generated.
An overflow of the MTIM timer generates an RPI
interrupt if the RIM bit is set.
The MTIM timer prescaler (Step ratio bits ST[3:0]
in the MPRSR register) is user programmable. Access to this register is not allowed while the MTIM
timer is running (access is possible only before the
starting the timer by means of the MOE bit) but the
prescaler contents can be incremented/decremented at the next commutation event by setting
the RMI (decrement) or RPI (increment) bits in the
MISR register. When this method is used, at the
next commutation event the prescaler value will be
updated but also all the MTIM timer-related registers will be shifted in the appropriate direction to
keep their value. After it has been taken into account, (at commutation) the RPI or RMI bit is reset.
See Table 17.
Only one update per step is allowed, so if both RPI
and RMI are set together, RPI is taken into account at the next commutation and RMI is used
one commutation latter.
In switched mode, BEMF and demagnetization detection are already possible in order to pass in autoswitched mode as soon as possible but Z and D
events do not affect the timer contents.
Warning: In this mode, MCOMP must never be
written to 0.
Table 17. Step Ratio Update
MOE bit SWA bit Clock State
0
x
Disabled
1
0
Enabled
1
1
Enabled
54/132
Read
Always
possible
Ratio Increment
Ratio Decrement
(Slow Down)
(Speed-Up)
Write the ST[3:0] value directly in the MPRSR register
Set RPI bit in the MISR register Set RMI bit in the MISR register
till next commutation
till next commutation
Automatically updated according to MZREG value
ST72141K
MOTOR CONTROLLER (Cont’d)
Figure 34. Step Ratio Functional Diagram
4MHz
R+
+1
MPRSR Register
MTIM Timer = FFh?
4
ST[3:0] Bits
-1
1/2
1 / 2Ratio
Zn < 55h?
R-
Tratio
ck
2 MHz - 62.5 Hz
MTIM Timer control over Tratio and register operation
MTIM Timer Overflow
Begin
Z Capture with MTIM Timer Underflow (Zn < 55h)
Begin
No
No
Ratio < Fh?
Ratio > 0?
Yes
Yes
Ratio = Ratio + 1
Ratio = Ratio - 1
Zn = Zn / 2
Zn+1 = Zn+1/2
Dn = Dn/2
Counter = Counter/2
Zn = Zn x 2
Zn+1 = Zn+1 x 2
Dn = Dn x 2
Counter = Counter x 2
Re-compute Cn
Compute Cn
End
End
Slow-down control
Speed-up control
55/132
ST72141K
MOTOR CONTROLLER (Cont’d)
Autoswitched Mode
In this mode the MCOMP register content is automatically computed in real time as described below and in Figure 35. This register is READ ONLY.
The C event has no effect on the contents of the
MTIM timer.
When a Z event occurs the MTIM timer value is
captured in the MZREG register, the previous captured value is shifted into the MZPRV register and
the MTIM timer is reset. See Figure 26.
One of these two registers (depending on the DCB
bit in the MCRA register) is multiplied with the contents of the MWGHT register and divided by 32.
The result is loaded in the MCOMP compare register, which automatically triggers the next commutation (C event)
Table 18. Multiplier Result
DCB bit
0
1
Commutation Delay
MCOMP = MWGHT x MZPRV / 32
MCOMP = MWGHT x MZREG / 32
When an overflow occurs during the multiply operation, FFh is written in the MCOMP register and an
interrupt (O event) is generated if enabled by the
OIM bit in the MIMR register.
Figure 35. Commutation Processor Block
MZREG [Zn]§
Z
MZPRV [Zn-1]§
MCRA Register
DCB bit
n-1
n
MWGHT [an+1]
8
8
A x B / 32
MCRA Register
SWA bit
8
MCOMP [Cn+1]§
§
= Register updated on R event
56/132
3
set
O
To
interrupt
generator
When the timer reaches this value an RPI interrupt
is generated (timer overflow).
After each shift operation the multiply is recomputed for greater precision.
Using either the MZREG or MZPRV register depends on the motor symmetry and type.
The MWGHT register gives directly the phase shift
between the motor driven voltage and the BEMF.
This parameter generally depends on the motor
and on the speed.
Auto-updated Step Ratio Register: In switched
mode, the MTIM timer is driven by software only
and any prescaler change has to be done by software (see Section 8.1.4.2 for more details).
– In autoswitched mode an auto-updated prescaler always configures the MTIM timer for best accuracy. Figure 34 shows process of updating the
Step Ratio bits:
– When the MTIM timer value reaches FFh, the
prescaler is automatically incremented in order
to slow down the MTIM timer and avoid an overflow. To keep consistent values, the MTIM register and all the relevant registers are shifted right
(divided by two). The RPI bit in the MISR register
is set and an interrupt is generated (if RIM is set).
– When a Z-event occurs, if the MTIM timer value
is below 55h, the prescaler is automatically decremented in order to speed up the MTIM timer
and keep precision better than 1.2%. The MTIM
register and all the relevant registers are shifted
left (multiplied by two). The RMI bit in the MISR
register is set and an interrupt is generated if RIM
is set.
– If the prescaler contents reach the value 0, it can
no longer be automatically decremented, the
MTC continues working with the same prescaler
value, i.e. with a lower accuracy. No RMI interrrupt can be generated.
– If the prescaler contents reach the value 15, it
can no longer be automatically incremented.
When the timer reaches the value FFh, the prescaler and all the relevant registers remain unchanged and no interrupt is generated, the timer
clock is disabled, and its contents stay at FFh
The PWM is still generated and the D and Z detection circuitry still work, enabling the capture of
the maximum timer value.
The automatically updated registers are: MTIM,
MZREG, MZPRV, MCOMP and MDREG. Access
to these registers is summarised in Table 21.
ST72141K
MOTOR CONTROLLER (Cont’d)
Table 19. MTIM Timer-related Registers
Name
MTIM
MZPRV
MZREG
MCOMP
MDREG
Reset Value
00h
00h
00h
00h
00h
Contents
Timer Value
Capture Zn-1
Capture Zn
Compare Cn+1
Demagnetization Dn
Note on using the auto-updated MTIM timer:
The auto-updated MTIM timer works accurately
within its operating range but some care has to be
taken when processing timer-dependent data such
as the step duration for regulation or demagnetization.
For example if an overflow occurs when calculating a software end of demagnetization
(MCOMP+demagnetisation_time>FFh), the value
that stored in MDREG will be:
7Fh+(MCOMP+demagnetization_time-FFh)/2.
Note on commutation interrupts: It is good practice to modify the configuration for the next step as
soon as possible, i.e within the commutation interrupt routine.
All registers that need to be changed at each step
have a preload register that enables the modifications for a complete new configuration to be performed at the same time (at C event in normal
mode or when writing the MPHST register in direct
access mode).
These configuration bits are:
CPB, HDM, SDM and OS2 in the MCRB register
and IS[1:0], OO[5:0] in the MPHST register.
Note on initializing the MTC: As shown in Table
21 all the MTIM timer registers are in read-write
mode until the MTC clock is enabled (with the
MOE and DAC bits). This allows the timer, prescaler and compare registers to be properly initialized
for start-up.
In sensorless mode, the motor has to be started in
switched mode until a BEMF voltage is present on
the inputs. This means the prescaler ST[3:0] bits
and MCOMP register have to be modified by software. When running the ST[3:0] bits can only be
incremented/decremented, so the initial value is
very important.
When starting directly in autoswitched mode (in
sensor mode for example), write an appropriate
value in the MZREG and MZPRV register to perform a step calculation as soon as the clock is enabled.
57/132
ST72141K
MOTOR CONTROLLER (Cont’d)
The Figure 36 gives the step ratio register value
(left axis) and the number of BEMF sampling during one electrical step with the corresponding accuracy on the measure (right axis) as a function of
the mechanical frequency.
For a given prescaler value (step ratio register) the
mechanical frequency can vary between two fixed
values shown on the graph as the segment ends.
In autoswitched mode, this register is automatically incremented/decremented when the step frequency goes out of this segment.
At fcpu=4MHz, the range covered by the Step Ratio mechanism goes from 2.39 to 235000 (pole
pair x rpm) with a minimum accuracy of 1.2% on
the step period.
To read the number of samples for Zn within one
step (right Y axis), select the mechanical frequency on the X axis and the sampling frequency curve
used for BEMF detection (PWM frequency or
measurment window frequency). For example, for
N.Frpm = 15,000 and a sampling frequency of
20kHz, there are approximately 10 samples in one
step and there is a 10% error rate on the measurement.
Figure 36. Step Ratio Bits decoding and accuracy results and BEMF Sampling Rate
avg Zn ~ 55h ± 1.2%
avg Zn ~ 7Fh ± 0.6%
ST[3:0]
Step Ratio (Decimal)
avg Zn ~ FFh ± 0.4%
BEMF
samples
0
∆Zn/Zn
1 100%
1
2
Fn+1 = 2.Fn
3
4
200 Hz
avg Zn ~ 55h ± 1.2%
20 kHz
5
3.Fn+1 = 6.Fn
6
avg Zn ~ 7Fh ± 0.6%
7
2
3.Fn
8
50%
Fn
avg Zn ~ FFh ± 0.4%
9
10
4
11
12
10
10%
13
0%
14
15
Fstep = 6.N.Frpm = N.F / 10 ⇔ N.F = 10.Fstep
Fstep: Electrical step frequency
N: Pole pair number
58/132
157000
235000
78400
118000
39200
58800
19600
29400
9800
14700
4900
7350
2450
3680
1230
1840
614
920
306
460
153
230
76.6
115
38.3
57.4
19.1
28.7
9.57
14.4
4.79
7.18
2.39
1
N.Frpm
ST72141K
MOTOR CONTROLLER (Cont’d)
Table 20. Step Frequency/Period Range
Step Ratio Bits
ST[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Maximum
Step Frequency
23.5 kHz
11.7 kHz
5.88 kHz
2.94 kHz
1.47 kHz
735 Hz
367 Hz
183 Hz
91.9 Hz
45.9 Hz
22.9 Hz
11.4 Hz
5.74 Hz
2.87 Hz
1.43 Hz
0.718 Hz
Minimum
Step Frequency
7.85 kHz
3.93 kHz
1.96 kHz
980 Hz
490 Hz
245 Hz
123 Hz
61.3 Hz
30.7 Hz
15.4 Hz
7.66 Hz
3.83 Hz
1.92 Hz
0.958 Hz
0.479 Hz
0.240 Hz
Minimum
Step Period
42.5 µs
85 µs
170 µs
340 µs
680 µs
1.36 ms
2.72 ms
5.44 ms
10.9 ms
21.8 ms
43.6 ms
87 ms
174 ms
349 ms
697 ms
1.40 s
Maximum
Step Period
127.5 µs
255 µs
510 µs
1.02 ms
2.04 ms
4.08 ms
8.16 ms
16.32 ms
32.6 ms
65.2 ms
130 ms
261 ms
522 ms
1.04 s
2.08 s
4.17 s
Table 21. Modes of Accessing MTIM Timer-Related Registers
RST bit
0
0
State of MCRA Register Bits
SWA bit
MOE bit
Mode
0
0
0
1
Configuration Mode
Switched Mode
0
1
0
Emergency Stop
0
1
1
Autoswitched Mode
Access to MTIM Timer Related Registers
Read Only Access
Read / Write Access
MTIM, MZPRV, MZREG, MCOMP,
MDREG, ST[3:0]
MCOMP, MDREG,
MTIM, MZPRV,
MZREG, ST[3:0]
MTIM, MZPRV,
MZREG, MCOMP,
ST[3:0]
RMI bit of MISR:
0: No action
1: Decrement ST[3:0]
RPI bit of MISR:
0: No action
1: Increment ST[3:0]
MTIM, MZPRV, MZREG, MCOMP,
MDREG, ST[3:0]
MDREG,RMI, RPI bit of MISR:
Set by hardware, (increment ST[3:0])
Cleared by software
59/132
ST72141K
MOTOR CONTROLLER (Cont’d)
8.1.4.3 PWM Manager
The PWM manager controls the motor via the six
output channels in voltage mode or current mode
depending on the V0C1 bit in the MCRA register.
A block diagram of this part is given in Figure 37.
Voltage Mode
In Voltage mode (V0C1 bit = ”0”), the PWM is generated by the 16-bit A Timer.
Its duty cycle is programmed by software (refer to
the chapter on the 16-bit Timer) as required by the
application (speed regulation for example).
The current comparator is used for safety purposes as a current limitation. For this feature, the detected current must be present on the MCCFI pin
and the current limitation must be present on pin
OCP1A. This current limitation is fixed by a voltage
reference depending on the maximum current acceptable for the motor. This current limitation is
generated with the V DD voltage by means of an
external divider but can also be adjusted with an
external reference voltage (≤ 3.7 V). The external
components are adjusted by the user depending
on the application needs. In Voltage mode, it is
mandatory to set a current limitation.
In sensorless mode the BEMF zero crossing is
done during the PWM off time.
The PWM signal is directed to the channel manager that connects it to the programmed outputs
(See Figure 39).
Current Mode
In current mode, the PWM output signal is generated by a combination of the output of the measurement window generator (see Figure 38) and
the output of the current comparator, and is directed to the output channel manager as well (Figure
39).
The current reference is provided to the comparator by the PWM output of the 16-bit Timer (0.25%
accuracy), filtered through a RC filter (external capacitor on pin OCP1A and an internal voltage divider 30K and 70K).
The detected current input must be present on the
MCCFI pin.
To avoid spurious commutations due to parasitic
noise after switching on the PWM, a 2.5-µs filter
can be applied on the comparator output by setting the CFF bit in the MCRB register.
The On state of the resulting PWM starts at the
end of the measurement window (rising edge),
and ends either at the beginning of the next measurement window (falling edge), or when the current level is reached.
Figure 37. Current Feedback
16-bit Timer - PWM
MCRA
Register
MCRA Register
V0C1 bit
(V)
CFF bit
R1
(I)
R2
Sampling frequency
VDD
R1ext (I) MCCFI
OCP1A
(V) C
EXT
R2ext
To Phase State
Control
+
VCREF
-
Common Mode = VDD - (1,4...1,0)V
VCREF MAX = VDD - 1,3 V
Power down mode
60/132
2.5-µs Filter
LEGEND:
(I): Current mode
(V): Voltage mode
ST72141K
MOTOR CONTROLLER (Cont’d)
The measurement window frequency can be programmed between 195Hz and 25KHz by the
means of the SA[3:0] bits in the MPRSR register.
In sensorless mode this measurement window can
be used to detect either End of Demagnetization
or BEMF zero crossing events. Its width can be
defined between 5µs and 30µs in sensorless
mode by the OT[1:0] bits in the MPOL register. In
sensor mode (SR=1) this off time is fixed at
1.25µs.
Table 22. Off-Time Table
OT1
bit
OT0
bit
0
0
1
1
0
1
0
1
Off-Time
Sensorless Mode
(SR bit=0)
5 µs
10 µs
15 µs
30 µs
Off-Time
Sensor Mode
(SR bit =1)
1.25 µs
Table 23. Sampling Frequency Selection
SA3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SA2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SA1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SA0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Sampling Frequency
25.0 KHz
20.0 KHz
18.1 KHz
15.4 KHz
12.5 KHz
10.0 KHz
6.25 KHz
3.13 KHz
1.56 KHz
1.25 KHz
1.14 KHz
961 Hz
781 Hz
625 Hz
390 Hz
195 Hz
Figure 38. Sampling clock generation block
MPRSR Register
SA[3:0] bits
4
4 MHz1
Frequency logic
R
Off-Time logic
S
Q
Tsampling
Toff
2
OT[1:0] bits
MPOL Register
(1) The MTC controller input frequency must always be 4 MHz,
whatever the crystal frequency is. The appropriate internal
frequency can be selected in the Miscellaneous register.
61/132
ST72141K
MOTOR CONTROLLER (Cont’d)
8.1.4.4 Channel Manager
The channel manager consists of:
– A Phase State register with preload and polarity
function
– A multiplexer to direct the PWM to the odd and/
or even channel group
– A tristate buffer asynchronously driven by an
emergency input.
The block diagram is shown in Figure 39.
MPHST Phase State Register
A preload register enables software to asynchronously update (during the previous commutation
interrupt routine for example) the channel configuration for the next step: the OO[5:0] bits in the
MPHST register are copied to the Phase register
on a C event.
Table 24. Output State
OP[5:0] bit
0
0
1
1
OO[5:0] bit
0
1
0
1
MCO[5:0] Pin
1 (OFF)
0-(PWM allowed)
0 (OFF)
1-(PWM allowed)
Figure 39. Channel Manager Block Diagram
MCRA Register
Notes:
V0C1 bit
Updated/Shifted on R
Reg
16-bit Timer PWM
16-bit timer PWM
V
V
I
V
S Q
Sampling frequency
I
I
Current comparator
output
2.5-µs
Filter
MCRA Register
Updated with Regn+1 on C
Regn
Current Mode
Voltage Mode
events:
C Commutation
Z BEFM Zero-crossing
DS,H End Of Demagnetization
E Emergency Stop
R+/- Ratio Updated (+1 or -1)
O Multiplier Overflow
R
CFF bit
1
Branch taken after C event
2
Branch taken after D event
MCRA Register
DAC bit
MCRA Register
C
SR bit
MPHST Register
OO bits*
Phasen Register*
6
MPAR Register
OE[5:0] bits
Channel [5:0]
x6
6
x6
* = Preload register, changes taken into account at next C event.
MCO0
MCO2
MCO4
MCO3
MCO5
1
MCO1
NMCES
MRCA Register
MOE bit
MCRB Register
OS[2:0] bits*
6
MPOL Register
OP[5:0] bits
62/132
3
ST72141K
MOTOR CONTROLLER (Cont’d)
Direct access to the phase register is also possible
when the DAC bit in the MCRA register is set.
Table 25. DAC and MOE Bit Meaning
MOE bit
DAC bit
0
x
1
0
1
1
Effect on
Effect on MTIM
Output
Timer
High Z
Clock disabled
Standard runStandard running mode
ning mode
MPHST value
same as MPOL Clock disabled
value
The polarity register is used to match the polarity
of the power drivers keeping the same control logic and software. If one of the OPx bits in the MPOL
register is set, this means the switch x is ON when
MCOx is VDD.
Each output status depends also on the momentary state of the PWM, its group (odd or even), and
the peripheral state.
PWM Features
The outputs can be split in two PWM groups in order to differentiate the high side and the low side
switches. This output property can be programmed using the OE[5:0] bits in the MPAR register
Table 26. Meaning of the OE[5:0] Bits
OE[5:0]
0
1
Channel group
Even channel
Odd channel
The multiplexer directs the PWM to the upper
channel, the lower channel or both of them alternatively or simultaneously according to the peripheral state.
This means that the PWM can affect any of the upper or lower channels allowing the selection of the
most appropriate reference potential when freewheeling the motor in order to:
– Improve system efficiency
– Speed up the demagnetization phase
– Enable Back EMF zero crossing detection.
The OS[2:0] bits in the MCRB register allow the
PWM configuration to be configured for each case
as shown in Figure 41, Figure 42 and Figure 40.
This configuration depends also on the current/
voltage mode (V0C1 bit in the MCRA register) because the OS[2:0] have not the same meaning in
voltage mode and in current mode.
During demagnetization, the OS2 bit is used to
control PWM mode, and it is latched in a preload
register so it can be modified when a commutation
event occurs.
The OS[1:0] bits are used to control the PWM between the D and C events.
Warning: In Voltage Mode the OS[2:0] bits have a
special configuration value: OS[2:0] = 010.
In this mode, there is NO current limitation and NO
PWM applied to active outputs. The active outputs
are always at 100% whether in demagnetization,
or normal mode.
Note about demagnetization speed-up: during
demagnetization the voltage on the winding has to
be as high as possible in order to reduce the demagnetization time. Software can apply a different
PWM configuration on the outputs between the C
and D events, to force the free wheeling on the appropriate diodes to maximize the demagnetization
voltage.
Emergency Feature
When the NMCES pin goes low
– The tristate output buffer is put in HiZ asynchronously
– The MOE bit in the MCRA register is reset
– An interrupt request is sent to the CPU if the EIM
bit in the MIMR register is set
This bit can be connected to an alarm signal from
the drivers, thermal sensor or any other security
component.
This feature functions even if the MCU oscillator is
off.
63/132
ST72141K
MOTOR CONTROLLER (Cont’d)
Figure 40. Step Behaviour of one Output Channel MCO[n] in Voltage Mode
(Voltage Mode without polarity effect)
OS2
0
1
X
OS2
OS1
OS0
xxx
001 0 Even
1 Odd
On (1)
Voltage (V0C1=0)
0 Even
010 1
Odd
!
64/132
PWM behaviour after D
On Even Channels
On Odd Channels
Alternate Odd/Even
On all active Channels
Even
011 0
1 Odd
100 0
1
Even
Odd
101 0
1 Even
Even
Odd
Odd
110 0
1
Even
Odd
0
1
Even
Odd
WARNING: OS[2:0] = 010 has NO current regulation!
C
D
C
Demagnetization
1
0
000 0 Even
1 Odd
111
OS[1:0]
00
01
10
11
Step
X
t ]
en
Ev E[1:0
O 0]
[2:
O S :0 ]
[5
OO de
Mo
Off (0)
PWM behaviour before D
Not Alternate
Alternate
ST72141K
MOTOR CONTROLLER (Cont’d)
Figure 41. Step Behaviour of one Output Channel MCO[n] in Current / Sensorless Mode
(Current Mode without polarity effect, sensorless mode: SR=0)
OS2
0
1
X
Odd (1)
On (1)
Even (0)
Off (0)
PWM behaviour after D
On Even Channels
On Odd Channels
Alternate Odd/Even
On all active Channels
D
C
Step
C
t
en
]
Ev [1:0
OE 0]
[5:
OO e
d
Mo
Current (V0C1=1)
OS[1:0]
00
01
10
11
PWM behaviour before D
On Even Channels
On Odd Channels
Demagnetization
x
0
1
1
0
1
0
xx
1
0
00
11
Toff
10
01
1
0
1
0
01
11
10
00
Toff
1
0
xx
x
OS0
OS1
OS2
Figure 42. Step Behaviour of one Output Channel MCO[n] in Current / Sensor Mode
OS2
-
X
Odd (1)
On (1)
Even (0)
Off (0)
Step
C
C
t
e n :0 ]
Ev
5
[
OE :0]
[5
OO de
Mo
Current (V0C1=1)
(Current Mode without polarity effect, sensor mode: SR=1)
OS[1:0]
Not used
PWM behaviour after D
00
On Even Channels
01
On Odd Channels
10
Alternate Odd/Even
11
On all active Channels
xx
1
0
00
11
1.25us
10
01
01
11
10
00
1.25us
xx
OS1
OS0
In sensor mode, there is no demagnetisation event and the PWM behaviour is the
same for the complete step time.
65/132
ST72141K
MOTOR CONTROLLER (Cont’d)
8.1.5 Low Power Modes
Before executing a HALT or WFI instruction, software must stop the motor, and may choose to put
the outputs in high impedance.
Mode
WAIT
HALT
66/132
Description
No effect on MTC interface.
MTC interrupts exit from Wait mode.
MTC registers are frozen.
In Halt mode, the MTC interface is inactive. The MTC interface becomes
operational again when the MCU is
woken up by an interrupt with “exit
from Halt mode” capability.
8.1.6 Interrupts
Interrupt Event
Ratio increment
Ratio decrement
Multiplier overflow
Emergency Stop
BEMF Zero-Crossing
End of Demagnetization
Commutation
Enable Exit Exit
Event
Control from from
Flag
Bit
Wait Halt
RPI
Yes No
RIM
RMI
Yes No
OI
OIM
Yes No
EI
EIM
Yes No
ZI
ZIM
Yes No
DI
DIM
Yes No
CI
CIM
Yes No
The MTC interrupt events are connected to the
three interrupt vectors (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the I-bit in the CC
register is reset (RIM instruction).
ST72141K
MOTOR CONTROLLER (Cont’d)
8.1.7 Register Description
TIMER COUNTER REGISTER (MTIM)
Read/Write
Reset Value: 0000 0000 (00h)
DEMAGNETIZATION REGISTER (MDREG)
Read/Write
Reset Value: 0000 0000 (00h)
7
7
T7
0
T6
T5
T4
T3
T2
T1
DN7
0
DN6
DN5
DN4
DN3
DN2
DN1
DN0
T0
Bits 7:0 = T[7:0]: MTIM Counter Value.
These bits contain the current value of the 8-bit up
counter.
Bits 7:0 = DN[7:0]: D Value.
These bits contain the compare value for software
demagnetization (DN) and the captured value for
hardware demagnetization (DH).
CAPTURE Z n-1 REGISTER (MZPRV)
Read/Write
Reset Value: 0000 0000 (00h)
AN WEIGHT REGISTER (MWGHT)
Read/Write
Reset Value: 0000 0000 (00h)
7
ZP7
0
ZP6
ZP5
ZP4
ZP3
ZP2
ZP1
ZP0
Bits 7:0 = ZP[7:0]: Previous Z Value.
These bits contain the previous captured BEMF
value (ZN-1).
7
0
ZC6
ZC5
ZC4
ZC3
ZC2
ZC1
ZC0
Bits 7:0 = ZC[7:0]: Current Z Value.
These bits contain the current captured BEMF value (Z N).
COMPARE Cn+1 REGISTER (MCOMP)
Read/Write
Reset Value: 0000 0000 (00h)
7
DC7
DC5
DC4
DC3
DC2
AN6
DC1
AN5
AN4
AN3
AN2
AN1
AN0
Bits 7:0 = AN[7:0]: A Weight Value.
These bits contain the AN weight value for the multiplier. In autoswitched mode the MCOMP register
is automatically loaded with:
or
ZN-1 x MWGHT
32(d)
(*)
when a Z event occurs.
(*) depending on the DCB bit in the MCRA register.
PRESCALER & SAMPLING REGISTER
(MPRSR)
Read/Write
Reset Value: 0000 0000 (00h)
7
SA3
0
DC6
AN7
0
Zn x MWGHT
32(d)
CAPTURE Z n REGISTER (MZREG)
Read/Write
Reset Value: 0000 0000 (00h)
ZC7
7
0
SA2
SA1
SA0
ST3
ST2
ST1
ST0
Bits 7:4 = SA[3:0]: Sampling Ratio.
These bits contain the sampling ratio value for current mode. Refer to Table 23.
DC0
Bits 7:0 = DC[7:0]: Next Compare Value.
These bits contain the compare value for the next
commutation (C N+1).
Bits 3:0 = ST[3:0]: Step Ratio.
These bits contain the step ratio value. It acts as a
prescaler for the MTIM timer and is auto incremented/decremented with each R+ or R- event.
Refer to Table 20.
67/132
ST72141K
MOTOR CONTROLLER (Cont’d)
INTERRUPT MASK REGISTER (MIMR)
Read/Write (except bits 7:6)
Reset Value: 0000 0000 (00h)
7
HST
CL
RIM
OIM
EIM
ZIM
DIM
INTERRUPT STATUS REGISTER (MISR)
Read/Write
Reset Value: 0000 0000 (00h)
0
7
CIM
0
Bit 7 = HST: Hysteresis Comparator Value.
This read only bit contains the hysteresis comparator output.
0: Demagnetisation/BEMF comparator is under
VREF
1: Demagnetisation/BEMF comparator is above
VREF
Bit 6 = CL: Current Loop Comparator Value.
This read only bit contains the current loop comparator output value.
0: Current detect voltage is under VCREF
1: Current detect voltage is above VCREF
0
RPI
RMI
OI
EI
ZI
DI
CI
Bit 7 = Reserved. Forced by hardware to 0.
Bit 6 = RPI: Ratio Increment interrupt flag.
Autoswitched mode (SWA bit =0):
0: No R+ interrupt pending
1: R+ Interrupt pending
Switched mode (SWA bit =1):
0: No R+ action
1: The hardware will increment the ST[3:0] bits
when the next commutation occurs and shift all
timer registers right.
Bit 4 = OIM: Multiplier Overflow Interrupt Mask bit.
0: Multiplier Overflow interrupt disabled
1: Multiplier Overflow interrupt enabled
Bit 5 = RMI: Ratio Decrement interrupt flag.
Autoswitched mode (SWA bit =0):
0: No R- interrupt pending
1: R- Interrupt pending
Switched mode (SWA bit =1):
0: No R- action
1: The hardware will decrement the ST[3:0] bits
when the next commutation occurs and shift all
timer registers left.
Bit 3 = EIM: Emergency stop Interrupt Mask bit.
0: Emergency stop interrupt disabled
1: Emergency stop interrupt enabled
Bit 4 = OI: Multiplier Overflow interrupt flag.
0: No Multiplier Overflow interrupt pending
1: Multiplier Overflow interrupt pending
Bit 2 = ZIM: Back EMF Zero-crossing Interrupt
Mask bit.
0: BEMF Zero-crossing Interrupt disabled
1: BEMF Zero-crossing Interrupt enabled
Bit 3 = EI: Emergency stop Interrupt flag.
0: No Emergency stop interrupt pending
1: Emergency stop interrupt pending
Bit 5 = RIM: Ratio update Interrupt Mask bit.
0: Ratio update interrupts (R+ and R-) disabled
1: Ratio update interrupts (R+ and R-) enabled
Bit 1 = DIM: End of Demagnetization Interrupt
Mask bit.
0: End of Demagnetization interrupt disabled
1: End of Demagnetization interrupt enabled if the
HDM or SDM bit in the MCRB register is set
Bit 0 = CIM: Commutation Interrupt Mask bit
0: Commutation Interrupt disabled
1: Commutation Interrupt enabled
68/132
Bit 2 = ZI: BEMF Zero-crossing interrupt flag.
0: No BEMF Zero-crossing Interrupt pending
1: BEMF Zero-crossing Interrupt pending
Bit 1 = DI: End of Demagnetization interrupt flag.
0: No End of Demagnetization interrupt pending
1: End of Demagnetization interrupt pending
Bit 0 = CI: Commutation interrupt flag
0: No Commutation Interrupt pending
1: Commutation Interrupt pending
ST72141K
MOTOR CONTROLLER (Cont’d)
Table 27. Step Ratio Update
MOE SWA Clock
Read
bit bit State
0
x
Disabled
1
0
Enabled
1
Enabled
1
Ratio
Ratio
Increment
Decrement
(Slow Down) (Speed-Up)
Write the ST[3:0] value directly in the MPRSR register
Set RPI bit in Set RMI bit in
Always the MISR reg- the MISR regpossi- ister till next ister till next
commutation commutation
ble
Updated automatically according to MZREG value
CONTROL REGISTER A (MCRA)
Read/Write
Reset Value: 0000 0000 (00h)
7
MOE
0
RST
SR
DAC
V0C1
SWA
CFF
0
1
Table 29. DAC Bit Meaning
MOE DAC
bit bit
0
x
1
0
1
1
Effect on Output
High Z
Standard
running mode
MPHST register value
(depending on MPOL
register value)
Effect on MTIM
Timer
Clock disabled
Standard running
mode
Clock disabled
DCB
Bit 7 = MOE: Output Enable bit.
0: Outputs and Clocks disabled
1: Outputs and Clocks enabled
MOE bit
Bit 4 = DAC: Direct Access to phase state register.
0: No Direct Access (reset value). In this mode all
the registers with a preload register are taken
into account at the C event.
1: Direct Access enabled. In this mode, write a value in the MPHST register to access the outputs
directly. All other registers with a preload register are taken into account at the same time.
MCO[5:0] Output pin
State
Tristate
Output enabled
Bit 6 = RST: Reset MTC registers.
Software can set this bit to reset all MTC registers
without resetting the ST7.
0: No MTC register reset
1: Reset all MTC registers
Bit 5 = SR: Sensor ON/OFF.
0: Sensorless mode
1: Sensor mode
Note 1: When the MTC clock is disabled, the
MTIM counter is not reset but as in this case it is in
write access, a reset can be done by software.
Note 2: In direct access mode, only logical levels
(0 or 1) can be output on the MCOx pins. There is
no PWM signal generation in this mode.
Bit 3 = V0C1: Voltage/Current Mode
0: Voltage Mode
1: Current Mode
Bit 2 = SWA: Switched/Autoswitched Mode
0: Switched Mode
1: Autoswitched Mode
Table 30. Switched and Autoswitched Modes
SWA
bit
0
1
Commutation Type
Switched mode
Autoswitched mode
MCOMP Register
access
Read/Write
Read only
Table 28. Sensor Mode Selection
SR
bit
0
1
OS2 bit Behaviour of the output
enable
PWM
Sensors not
OS2
“Before D” behaviour & “afused
enabled
ter D” behaviour
Sensors
OS2
Only “after D” behaviour
used
disabled
Mode
Bit 1 = CFF: Current Feedback Filter
0: Current Feedback Filter disabled
1: Current Feedback Filter enabled
Bit 0 = DCB: Data Capture bit
0: Use MZPRV (ZN-1) for multiplication
1: Use MZREG (ZN) for multiplication
69/132
ST72141K
MOTOR CONTROLLER (Cont’d)
Table 32. Step Behaviour Summary
Table 31. Multiplier Result
Commutation Delay
MCOMP = MWGHT x MZPRV / 32
MCOMP = MWGHT x MZREG / 32
CONTROL REGISTER B (MCRB)
Read/Write
Reset Value: 0000 0000 (00h)
VR0
CPB*
HDM*
SDM*
OS2*
OS1
OS0
Bits 7:6 = VR[1:0]: BEMF/demagnetization Reference threshold
These bits select the VREF value as shown in the
following table.
VR1
0
0
1
1
VR0
0
1
0
1
VREF Voltage threshold
0.2V
0.6V
1.2V
2.5V
Sensor (SR=1)
VR1
0
Voltage mode(V0C1=0)
7
Bits 2:0 = OS2*,OS[1:0]: Operating output mode
Selection bits
Refer to the Step behaviour diagrams (Figure 40,
Figure 41, Figure 42) and Table 32.
These bits are used to configure the various PWM
output configurations.
Note: The OS2 bit is the only one with a preload
register.
70/132
OS
PWM after D and
OS2 PWM after C
[1:0]
before C
bit and before D
bits
On even
00
channels
On odd
Same as
01
channels
0
after D and
before C
10
Continuous
All active
11
channels
On even
00
channels
On odd
01
channels
1
Alternate
10 Alternate odd/even
All active
11
channels
On even
00
channels
On odd
01
channels
x
Unused
10 Alternate odd/even
All active
11
channels
On even
00
channels
On odd
01
On even
channels
0
Channels
10 Alternate odd/even
All active
11
channels
On even
00
channels
On odd
01
On odd
channels
1
channels
10 Alternate odd/even
11
Sensor (SR=1)
Bit 3 = SDM*: Software Demagnetization event
Mask bit
0: Software Demagnetization disabled
1: Software Demagnetization enabled
Current mode (V0C1=1)
Bit 5 = CPB*: Compare Bit for Zero-crossing detection.
0: Zero crossing detection on falling edge
1: Zero crossing detection on rising edge
Bit 4 = HDM*: Hardware Demagnetization event
Mask bit
0: Hardware Demagnetization disabled
1: Hardware Demagnetization enabled
Sensorless (SR=0)
Mode
Sensorless (SR=0)
DCB bit
0
1
00
x
Unused
01
10
11
All active
channels
On even
channels
On odd
channels
Alternate odd/even
All active
channels
Note: For more details, see Step behaviour diagrams (Figure 40, Figure 41, and Figure 42).
* Preload bits, new value taken into account at
next C event.
ST72141K
MOTOR CONTROLLER (Cont’d)
PHASE STATE REGISTER (MPHST)
Read/Write
Reset Value: 0000 0000 (00h)
1: Zero-crossing and End of Demagnetisation
have same edge
7
IS1*
0
IS0*
OO5*
OO4*
OO3*
OO2*
OO1*
OO0*
Bits 7:6 = IS[1:0]*: Input Selection bits
These bits select the input to connect to comparator as shown in the following table:
Bit 6 = REO: Read on Even or Odd channel bit
0: Read the BEMF signal during the off time on
even channels
1: Read on odd channels
Bits 5:0 = OE[5:0]: Output Parity Mode.
0: Output channel is Even
1: Output channel Odd
Table 33. Input Channel Selection
IS1
0
0
1
1
IS0
0
1
0
1
Channel selected
MCIA
MCIB
MCIC
Not Used
POLARITY REGISTER (MPOL)
Read/Write
Reset Value: 0000 0000 (00h)
7
OT1
Bits 5:0 =OO[5:0]*: Channel On/Off bits
These bits are used to switch channels on/off at
the next C event if the DAC bit =0 or directly if
DAC=1
0: Channel Off, the relevant switch is OFF, no
PWM possible
1: Channel On the relevant switch is ON, PWM is
possible.
Table 34. OO[5:0] Bit Meaning
OO[5:0]
Output Channel State
0
1
Inactive
Active
* Preload bits, new value taken into account at
next C event.
PARITY REGISTER (MPAR)
Read/Write
Reset Value: 0000 0000 (00h)
0
REO
OE5
OE4
OE3
OT0
OP5
OP4
OP3
OP2
OP1
OP0
Bits 7:6 = OT[1:0]: Off Time selection.
These bits are used to select the off time in sensorless mode as shown in the following table.
Table 35. Off-Time bit Meaning
OT1
OT0
0
0
1
1
0
1
0
1
Off-Time
Off-Time
Sensorless
Mode (SR=0)
5 µs
10 µs
15 µs
30 µs
Sensor Mode
(SR=1)
1.25 µs
Bits 5:0 = OP[5:0]: Output channel polarity.
These bits are used together with the OO[5:0] bits
in the MPHST register to control the output channels.
0: Output channel is Active Low
1: Output channel is Active High.
Table 36. Output Channel State Control
7
ZVD
0
OE2
OE1
OE0
Bit 7 = ZVD: Z vs D edge polarity.
0: Zero-crossing and End of Demagnetisation
have opposite edges
OP[5:0] bit
0
0
1
1
OO[5:0] bit
0
1
0
1
MCO[5:0] pin
1 (Off)
0 (PWM possible)
0 (Off)
1 (PWM possible)
71/132
ST72141K
MOTOR CONTROLLER (Cont’d)
Note: The CPB, HDM, SDM, OS2 bits in the
MCRB and the bits OE[5:0] are marked with *. It
means that these bits are taken into account at the
following commutation event (in normal mode) or
when a value is written in the MPHST register
when in direct access mode. For more details, refer to the description of the DAC bit in the MCRA
register. The use of a Preload register allows all
the registers to be updated at the same time.
72/132
Warning: Access to Preload registers
Special care has to be taken with Preload registers, especially when using the ST7 BSET and
BRES instructions on MTC registers.
For instance, while writing to the MPHST register,
you will write the value in the preload register.
However, while reading at the same address, you
will get the current value in the register and not the
value of the preload register.
All preload registers are loaded in the real registers at the same time. In normal mode this is done
automatically when a C event occurs, however in
direct access mode (DAC bit=1) the preload registers are loaded as soon as a value is written in the
MPHST register.
R-
1/5
8
8
O
Compare
3
set
8
n-1 n
A x B / 32
MCOMP Reg [Cn+1]
SWA bit
8
MWGHT Reg [an+1]
DCB bit
MZPRV Reg [Zn-1]
Z
ck
1 / 2Ratio
1/ 2
or
C
0
1
SWA bit
1
2
C
DS,H
Z
E
R-/+
O
DS
SDMn bit
Compare
C
Z
CP
Q D
DS,H
C
MDREG Reg [Dn]
DH
clr
1 ➘ 1/128
1 / 32
CPBn bit
or
SA3-0 &
OT1-0 bits
HDMn bit
20µs / C
or
MTIM [8-bit Up Counter]
MZREG
< 55h?
4
MZREG Reg [Zn]
Z
-1
R+
MTIM
= FFh?
ST3-0 bits
+1
4MHz
DH
SR bit
or
REO bit
20µs / C
Z
CPBn bit
MISR Reg
R
S Q
1
ZVD bit
DS,H
DS,H
(I)
(V) VCREF
V0C1 bit
MCRA Reg.
VR1-0
6
3
+
-
x6
6
OSn bits
SR bit
1
x6
16-bit Timer A used as PWM
VREF
2.5-µs / PWM
C
+
-
ISn bit
MPHSTn Reg
20µs / D
MIMR Reg
2
I
CFF bit
I
MPAR Reg
V
VCREF
MPOL Reg
V
MOE bit
Microcontroller
(V)
MCCFI
NMCES
MCO1
MCO5
MCO3
MCO4
MCO2
MCO0
Cext
OCP1A
MCIB
MCIA
MCIC
A
A
B
R2ext
R1ext
VDD
(I)
C
HV
Current Mode
Voltage Mode
Updated with Regn+1 on C
Updated/Shifted on R
Branch taken after C event
Branch taken after D event
1
2
events:
C Commutation
Z BEFM Zero-crossing
DS,H End Of Demagnetization
E Emergency Stop
R+/- Ratio Updated (+1 or -1)
O Multiplier Overflow
I
V
Regn
Reg
Notes:
Board + Motor
ST72141K
MOTOR CONTROLLER (Cont’d)
Figure 43. Detailed view of the MTC
73/132
ST72141K
MOTOR CONTROLLER (Cont’d)
Table 37. MTC Register Map and Reset Values
Address
Register
Name
7
6
5
4
3
2
1
0
0060h
MTIM
Reset Value
T7
0
T6
0
T5
0
T4
0
T3
0
T2
0
T1
0
T0
0
0061h
MZPRV
Reset Value
ZP7
0
ZP6
0
ZP5
0
ZP4
0
ZP3
0
ZP2
0
ZP1
0
ZP0
0
0062h
MZREG
Reset Value
ZC7
0
ZC6
0
ZC5
0
ZC4
0
ZC3
0
ZC2
0
ZC1
0
ZC0
0
0063h
MCOMP
Reset Value
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
0064h
MDREG
Reset Value
DN7
0
DN6
0
DN5
0
DN4
0
DN3
0
DN2
0
DN1
0
DN0
0
0065h
MWGHT
Reset Value
AN7
0
AN6
0
AN5
0
AN4
0
AN3
0
AN2
0
AN1
0
AN0
0
0066h
MPRSR
Reset Value
SA3
0
SA2
0
SA1
0
SA0
0
ST3
0
ST2
0
ST1
0
ST0
0
0067h
MIMR
Reset Value
HST
0
CL
0
RIM
0
OIM
0
EIM
0
ZIM
0
DIM
0
CIM
0
0068h
MISR
Reset Value
0
RPI
0
RMI
0
OI
0
EI
0
ZI
0
DI
0
CI
0
0069h
MCRA
Reset Value
MOE
0
RST
0
SR
0
DAC
0
V0C1
0
SWA
0
CFF
0
DCB
0
006Ah
MCRB
Reset Value
VR1
0
VR0
0
CPB
0
HDM
0
SDM
0
OS2
0
OS1
0
OS0
0
006Bh
MPHST
Reset Value
IS1
0
IS0
0
OO5
0
OO4
0
OO3
0
OO2
0
OO1
0
OO0
006Ch
MPAR
Reset Value
ZVD
0
REO
0
OE5
0
OE4
0
OE3
0
OE2
0
OE1
0
OE0
0
006Dh
MPOL
Reset Value
OT1
0
OT0
0
OP5
0
OP4
0
OP3
0
OP2
0
OP1
0
OP0
0
(Hex.)
74/132
ST72141K
8.2 WATCHDOG TIMER (WDG)
8.2.1 Introduction
The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to
abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared.
8.2.2 Main Features
■ Programmable timer (64 increments of 12288
CPU cycles)
■ Programmable reset
■ Reset (if watchdog activated) after a HALT
instruction or when the T6 bit reaches zero
■ Watchdog Reset indicated by status flag
Figure 44. Watchdog Block Diagram
RESET
WATCHDOG CONTROL REGISTER (CR)
WDGA
T6
T5
T4
T3
T2
T1
T0
7-BIT DOWNCOUNTER
fCPU
CLOCK DIVIDER
÷ 12288
75/132
ST72141K
WATCHDOG TIMER (Cont’d)
8.2.3 Functional Description
The counter value stored in the CR register (bits
T6:T0), is decremented every 12288 machine cycles, and the length of the timeout period can be
programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T6:T0) rolls over
from 40h to 3Fh (T6 become cleared), it initiates a
reset cycle pulling low the reset pin for typically
500ns.
The application program must write in the CR register at regular intervals during normal operation to
prevent an MCU reset. The value to be stored in
the CR register must be between FFh and C0h
(see Table 38 . Watchdog Timing (fCPU = 8
MHz)):
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an immediate reset
– The T5:T0 bits contain the number of increments
which represents the time delay before the
watchdog produces a reset.
Table 38. Watchdog Timing (fCPU = 8 MHz)
Max
Min
CR Register
initial value
FFh
C0h
WDG timeout period
(ms)
98.304
1.536
8.2.6 Register Description
CONTROL REGISTER (CR)
Read /Write
Reset Value: 0111 1111 (7Fh)
7
WDGA
T6
T5
T4
T3
T2
T1
Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared) if WDGA=1.
STATUS REGISTER (SR)
Read /Write
Reset Value*: xxxx xxxx0
7
0
-
-
-
-
-
-
WDOGF
Bit 0 = WDOGF Watchdog flag.
This bit is set by a watchdog reset and cleared by
software or a power on/off reset. This bit is useful
for distinguishing power/on off or external reset
and watchdog reset.
0: No Watchdog reset occurred
1: Watchdog reset occurred
8.2.4 Low Power Modes
Mode
WAIT
HALT
Description
No effect on Watchdog.
Immediate reset generation as soon as
the HALT instruction is executed if the
Watchdog is activated (WDGA bit is
set).
8.2.5 Interrupts
None.
76/132
T0
Bit 7= WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
-
Notes: Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except
by a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared).
If the watchdog is activated, the HALT instruction
will generate a Reset.
0
* Only by software and power on/off reset
ST72141K
WATCHDOG TIMER (Cond’t)
Table 39. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
0024h
WDGCR
Reset Value
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
0025h
WDGSR
Reset Value
0
0
0
0
0
0
0
WDOGF
0
77/132
ST72141K
8.3 16-BIT TIMER
8.3.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
It may be used for a variety of purposes, including
measuring the pulse lengths of up to two input signals ( input capture) or generating up to two output
waveforms (output compare and PWM ).
Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU
clock prescaler.
Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not
share any resources. They are synchronized after
a MCU reset as long as the timer clock frequencies are not modified.
This description covers one or two 16-bit timers. In
ST7 devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).
8.3.2 Main Features
■ Programmable prescaler: fCPU divided by 2, 4 or 8.
■ Overflow status flag and maskable interrupt
■ External clock input (must be at least 4 times
slower than the CPU clock speed) with the choice
of active edge
■ Output compare functions with:
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■ Input capture functions with:
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■ Pulse Width Modulation mode (PWM)
■ One Pulse mode
■ 5 alternate functions on I/O ports (ICAP1, ICAP2,
OCMP1, OCMP2, EXTCLK)*
The Block Diagram is shown in Figure 45.
*Note: Some timer pins may not be available (not
bonded) in some ST7 devices. Refer to the device
pin out description.
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.
78/132
8.3.3 Functional Description
8.3.3.1 Counter
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high & low.
Counter Register (CR):
– Counter High Register (CHR) is the most significant byte (MS Byte).
– Counter Low Register (CLR) is the least significant byte (LS Byte).
Alternate Counter Register (ACR)
– Alternate Counter High Register (ACHR) is the
most significant byte (MS Byte).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LS Byte).
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register (SR).
(See note at the end of paragraph titled 16-bit read
sequence).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit timer). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 40 Clock
Control Bits. The value in the counter register repeats every 131072, 262144 or 524288 CPU clock
cycles depending on the CC[1:0] bits.
The timer frequency can be fCPU/2, fCPU/4, fCPU/8
or an external frequency.
ST72141K
16-BIT TIMER (Cont’d)
Figure 45. Timer Block Diagram
ST7 INTERNAL BUS
fCPU
MCU-PERIPHERAL INTERFACE
8 low
8
8
8
low
8
high
8
low
8
high
EXEDG
8
low
high
8
high
8-bit
buffer
low
8 high
16
1/2
1/4
1/8
OUTPUT
COMPARE
REGISTER
2
OUTPUT
COMPARE
REGISTER
1
COUNTER
REGISTER
ALTERNATE
COUNTER
REGISTER
EXTCLK
pin
INPUT
CAPTURE
REGISTER
1
INPUT
CAPTURE
REGISTER
2
16
16
16
CC[1:0]
TIMER INTERNAL BUS
16 16
OVERFLOW
DETECT
CIRCUIT
OUTPUT COMPARE
CIRCUIT
6
ICF1 OCF1 TOF ICF2 OCF2 0
0
EDGE DETECT
CIRCUIT1
ICAP1
pin
EDGE DETECT
CIRCUIT2
ICAP2
pin
LATCH1
OCMP1
pin
LATCH2
OCMP2
pin
0
(Status Register) SR
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
(Control Register 1) CR1
OC1E OC2E OPM PWM
CC1
CC0 IEDG2 EXEDG
(Control Register 2) CR2
(See note)
TIMER INTERRUPT
Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See device Interrupt Vector Table)
79/132
ST72141K
16-BIT TIMER (Cont’d)
16-bit Read Sequence: (from either the Counter
Register or the Alternate Counter Register).
Beginning of the sequence
At t0
Read
MS Byte
LS Byte
is buffered
Other
instructions
Read
At t0 +∆t LS Byte
Returns the buffered
LS Byte value at t0
Sequence completed
The user must read the MS Byte first, then the LS
Byte value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS Byte several times.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they return the LS Byte of the count value at the time of
the read.
Whatever the timer mode used (input capture, output compare, One Pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt remains pending to be issued as soon as they are
both true.
80/132
Clearing the overflow interrupt request is done in
two steps:
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Note: The TOF bit is not cleared by accessing the
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
8.3.3.2 External Clock
The external clock (where available) is selected if
CC0=1 and CC1=1 in the CR2 register.
The status of the EXEDG bit in the CR2 register
determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter.
The counter is synchronised with the falling edge
of the internal CPU clock.
A minimum of four falling edges of the CPU clock
must occur between two consecutive active edges
of the external clock; thus the external clock frequency must be less than a quarter of the CPU
clock frequency.
ST72141K
16-BIT TIMER (Cont’d)
Figure 46. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000
COUNTER REGISTER
0001
0002
0003
TIMER OVERFLOW FLAG (TOF)
Figure 47. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
FFFC
FFFD
0000
0001
TIMER OVERFLOW FLAG (TOF)
Figure 48. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
FFFC
FFFD
0000
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high. When it is low, the MCU is running.
81/132
ST72141K
16-BIT TIMER (Cont’d)
8.3.3.3 Input Capture
In this section, the index, i, may be 1 or 2 because
there are 2 input capture functions in the 16-bit
timer.
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free running counter after a transition is detected by the
ICAP i pin (see figure 5).
ICiR
MS Byte
ICiHR
LS Byte
ICiLR
The ICiR register is a read-only register.
The active transition is software programmable
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
counter: (fCPU/CC[1:0]).
Procedure:
To use the input capture function, select the following in the CR2 register:
– Select the timer clock (CC[1:0]) (see Table 40
Clock Control Bits).
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as a floating input or input
with pull-up without interrupt if this configuration
is available).
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or the ICAP2 pin
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as a floating input or input
with pull-up without interrupt if this configuration
is available).
82/132
When an input capture occurs:
– The ICFi bit is set.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 50).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both
conditions become true.
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
Notes:
1. After reading the ICiHR register, the transfer of
input capture data is inhibited and ICFi will
never be set until the ICiLR register is also
read.
2. The ICiR register contains the free running
counter value which corresponds to the most
recent input capture.
3. The 2 input capture functions can be used
together even if the timer also uses the 2 output
compare functions.
4. In One Pulse mode and PWM mode only the
input capture 2 function can be used.
5. The alternate inputs (ICAP1 & ICAP2) are
always directly connected to the timer. So any
transitions on these pins activate the input capture function.
Moreover if one of the ICAPi pin is configured
as an input and the second one as an output,
an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set.
This can be avoided if the input capture function i is disabled by reading the IC iHR (see note
1).
6. The TOF bit can be used with an interrupt in
order to measure events that exceed the timer
range (FFFFh).
ST72141K
16-BIT TIMER (Cont’d)
Figure 49. Input Capture Block Diagram
ICAP1
pin
ICAP2
pin
(Control Register 1) CR1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
IEDG1
(Status Register) SR
IC1R Register
IC2R Register
ICF1
ICF2
0
0
0
(Control Register 2) CR2
16-BIT
16-BIT FREE RUNNING
CC1
CC0
IEDG2
COUNTER
Figure 50. Input Capture Timing Diagram
TIMER CLOCK
COUNTER REGISTER
FF01
FF02
FF03
ICAPi PIN
ICAPi FLAG
ICAPi REGISTER
FF03
Note: Active edge is rising edge.
83/132
ST72141K
16-BIT TIMER (Cont’d)
8.3.3.4 Output Compare
In this section, the index, i, may be 1 or 2 because
there are 2 output compare functions in the 16-bit
timer.
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
When a match is found between the Output Compare register and the free running counter, the output compare function:
– Assigns pins with a programmable value if the
OCiE bit is set
– Sets a flag in the status register
– Generates an interrupt if enabled
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
OCiR
MS Byte
OCiHR
LS Byte
OCiLR
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
Timing resolution is one count of the free running
counter: (fCPU/CC[1:0]).
Procedure:
To use the output compare function, select the following in the CR2 register:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
signal.
– Select the timer clock (CC[1:0]) (see Table 40
Clock Control Bits).
And select the following in the CR1 register:
– Select the OLVLi bit to applied to the OCMP i pins
after the match occurs.
– Set the OCIE bit to generate an interrupt if it is
needed.
When a match is found between OCRi register
and CR register:
– OCFi bit is set.
84/132
– The OCMP i pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset).
– A timer interrupt is generated if the OCIE bit is
set in the CR1 register and the I bit is cleared in
the CC register (CC).
The OCiR register value required for a specific timing application can be calculated using the following formula:
∆ OCiR =
∆t * fCPU
PRESC
Where:
∆t
= Output compare period (in seconds)
fCPU
= CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 40
Clock Control Bits)
If the timer clock is an external clock, the formula
is:
∆ OCiR = ∆t * fEXT
Where:
∆t
= Output compare period (in seconds)
fEXT
= External timer clock frequency (in hertz)
Clearing the output compare interrupt request (i.e.
clearing the OCFi bit) is done by:
1. Reading the SR register while the OCFi bit is
set.
2. An access (read or write) to the OCiLR register.
The following procedure is recommended to prevent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
– Write to the OCiHR register (further compares
are inhibited).
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
ST72141K
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OCiHR register, the output compare function is inhibited
until the OCiLR register is also written.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
3. When the timer clock is fCPU/2, OCFi and
OCMPi are set while the counter value equals
the OCiR register value (see Figure 52). This
behaviour is the same in OPM or PWM mode.
When the timer clock is fCPU/4, fCPU/8 or in
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR register value plus 1 (see Figure 53).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each successful comparison in order to control an output
waveform or establish a new elapsed timeout.
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
FOLVLi bits have no effect in either One-Pulse
mode or PWM mode.
Figure 51. Output Compare Block Diagram
16 BIT FREE RUNNING
COUNTER
OC1E OC2E
CC1
CC0
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
16-bit
OCIE
FOLV2 FOLV1 OLVL2
OLVL1
16-bit
Latch
1
Latch
2
OC1R Register
OCF1
OCF2
0
0
OCMP1
Pin
OCMP2
Pin
0
OC2R Register
(Status Register) SR
85/132
ST72141K
16-BIT TIMER (Cont’d)
Figure 52. Output Compare Timing Diagram, fTIMER =fCPU/2
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
2ECF 2ED0
2ED1 2ED2 2ED3 2ED4
OUTPUT COMPARE REGISTER i (OCRi)
2ED3
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
Figure 53. Output Compare Timing Diagram, fTIMER =fCPU/4
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCRi)
COMPARE REGISTER i LATCH
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
86/132
2ECF 2ED0
2ED1 2ED2 2ED3 2ED4
2ED3
ST72141K
16-BIT TIMER (Cont’d)
8.3.3.5 One Pulse Mode
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
The One Pulse mode uses the Input Capture1
function and the Output Compare1 function.
Procedure:
To use One Pulse mode:
1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column).
2. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse.
– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).
3. Select the following in the CR2 register:
– Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function.
– Set the OPM bit.
– Select the timer clock CC[1:0] (see Table 40
Clock Control Bits).
One Pulse mode cycle
When
event occurs
on ICAP1
OCMP1 = OLVL2
Counter is reset
to FFFCh
ICF1 bit is set
When
Counter
= OC1R
OCMP1 = OLVL1
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and the OLVL2 bit is
loaded on the OCMP1 pin, the ICF1 bit is set and
the value FFFDh is loaded in the IC1R register.
Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The OC1R register value required for a specific
timing application can be calculated using the following formula:
OCiR Value =
t * fCPU
-5
PRESC
Where:
t
= Pulse period (in seconds)
fCPU = CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 40
Clock Control Bits)
If the timer clock is an external clock the formula is:
OCiR = t * fEXT -5
Where:
t
= Pulse period (in seconds)
fEXT
= External timer clock frequency (in hertz)
When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin (see Figure 54).
Notes:
1. The OCF1 bit cannot be set by hardware in
One Pulse mode but the OCF2 bit can generate
an Output Compare interrupt.
2. When the Pulse Width Modulation (PWM) and
One Pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
3. If OLVL1=OLVL2 a continuous signal will be
seen on the OCMP1 pin.
4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
5. When One Pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate that a period of
time has elapsed but cannot generate an output
waveform because the OLVL2 level is dedicated to One Pulse mode.
87/132
ST72141K
16-BIT TIMER (Cont’d)
Figure 54. One Pulse Mode Timing Example
COUNTER
FFFC FFFD FFFE
2ED0 2ED1 2ED2
FFFC FFFD
2ED3
ICAP1
OLVL2
OCMP1
OLVL1
OLVL2
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 55. Pulse Width Modulation Mode Timing Example
COUNTER 34E2 FFFC FFFD FFFE
2ED0 2ED1 2ED2
OLVL2
OCMP1
compare2
OLVL1
compare1
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
88/132
34E2
FFFC
OLVL2
compare2
ST72141K
16-BIT TIMER (Cont’d)
8.3.3.6 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
The Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R
register, and so these functions cannot be used
when the PWM mode is activated.
Procedure
To use Pulse Width Modulation mode:
1. Load the OC2R register with the value corresponding to the period of the signal using the
formula in the opposite column.
2. Load the OC1R register with the value corresponding to the period of the pulse if OLVL1=0
and OLVL2=1, using the formula in the opposite column.
3. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful
comparison with OC1R register.
– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful
comparison with OC2R register.
4. Select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see Table 40
Clock Control Bits).
If OLVL1=1 and OLVL2=0, the length of the positive pulse is the difference between the OC2R and
OC1R registers.
If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.
Pulse Width Modulation cycle
When
Counter
= OC1R
When
Counter
= OC2R
OCMP1 = OLVL1
The OCiR register value required for a specific timing application can be calculated using the following formula:
OCiR Value =
t * fCPU
-5
PRESC
Where:
t
= Signal or pulse period (in seconds)
fCPU = CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 40 Clock
Control Bits)
If the timer clock is an external clock the formula is:
OCiR = t * fEXT -5
Where:
t
= Signal or pulse period (in seconds)
fEXT
= External timer clock frequency (in hertz)
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 55)
Notes:
1. After a write instruction to the OCiHR register,
the output compare function is inhibited until the
OCiLR register is also written.
2. The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode, therefore the Output
Compare interrupt is inhibited.
3. The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
4. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is disconnected from the timer. The ICAP2 pin can be
used to perform input capture (ICF2 can be set
and IC2R can be loaded) but the user must
take care that the counter is reset after each
period and ICF1 can also generate an interrupt
if ICIE is set.
5. When the Pulse Width Modulation (PWM) and
One Pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
OCMP1 = OLVL2
Counter is reset
to FFFCh
ICF1 bit is set
89/132
ST72141K
16-BIT TIMER (Cont’d)
8.3.4 Low Power Modes
Mode
WAIT
HALT
Description
No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
8.3.5 Interrupts
Event
Flag
Interrupt Event
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
ICF1
ICF2
OCF1
OCF2
TOF
Enable
Control
Bit
ICIE
OCIE
TOIE
Exit
from
Wait
Yes
Yes
Yes
Yes
Yes
Exit
from
Halt
No
No
No
No
No
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
8.3.6 Summary of Timer modes
MODES
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One Pulse mode
PWM Mode
1)
Input Capture 1
Yes
Yes
No
No
AVAILABLE RESOURCES
Input Capture 2
Output Compare 1 Output Compare 2
Yes
Yes
Yes
Yes
Yes
Yes
1)
No
Partially 2)
Not Recommended
3)
Not Recommended
No
No
See note 4 in Section 8.3.3.5 One Pulse Mode
See note 5 in Section 8.3.3.5 One Pulse Mode
3)
See note 4 in Section 8.3.3.6 Pulse Width Modulation Mode
2)
90/132
ST72141K
16-BIT TIMER (Cont’d)
8.3.7 Register Description
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the alternate counter.
CONTROL REGISTER 1 (CR1)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1: Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
1: Forces OLVL1 to be copied to the OCMP1 pin, if
the OC1E bit is set and even if there is no successful comparison.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse mode
and Pulse Width Modulation mode.
Bit 1 = IEDG1 Input Edge 1.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
91/132
ST72141K
16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 7 = OC1E Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E
bit, the internal Output Compare 1 function of the
timer remains active.
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
Bit 6 = OC2E Output Compare 2 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit,
the internal Output Compare 2 function of the timer
remains active.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Bit 5 = OPM One Pulse mode.
0: One Pulse mode is not active.
1: One Pulse mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
92/132
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R register.
Bits 3:2 = CC[1:0] Clock Control.
The timer clock mode depends on these bits:
Table 40. Clock Control Bits
Timer Clock
fCPU / 4
fCPU / 2
fCPU / 8
External Clock (where
available)
CC1
0
0
1
CC0
0
1
0
1
1
Note: If the external clock pin is not available, programming the external clock configuration stops
the counter.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = EXEDG External Clock Edge.
This bit determines which type of level transition
on the external clock pin (EXTCLK) will trigger the
counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
ST72141K
16-BIT TIMER (Cont’d)
STATUS REGISTER (SR)
Read Only
Reset Value: 0000 0000 (00h)
The three least significant bits are not used.
7
ICF1
0
OCF1
TOF
ICF2
OCF2
0
0
0
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the low byte of the
IC1R (IC1LR) register.
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter matches
the content of the OC1R register. To clear this
bit, first read the SR register, then read or write
the low byte of the OC1R (OC1LR) register.
Bit 5 = TOF Timer Overflow Flag.
0: No timer overflow (reset value).
1: The free running counter has rolled over from
FFFFh to 0000h. To clear this bit, first read the
SR register, then read or write the low byte of
the CR (CLR) register.
Note: Reading or writing the ACLR register does
not clear TOF.
Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
(IC2LR) register.
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter matches
the content of the OC2R register. To clear this
bit, first read the SR register, then read or write
the low byte of the OC2R (OC2LR) register.
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
7
0
MSB
LSB
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the input capture 1 event).
7
0
MSB
LSB
OUTPUT COMPARE 1 HIGH REGISTER
(OC1HR)
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
7
0
MSB
LSB
OUTPUT COMPARE 1 LOW REGISTER
(OC1LR)
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
MSB
LSB
Bit 2-0 = Reserved, forced by hardware to 0.
93/132
ST72141K
16-BIT TIMER (Cont’d)
OUTPUT COMPARE 2 HIGH REGISTER
(OC2HR)
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the counter value.
7
0
7
0
MSB
LSB
MSB
LSB
OUTPUT COMPARE 2 LOW REGISTER
(OC2LR)
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
MSB
LSB
COUNTER HIGH REGISTER (CHR)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the counter value.
7
0
MSB
LSB
COUNTER LOW REGISTER (CLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after accessing
the SR register clears the TOF bit.
7
0
MSB
LSB
94/132
ALTERNATE COUNTER LOW REGISTER
(ACLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to SR register does not clear the TOF bit in SR
register.
7
0
MSB
LSB
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
7
0
MSB
LSB
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the Input Capture 2 event).
7
0
MSB
LSB
ST72141K
16-BIT TIMER (Cont’d)
Table 41. 16-Bit Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
Timer A: 32 CR1
Timer B: 42 Reset Value
Timer A: 31 CR2
Timer B: 41 Reset Value
Timer A: 33 SR
Timer B: 43 Reset Value
Timer A: 34 ICHR1
Timer B: 44 Reset Value
Timer A: 35 ICLR1
Timer B: 45 Reset Value
Timer A: 36 OCHR1
Timer B: 46 Reset Value
Timer A: 37 OCLR1
Timer B: 47 Reset Value
Timer A: 3E OCHR2
Timer B: 4E Reset Value
Timer A: 3F OCLR2
Timer B: 4F Reset Value
Timer A: 38 CHR
Timer B: 48 Reset Value
Timer A: 39 CLR
Timer B: 49 Reset Value
Timer A: 3A ACHR
Timer B: 4A Reset Value
Timer A: 3B ACLR
Timer B: 4B Reset Value
Timer A: 3C ICHR2
Timer B: 4C Reset Value
Timer A: 3D ICLR2
Timer B: 4D Reset Value
7
6
5
4
3
2
1
0
ICIE
OCIE
TOIE
FOLV2
FOLV1
OLVL2
IEDG1
OLVL1
0
0
0
0
0
0
0
0
OC1E
OC2E
OPM
PWM
CC1
CC0
IEDG2
EXEDG
0
0
0
0
0
0
0
0
ICF1
OCF1
TOF
ICF2
OCF2
-
-
-
0
0
0
0
0
0
0
0
MSB
-
-
-
-
-
-
-
LSB
-
MSB
-
-
-
-
-
-
-
LSB
-
MSB
-
-
-
-
-
-
-
LSB
-
MSB
-
-
-
-
-
-
-
LSB
-
MSB
-
-
-
-
-
-
-
LSB
-
MSB
-
-
-
-
-
-
-
LSB
-
MSB
1
1
1
1
1
1
1
LSB
1
MSB
1
1
1
1
1
1
0
LSB
0
MSB
1
1
1
1
1
1
1
LSB
1
MSB
1
1
1
1
1
1
0
LSB
0
MSB
-
-
-
-
-
-
-
LSB
-
MSB
-
-
-
-
-
-
-
LSB
-
95/132
ST72141K
8.4 SERIAL PERIPHERAL INTERFACE (SPI)
8.4.1 Introduction
The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
The SPI is normally used for communication between the microcontroller and external peripherals
or another microcontroller.
Refer to the Pin Description chapter for the devicespecific pin-out.
8.4.3 General description
The SPI is connected to external devices through
4 alternate pins:
– MISO: Master In Slave Out pin
– MOSI: Master Out Slave In pin
– SCK: Serial Clock pin
– SS: Slave select pin
A basic example of interconnections between a
single master and a single slave is illustrated on
Figure 56.
The MOSI pins are connected together as are
MISO pins. In this way data is transferred serially
between master and slave (most significant bit
first).
When the master device transmits data to a slave
device via MOSI pin, the slave device responds by
sending data to the master device via the MISO
pin. This implies full duplex transmission with both
data out and data in synchronized with the same
clock signal (which is provided by the master device via the SCK pin).
Thus, the byte transmitted is replaced by the byte
received and eliminates the need for separate
transmit-empty and receiver-full bits. A status flag
is used to indicate that the I/O operation is complete.
Four possible data/clock timing relationships may
be chosen (see Figure 59) but master and slave
must be programmed with the same timing mode.
8.4.2 Main Features
■ Full duplex, three-wire synchronous transfers
■ Master or slave operation
■ Four master mode frequencies
■ Maximum slave mode frequency = fCPU/4.
■ Four programmable master bit rates
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
■ Write collision flag protection
■ Master mode fault protection capability.
Figure 56. Serial Peripheral Interface Master/Slave
SLAVE
MASTER
MSBit
LSBit
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
96/132
MSBit
MISO
MISO
MOSI
MOSI
SCK
SS
SCK
+5V
SS
LSBit
8-BIT SHIFT REGISTER
ST72141K
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 57. Serial Peripheral Interface Block Diagram
Internal Bus
Read
DR
IT
Read Buffer
request
MOSI
MISO
SR
8-Bit Shift Register
SPIF WCOL - MODF
-
-
-
-
Write
SPI
STATE
CONTROL
SCK
SS
CR
SPIE
SPE
SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER
CONTROL
SERIAL
CLOCK
GENERATOR
97/132
ST72141K
SERIAL PERIPHERAL INTERFACE (Cont’d)
8.4.4 Functional Description
Figure 56 shows the serial peripheral interface
(SPI) block diagram.
This interface contains 3 dedicated registers:
– A Control Register (CR)
– A Status Register (SR)
– A Data Register (DR)
Refer to the CR, SR and DR registers in Section
8.4.7for the bit definitions.
8.4.4.1 Master Configuration
In a master configuration, the serial clock is generated on the SCK pin.
Procedure
– Select the SPR0 & SPR1 bits to define the serial clock baud rate (see CR register).
– Select the CPOL and CPHA bits to define one
of the four relationships between the data
transfer and the serial clock (see Figure 59).
– The SS pin must be connected to a high level
signal during the complete byte transmit sequence.
– The MSTR and SPE bits must be set (they remain set only if the SS pin is connected to a
high level signal).
98/132
In this configuration the MOSI pin is a data output
and to the MISO pin is a data input.
Transmit sequence
The transmit sequence begins when a byte is written the DR register.
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt is generated if the SPIE bit is set
and the I bit in the CCR register is cleared.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SR register while the SPIF bit
is set
2. A read to the DR register.
Note: While the SPIF bit is set, all writes to the DR
register are inhibited until the SR register is read.
ST72141K
SERIAL PERIPHERAL INTERFACE (Cont’d)
8.4.4.2 Slave Configuration
In slave configuration, the serial clock is received
on the SCK pin from the master device.
The value of the SPR0 & SPR1 bits is not used for
the data transfer.
Procedure
– For correct data transfer, the slave device
must be in the same timing mode as the master device (CPOL and CPHA bits). See Figure
59.
– The SS pin must be connected to a low level
signal during the complete byte transmit sequence.
– Clear the MSTR bit and set the SPE bit to assign the pins to alternate function.
In this configuration the MOSI pin is a data input
and the MISO pin is a data output.
Transmit Sequence
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MISO pin most
significant bit first.
The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt is generated if SPIE bit is set and
I bit in CCR register is cleared.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SR register while the SPIF bit
is set.
2.A read to the DR register.
Notes: While the SPIF bit is set, all writes to the
DR register are inhibited until the SR register is
read.
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an overrun
condition (see Section 8.4.4.6).
Depending on the CPHA bit, the SS pin has to be
set to write to the DR register between each data
byte transfer to avoid a write collision (see Section
8.4.4.4).
99/132
ST72141K
SERIAL PERIPHERAL INTERFACE (Cont’d)
8.4.4.3 Data Transfer Format
During an SPI transfer, data is simultaneously
transmitted (shifted out serially) and received
(shifted in serially). The serial clock is used to synchronize the data transfer during a sequence of
eight clock pulses.
The SS pin allows individual selection of a slave
device; the other slave devices that are not selected do not interfere with the SPI transfer.
Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits.
The CPOL (clock polarity) bit controls the steady
state value of the clock when no data is being
transferred. This bit affects both master and slave
modes.
The combination between the CPOL and CPHA
(clock phase) bits selects the data capture clock
edge.
Figure 59, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
The SS pin is the slave device select input and can
be driven by the master device.
The master device applies data to its MOSI pinclock edge before the capture clock edge.
CPHA bit is set
The second edge on the SCK pin (falling edge if
the CPOL bit is reset, rising edge if the CPOL bit is
set) is the MSBit capture strobe. Data is latched on
the occurrence of the second clock transition.
No write collision should occur even if the SS pin
stays low during a transfer of several bytes (see
Figure 58).
CPHA bit is reset
The first edge on the SCK pin (falling edge if CPOL
bit is set, rising edge if CPOL bit is reset) is the
MSBit capture strobe. Data is latched on the occurrence of the first clock transition.
The SS pin must be toggled high and low between
each byte transmitted (see Figure 58).
To protect the transmission from a write collision a
low value on the SS pin of a slave device freezes
the data in its DR register and does not allow it to
be altered. Therefore the SS pin must be high to
write a new data byte in the DR without producing
a write collision.
Figure 58. CPHA / SS Timing Diagram
MOSI/MISO
Byte 1
Byte 2
Byte 3
Master SS
Slave SS
(CPHA=0)
Slave SS
(CPHA=1)
VR02131A
100/132
ST72141K
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 59. Data Clock Timing Diagram
CPHA =1
SCLK (with
CPOL = 1)
SCLK (with
CPOL = 0)
MISO
(from master)
MOSI
(from slave)
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
SS
(to slave)
CAPTURE STROBE
CPHA =0
CPOL = 1
CPOL = 0
MSBit
MISO
(from master)
MOSI
(from slave)
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
VR02131B
101/132
ST72141K
SERIAL PERIPHERAL INTERFACE (Cont’d)
8.4.4.4 Write Collision Error
A write collision occurs when the software tries to
write to the DR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and
the software write will be unsuccessful.
Write collisions can occur both in master and slave
mode.
Note: a "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU operation.
In Slave mode
When the CPHA bit is set:
The slave device will receive a clock (SCK) edge
prior to the latch of the first data transfer. This first
clock edge will freeze the data in the slave device
DR register and output the MSBit on to the external MISO pin of the slave device.
The SS pin low state enables the slave device but
the output of the MSBit onto the MISO pin does
not take place until the first data transfer clock
edge.
When the CPHA bit is reset:
Data is latched on the occurrence of the first clock
transition. The slave device does not have any
way of knowing when that transition will occur;
therefore, the slave device collision occurs when
software attempts to write the DR register after its
SS pin has been pulled low.
For this reason, the SS pin must be high, between
each data byte transfer, to allow the CPU to write
in the DR register without generating a write collision.
In Master mode
Collision in the master device is defined as a write
of the DR register while the internal serial clock
(SCK) is in the process of transfer.
The SS pin signal must be always high on the
master device.
WCOL bit
The WCOL bit in the SR register is set if a write
collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 60).
Figure 60. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
1st Step
Read SR
OR
Read SR
THEN
THEN
2nd Step
Read DR
SPIF =0
WCOL=0
Write DR
SPIF =0
WCOL=0 if no transfer has started
WCOL=1 if a transfer has started
before the 2nd step
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st Step
Read SR
THEN
2nd Step
102/132
Read DR
WCOL=0
Note: Writing to the DR register
instead of reading in it does not
reset the WCOL bit
ST72141K
SERIAL PERIPHERAL INTERFACE (Cont’d)
8.4.4.5 Master Mode Fault
Master mode fault occurs when the master device
has its SS pin pulled low, then the MODF bit is set.
Master mode fault affects the SPI peripheral in the
following ways:
– The MODF bit is set and an SPI interrupt is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI peripheral.
– The MSTR bit is reset, thus forcing the device
into slave mode.
Clearing the MODF bit is done through a software
sequence:
1. A read or write access to the SR register while
the MODF bit is set.
2. A write to the CR register.
Notes: To avoid any multiple slave conflicts in the
case of a system comprising several MCUs, the
SS pin must be pulled high during the clearing sequence of the MODF bit. The SPE and MSTR bits
may be restored to their original state during or after this clearing sequence.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
In a slave device the MODF bit can not be set, but
in a multi master configuration the device can be in
slave mode with this MODF bit set.
The MODF bit indicates that there might have
been a multi-master conflict for system control and
allows a proper exit from system operation to a reset or default system state using an interrupt routine.
8.4.4.6 Overrun Condition
An overrun condition occurs when the master device has sent several data bytes and the slave device has not cleared the SPIF bit issuing from the
previous data byte transmitted.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the DR register returns this byte. All other bytes
are lost.
This condition is not detected by the SPI peripheral.
103/132
ST72141K
SERIAL PERIPHERAL INTERFACE (Cont’d)
8.4.4.7 Single Master and Multimaster Configurations
For more security, the slave device may respond
There are two types of SPI systems:
to the master with the received data byte. Then the
– Single Master System
master will receive the previous byte back from the
– Multimaster System
slave device if all MISO and MOSI pins are connected and the slave has not written its DR register.
Single Master System
Other transmission security methods can use
A typical single master system may be configured,
ports for handshake lines or data bytes with comusing an MCU as the master and four MCUs as
mand fields.
slaves (see Figure 61).
Multi-master System
The master device selects the individual slave deA multi-master system may also be configured by
vices by using four pins of a parallel port to control
the user. Transfer of master control could be imthe four SS pins of the slave devices.
plemented using a handshake method through the
The SS pins are pulled high during reset since the
I/O ports or by an exchange of code messages
master device ports will be forced to be inputs at
through the serial peripheral interface system.
that time, thus disabling the slave devices.
The multi-master system is principally handled by
the MSTR bit in the CR register and the MODF bit
Note: To prevent a bus conflict on the MISO line
in the SR register.
the master allows only one active slave device
during a transmission.
Figure 61. Single Master Configuration
SS
SCK
Slave
MCU
Slave
MCU
MOSI MISO
MOSI MISO
SCK
Master
MCU
5V
104/132
SS
Ports
MOSI MISO
SS
SS
SCK
SS
SCK
Slave
MCU
SCK
Slave
MCU
MOSI MISO
MOSI MISO
ST72141K
SERIAL PERIPHERAL INTERFACE (Cont’d)
8.4.5 Low Power Modes
Mode
WAIT
HALT
Description
No effect on SPI.
SPI interrupt events cause the device to exit from WAIT mode.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with
“exit from HALT mode” capability.
8.4.6 Interrupts
Interrupt Event
SPI End of Transfer Event
Master Mode Fault Event
Event
Flag
Enable
Control
Bit
SPIF
MODF
SPIE
Exit
from
Wait
Yes
Yes
Exit
from
Halt
No
No
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
105/132
ST72141K
SERIAL PERIPHERAL INTERFACE (Cont’d)
8.4.7 Register Description
CONTROL REGISTER (CR)
Read/Write
Reset Value: 0000xxxx (0xh)
7
SPIE
0
SPE
SPR2
MSTR
CPOL
CPHA
SPR1
SPR0
Bit 7 = SPIE Serial peripheral interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever SPIF=1
or MODF=1 in the SR register
Bit 6 = SPE Serial peripheral output enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 8.4.4.5 Master Mode Fault).
0: I/O port connected to pins
1: SPI alternate functions connected to pins
The SPE bit is cleared by reset, so the SPI peripheral is not initially connected to the external pins.
Bit 5 = SPR2 Divider Enable.
this bit is set and cleared by software and it is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 42.
0: Divider by 2 enabled
1: Divider by 2 disabled
Bit 4 = MSTR Master.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 8.4.4.5 Master Mode Fault).
0: Slave mode is selected
1: Master mode is selected, the function of the
SCK pin changes from an input to an output and
the functions of the MISO and MOSI pins are reversed.
106/132
Bit 3 = CPOL Clock polarity.
This bit is set and cleared by software. This bit determines the steady state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: The steady state is a low value at the SCK pin.
1: The steady state is a high value at the SCK pin.
Bit 2 = CPHA Clock phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 1:0 = SPR[1:0] Serial peripheral rate.
These bits are set and cleared by software.Used
with the SPR2 bit, they select one of six baud rates
to be used as the serial clock when the device is a
master.
These 2 bits have no effect in slave mode.
Table 42. Serial Peripheral Baud Rate
Serial Clock
SPR2
SPR1
SPR0
fCPU/4
1
0
0
fCPU/8
0
0
0
fCPU/16
0
0
1
fCPU/32
1
1
0
fCPU/64
0
1
0
fCPU/128
0
1
1
ST72141K
SERIAL PERIPHERAL INTERFACE (Cont’d)
STATUS REGISTER (SR)
Read Only
Reset Value: 0000 0000 (00h)
7
SPIF
WCOL
-
MODF
-
-
-
DATA I/O REGISTER (DR)
Read/Write
Reset Value: Undefined
0
7
-
D7
Bit 7 = SPIF Serial Peripheral data transfer flag.
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the CR register. It is cleared by a software sequence (an access to the SR register followed by a read or write to the DR register).
0: Data transfer is in progress or has been approved by a clearing sequence.
1: Data transfer between the device and an external device has been completed.
Note: While the SPIF bit is set, all writes to the DR
register are inhibited.
Bit 6 = WCOL Write Collision status.
This bit is set by hardware when a write to the DR
register is done during a transmit sequence. It is
cleared by a software sequence (see Figure 60).
0: No write collision occurred
1: A write collision has been detected
0
D6
D5
D4
D3
D2
D1
D0
The DR register is used to transmit and receive
data on the serial bus. In the master device only a
write to this register will initiate transmission/reception of another byte.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
Warning:
A write to the DR register places data directly into
the shift register for transmission.
A read to the the DR register returns the value located in the buffer and not the contents of the shift
register (See Figure 57 ).
Bit 5 = Unused.
Bit 4 = MODF Mode Fault flag.
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 8.4.4.5
Master Mode Fault). An SPI interrupt can be generated if SPIE=1 in the CR register. This bit is
cleared by a software sequence (An access to the
SR register while MODF=1 followed by a write to
the CR register).
0: No master mode fault detected
1: A fault in master mode has been detected
Bits 3-0 = Unused.
107/132
ST72141K
SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 43. SPI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
0021h
SPIDR
Reset Value
MSB
x
x
x
x
x
x
x
LSB
x
0022h
SPICR
Reset Value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
0023h
SPISR
Reset Value
SPIF
0
WCOL
0
0
MODF
0
0
0
0
0
108/132
ST72141K
8.5 8-BIT A/D CONVERTER (ADC)
8.5.1 Introduction
The on-chip Analog to Digital Converter (ADC) peripheral is a 8-bit, successive approximation converter with internal sample and hold circuitry. This
peripheral has up to 8 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 8 different sources.
The result of the conversion is stored in a 8-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
8.5.2 Main Features
■ 8-bit conversion
■ Up to 8 channels with multiplexed input
■ Linear successive approximation
■ Data register (DR) which contains the results
■ Conversion complete status flag
■ On/Off bit (to reduce consumption)
The block diagram is shown in Figure 62.
Figure 62. ADC Block Diagram
COCO
-
ADON
0
-
CH2
CH1
CH0
(Control Status Register) CSR
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
ANALOG
MUX
fCPU
SAMPLE
&
HOLD
ANALOG TO
DIGITAL
CONVERTER
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
(Data Register) DR
109/132
ST72141K
8-BIT A/D CONVERTER (ADC) (Cont’d)
8.5.3 Functional Description
The high level reference voltage VDDA must be
connected externally to the V DD pin. The low level
reference voltage V SSA must be connected externally to the VSS pin. In some devices (refer to device pin out description) high and low level reference voltages are internally connected to the VDD
and VSS pins.
Conversion accuracy may therefore be degraded
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
Figure 63. Recommended Ext. Connections
VDD
VDDA
0.1µF
VSSA
ST7
RAIN
VAIN
Px.x/AINx
Characteristics:
The conversion is monotonic, meaning the result
never decreases if the analog input does not and
never increases if the analog input does not.
If input voltage is greater than or equal to VDD
(voltage reference high) then results = FFh (full
scale) without overflow indication.
If input voltage ≤ VSS (voltage reference low) then
the results = 00h.
The conversion time is 64 CPU clock cycles including a sampling time of 31.5 CPU clock cycles.
RAIN is the maximum recommended impedance
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
The A/D converter is linear and the digital result of
the conversion is given by the formula:
Digital result =
255 x Input Voltage
Reference Voltage
Where Reference Voltage is VDD - VSS.
110/132
The accuracy of the conversion is described in the
Electrical Characteristics Section.
Procedure:
Refer to the CSR and DR register description section for the bit definitions.
Each analog input pin must be configured as input,
no pull-up, no interrupt. Refer to the “I/O Ports”
chapter. Using these pins as analog inputs does
not affect the ability of the port to be read as a logic
input.
In the CSR register:
– Select the CH2 to CH0 bits to assign the analog channel to convert. Refer to Table 44
Channel Selection.
– Set the ADON bit. Then the A/D converter is
enabled after a stabilization time (typically 30
µs). It then performs a continuous conversion
of the selected channel.
When a conversion is complete
– The COCO bit is set by hardware.
– No interrupt is generated.
– The result is in the DR register.
A write to the CSR register aborts the current conversion, resets the COCO bit and starts a new
conversion.
8.5.4 Low Power Modes
Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed.
Mode
WAIT
HALT
Description
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D
Converter requires a stabilisation time
before accurate conversions can be
performed.
8.5.5 Interrupts
None.
ST72141K
8-BIT A/D CONVERTER (ADC) (Cont’d)
8.5.6 Register Description
CONTROL/STATUS REGISTER (CSR)
Read/Write
Reset Value: 0000 0000 (00h)
7
COCO
These bits are set and cleared by software. They
select the analog input to convert.
Table 44. Channel Selection
0
-
ADON
0
-
CH2
CH1
CH0
Bit 7 = COCO Conversion Complete
This bit is set by hardware. It is cleared by software reading the result in the DR register or writing
to the CSR register.
0: Conversion is not complete.
1: Conversion can be read from the DR register.
Pin*
CH2
CH1
CH0
AIN0
0
0
0
AIN1
0
0
1
AIN2
0
1
0
AIN3
0
1
1
AIN4
1
0
0
AIN5
1
0
1
AIN6
1
1
0
AIN7
1
1
1
*IMPORTANT NOTE: The number of pins AND
the channel selection vary according to the device.
REFER TO THE DEVICE PINOUT).
Bit 6 = Reserved. Must always be cleared.
Bit 5 = ADON A/D converter On
This bit is set and cleared by software.
0: A/D converter is switched off.
1: A/D converter is switched on.
Note: A typical 30 µs delay time is necessary for
the ADC to stabilize when the ADON bit is set.
DATA REGISTER (DR)
Read Only
Reset Value: 0000 0000 (00h)
7
0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Bit 4 = Reserved. Forced by hardware to 0.
Bit 7:0 = AD[7:0] Analog Converted Value
This register contains the converted analog value
in the range 00h to FFh.
Reading this register resets the COCO flag.
Bit 3 = Reserved. Must always be cleared.
Bits 2:0: CH[2:0] Channel Selection
Table 45. ADC Register Map and Reset Values
Address
Register
Label
7
6
5
4
3
2
1
0
0070h
ADCDR
Reset Value
IS11
0
IS10
0
MCO
0
IS21
0
IS20
0
CP1
0
CP0
0
SMS
0
0071h
ADCCSR
Standard
Reset Value
COCO
0
0
ADON
0
0
0
CH2
0
CH1
0
CH0
0
(Hex.)
111/132
ST72141K
9 INSTRUCTION SET
9.1 ST7 ADDRESSING MODES
The ST7 Core features 17 different addressing
modes which can be classified in 7 main groups:
Addressing Mode
Example
Inherent
nop
Immediate
ld A,#$55
Direct
ld A,$55
Indexed
ld A,($55,X)
Indirect
ld A,([$55],X)
Relative
jrne loop
Bit operation
bset
byte,#5
The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
so, most of the addressing modes may be subdivided in two sub-modes called long and short:
– Long addressing mode is more powerful because it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cycles.
– Short addressing mode is less powerful because
it can generally only access page zero (0000h 00FFh range), but the instruction size is more
compact, and faster. All memory to memory instructions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
The ST7 Assembler optimizes the use of long and
short addressing modes.
Table 46. ST7 Addressing Mode Overview
Mode
Syntax
Pointer
Address
(Hex.)
Destination/
Source
Pointer
Size
(Hex.)
Length
(Bytes)
Inherent
nop
+0
Immediate
ld A,#$55
+1
Short
Direct
ld A,$10
00..FF
+1
Long
Direct
ld A,$1000
0000..FFFF
+2
No Offset
Direct
Indexed
ld A,(X)
00..FF
+ 0 (with X register)
+ 1 (with Y register)
Short
Direct
Indexed
ld A,($10,X)
00..1FE
+1
Long
Direct
Indexed
Short
Indirect
ld A,($1000,X)
0000..FFFF
ld A,[$10]
00..FF
+2
00..FF
byte
+2
Long
Indirect
ld A,[$10.w]
0000..FFFF
00..FF
word
+2
Short
Indirect
Indexed
ld A,([$10],X)
00..1FE
00..FF
byte
+2
Long
Indirect
Indexed
ld A,([$10.w],X)
0000..FFFF
00..FF
word
+2
00..FF
byte
00..FF
byte
1)
Relative
Direct
jrne loop
PC-128/PC+127
Relative
Indirect
jrne [$10]
PC-128/PC+1271)
Bit
Direct
bset $10,#7
00..FF
Bit
Indirect
bset [$10],#7
00..FF
Bit
Direct
Relative
btjt $10,#7,skip
00..FF
Bit
Indirect
Relative
btjt [$10],#7,skip 00..FF
+1
+2
+1
+2
+2
00..FF
byte
+3
Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
112/132
ST72141K
ST7 ADDRESSING MODES (Cont’d)
9.1.1 Inherent
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required information for the CPU to process the operation.
Inherent Instruction
Function
NOP
No operation
TRAP
S/W Interrupt
WFI
Wait For Interrupt (Low Power
Mode)
HALT
Halt Oscillator (Lowest Power
Mode)
RET
Sub-routine Return
IRET
Interrupt Sub-routine Return
SIM
Set Interrupt Mask
RIM
Reset Interrupt Mask
SCF
Set Carry Flag
RCF
Reset Carry Flag
RSP
Reset Stack Pointer
LD
Load
CLR
Clear
PUSH/POP
Push/Pop to/from the stack
INC/DEC
Increment/Decrement
TNZ
Test Negative or Zero
CPL, NEG
1 or 2 Complement
MUL
Byte Multiplication
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
9.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte contains the operand value.
Immediate Instruction
Function
LD
Load
CP
Compare
BCP
Bit Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC
Arithmetic Operations
9.1.3 Direct
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two submodes:
Direct (short)
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF addressing space.
Direct (long)
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode.
9.1.4 Indexed (No Offset, Short, Long)
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three
sub-modes:
Indexed (No Offset)
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
Indexed (Short)
The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing
space.
Indexed (long)
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode.
9.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two sub-modes:
Indirect (short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
113/132
ST72141K
ST7 ADDRESSING MODES (Cont’d)
9.1.6 Indirect Indexed (Short, Long)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the unsigned addition of an index register value (X or Y)
with a pointer value located in memory. The pointer address follows the opcode.
The indirect indexed addressing mode consists of
two sub-modes:
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
Indirect Indexed (Long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
Table 47. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Instructions
Function
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC
Arithmetic Addition/subtraction operations
BCP
Bit Compare
Short Instructions Only
Function
CLR
Clear
INC, DEC
Increment/Decrement
TNZ
Test Negative or Zero
CPL, NEG
1 or 2 Complement
BSET, BRES
Bit Operations
BTJT, BTJF
Bit Test and Jump Operations
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
114/132
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
9.1.7 Relative Mode (Direct, Indirect)
This addressing mode is used to modify the PC
register value by adding an 8-bit signed offset to it.
Available Relative Direct/
Indirect Instructions
Function
JRxx
Conditional Jump
CALLR
Call Relative
The relative addressing mode consists of two submodes:
Relative (Direct)
The offset follows the opcode.
Relative (Indirect)
The offset is defined in memory, of which the address follows the opcode.
ST72141K
9.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
Stack operation
PUSH
POP
Increment/Decrement
INC
DEC
Compare and Tests
CP
TNZ
BCP
Logical operations
AND
OR
XOR
CPL
NEG
Bit Operation
BSET
BRES
Conditional Bit Test and Branch
BTJT
BTJF
Arithmetic operations
ADC
ADD
SUB
SBC
MUL
Shift and Rotates
SLL
SRL
SRA
RLC
RRC
SWAP
SLA
Unconditional Jump or Call
JRA
JRT
JRF
JP
CALL
CALLR
NOP
Conditional Branch
JRxx
Interruption management
TRAP
WFI
HALT
IRET
Condition Code Flag modification
SIM
RIM
SCF
RCF
Using a pre-byte
The instructions are described with one to four
bytes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they precede.
The whole instruction becomes:
PC-2 End of previous instruction
PC-1 Prebyte
PC
Opcode
PC+1 Additional word (0 to 2) according to the
number of bytes required to compute the
effective address
RSP
RET
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
PDY 90 Replace an X based instruction using
immediate, direct, indexed, or inherent
addressing mode by a Y one.
PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing
mode to an instruction using the corresponding indirect addressing mode.
It also changes an instruction using X
indexed addressing mode to an instruction using indirect X indexed addressing
mode.
PIY 91 Replace an instruction using X indirect
indexed addressing mode by a Y one.
115/132
ST72141K
INSTRUCTION GROUPS (Cont’d)
Mnemo
Description
Function/Example
Dst
Src
H
I
N
Z
C
ADC
Add with Carry
A=A+M+C
A
M
H
N
Z
C
ADD
Addition
A=A+M
A
M
H
N
Z
C
AND
Logical And
A=A.M
A
M
N
Z
BCP
Bit compare A, Memory
tst (A . M)
A
M
N
Z
BRES
Bit Reset
bres Byte, #3
M
BSET
Bit Set
bset Byte, #3
M
BTJF
Jump if bit is false (0)
btjf Byte, #3, Jmp1
M
C
BTJT
Jump if bit is true (1)
btjt Byte, #3, Jmp1
M
C
CALL
Call subroutine
CALLR
Call subroutine relative
CLR
Clear
CP
Arithmetic Compare
tst(Reg - M)
reg
reg, M
CPL
One Complement
A = FFH-A
DEC
Decrement
dec Y
HALT
Halt
IRET
Interrupt routine return
Pop CC, A, X, PC
INC
Increment
inc X
JP
Absolute Jump
jp [TBL.w]
JRA
Jump relative always
JRT
Jump relative
JRF
Never jump
JRIH
Jump if ext. interrupt = 1
JRIL
Jump if ext. interrupt = 0
JRH
Jump if H = 1
H=1?
JRNH
Jump if H = 0
H=0?
JRM
Jump if I = 1
I=1?
JRNM
Jump if I = 0
I=0?
JRMI
Jump if N = 1 (minus)
N=1?
JRPL
Jump if N = 0 (plus)
N=0?
JREQ
Jump if Z = 1 (equal)
Z=1?
JRNE
Jump if Z = 0 (not equal)
Z=0?
JRC
Jump if C = 1
C=1?
JRNC
Jump if C = 0
C=0?
JRULT
Jump if C = 1
Unsigned <
JRUGE
Jump if C = 0
Jmp if unsigned >=
JRUGT
Jump if (C + Z = 0)
Unsigned >
116/132
0
1
N
Z
C
reg, M
N
Z
1
reg, M
N
Z
N
Z
N
Z
M
0
jrf *
H
reg, M
I
C
ST72141K
INSTRUCTION GROUPS (Cont’d)
Mnemo
Description
Function/Example
Dst
Src
JRULE
Jump if (C + Z = 1)
Unsigned <=
LD
Load
dst <= src
reg, M
M, reg
MUL
Multiply
X,A = X * A
A, X, Y
X, Y, A
NEG
Negate (2’s compl)
neg $10
reg, M
NOP
No Operation
OR
OR operation
A=A+M
A
M
POP
Pop from the Stack
pop reg
reg
M
pop CC
CC
M
M
reg, CC
H
I
N
Z
N
Z
0
H
C
0
I
N
Z
N
Z
N
Z
C
C
PUSH
Push onto the Stack
push Y
RCF
Reset carry flag
C=0
RET
Subroutine Return
RIM
Enable Interrupts
I=0
RLC
Rotate left true C
C <= Dst <= C
reg, M
N
Z
C
RRC
Rotate right true C
C => Dst => C
reg, M
N
Z
C
RSP
Reset Stack Pointer
S = Max allowed
SBC
Subtract with Carry
A=A-M-C
N
Z
C
SCF
Set carry flag
C=1
SIM
Disable Interrupts
I=1
SLA
Shift left Arithmetic
C <= Dst <= 0
reg, M
N
Z
C
SLL
Shift left Logic
C <= Dst <= 0
reg, M
N
Z
C
SRL
Shift right Logic
0 => Dst => C
reg, M
0
Z
C
SRA
Shift right Arithmetic
Dst7 => Dst => C
reg, M
N
Z
C
SUB
Subtraction
A=A-M
A
N
Z
C
SWAP
SWAP nibbles
Dst[7..4] <=> Dst[3..0] reg, M
N
Z
TNZ
Test for Neg & Zero
tnz lbl1
N
Z
TRAP
S/W trap
S/W interrupt
WFI
Wait for Interrupt
XOR
Exclusive OR
N
Z
0
0
A
M
1
1
M
1
0
A = A XOR M
A
M
117/132
ST72141K
10 ELECTRICAL CHARACTERISTICS
10.1 ABSOLUTE MAXIMUM RATINGS
This product contains devices for protecting the inputs against damage due to high static voltages,
however it is advisable to take normal precautions
to avoid applying any voltage higher than the
specified maximum rated voltages.
For proper operation it is recommended that VI
and VO be higher than V SS and lower than V DD.
Reliability is enhanced if unused inputs are connected to an appropriate logic voltage level (VDD
or V SS).
Symbol
VDD - VSS
VIN
VOUT
Power Considerations. The average chip-junction temperature, TJ, in Celsius can be obtained
from:
TJ =
TA + PD x RthJA
Where: TA =
Ambient Temperature.
RthJA =Package thermal resistance
(junction-to ambient).
PD = PINT + P PORT.
PINT = IDD x VDD (chip internal power).
PPORT =Port power dissipation
determined by the user)
Ratings
Supply voltage
Input voltage on true open drain pin
Value
Unit
6.5
V
VSS - 0.3 to 6.5
V
Input voltage on any other pin
VSS - 0.3 to VDD + 0.3
Output voltage
VSS - 0.3 to VDD + 0.3
V
2000
V
ESD
ESD susceptibility
IVDD_i
Total current into VDD_i (source)
80
IVSS_i
Total current out of VSS_i (sink)
80
mA
Note:
Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
General Warning:
Direct connection to VDD or VSS of the RESET and I/O pins could damage the device in case of unintentional internal
reset generation or program counter corruption (due to unwanted change of the I/O configuration). To guarantee safe
conditions, this connection has to be done through a 10KΩ typical pull-up or pull-down resistor.
Thermal Characteristics
Symbol
RthJA
Package thermal resistance
SO34
SDIP32
Value
Unit
75
60
°C/W
TJmax
Max. junction temperature
150
°C
TSTG
Storage temperature range
-65 to +150
°C
500
mW
PD
118/132
Ratings
Power dissipation
ST72141K
10.2 RECOMMENDED OPERATING CONDITIONS
GENERAL
Symbol
VDD
fOSC
TA
Parameter
Conditions
Typ 1)
Min
Supply voltage
4.0
Resonator oscillator frequency
Unit
5.5
V
8 or 16 2)
External clock source
Ambient temperature range
Max
MHz
1 Suffix Version
0
70
6 Suffix Version
-40
85
3 Suffix Version
-40
125
°C
10.3 DC ELECTRICAL CHARACTERISTICS
Recommended operating conditions with T A=-40 to +125oC, VDD-VSS=5V unless otherwise specified.
Symbol
IDD
Parameter
Conditions
Min
Supply current in RUN mode 3)
fOSC = 8 MHz, fCPU = 4 MHz
fOSC = 16 MHz, fCPU = 8 MHz
Supply current in SLOW mode 3)
fOSC = 8 MHz, fCPU = 250 kHz
fOSC = 16 MHz, fCPU = 500 kHz
Supply current in WAIT mode 4)
fOSC = 8MHz, fCPU = 4 MHz
fOSC = 16MHz, fCPU = 8 MHz
f
= 8 MHz, fCPU = 250 kHz
Supply current in SLOW WAIT mode 4) OSC
fOSC = 16 MHz, fCPU = 500 kHz
VRM
Supply current in HALT mode 5)
Data retention mode 6)
ILOAD = 0mA (current on IOs)
HALT mode
Typ 1)
Max
5
7
0.7
1
2
3.3
0.65
0.8
8
12
1.1
1.7
3
5
1
1.4
200
2
Unit
mA
µA
V
10.4 GENERAL TIMING CHARACTERISTICS
Symbol
Parameter
tINST
Instruction time
tIRT
Interrupt reaction time
Conditions
Min
Typ
Max
Unit
2
12
tCPU
tIRT = ∆tINST + 10 7)
10
22
tCPU
Notes:
1) Unless otherwise specified, typical data is based on TA=25°C and VDD-VSS=5V. This data is provided only as design
guidelines and is not tested.
2) Fixed frequencies required to obtain 4MHz for the motor control peripheral.
3) CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS, all peripherals switched
off; clock input (OSC2) driven by external square wave.
4) All I/O pins in input mode with a static value at VDD or VSS, all peripherals switched off; clock input (OSC2) driven by
external square wave.
5) All I/O pins in input mode with a static value at VDD or VSS.
6) Data based on characterization results, not tested in production.
7) ∆tINST is the number of tCPU to finish the current instruction execution.
119/132
ST72141K
10.5 I/O PORT CHARACTERISTICS
Recommended operating conditions
with TA=-40 to +125oC and 4.5V<V DD-VSS<5.5V unless otherwise specified.
I/O PORT PINS
Symbol
VIL
VIH
VHYS
VOL
Parameter
Input low level voltage
Typ 1)
Max
0.3xVDD
Input high level voltage 2)
0.7xVDD
Schmitt trigger voltage hysteresis 3)
400
I=-5mA
1.3
I=-2mA
0.5
Output low level voltage
for high sink I/O port pins
I=-20mA
1.3
I=-8mA
0.5
RPU
Pull-up equivalent resistor
Input leakage current
2)
ISV
Static current consumption
IPINJ
Single pin injected current
IINJ
Total injected current 7)
(sum of all I/O and control pins)
tOHL
Output high to low level fall time
tOLH
Output low to high rise time
External interrupt pulse time 8)
I=-5mA
VDD-2.0
I=-2mA
VDD-0.8
VIN > VIH
VIN < VIL
20
50
40
120
80
240
VSS<VPIN<VDD
1
Floating input mode
200
Positive 5): VEXT >VDD
Negative 6): VEXT<VSS
-5
Positive: VEXT>VDD
20
V
V
kΩ
µA
5
Negative: VEXT<VSS
Cl=50pF
Unit
mV
Output low level voltage
for standard I/O port pins
Output high level voltage
tITEXT
Min
2)
VOH
IL
Conditions
mA
20
14.8 4)
25
45.6 4)
14.4 4)
25
45.9 4)
1
ns
tCPU
Notes:
1) Unless otherwise specified, typical data is based on TA=25°C and VDD-VSS=5V. This data is provided only as design
guidelines and is not tested.
2) Data based on design simulations and/or technology characteristics, not tested in production.
3) Hysteresis voltage between Schmitt trigger switching levels. Based on characterisation results, not tested.
4) Data based on characterization results, not tested in production.
5) Positive injection (IINJ+)
The IINJ+ is performed through protection diodes insulated from the substrate of the die.
The true open-drain pins do not accept positive injection. In this case the maximum voltage rating must be respected.
6) ADC accuracy reduced by negative injection (IINJ- )
The IINJ- is performed through protection diodes NOT INSULATED from the substrate of the die. The drawback is a small
leakage (a few µA) induced inside the die when a negative injection is performed. This leakage is tolerated by the digital
structure, but it acts on the analog line depending on the impedance versus a leakage current of a few µA (if the MCU
has an AD converter). The effect depends on the pin which is submitted to the injection. Of course, external digital signals
applied to the component must have a maximum impedance close to 50KΩ.
Location of the negative current injection:
- Pins with analog input capability are the most sensitive. IINJ- maximum is 0.8 mA (assuming that the impedance of the
analog voltage is lower than 25KΩ)
- Pure digital pins can tolerate 1.6mA. In addition, the best choice is to inject the current as far as possible from the analog
input pins.
7) When several inputs are submitted to a current injection, the maximum IINJ is the sum of the positive (or negative) currents (instantaneous values). These results are based on characterisation with IINJ maximum current injection on four I/
O port pins of the device.
8) To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
120/132
ST72141K
10.6 SUPPLY, RESET AND CLOCK CHARACTERISTICS
10.6.1 Supply Manager
Recommended operating conditions with T A=-40 to +125oC and voltages referred to VSS.
LOW VOLTAGE DETECTOR (LVD)
Symbol
VLVDr
VLVDf
VLVDhyst
VtPOR
IDD
Conditions
Min
Typ 1)
Max
Unit
VDD rise
VDD fall
VLVDr - VLVDf
3.5
4.05
3.75
250
4.30
4.0
V
Parameter
Reset release threshold
Reset generation threshold
VLVD Hysteresis 2)
VDD rise time rate 3)
LVD Supply Current
0.2
HALT mode
100
50
2004)
mV
V/ms
µA
10.6.2 RESET Sequence Manager
Recommended operating conditions with T A=-40...+125oC and 4.5V<V DD-VSS<5.5V.
RESET SEQUENCE MANAGER (RSM)
Symbol
RON
tDELAYmin
tPULSE
Parameter
Reset weak pull-up resistance
Conditions
Min
Typ 5)
Max
Unit
VIN > VIH
VIN ≥VSS
5
20
10
80
6
30
20
180
kΩ
Reset delay for external and
watchdog reset sources
External RESET pin Pulse time
1/fSFOSC
µs
µs
20
10.6.3 Clock System
Recommended operating conditions with T A=-40 to +125oC and voltages referred to VSS.
EXTERNAL CLOCK SOURCE
Symbol
VOSC2h
VOSC2l
Parameter
OSC2 input pin high level voltage
OSC2 input pin low level voltage
Conditions
Min
Typ
Max
Square wave signal
with ~50% Duty Cycle
0.7xVDD
VDD
VSS
0.3xVDD
Unit
V
CRYSTAL AND CERAMIC RESONATOR OSCILLATORS
Symbol
fOSC
CLi
IDD
tSTART
Parameter
Frequency 6)
Oscillator
Load Capacitor
Supply Current
Oscillator start-up time
Conditions
Min
Typ 5)
Max
Unit
16
MHz
18
21 6)
pF
700
1100 4)
µA
Depends on resonator quality. A typical value is 10ms
RSmax=100 Ω 7)
8
15 8)
Notes:
1) LVD typical data is based on TA=25°C. This data is provided only as design guidelines and are not tested.
2) The VLVDhyst hysteresis is constant.
3) The VDD rise time rate condition is needed to ensure a correct device power-on reset. Not tested in production.
4) Data based on characterization results, not tested in production.
5) Unless otherwise specified, typical data is based on TA=25°C and VDD-VSS=5V. This data is provided only as design
guidelines and is not tested.
6) This data is based on typical a RSmax value. The oscillator selection can be optimized in terms of supply current with
a high quality resonator.
7) RSmax is the equivalent serial resistor of the crystal or ceramic resonator.
8) Data based on design simulations and/or technology characteristics, not tested in production.
121/132
ST72141K
10.7 MEMORY AND PERIPHERAL CHARACTERISTICS
EPROM
Symbol
Parameter
WERASE
UV lamp
tERASE
Erase Time
Conditions
Min
Lamp wavelength 2537Å
Typ
Max
W-sec/cm2
15
UV lamp placed 1 inch from
the device window without
any interposed filters
15
Conditions
Min
Unit
20
min
Max
Unit
786,432
tCPU
98.3
ms
WATCHDOG
Symbol
Parameter
tw(WDG)
Watchdog time-out duration
tWDGRST
Watchdog RESET pulse width
Typ
12,288
fCPU=8MHz
1.54
500
ns
Recommended operating conditions with TA=-40 to +125oC and VDD-VSS=5V unless otherwise specified.
MOTOR CONTROL
Symbol
Parameter
VOFFSET
Comparator offset error
VMTChyst
MCIA/B/C comparator hysteresis 2)
tPROPAG
∆VREF
VREF
Conditions
Min
Typ 1)
Max
<10
100
mV
80
130
mV
Comparator propagation delay
1
µs
Reference voltage tolerance
5
%
35
R1
30
R2
α= R2
R1+R2
∆α/α
Unit
kΩ
70
VCREF resistance bridge
0.7
α tolerance
5
%
Note:
1) Unless otherwise specified, typical data is based on TA = 25° C and VDD-VSS = 5 V. This data is provided only as design guidelines and are not tested.
2) The VMTChyst hysteresis is constant.
Figure 64. Motor Control Comparator Characteristics
V
VREF+ MTChyst
VOFFSET
2
VMTChyst
VOFFSET
2
COMPARATOR
VIN
IDEAL
REAL
tPROPAG
122/132
tPROPAG
t
COMPARATOR
OUTPUT
VREF-
ST72141K
MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d)
SPI Serial Peripheral Interface
Value 1)
Ref.
Symbol
Parameter
Condition
Min
Max
1/4
1/2
Unit
fSPI
SPI frequency
Master
Slave
1/128
dc
1
tSPI
SPI clock period
Master
Slave
4
2
2
tLead
Enable lead time
Slave
120
ns
3
tLag
Enable lag time
Slave
120
ns
4
tSPI_H
Clock (SCK) high time
Master
Slave
100
90
ns
5
tSPI_L
Clock (SCK) low time
Master
Slave
100
90
ns
6
tSU
Data set-up time
Master
Slave
100
100
ns
7
tH
Data hold time (inputs)
Master
Slave
100
100
ns
8
tA
Access time (time to data active
from high impedance state)
9
tDis
10
tV
11
0
Disable time (hold time to high impedance state)
fCPU
tCPU
120
ns
240
ns
120
tCPU
ns
Slave
Data valid
Master (before capture edge)
Slave (after enable edge)
0.25
tHold
Data hold time (outputs)
Master (before capture edge)
Slave (after enable edge)
0.25
0
12
tRise
Rise time
Outputs: SCK,MOSI,MISO
(20% VDD to 70% VDD, CL = 200pF) Inputs: SCK,MOSI,MISO,SS
100
100
ns
µs
13
tFall
Fall time
Outputs: SCK,MOSI,MISO
(70% VDD to 20% VDD, CL = 200pF) Inputs: SCK,MOSI,MISO,SS
100
100
ns
µs
tCPU
ns
Figure 65. SPI Master Timing Diagram CPHA=0, CPOL=0 2)
SS
(INPUT)
1
SCK
(OUTPUT)
4
MISO
(INPUT)
MOSI
(OUTPUT)
6
10
D7-IN
7
D7-OUT
11
13
12
5
D6-IN
D6-OUT
D0-IN
D0-OUT
VR000109
Notes:
1) Data based on characterization results, not tested in production.
2) Measurement points are VOL, VOH, VIL and VIH in the SPI timing diagram
123/132
ST72141K
MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d)
Figure 66. SPI Master Timing Diagram CPHA=0, CPOL=1 1)
SS
(INPUT)
1
13
SCK
(OUTPUT)
5
MISO
(INPUT)
6
MOSI
(OUTPUT)
10
12
4
D7-IN
7
D6-IN
D7-OUT
11
D0-IN
D6-OUT
D0-OUT
VR000110
Figure 67. SPI Master Timing Diagram CPHA=1, CPOL=0 1)
SS
(INPUT)
1
13
SCK
(OUTPUT)
4
MISO
(INPUT)
5
D7-OUT
6
MOSI
(OUTPUT)
12
10
D6-OUT
D0-OUT
7
D6-IN
D7-IN
11
D0-IN
VR000107
Figure 68. SPI Master Timing Diagram CPHA=1, CPOL=1
SS
(INPUT)
1)
1
12
SCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
5
13
4
6
10
D7-IN
7
D7-OUT
11
D6-IN
D6-OUT
D0-IN
D0-OUT
VR000108
Note:
1) Measurement points are VOL, VOH, VIL and VIH in the SPI timing diagram
124/132
ST72141K
MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d)
Measurement points are V OL, VOH, VIL and VIH in the SPI Timing Diagram
Figure 69. SPI Slave Timing Diagram CPHA=0, CPOL=0 1)
SS
(INPUT)
2
1
4
MISO HIGH-Z
(OUTPUT)
8
MOSI
(INPUT)
3
12
13
SCK
(INPUT)
5
D7-OUT
D6-OUT
10
D0-OUT
11
D7-IN
9
D6-IN
D0-IN
7
6
VR000113
Figure 70. SPI Slave Timing Diagram CPHA=0, CPOL=1 1)
SS
(INPUT)
2
1
13
12
SCK
(INPUT)
4
5
HIGH-Z
MISO
(OUTPUT)
8
MOSI
(INPUT)
3
D7-OUT
D6-OUT
10
D0-OUT
11
D7-IN
9
D6-IN
D0-IN
7
6
VR000114
Figure 71. SPI Slave Timing Diagram CPHA=1, CPOL=0 1)
SS
(INPUT)
2
SCK
(INPUT)
HIGH-Z
MISO
(OUTPUT)
1
4
13
3
5
D7-OUT
D6-OUT
8
D7-IN
D0-OUT
9
11
10
MOSI
(INPUT)
12
D6-IN
D0-IN
7
6
VR000111
Figure 72. SPI Slave Timing Diagram CPHA=1, CPOL=1 1)
SS
(INPUT)
2
SCK
(INPUT)
HIGH-Z
MISO
(OUTPUT)
MOSI
(INPUT)
1
5
12
3
4
D7-OUT
8
D6-OUT
D7-IN
D0-OUT
11
10
6
13
D6-IN
9
D0-IN
7
VR000112
Note:
1) Measurement points are VOL, VOH, VIL and VIH in the SPI timing diagram
125/132
ST72141K
MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d)
ADC Analog to Digital Converter (8-bit)
Symbol
|TUE|
Parameter
Total unadjusted error
Conditions
OE
Offset error
Gain Error 3)
Typ 1)
3)
|DLE|
Differential linearity error
|ILE|
Integral linearity error 3)
Max
Unit
2
3)
GE
Min
3)
VAIN
Conversion range voltage
IADC
A/D conversion supply current
tSTAB
Stabilization time after ADC enable
TA=25°C,VDD=VDDA=5V,2)
fCPU=8MHz
-1
1
-2
2
LSB
1
2
VSSA
VDDA
1
30
fADC=fCPU=4MHz
VDD=VDDA=5V
V
mA
µs
8
32
µs
1/fADC
8
32
µs
1/fADC
tLOAD
Sample capacitor loading time
tCONV
Hold conversion time
RAIN
External input resistor
20 4)
kΩ
RADC
Internal input resistor
18
kΩ
22
pF
CSAMPLE Sample capacitor
Notes:
1) Unless otherwise specified, typical data is based on TA=25°C and VDD-VSS=5V. This data is provided only for design
guidelines and is not tested.
2) Tested in production at TA=25°C, characterized over all temperature range.
3) ADC Accuracy vs. Negative Injection Current:
For IINJ-=0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is a loss of 1 LSB
by 10KΩ increase of the external analog source impedance.
These measurement results and recommendations have been done under worst conditions for injection:
- negative injection
- injection to an Input with analog capability, adjacent to the enabled Analog Input
- at 5V VDD supply, and worst case temperature.
4) Data based on characterization results, not tested in production.
126/132
ST72141K
MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d)
VDD
Sampling
Switch
VT = 0.6V
RAIN
VAIN
Cpin
VT
= input capacitance
= threshold voltage
SS
= sampling switch
RSS
SS
Px.x/AINx
2ΚΩ
Cpin
5pF
Chold
6 pF
VT = 0.6V
leakage
±1µA
VSS
Chold
= sample/hold
capacitance
leakage = leakage current
at the pin due
to various junctions
Digital Result ADCDR
GE
255
254
253
1LSB
i deal
V
–V
DDA
SSA
= ----------------------------------------256
(2)
(3)
TUE
7
(1)
6
5
4
ILE
OE
3
DLE
2
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
TUE=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
OE=Offset Error: deviation between the first actual
transition and the first ideal one.
GE=Gain Error: deviation between the last ideal
transition and the last actual one.
DLE=Differential Linearity Error: maximum deviation between actual steps and the ideal one.
ILE=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
1 LSB (ideal)
1
0
1
VSSA
Vin (LSBideal)
2
3
4
5
6
7
253 254 255 256
VDDA
127/132
ST72141K
11 GENERAL INFORMATION
11.1 PACKAGE MECHANICAL DATA
Figure 73. 32-Pin Plastic Dual In-Line Package, Shrink 400-mil Width
Dim.
E
A1
L
C
b
b2
e
inches
Typ
A
3.56
3.76 5.08 0.140 0.148 0.200
A1
0.51
0.020
A2
3.05
3.56 4.57 0.120 0.140 0.180
eC
A2 A
mm
Min
Max
Min
Typ
Max
b
0.36
0.46 0.58 0.014 0.018 0.023
E1
b1
0.76
1.02 1.40 0.030 0.040 0.055
eA
eB
C
0.20
0.25 0.36 0.008 0.010 0.014
D
27.43
28.45 1.080 1.100 1.120
E
9.91 10.41 11.05 0.390 0.410 0.435
E1
7.62
D
8.89 9.40 0.300 0.350 0.370
e
1.78
0.070
eA
10.16
0.400
eB
12.70
0.500
eC
1.40
0.055
L
2.54
3.05 3.81 0.100 0.120 0.150
Number of Pins
N
32
Figure 74. 34-Pin Plastic Small Outline Package, Shrink 300-mil Width
Dim.
h x 45×
L
A1
A
C
a
B
e
D
mm
Min
H
inches
Max
Min
Typ
A
2.464
2.642 0.097
0.104
0.127
0.292 0.005
0.012
B
0.356
0.483 0.014
0.019
C
0.231
0.318 0.009
0.013
D
17.72
9
18.05
0.698
9
0.711
E
7.417
7.595 0.292
0.299
1.016
0.040
H
10.16
0
10.41
0.400
4
0.410
0.737 0.025
0.029
h
0.635
α
0°
L
0.610
8°
0°
1.016 0.024
Number of Pins
N
128/132
Max
A1
e
E
Typ
34
8°
0.040
ST72141K
11.2 ORDERING INFORMATION
Transfer Of Customer Code
Customer code is made up of the ROM contents
and the list of the selected options (if any). The
ROM contents are to be sent on diskette, or by
electronic means, with the hexadecimal file generated by the development tool. All unused bytes
must be set to FFh.
The selected options are communicated to STMicroelectronics using the correctly completed OPTION LIST appended.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on contractual points.
Figure 75. ROM Factory Coded Device Types
TEMP.
DEVICE PACKAGE RANGE / XXX
Code name (defined by STMicroelectronics)
6= industrial -40 to +85 °C
3= automotive -40 to +125 °C
B= Plastic DIP
M= Plastic SOIC
ST72141K2
Figure 76. OTP User Programmable Device Types
TEMP.
DEVICE PACKAGE RANGE
XXX
Code name (defined by STMicroelectronics)
6= industrial -40 to +85 °C
3= automotive -40 to +125 °C
B= Plastic DIP
M= Plastic SOIC
ST72T141K2
129/132
ST72141K
MICROCONTROLLER OPTION LIST
Customer
Address
.............................
.............................
.............................
Contact
.............................
Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STMicroelectronics references
Device:
[ ] ST72141K2
Package:
[ ] SO34
[ ] SDIP32
Conditioning:
[ ] Tube
[ ] Tape & Reel (not available for SDIP packages)
Temperature Range:
[ ] -40 to 85°C
[ ] -40 to 125°C
Readout Protection:
[ ] Enabled
[ ] Disabled
Special Marking:
[ ] No
[ ] Yes "_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _"
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Maximum character count:
DIP32
10
SO34
13
Comments
Notes
Signature
Date
130/132
:
.............................
.............................
.............................
ST72141K
12 SUMMARY OF CHANGES
Description of the changes between the current release of the specification and the previous one.
Rev.
Main Changes
Date
Added VtPOR in section 10.6.1 on page 121
1.8
Modified VMTChyst and Voffset in section 10.7 on page 122
Oct 01
Modified Option list in Section 11.2
131/132
ST72141K
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2002 STMicroelectronics - All Rights Reserved.
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
132/132