STC Very Low Power/Voltage CMOS SRAM 128K X 16 bit STC62WV12816 FEATURES • Wide Vcc operation voltage : 2.4V ~ 5.5V • Very low power consumption : Vcc = 3.0V C-grade: 29mA (@55ns) operating current I -grade: 30mA (@55ns) operating current C-grade: 24mA (@70ns) operating current I -grade: 25mA (@70ns) operating current 0.3uA(Typ.) CMOS standby current Vcc = 5.0V C-grade: 60mA (@55ns) operating current I -grade: 62mA (@55ns) operating current C-grade: 53mA (@70ns) operating current I -grade: 55mA (@70ns) operating current 1.0uA(Typ.) CMOS standby current • High speed access time : -55 55ns -70 70ns • Automatic power down when chip is deselected • Three state outputs and TTL compatible PRODUCT FAMILY PRODUCT FAMILY OPERATING TEMPERATURE STC62WV12816DC STC62WV12816EC +0 O C to +70 O C STC62WV12816AC STC62WV12816DI STC62WV12816EI -40 O C to +85 O C STC62WV12816AI Vcc RANGE • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE and OE options • I/O Configuration x8/x16 selectable by LB and UB pin DESCRIPTION The STC62WV12816 is a high performance , very low power CMOS Static Random Access Memory organized as 131,072 words by 16 bits and operates from a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.3uA at 3.0V /25oC and maximum access time of 55ns at 3.0V / 85oC. Easy memory expansion is provided by active LOW chip enable (CE), active LOW output enable(OE) and three-state output drivers. The STC62WV12816 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The STC62WV12816 is available in DICE form , JEDEC standard 44-pin TSOP Type II package and 48-ball BGA package. SPEED ( ns ) A4 A3 A2 A1 A0 CE DQ0 DQ1 DQ2 DQ3 VCC GND DQ4 DQ5 DQ6 DQ7 WE A16 A15 A14 A13 A12 1 Vcc=3.0V Vcc=5.0V Vcc=3.0V 70ns 2.4V ~5.5V 55/70 3.0uA 10uA 24mA 53mA 2.4V ~ 5.5V 55/70 5.0uA 30uA 25mA 55mA 3 Vcc=5.0V 70ns DICE TSOP2-44 BGA-48-0608 DICE TSOP2-44 BGA-48-0608 BLOCK DIAGRAM 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 62WV12816EC 62WV12816EI 2 PKG TYPE ( ICC, Max ) 55ns: 3.0~5.5V 70ns: 2.7~5.5V PIN CONFIGURATIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 POWER DISSIPATION STANDBY Operating ( ICCSB1, Max ) 4 5 A5 A6 A7 OE UB LB DQ15 DQ14 DQ13 DQ12 GND VCC DQ11 DQ10 DQ9 DQ8 NC A8 A9 A10 A11 NC A8 A13 A15 Address A16 A14 A12 Input Buffer A7 OE A0 A1 A2 N.C. B D8 UB A3 A4 CE D0 Memory Array Decoder 1024 x 2048 2048 16 DQ0 . . . . . . . . Data Input Buffer 16 Column I/O Write Driver Sense Amp 16 Data Output Buffer DQ15 LB 1024 Row A6 A5 A4 6 A 20 128 16 Column Decoder 14 CE WE C D9 D10 A5 A6 D1 D2 OE UB LB D VSS D11 N.C. A7 D3 VCC E VCC D12 N.C. A16 D4 VSS F D14 D13 A14 A15 D5 D6 G D15 N.C. A12 A13 WE D7 H N.C. A8 A9 A10 A11 N.C. Control Address Input Buffer A11 A9 A3 A2 A1 A0 A10 Vcc Gnd STC International Limited. reserves the right to modify document contents without notice. R0201-STC62WV12816 1 Revision 1.1 Jan. 2004 STC STC62WV12816 PIN DESCRIPTIONS Name Function A0-A16 Address Input These 17 address inputs select one of the 131,072 x 16-bit words in the RAM. CE Chip Enable Input CE is active LOW. Chip enables must be active when data read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. LB and UB Data Byte Control Input Lower byte and upper byte data input/output control pins. DQ0 - DQ15 Data Input/Output Ports These 16 bi-directional ports are used to read data from or write data into the RAM. Vcc Power Supply Gnd Ground TRUTH TABLE MODE Not selected (Power Down) Output Disabled Read Write R0201-STC62WV12816 CE H WE OE LB UB D0~D7 D8~D15 Vcc CURRENT X X X X High Z High Z ICCSB , I CCSB1 X X X H H High Z L L X H X H H X H X High Z High Z High Z High Z ICCSB , I CCSB1 ICC High Z ICC L L Dout Dout ICC H L High Z Dout ICC L L H L L X L H Dout High Z ICC L L Din Din ICC H L X Din ICC L H Din X ICC 2 Revision 1.1 Jan. 2004 STC STC62WV12816 ABSOLUTE MAXIMUM RATINGS(1) SYMBOL PARAMETER OPERATING RANGE RATING UNITS -0.5 to Vcc+0.5 V V TERM Terminal Voltage with Respect to GND T BIAS Temperature Under Bias -40 to +85 O T STG Storage Temperature -60 to +150 O PT Power Dissipation 1.0 W I OUT DC Output Current 20 mA RANGE AMBIENT TEMPERATURE Vcc Commercial 0 O C to +70 O C 2.4V ~ 5.5V Industrial -40 O C to +85 O C 2.4V ~ 5.5V C C CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. SYMBOL CIN CDQ PARAMETER Input Capacitance Input/Output Capacitance CONDITIONS MAX. UNIT VIN=0V 6 pF VI/O=0V 8 pF 1. This parameter is guaranteed and not 100% tested. DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC ) PARAMETER NAME PARAMETER V IL Guaranteed Input Low (3) Voltage Vcc =5.0V V IH Guaranteed Input High (3) Voltage Vcc =3.0V 2.0 Vcc =5.0V 2.2 IIL Input Leakage Current Vcc = Max, VIN = 0V to Vcc ILO Output Leakage Current Vcc = Max,CE = V IH or OE = V IH, V I/O = 0V to Vcc V OL Output Low Voltage Vcc = Max, IOL = 2.0mA V OH Output High Voltage Vcc = Min, IOH = -1.0mA Operating Power Supply Current CE = V IL, (2) IDQ = 0mA, F = Fmax Standby Current-TTL CE=V IH IDQ = 0mA TEST CONDITIONS Vcc =3.0V MIN. TYP. (1) MAX. UNITS -0.5 -- 0.8 V -- V cc+0.3 V -- -- 1 uA -- -- 1 uA -- -- 0.4 V 2.4 -- -- V -- -- -- -- Vcc =3.0V Vcc =5.0V Vcc =3.0V ICC (5) ICCSB ICCSB1 (4) Standby Current-CMOS Vcc =5.0V Vcc =3V 70ns Vcc =5V 70ns Vcc =3.0V mA 0.5 Vcc =5.0V CE ≧ V cc-0.2V, V IN≧V cc-0.2V or V IN≦0.2V 25 55 mA 1.0 Vcc =3.0V -- Vcc =5.0V 0.3 5 1.0 30 uA 1. Typical characteristics are at TA = 25oC. 2. Fmax = 1/tRC. 3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 4.IccsB1_Max. is 3uA / 10uA at Vcc=3V / 5V and TA=70oC. 5. Icc_Max. is 30mA(@3V) / 62mA(@5V) under 55ns operation. DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85oC ) SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS Vcc for Data Retention CE ≧ Vcc - 0.2V VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V 1.5 -- -- V ICCDR Data Retention Current CE ≧ Vcc - 0.2V VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V -- 0.1 1.0 uA tCDR Chip Deselect to Data Retention Time -- -- ns -- -- ns VDR (3) tR See Retention Waveform Operation Recovery Time 1. Vcc = 1.5V, TA = + 25 C O R0201-STC62WV12816 0 TRC 2. tRC = Read Cycle Time 3 (2) 3. IccDR_MAX. is 0.7uA at TA=70oC. Revision 1.1 Jan. 2004 STC STC62WV12816 LOW VCC DATA RETENTION WAVEFORM ( CE Controlled ) Data Retention Mode Vcc VDR ≥ 1.5V Vcc Vcc tR t CDR CE ≥ Vcc - 0.2V VIH CE VIH KEY TO SWITCHING WAVEFORMS AC TEST CONDITIONS (Test Load and Input/Output Reference) Input Pulse Levels Vcc / 0V Input Rise and Fall Times 1V/ns WAVEFORM Input and Output Timing Reference Level 0.5Vcc Output Load CL = 100pF+1TTL CL = 30pF+1TTL INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H , DON T CARE: ANY CHANGE PERMITTED CHANGE : STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC ) READ CYCLE JEDEC PARAMETER NAME PARAMETER NAME tAVAX tRC tAVQV tAA tELQV tACS Chip Select Access Time (CE) -- -- 55 -- -- 70 ns tBA tBA (1) Data Byte Control Access Time (LB,UB) -- -- 30 -- -- 35 ns -- -- 30 -- -- 35 ns CYCLE TIME : 55ns CYCLE TIME : 70ns MIN. TYP. MAX. MIN. TYP. MAX. Read Cycle Time 55 -- -- 70 -- -- ns Address Access Time -- -- 55 -- -- 70 ns DESCRIPTION (Vcc = 2.7~5.5V) (Vcc = 3.0~5.5V) UNIT tGLQV tOE Output Enable to Output Valid t E1LQX tCLZ Chip Select to Output Low Z (CE) 10 -- -- 10 -- -- ns tBE tBE Data Byte Control to Output Low Z (LB,UB) 10 -- -- 10 -- -- ns tGLQX tOLZ Output Enable to Output in Low Z 5 -- -- 5 -- -- ns tEHQZ tCHZ Chip Deselect to Output in High Z (CE) -- -- 30 -- -- 35 ns tBDO tBDO Data Byte Control to Output High Z (LB,UB) tGHQZ tOHZ Output Disable to Output in High Z tAXOX tOH Data Hold from Address Change -- -- 30 -- -- 35 ns -- -- 25 -- -- 30 ns 10 -- -- 10 -- -- ns NOTE : 1. tBA is 30ns/35ns (@speed=55ns/70ns) with address toggle. ; tBA is 55ns/70ns (@speed=55ns/70ns) without address toggle. R0201-STC62WV12816 4 Revision 1.1 Jan. 2004 STC STC62WV12816 SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) t RC ADDRESS t t t OH AA OH D OUT READ CYCLE2 (1,3,4) CE t ACS t BA LB,UB t BE t D OUT READ CYCLE3 t BDO (5) CLZ t (5) CHZ (1,4) t RC ADDRESS t AA OE t OH t OE t OLZ CE (5) t CLZ t t OHZ (5) t CHZ(1,5) ACS t BA LB,UB t BE t BDO D OUT NOTES: 1. WE is high for read Cycle. 2. Device is continuously selected when CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL . 5. The parameter is guaranteed but not 100% tested. R0201-STC62WV12816 5 Revision 1.1 Jan. 2004 STC STC62WV12816 AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC ) WRITE CYCLE JEDEC PARAMETER NAME PARAMETER NAME tAVAX tE1LWH tAVWL tAVWH tWLWH tWHAX tBW tWLQZ tDVWH tWHDX tGHQZ t WC t CW t AS t AW t WP t WR t BW (1) t WHZ t DW t DH t OHZ tWHOX t OW Write Cycle Time Chip Select to End of Write CYCLE TIME : 55ns CYCLE TIME : 70ns MIN. TYP. MAX. MIN. TYP. MAX. (Vcc = 2.7~5.5V) (Vcc = 3.0~5.5V) DESCRIPTION (CE) Address Setup Time UNIT 55 -- -- 70 -- -- ns 55 -- -- 70 -- -- ns 0 -- -- 0 -- -- ns Address Valid to End of Write 55 -- -- 70 -- -- ns Write Pulse Width 30 -- -- 35 -- -- ns (CE,WE) 0 -- -- 0 -- -- ns (LB,UB) 25 -- -- 30 -- -- ns -- -- 25 -- -- 30 ns 25 -- -- 30 -- -- ns Data Hold from Write Time 0 -- -- 0 -- -- ns Output Disable to Output in High Z -- -- 25 -- -- 30 ns End of Write to Output Active 5 -- -- 5 -- -- ns Write recovery Time Date Byte Control to End of Write Write to Output in High Z Data to Write Time Overlap NOTE : 1. tBW is 25ns/30ns (@speed=55ns/70ns) with address toggle. ; tBW is 55ns/70ns (@speed=55ns/70ns) without address toggle. SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) t WC ADDRESS (3) t WR OE (11) t CW (5) CE t BW LB,UB t AW WE (3) t WP t AS (2) (4,10) t OHZ D OUT t DH t DW D IN R0201-STC62WV12816 6 Revision 1.1 Jan. 2004 STC STC62WV12816 WRITE CYCLE2 (1,6) t WC ADDRESS (11) t CW (5) CE t BW LB,UB t AW WE t WR t WP (3) (2) t AS (4,10) t WHZ D OUT t OW t DH (7) (8) t DW (8,9) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE going low to the end of write. R0201-STC62WV12816 7 Revision 1.1 Jan. 2004 STC STC62WV12816 ORDERING INFORMATION STC62WV12816 X X Z YY SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green P: Pb free GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE E: TSOP2-44 A: BGA-48-0608 D: DICE Note: STC (STC International Limited.) assumes no responsibility for the application or use of any product or circuit described herein. STC does not authorize its products for use as critical components in any application in which the failure of the STC product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. PACKAGE DIMENSIONS NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 1.4 Max. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. BALL PITCH e = 0.75 D E N D1 E1 8.0 6.0 48 5.25 3.75 E1 e D1 VIEW A 48 mini-BGA (6 x 8) R0201-STC62WV12816 8 Revision 1.1 Jan. 2004 STC STC62WV12816 PACKAGE DIMENSIONS TSOP2-44 R0201-STC62WV12816 9 Revision 1.1 Jan. 2004