TC74HCT573AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HCT573AP,TC74HCT573AF Octal D-Type Latch with 3-State Output The TC74HCT573A is a high speed CMOS OCTAL LATCH with 3-STATE OUTPUT fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. Its inputs are compatible with TTL, NMOS, and CMOS output voltage levels. Its 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input ( OE ). When the OE input is high, the eight outputs are in a high impedance state. All inputs are equipped with protection circuits against static discharge or transient excess voltage. TC74HCT573AP TC74HCT573AF Features • High speed: tpd = 18 ns (typ.) at VCC = 5 V • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C • Compatible with TTL outputs: VIL = 0.8 V (max) VIH = 2.0 V (min) • Output drive capability: 15 LSTTL loads • • Symmetrical output impedance: |IOH| = IOL = 6 mA (min) ∼ tpHL Balanced propagation delays: tpLH − • Pin and function compatible with 74LS573 Weight DIP20-P-300-2.54A SOP20-P-300-1.27A : 1.30 g (typ.) : 0.22 g (typ.) Pin Assignment 1 2007-10-01 TC74HCT573AP/AF IEC Logic Symbol Truth Table Inputs Output OE LE D Q H X X Z L L X Qn L H L L L H H H X: Don’t care Z: High impedance Qn: Q outputs are latched at the time when the LE input is taken to a low logic level. System Diagram 2 2007-10-01 TC74HCT573AP/AF Absolute Maximum Ratings (Note 1) Characteristics Supply voltage range Symbol Rating Unit VCC −0.5~7 V VIN −0.5~VCC + 0.5 V VOUT −0.5~VCC + 0.5 V Input diode current IIK ±20 mA Output diode current IOK ±20 mA DC output current IOUT ±35 mA DC VCC/ground current ICC ±75 mA Power dissipation PD 500 (DIP) (Note 2)/180 (SOP) mW Storage temperature Tstg −65~150 °C DC input voltage DC output voltage Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: 500 mW in the range of Ta = −40 to 65°C. From Ta = 65 to 85°C a derating factor of −10 mW/°C shall be applied until 300 mW. Operating Ranges (Note) Characteristics Supply voltage Input voltage Symbol Rating Unit VCC 4.5~5.5 V VIN 0~VCC V VOUT 0~VCC V Operating temperature Topr −40~85 °C Input rise and fall time tr, tf 0~500 ns Output voltage Note: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. Electrical Characteristics DC Characteristics Characteristics Symbol Ta = 25°C Test Condition Ta = −40~85°C VCC (V) Min Typ. Max Min Max Unit High-level input voltage VIH ⎯ 4.5~5.5 2.0 ⎯ ⎯ 2.0 ⎯ V Low-level input voltage VIL ⎯ 4.5~5.5 ⎯ ⎯ 0.8 ⎯ 0.8 V High-level output voltage VOH IOH = −20 μA VIN = VIH or VIL I OH = −6 mA 4.5 4.4 4.5 ⎯ 4.4 ⎯ 4.5 4.18 4.31 ⎯ 4.13 ⎯ Low-level output voltage VOL IOL = 20 μA VIN = VIH or VIL I = 6 mA OL 4.5 ⎯ 0.0 0.1 ⎯ 0.1 4.5 ⎯ 0.17 0.26 ⎯ 0.33 3-state output off-state current IOZ 5.5 ⎯ ⎯ ±0.5 ⎯ ±5.0 μA Input leakage current IIN VIN = VCC or GND 5.5 ⎯ ⎯ ±0.1 ⎯ ±1.0 μA ICC VIN = VCC or GND 5.5 ⎯ ⎯ 4.0 ⎯ 40.0 μA Per input: VIN = 0.5 V or 2.4 V Other input: VCC or GND 5.5 ⎯ ⎯ 2.0 ⎯ 2.9 mA Quiescent supply current IC VIN = VIH or VIL VOUT = VCC or GND 3 V V 2007-10-01 TC74HCT573AP/AF Timing Requirements (input: tr = tf = 6 ns) Characteristics Symbol Minimum pulse width (LE) tW (H) ⎯ ts ⎯ th ⎯ Minimum set-up time (data) Minimum hold time (data) Ta = 25°C Test Condition Ta = −40 ~85°C VCC (V) Typ. Limit Limit 4.5 ⎯ 15 19 5.5 ⎯ 14 17 4.5 ⎯ 10 13 5.5 ⎯ 9 11 4.5 ⎯ 5 5 5.5 ⎯ 5 5 Unit ns ns ns AC Characteristics (input: tr = tf = 6 ns) Characteristics Output transition time (LE-Q) tpHL Propagation delay time tpLH (D-Q) tpHL Output disable time Input capacitance Output capacitance Power dissipation capacitance Note: ⎯ tTHL tpLH Output enable time CL (pF) VCC (V) tTLH Propagation delay time tpZL tpZH tpLZ tpHZ Ta = 25°C Test Condition Symbol 50 50 ⎯ 150 50 ⎯ 150 50 RL = 1 kΩ 150 RL = 1 kΩ 50 Ta = −40~85°C Min Typ. Max Min Max 4.5 ⎯ 7 12 ⎯ 15 5.5 ⎯ 6 11 ⎯ 14 4.5 ⎯ 19 29 ⎯ 36 5.5 ⎯ 17 26 ⎯ 33 4.5 ⎯ 24 37 ⎯ 46 5.5 ⎯ 22 34 ⎯ 43 4.5 ⎯ 17 26 ⎯ 33 5.5 ⎯ 14 23 ⎯ 29 4.5 ⎯ 22 34 ⎯ 43 5.5 ⎯ 20 31 ⎯ 39 4.5 ⎯ 18 27 ⎯ 34 5.5 ⎯ 15 24 ⎯ 30 4.5 ⎯ 23 35 ⎯ 44 5.5 ⎯ 20 32 ⎯ 40 4.5 ⎯ 18 24 ⎯ 30 5.5 ⎯ 16 22 ⎯ 28 Unit ns ns ns ns ns CIN ⎯ ⎯ 5 10 ⎯ 10 pF COUT ⎯ ⎯ 10 ⎯ ⎯ ⎯ pF ⎯ ⎯ 38 ⎯ ⎯ ⎯ pF CPD (Note) CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD･VCC･fIN + ICC And the total CPD when n pcs. of latch operate can be gained by the following equation: CPD (total) = 25 + 13･n 4 2007-10-01 TC74HCT573AP/AF Package Dimensions Weight: 1.30 g (typ.) 5 2007-10-01 TC74HCT573AP/AF Package Dimensions Weight: 0.22 g (typ.) 6 2007-10-01 TC74HCT573AP/AF RESTRICTIONS ON PRODUCT USE 20070701-EN GENERAL • The information contained herein is subject to change without notice. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. 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Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. 7 2007-10-01