TI TL7759CDR

TL7759
SUPPLY-VOLTAGE SUPERVISORS
SLVS042D – JANUARY 1991 – REVISED JULY 1999
D
D
D
D
D
D
D
D, P, OR PW PACKAGE
(TOP VIEW)
Power-On Reset Generator
Automatic Reset Generation After Voltage
Drop
Precision Input Threshold
Voltage . . . 4.55 V ±120 mV
Low Standby Current . . . 20 µA
Reset Outputs Defined When VCC
Exceeds 1 V
True and Complementary Reset Outputs
Wide Supply-Voltage Range . . . 1 V to 7 V
NC
NC
NC
GND
1
8
2
7
3
6
4
5
RESET
RESET
NC
VCC
NC – No internal connection
description
The TL7759 is a supply-voltage supervisor designed for use as a reset controller in microcomputer and
microprocessor systems. The supervisor monitors the supply voltage for undervoltage conditions. During power
up, when the supply voltage, VCC, attains a value approaching 1 V, the RESET and RESET outputs become
active (high and low, respectively) to prevent undefined operation. If the supply voltage drops below the input
threshold voltage level (VIT– ), the reset outputs go to the reset active state until the supply voltage has returned
to its nominal value (see timing diagram).
The TL7759C is characterized for operation from 0°C to 70°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SMALL
OUTLINE
(D)
PLASTIC
DIP
(P)
SHRINK
SMALL
OUTLINE
(PW)
CHIP
FORM
(Y)
0°C to 70°C
TL7759CD
TL7759CP
TL7759CPW
TL7759Y
The D and PW packages are available taped and reeled. Add the suffix R to
the device type (e.g., TL7759CDR). Chip forms are tested at 25°C.
functional block diagram
5
+
7
–
8
VCC
RESET
RESET
Reference
Voltage
4
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TL7759
SUPPLY-VOLTAGE SUPERVISORS
SLVS042D – JANUARY 1991 – REVISED JULY 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
Off-state output voltage range: RESET voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 20 V
RESET voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 20 V
Low-level output current, IOL (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
High-level output current, IOH (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10 mA
Package thermal impedance, θJA (see Notes 2 and 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
P package . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the network ground terminal.
2. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can impact reliability.
3. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions
Supply voltage, VCC
MIN
MAX
1
7
15
Transistor off RESET voltage
Output voltage,
voltage VO (see Note 4)
Transistor off RESET voltage
Low-level output current, IOL
RESET
High-level output current, IOH
RESET
Operating free-air temperature, TA
TL7759C
0
0
UNIT
V
V
24
mA
–8
mA
70
°C
NOTE 4: RESET output must not be pulled down below GND potential.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TL7759C
PARAMETER
VOL
VOH
TEST CONDITIONS
Low-level output voltage
RESET
High-level output voltage
RESET
IOL = 24 mA
IOH = –8 mA
VCC = 4
4.3
3V
VIT
IT–
Input threshold voltage
g
(negative-going VCC)
TA = 25°C
TA = 0°C to 70°C
Vres§
Power up reset voltage
Power-up
RL = 2.2
2 2 kΩ
Vhys¶
Hysteresis at VCC input
TA = 25°C
TA = 0°C to 70°C
IOH
IOL
High-level output current
RESET
Low-level output current
RESET
ICC
Supply current
MIN
VCC–1
4.43
TYP‡
MAX
0.4
0.8
4.55
4.67
4.7
0.8
1
1.2
40
50
60
30
VCC = 7 V
V, See Figure 1
VOH = 15 V
VOL = 0 V
No load
VCC = 4.3 V
VCC = 5.5 V
70
1400
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V
V
mV
1
µA
–1
µA
2000
‡ Typical values are at TA = 25°C.
§ This is the lowest voltage at which RESET becomes active, VCC slew rate ≤ 5 V/µs.
¶ This is the difference between positive-going input threshold voltage, VIT+, and negative-going input threshold voltage, VIT–.
2
V
V
4.4
TA = 25°C
TA = 0°C to 70°C
UNIT
40
µA
TL7759
SUPPLY-VOLTAGE SUPERVISORS
SLVS042D – JANUARY 1991 – REVISED JULY 1999
electrical characteristics, TA = 25°C (unless otherwise noted)
TL7759Y
PARAMETER
TEST CONDITIONS
VOL
Low-level output voltage
VIT–
Vres†
Input threshold voltage (negative-going VCC)
RESET
Power-up reset voltage
VCC = 4.3 V,
MIN
IOL = 24 mA
RL = 2.2 kΩ
TYP
MAX
UNIT
0.4
V
4.55
V
0.8
V
Vhys‡
Hysteresis at VCC input
50
ICC
Supply current
VCC = 4.3 V,
No load
1400
† This is the lowest voltage at which RESET becomes active, VCC slew rate ≤ 5 V/µs.
‡ This is the difference between positive-going input threshold voltage, VIT+, and negative-going input threshold voltage, VIT–.
mV
µA
timing diagram
VCC
VIT+
Vres
VIT–
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
0
RESET
Output Undefined
for VCC Less Than 1 V
VIT –
Vres
VIT+
0
Output Undefined
switching characteristics at TA = 25°C (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
TL7759C
MIN
MAX
UNIT
tPLH
Propagation delay time, low-to high-level output
VCC
RESET
See Figures 2 and 3§
5
µs
tPHL
Propagation delay time, high-to low-level output
VCC
RESET
See Figures 2 and 4
5
µs
tr
Rise time
RESET
See Figures 2 and 4§
1
µs
tf
Fall time
RESET
See Figures 2 and 4
1
µs
tw(min)
Minimum pulse duration
RESET
See Figures 2 and 4
VCC
5
µs
§ VCC slew rate ≤ 5 V/µs
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• DALLAS, TEXAS 75265
3
TL7759
SUPPLY-VOLTAGE SUPERVISORS
SLVS042D – JANUARY 1991 – REVISED JULY 1999
PARAMETER MEASUREMENT INFORMATION
15 V
VCC
RESET
+
7V
A
TL7759
_
RESET
GND
A
Figure 1. Test Circuit for Output Leakage Current
4.8 V
VCC
(see Note A)
4.3 V
tPLH
tPHL
90%
90%
RESET
50%
50%
10%
10%
tr
tf
NOTE A: VCC slew rate ≤ 5 V/µs.
Figure 2. Switching Diagram
VCC
Pulse
Generator
TL7759
0.1 mF
RESET
GND
RL = 1 kΩ
CL = 100 pF†
† CL Includes jig and probe capacitance.
Figure 3. Test Circuit for RESET Output Switching Characteristics
VCC
Pulse
Generator
0.1 mF
RL= 1k Ω
RESET
TL7759
GND
CL = 100 pF†
† CL Includes jig and probe capacitance.
Figure 4. Test Circuit for RESET Output Switching Characteristics
4
POST OFFICE BOX 655303
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TL7759
SUPPLY-VOLTAGE SUPERVISORS
SLVS042D – JANUARY 1991 – REVISED JULY 1999
APPLICATION INFORMATION
5V
0.1 µF
5
VCC
RESET
7
System Reset
TL7759
RESET
8
1 kΩ
GND
4
Figure 5. Power-Supply System Reset Generation
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5
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TL7759CD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL7759CDE4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL7759CDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL7759CDRE4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL7759CP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TL7759CPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TL7759CPSR
ACTIVE
SO
PS
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL7759CPSRE4
ACTIVE
SO
PS
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL7759CPW
ACTIVE
TSSOP
PW
8
150
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL7759CPWE4
ACTIVE
TSSOP
PW
8
150
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL7759CPWLE
OBSOLETE
TSSOP
PW
8
TL7759CPWR
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL7759CPWRE4
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TBD
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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