TL7770-5, TL7770-12 DUAL POWER-SUPPLY SUPERVISORS SLVS019F – OCTOBER 1987 – REVISED JULY 1999 D D D D D D D D D D Power-On Reset Generator Automatic Reset Generation After Voltage Drop RESET Defined When VCC Exceeds 1 V Wide Supply-Voltage Range . . . 3.5 V to 18 V Precision Overvoltage and Undervoltage Sensing 250-mA Peak Output Current for Driving SCR Gates 2-mA Active-Low SCR Gate Drive for False-Trigger Protection Temperature-Compensated Voltage Reference True and Complementary Reset Outputs Externally Adjustable Output Pulse Duration DW OR N PACKAGE (TOP VIEW) 1RESIN 1CT 1RESET 1RESET 1VSU 1VSO 1SCR DRIVE GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 2RESIN 2CT 2RESET 2RESET 2VSU 2VSO 2SCR DRIVE description The TL7770 is an integrated-circuit system supervisor designed for use as a reset controller in microcomputer and microprocessor power-supply systems. This device contains two independent supply-voltage supervisors that monitor the supplies for overvoltage and undervoltage conditions at the VSO and VSU terminals, respectively. When VCC attains the minimum voltage of 1 V during power up, the RESET output becomes active (low). As VCC approaches 3.5 V, the time-delay function activates, latching RESET and RESET active (high and low, respectively) for a time delay (td) after system voltages have achieved normal levels. Above VCC = 3.5 V, taking RESIN low activates the time-delay function during normal system-voltage levels. To ensure that the microcomputer system has reset, the outputs remain active until the voltage at VSU exceeds the threshold value, VIT+, for a time delay, which is determined by an external timing capacitor such that: td [ 20 10 3 capacitance where td is in seconds and capacitance is in farads. The overvoltage-detection circuit is programmable for a wide range of designs. During an overvoltage condition, an internal silicon-controlled rectifier (SCR) is triggered, providing 250-mA peak instantaneous current and 25-mA continuous current to the SCR gate drive terminal, which can drive an external high-current SCR gate or an overvoltage-warning circuit. The TL7770C series is characterized for operation from 0°C to 70°C. The TL7770I series is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TL7770-5, TL7770-12 DUAL POWER-SUPPLY SUPERVISORS SLVS019F – OCTOBER 1987 – REVISED JULY 1999 AVAILABLE OPTIONS PACKAGED DEVICES TA SMALL OUTLINE (DW) PLASTIC DIP (N) 0°C to 70°C TL7770-5CDW TL7770-12CDW TL7770-5CN TL7770-12CN –40°C to 85°C TL7770-5IDW TL7770-5IN CHIP FORM (Y) TL7770-5Y TL7770-12Y — DW package is available taped and reeled. Add the suffix R to the device type (e.g., TL7770-5CDWR). Chip forms are tested at 25°C. functional block diagram (each channel) VCC Vref 65 µA (TYP) CT RESET RESET VSU R1 R2 RESIN VSO 1 VSU DEVICE TL7770-5 TL7770-12 2 VSU R1† R2† R1 R2 24 kΩ 70 kΩ 10 kΩ 10 kΩ Short Short Open Open SCR DRIVE 2 mA (TYP) † The values listed are nominal. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL7770-5, TL7770-12 DUAL POWER-SUPPLY SUPERVISORS SLVS019F – OCTOBER 1987 – REVISED JULY 1999 timing requirements VIT+ VIT– VSU VCC = 1 V (TYP) td td td VOH RESET ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ VOL Undefined Operation for VCC Less Than 1 V VT VSO VOH SCR DRIVE VOL absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V Input voltage range, VI: 1VSU, 2VSU, 1VSO, and 2VSO (see Note 1) . . . . . . . . . . . . . . . . . . . . –0.3 V to 18 V Low-level output current (1RESET and 2RESET), IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA High-level output current (1RESET and 2RESET), IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Package thermal impedance, θJA (see Notes 2 and 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W Lead temperature 1,6 mm (1/16 in) from case for 10 seconds: DW or N package . . . . . . . . . . . . . . . . . 260°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to the network ground terminal. 2. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can impact reliability. 3. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TL7770-5, TL7770-12 DUAL POWER-SUPPLY SUPERVISORS SLVS019F – OCTOBER 1987 – REVISED JULY 1999 recommended operating conditions Supply voltage, VCC Input voltage range, VI (see Note 4) 1VSU, 2VSU, 2VSO, 1VSO MIN MAX 3.5 18 V 0 18 V 5 V V Output voltage, VO (1CT, 2CT) UNIT High-level input voltage range, VIH (1RESIN, 2RESIN) 2 18 Low-level input voltage range, VIL (1RESIN, 2RESIN) 0 0.8 V 50 µA High-level output current, IOH (1RESET, 2RESET) –16 mA Low-level output current, IOL (1RESET, 2RESET) 16 mA Continuous output current, IO (1SCR DRIVE, 2SCR DRIVE) 25 mA Timing capacitor, CT 10 µF 0 70 °C –40 85 °C Output sink current, IO (1CT, 2CT) TL7770C series Operating free-air free air temperature, temperature TA TL7770I series NOTE 4: The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for logic voltage levels only. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL7770-5, TL7770-12 DUAL POWER-SUPPLY SUPERVISORS SLVS019F – OCTOBER 1987 – REVISED JULY 1999 electrical characteristics over recommended operating conditions (unless otherwise noted) supply supervisor section TEST CONDITIONS† PARAMETER VOH High level output voltage High-level VOL Low-level output voltage RESET SCR DRIVE IOH = –15 mA IOH = –20 mA RESET IOL = 15 mA TL7770-5 (5-V sense, 1VSU) VIT– IT Undervoltage input threshold at VSU (negative-going) TL7770-12 (12-V sense, 1VSU) TL7770-5, TL7770-12 (programmable sense, 2VSU) TA = MIN to MAX TL7770-5C TL7770-12C TL7770-5I MIN TYP‡ MAX VCC–1.5 VCC–1.5 Vhys VT TL7770-12 (12-V sense, 1VSU) Overvoltage threshold at VSO TL7770-5, TL7770-12 (VSO) TL7770-5, TL7770-12 (programmable sense, 2VSU) RESIN II Input current IOH IOL High-level output current RESET Low-level output current RESET VSO V 0.4 4.46 4.64 10.68 11.12 1.47 1.53 TL7770-5 (5-V sense, 1VSU) Hysteresis at VSU (VIT+ – VIT–) UNIT V V 15 36 TA = MIN to MAX mV 5 TA = MIN to MAX VI = 5.5 V or 0.4 V 2.48 2.68 –10 VI = 2.4 V VO = 18 V 0.5 VO = 0 Duration = 1 ms 2 V µA 50 µA –50 µA IOH Peak output current SCR DRIVE 250 † For conditions shown as MIN or MAX, use the appropriate value specified in the recommended operating conditions. ‡ Typical values are at VCC = 5 V, TA = 25°C. mA total device PARAMETER Vres§ Power-up reset voltage ICC Supply current TEST CONDITIONS† VCC = VSU 1VSU = 18 V, 2VSU = 2 V, 1RESIN and 2RESIN at VCC, 1VSO and 2VSO at 0 V TL7770-5C TL7770-12C TL7770-5I MIN TYP‡ MAX UNIT 0.8 V TA = 25°C TA = MIN to MAX 1 5 mA 6.5 † For conditions shown as MIN or MAX, use the appropriate value specified in the recommended operating conditions. ‡ Typical values are at VCC = 5 V, TA = 25°C. § This is the lowest voltage at which RESET becomes active. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TL7770-5, TL7770-12 DUAL POWER-SUPPLY SUPERVISORS SLVS019F – OCTOBER 1987 – REVISED JULY 1999 electrical characteristics over recommended operating conditions (unless otherwise noted) supply supervisor section TEST CONDITIONS PARAMETER TL7770-5 (5-V sense, 1VSU) VIT– IT Undervoltage input threshold at VSU (negative-going) TL7770-12 (12-V sense, 1VSU) TL7770-5, TL7770-12 (programmable sense, 2VSU) TA = MIN to MAX TL7770-5Y TL7770-12Y MIN Vhys VT II TL7770-12 (12-V sense, 1VSU) Overvoltage threshold at VSO TL7770-5, TL7770-12 (VSO) TL7770-5, TL7770-12 (programmable sense, 2VSU) Input current † Typical values are at VCC = 5 V, TA = 25°C. VSO UNIT MAX 4.46 4.64 10.68 11.12 1.47 1.53 TL7770-5 (5-V sense, 1VSU) Hysteresis at VSU (VIT+ – VIT–) TYP† V 15 36 TA = MIN to MAX mV 5 TA = MIN to MAX VI = 2.4 V 2.48 2.68 V µA 0.5 total device PARAMETER TL7770-5Y TL7770-12Y TEST CONDITIONS MIN Vres‡ Power-up reset voltage ICC Supply current VCC = VSU, 1VSU = 18 V, 2VSU = 2 V, 1RESIN and 2RESIN at VCC, 1VSO and 2VSO at 0 V VOL = 0.4 V, IOL = 1 mA TYP† UNIT MAX 0.8 TA = 25°C V 5 mA † Typical values are at VCC = 5 V, TA = 25°C. ‡ This is the lowest voltage at which RESET becomes active. switching characteristics, VCC = 5 V, CT open, TA = 25°C PARAMETER 6 FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT tPLH tPHL Propagation delay time, low-to-high-level output RESIN RESET 270 500 ns Propagation delay time, high-to-low-level output RESIN RESET 270 500 ns tr tf Rise time tr tf Rise time tw(min) Minimum effective pulse ulse duration RESET Fall time See Figures g 1 and 3 75 150 75 RESET Fall time 50 RESIN See Figure 2a 150 VSU See Figure 2b 100 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ns ns TL7770-5, TL7770-12 DUAL POWER-SUPPLY SUPERVISORS SLVS019F – OCTOBER 1987 – REVISED JULY 1999 PARAMETER MEASUREMENT INFORMATION 5V 5V VCC 511 Ω DUT RESET DUT 15 pF (see Note A) RESET 15 pF (see Note A) 511 Ω GND RESET OUTPUT CONFIGURATION RESET OUTPUT CONFIGURATION NOTE A: This includes jig and probe capacitance. Figure 1. RESET and RESET Output Configurations tw tw 5V VIT + 2 V 2.5 V VIT 0V VIT – 2 V b) VSU a) RESIN WAVEFORMS Figure 2. Input Pulse Definition Voltage Fault VIT+ VSU VIT+ VIT– 0V VIH RESIN Undefined 2V 0.8 V tf tr VIL tPLH 90% 90% RESET 90% VOH 50% ÎÎ 10% tf td td td 90% 50% RESET 10% 10% tr 10% 10% V OL tPHL Figure 3. Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TL7770-5, TL7770-12 DUAL POWER-SUPPLY SUPERVISORS SLVS019F – OCTOBER 1987 – REVISED JULY 1999 APPLICATION INFORMATION VS System Supply 16 5 10 kΩ VCC 1VSU 1RESET 4 To System Reset 1 Reset Input (from system) 1RESIN RT (see Note B) 2 3 1CT CT To System Reset 1RESET GND 10 kΩ 8 NOTE B: When VCC and 1VSU are connected to the same point, it is recommended that series resistance (RT) be added between the time-delay programming capacitor (CT) and the voltage-supervisor device terminal (1CT). The suggested RT value is given by: RT u V1 *10V ** , I IT 3 where V I + ǒthe lesser of 7.1 V or V Ǔ S When this series resistor is used, the td calculation is as follows: td + 1.3 * ƪǒ (6.5E * 5) 6.5 10 *5 10 *5 Ǔ RT ƫ CT Figure 4. System Reset Controller With Undervoltage Sensing 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 PACKAGING INFORMATION Orderable Device Status (1) 5962-9093201MEA OBSOLETE CDIP J 16 TBD Call TI Call TI 5962-9093202M2A OBSOLETE LCCC FK 20 TBD Call TI Call TI 5962-9093202MEA OBSOLETE CDIP J 16 TBD Call TI Call TI TL7770-12CDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7770-12CDWE4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7770-12CDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7770-12CDWRE4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7770-12CN OBSOLETE PDIP N 16 TL7770-12MJB OBSOLETE CDIP J 16 TL7770-5CDW ACTIVE SOIC DW 16 40 TL7770-5CDWE4 ACTIVE SOIC DW 16 40 TL7770-5CDWR ACTIVE SOIC DW TL7770-5CDWRE4 ACTIVE SOIC TL7770-5CN ACTIVE TL7770-5CNE4 Package Type Package Drawing Pins Package Eco Plan (2) Qty TBD Lead/Ball Finish MSL Peak Temp (3) Call TI Call TI TBD Call TI Call TI Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL7770-5IDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7770-5IDWE4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7770-5IDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7770-5IDWRE4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7770-5MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI TL7770-5MJB OBSOLETE CDIP J 16 TBD Call TI Call TI TL7770-5QDW OBSOLETE SOIC DW 16 TBD Call TI Call TI TL7770-5QDWR OBSOLETE SOIC DW 16 TBD Call TI Call TI TL7770-5QN OBSOLETE PDIP N 16 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. 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