晶揚科技股份有限公司 Taiwan Micropaq Corporation 承 認 書 SPECIFICATION FOR APPROVAL TM54S816T-6G 新竹縣新竹工業區文化路 4 號 No.4 Wenhua Rd. HsinChu Industrial Park HuKou , Taiwan, R.O.C. TEL：886-3-597-9402 ˙ FAX：886-3-597-0775 http://www.tmc.com.tw TMC TM54S816T-6G Description The TM54S816T is organized as 4-bank x 2097152-word x 16-bit(8Mx16), fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Features Package: 400-mil 54-pin TSOP(II) JEDEC PC133/PC100 compatible Single 3.3V Power Supply LVTTL Signal Compatible Byte control(DQML and DQMU) Auto and Self Refresh 64ms refresh period (4K Refresh) 12-Row x 9-Column organization 4-Bank operation controlled by BA1,BA0 Pin36 and 40 are “No Connected” Fully synchronous operation referenced to clock rising edge Programmable - CAS Latency (3 or 2 clocks) - Burst Length (1,2,4, 8 & full page) - Burst type (Sequential & Interleave) Burst read/write and burst read/single write operations capability Frequency vs. AC Parameter Symbol Parameter fCK3 fCK2 tCK3 tAC3 tCK2 tAC2 trcd Max. operating frequency @CL=3 Max. operating frequency @CL=2 Min. clock cycle time @CL=3 Max. access time from CLK @CL=3 - 6G 166 133 6.0 5.0 - 7G 143 133 7.0 5.4 - 75G 133 100 7.5 5.4 Unit Mhz Mhz ns ns Min. clock cycle time @CL=2 Max. access time from CLK @CL=2 Min. row to column delay 7.5 5.4 15 7.5 5.4 18 10 6.0 18 ns ns ns For reference only. 2 TMC Rev: 1.1 TMC TM54S816T-6G Pin Description Pin Name CLK CKE /CS /RAS /CAS /WE DQ0~DQ15 Function Master Clock Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data I/O For reference only. Pin Name DQML/DQMU A0-11 BA1,BA0 Vdd VddQ Vss/VssQ NC 3 Function Output Disable(Write Mask) Address Input Bank Address Power Supply Power Supply for Output Ground No Connection TMC Rev: 1.1 TMC TM54S816T-6G Pin Function Pin Pin Function CLK Active on the positive going edge to sample all inputs. /CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK,CKE and DQML/DQMU. CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. A0~A11 Address input Row/column addresses are multiplexed on the same pins. Row address:A0~A11, Column address:A0~A7 BA1,BA0 Bank address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. /RAS Row address strobe Latches row addresses on the positive going edge of the CLK with /RAS low. Enables rows access & pre-charge. /CAS Column address strobe Latches column addresses on the positive going edge of the CLK with /CAS low. Enables column access. /WE Write enable Enables write operation and row pre-charge. Latches data in starting from /CAS,/WE active. DQMU/DQML Data I/O mask Makes data output Hi-Z, Tshz after the clock and masks the output. Blocks data input when DQML/DQMU active. DQ0~15 Data input/output Data inputs/outputs are multiplexed on the same pins. Vdd/Vss Power supply/ground Power and ground for the input buffers and the core logic. VddQ/VssQ Data output power / Isolated power supply and ground for the ground output buffers to provide improved noise immunity. For reference only. Name System clock 4 TMC Rev: 1.1 TMC TM54S816T-6G NC/RFU No connection / This pin is recommended to be left no reserved for future use connection on the device. Absolute maximum ratings Parameter Symbol Ratings Unit Voltage on any pin relative to Vss VIN, VOUT -0.5 to 4.6 V Voltage supply relative to Vss Vdd,VddQ -0.5 to 4.6 V Operating temperature Topr 0 to +70 ℃ Power dissipation PD 1 W Output Shorted current IOS 50 mA DC OPERATING CONDITIONS Recommended operating conditions(Referenced to Vss=0V,TA=0℃ to 70℃) Parameter Symbol Min. Typ. Max. Unit Power Supply Voltage Vdd, VddQ 3.0 3.3 3.6 V Input Logic High Voltage VIH 2.0 Vdd V Input Logic Low Voltage VIL -0.3 0.8 V Output Logic High Voltage VOH 2.4 V Output Logic Low Voltage VOL 0.4 V μA Input/Output Leakage Current IIL, IOL -5 5 DC Characteristics (Recommended operating condition TA = 0℃ to 70℃, unless otherwise noted.) Parameter Operating Current (One bank active) Pre-charge Standby Current in Power Down Mode Pre-charge Standby Current in Non-Power Down Mode Symbol -6G 120 Limits -7G -75G 110 100 ICC2P Burst length=1, CL=3, tRC = tRC(min), tCK = tCK(min) CKE <VIL(max), tCK = 15ns ICC2PS CKE & CLK<VIL(max) 2 ICC2N /CS =CKE >VIH(min), tCK = 15ns /CS=CKE >VIH(min), CLK< VIL(max) CKE<VIL(max), tCK =15ns 25 ICC1 ICC2NS Active Standby Current in Power I P CC3 Down Mode For reference only. Test Conditions 5 2 Unit mA mA mA 15 7 TMC Rev: 1.1 mA TMC TM54S816T-6G ICC3PS CKE & CLK<VIL(max) 5 35 160 150 140 mA 160 150 140 mA Operating Current (Burst) ICC4 /CS=CKE>VIH(min), tCK =15ns /CS=CKE>VIH(min), CLK < VIL(max ) BL=4,CL=3,All Banks Active Auto Refresh Current ICC5 CBR Command, tCK = tCK(min) Self Refresh Current ICC6 CKE < 0.2V Active Standby Current in Non- ICC3N Power Down Mode ICC3NS mA 30 2 mA AC Characteristics Recommended operating conditions(Vdd=VddQ=3.3V,Vss=0V,TA= 0 to 70℃) -6G fCK3 fCK2 tCK3 tCK2 tAC3 tAC2 tCH tCL tIS tIH tOH tT tRCD tRC tRAS tRP tRRD tREF -75G Unit Min 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 -7G Parameter Symbol Clock Frequency,CL=3 Clock Frequency,CL=2 Clock Cycle Time,CL=3 Clock Cycle Time,CL=2 Clock Access Time,CL=3 Clock Access Time,CL=2 Clock High Pulse Width Clock Low Pulse Width Input Setup time(all inputs) Input Hold time(all inputs) Data-out Hold time Transition time of clock Row to Column delay Row Cycle time Row active time Row Pre-charge time Row active to active delay Refresh time For reference only. Max 166 133 6.0 7.5 Min 7.0 7.5 5.0 5.4 2.5 2.5 1.5 0.8 1.5 1.0 15 60 42 15 12 64 6 Max 143 133 10 Min Max 133 100 7.5 10 5.4 5.4 2.5 2.5 1.5 0.8 1.8 1.0 18 63 42 18 14 64 10 5.4 6.0 2.5 2.5 1.5 0.8 1.8 1.0 18 63 42 18 14 64 TMC Rev: 1.1 10 Mhz Mhz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms TMC For reference only. TM54S416T 7 SDRAM TMC Rev:1.1