TI TPS2062DR

TPS2061, TPS2062, TPS2063
TPS2065, TPS2066, TPS2067
www.ti.com
SLVS490I – DECEMBER 2003 – REVISED OCTOBER 2009
CURRENT-LIMITED, POWER-DISTRIBUTION SWITCHES
Check for Samples: TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067
FEATURES
APPLICATIONS
•
•
•
•
•
•
1
2
•
•
•
•
•
•
•
•
•
•
70-mΩ High-Side MOSFET
1-A Continuous Current
Thermal and Short-Circuit Protection
Accurate Current Limit
(1.1 A min, 1.9 A max)
Operating Range: 2.7 V to 5.5 V
0.6-ms Typical Rise Time
Undervoltage Lockout
Deglitched Fault Report (OC)
No OC Glitch During Power Up
1-μA Maximum Standby Supply Current
Bidirectional Switch
Ambient Temperature Range: -40°C to 85°C
Built-in Soft-Start
UL Listed - File No. E169910
Heavy Capacitive Loads
Short-Circuit Protections
TPS2062/TPS2066
D AND DGN PACKAGE
(TOP VIEW)
TPS2061/TPS2065
D AND DGN PACKAGE
(TOP VIEW)
GND
IN
IN
EN
1
2
3
4
†
OUT
OUT
OUT
8
7
6
5
OC
GND
IN
†
EN1
†
EN2
GND
IN
IN1
GND
OC
†
EN
8
7
6
5
OC1
OUT1
OUT2
OC2
TPS2063/TPS2067
D PACKAGE
(TOP VIEW)
TPS2061/TPS2065
DBV PACKAGE
(TOP VIEW)
OUT
1
2
3
4
†
EN1
†
EN2
GND
IN2
†
EN3
NC
1
2
3
4
5
6
7
8
16
15
14
OC1
OUT1
OUT2
13
12
11
10
9
OC2
OC3
OUT3
NC
NC
† All Enable Inputs Are Active High For TPS2065, TPS2066, and TPS2067
DESCRIPTION
The TPS206x power-distribution switches are intended for applications where heavy capacitive loads and
short-circuits are likely to be encountered. This device incorporates 70-mΩ N-channel MOSFET power switches
for power-distribution systems that require multiple power switches in a single package. Each switch is controlled
by a logic enable input. Gate drive is provided by an internal charge pump designed to control the power-switch
rise times and fall times to minimize current surges during switching. The charge pump requires no external
components and allows operation from supplies as low as 2.7 V.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2009, Texas Instruments Incorporated
TPS2061, TPS2062, TPS2063
TPS2065, TPS2066, TPS2067
SLVS490I – DECEMBER 2003 – REVISED OCTOBER 2009
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION (CONTINUED)
When the output load exceeds the current-limit threshold or a short is present, the device limits the output current
to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic output low. When
continuous heavy overloads and short-circuits increase the power dissipation in the switch, causing the junction
temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a thermal
shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures that the switch remains
off until valid input voltage is present. This power-distribution switch is designed to set current limit at 1.5 A
typically.
AVAILABLE OPTION AND ORDERING INFORMATION
TA
RECOMMEND
ED
MAXIMUM
CONTINUOUS
LOAD
CURRENT
ENABLE
TYPICAL
SHORTCIRCUIT
CURRENT
LIMIT
AT 25°C
PACKAGED
DEVICES (1)
NUMBER OF
SWITCHES
Active low
Single
Active high
Active low
-40°C to 85°C
Dual
Active high
1A
Active low
1.5 A
Active high
Active low
TPS2061DGN
TPS2061D
-
TPS2065DGN
TPS2065D
-
TPS2062DGN
TPS2062D
-
TPS2066DGN
TPS2066D
-
-
TPS2063D
-
-
TPS2067D
-
-
-
TPS2061DBV
-
-
TPS2065DBV
Single
Active high
(1)
(2)
SOIC (D)
Triple
SOT23 (DBV)
(2)
MSOP (DGN)
The package is available taped and reeled. Add an R suffix to device types (e.g., TPS2062DR).
The printed circuit board layout is important for control of temperature rise when operated at high ambient temperatures.
spacer
ORDERING INFORMATION
TA
-40°C to 85°C
(1)
(2)
2
SOIC(D)
(1)
STATUS
MSOP (DGN)
(1)
STATUS
SOT23 (DBV)
(2)
STATUS
TPS2061DG4
Active
TPS2061DGNG4
Active
-
-
TPS2062DG4
Active
TPS2062DGNG4
Active
-
-
TPS2065DG4
Active
TPS2065DGNG4
Active
-
-
TPS2066DG4
Active
TPS2066DGNG4
Active
-
-
-
-
-
-
TPS2061DBV
Active
-
-
-
-
TPS2065DBV
Active
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
The printed circuit board layout is important for control of temperature rise when operated at high ambient temperatures.
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Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067
TPS2061, TPS2062, TPS2063
TPS2065, TPS2066, TPS2067
www.ti.com
SLVS490I – DECEMBER 2003 – REVISED OCTOBER 2009
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
UNIT
Input voltage range, VI(IN)
(2)
Output voltage range, VO(OUT)
-0.3 V to 6 V
(2)
-0.3 V to 6 V
, VO(OUTx)
Input voltage range, VI(EN), VI(EN), VI(ENx), VI(ENx)
-0.3 V to 6 V
Voltage range, VI(OC), VI(OCx)
-0.3 V to 6 V
Continuous output current, IO(OUT), IO(OUTx)
Internally limited
Continuous total power dissipation
See Dissipation Rating Table
Operating virtual junction temperature range, TJ
Electrostatic discharge (ESD) protection
(1)
(2)
-40°C to 150°C
Human body model
2 kV
Charge device model (CDM)
500 V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND.
DISSIPATING RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
D-8 (1)
585.82 mW
5.8582 mW/°C
322.20 mW
234.32 mW
DGN-8 (2)
1712.3 mW
17.123 mW/°C
941.78 mW
684.33 mW
D-16 (1)
898.47 mW
8.9847 mW/°C
494.15 mW
359.38 mW
285 mW
2.85 mW/°C
155 mW
114 mW
704 mW
7.04 mW/°C
387 mW
281 mW
DBV-5 (3)
(1)
(2)
(3)
Power ratings are based on the low-k board (1 signal, 1 layer).
Power ratings are based on the high-k board (2 signal, 2 plane) with PowerPAD™ vias to the internal ground plane.
Lower ratings are for low-k printed circuit board layout (single -sided). Higher ratings are for enhanced high-k layout, (2 signal, 2 plane)
with a 1mm2 copper pad on pin 2 and 2 vias to the ground plane.
RECOMMENDED OPERATING CONDITIONS
Input voltage, VI(IN)
Input voltage, VI(EN), VI(EN), VI(ENx), VI(ENx)
Continuous output current, IO(OUT), IO(OUTx)
Operating virtual junction temperature, TJ
MIN
MAX
2.7
5.5
UNIT
V
0
5.5
V
0
1
A
-40
125
°C
ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = 1 A, VI(ENx) = 0 V, or VI(ENx) = 5.5 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
(1)
MIN
TYP
MAX
UNIT
POWER SWITCH
rDS(on)
tr
tf
(1)
Static drain-source on-state
resistance, 5-V operation
and 3.3-V operation
VI(IN) = 5 V or 3.3 V, IO = 1 A, -40°C ≤ TJ ≤ 125°C
70
135
mΩ
Static drain-source on-state
resistance, 2.7-V
operation
VI(IN) = 2.7 V, IO = 1 A, -40°C ≤ TJ ≤ 125°C
75
150
mΩ
VI(IN) = 5.5 V
0.6
1.5
Rise time, output
Fall time, output
VI(IN) = 2.7 V
VI(IN) = 5.5 V
VI(IN) = 2.7 V
CL = 1 μF, RL = 5 Ω, TJ = 25°C
0.4
1
0.05
0.5
0.05
0.5
ms
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
Copyright © 2003–2009, Texas Instruments Incorporated
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Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067
3
TPS2061, TPS2062, TPS2063
TPS2065, TPS2066, TPS2067
SLVS490I – DECEMBER 2003 – REVISED OCTOBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = 1 A, VI(ENx) = 0 V, or VI(ENx) = 5.5 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
(1)
MIN
TYP
MAX
UNIT
ENABLE INPUT EN OR EN
VIH
High-level input voltage
2.7 V ≤ VI(IN) ≤ 5.5 V
VIL
Low-level input voltage
2.7 V ≤ VI(IN) ≤ 5.5 V
II
Input current
VI(ENx) = 0 V or 5.5 V, VI(ENx) = 0 V or 5.5 V
ton
Turnon time
CL = 100 μF, RL = 5 Ω
3
toff
Turnoff time
CL = 100 μF, RL = 5 Ω
10
2
0.8
-0.5
0.5
V
μA
ms
CURRENT LIMIT
IOS
Short-circuit output current
VI(IN) = 5 V, OUT connected to GND,
device enabled into short-circuit
IOC_TRIP
Overcurrent trip threshold
VI(IN) = 5 V, current ramp (≤ 100 A/s) on OUT
TJ = 25°C
1.1
1.5
1.9
-40°C ≤ TJ ≤ 125°C
1.1
1.5
2.1
TPS2061, TPS2062,
TPS2065, TPS2066
1.6
2.3
2.7
TPS2063, TPS2067
1.6
2.4
3.0
A
A
SUPPLY CURRENT (TPS2061, TPS2065)
Supply current, low-level output
No load on OUT, VI(ENx) = 5.5 V,
or VI(ENx) = 0 V
TJ = 25°C
0.5
1
-40°C ≤ TJ ≤ 125°C
0.5
5
Supply current, high-level output
No load on OUT, VI(ENx) = 0 V,
or VI(ENx) = 5.5 V
TJ = 25°C
43
60
-40°C ≤ TJ ≤ 125°C
43
70
Leakage current
OUT connected to ground, VI(EN) = 5.5 V,
or VI(EN) = 0 V
-40°C ≤ TJ ≤ 125°C
1
μA
Reverse leakage current
VI(OUTx) = 5.5 V, IN = ground
TJ = 25°C
0
μA
Supply current, low-level output
No load on OUT, VI(ENx) = 5.5 V,
or VI(ENx) = 0 V
TJ = 25°C
0.5
1
-40°C ≤ TJ ≤ 125°C
0.5
5
Supply current, high-level output
No load on OUT, VI(ENx) = 0 V,
or VI(ENx) = 5.5 V
TJ = 25°C
50
70
-40°C ≤ TJ ≤ 125°C
50
90
Leakage current
OUT connected to ground, VI(/ENx) = 5.5 V,
or VI(ENx) = 0 V
-40°C ≤ TJ ≤ 125°C
1
μA
Reverse leakage current
VI(OUTx) = 5.5 V, IN = ground
TJ = 25°C
0.2
μA
TJ = 25°C
0.5
2
-40°C ≤ TJ ≤ 125°C
0.5
10
TJ = 25°C
65
90
-40°C ≤ TJ ≤ 125°C
65
110
1
μA
0.2
μA
μA
μA
SUPPLY CURRENT (TPS2062, TPS2066)
μA
μA
SUPPLY CURRENT (TPS2063, TPS2067)
Supply current, low-level output
No load on OUT, VI(ENx) = 0 V
Supply current, high-level output
No load on OUT, VI(ENx) = 5.5 V
Leakage current
OUT connected to ground, VI(ENx) = 5.5 V,
or VI(ENx) = 0 V
-40°C ≤ TJ ≤ 125°C
Reverse leakage current
VI(OUTx) = 5.5 V, INx = ground
TJ = 25°C
μA
μA
UNDERVOLTAGE LOCKOUT
Low-level input voltage, IN
2
Hysteresis, IN
TJ = 25°C
2.5
75
V
mV
OVERCURRENT OC1 and OC2
Output low voltage, VOL(OCx)
IO(OCx) = 5 mA
Off-state current
VO(OCx) = 5 V or 3.3 V
OC deglitch
OCx assertion or deassertion
4
8
0.4
V
1
μA
15
ms
THERMAL SHUTDOWN (2)
Thermal shutdown threshold
135
Recovery from thermal shutdown
125
Hysteresis
(2)
4
°C
°C
10
°C
The thermal shutdown only reacts under overcurrent conditions.
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Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067
TPS2061, TPS2062, TPS2063
TPS2065, TPS2066, TPS2067
www.ti.com
SLVS490I – DECEMBER 2003 – REVISED OCTOBER 2009
DEVICE INFORMATION
Pin Functions (TPS2061 and TPS2065)
PINS
D or DGN Package
NAME
DBV Package
I/O
DESCRIPTION
TPS2061
TPS2065
TPS2061
TPS2065
4
-
4
-
I
Enable input, logic low turns on power switch
EN
-
4
-
4
I
Enable input, logic high turns on power switch
GND
1
1
2
2
2, 3
2,3
5
5
I
Input voltage
EN
IN
OC
OUT
PowerPAD™
Ground
5
5
3
3
O
Overcurrent, open-drain output, active-low
6, 7, 8
6, 7, 8
1
1
O
Power-switch output
-
-
-
-
Internally connected to GND; used to heat-sink the part
to the circuit board traces. Should be connected to GND
pin.
Functional Block Diagram
(See Note A)
CS
IN
OUT
Charge
Pump
EN
(See Note B)
Driver
Current
Limit
OC
UVLO
Thermal
Sense
GND
Deglitch
Note A: Current sense
Note B: Active low (EN) for TPS2061. Active high (EN) for TPS2065.
Copyright © 2003–2009, Texas Instruments Incorporated
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5
TPS2061, TPS2062, TPS2063
TPS2065, TPS2066, TPS2067
SLVS490I – DECEMBER 2003 – REVISED OCTOBER 2009
www.ti.com
Pin Functions (TPS2062 and TPS2066)
PINS
NAME
I/O
NO.
DESCRIPTION
TPS2062
TPS2066
EN1
3
-
I
Enable input, logic low turns on power switch IN-OUT1
EN2
4
-
I
Enable input, logic low turns on power switch IN-OUT2
EN1
-
3
I
Enable input, logic high turns on power switch IN-OUT1
EN2
-
4
I
Enable input, logic high turns on power switch IN-OUT2
GND
1
1
IN
2
2
I
Input voltage
OC1
8
8
O
Overcurrent, open-drain output, active low, IN-OUT1
OC2
5
5
O
Overcurrent, open-drain output, active low, IN-OUT2
OUT1
7
7
O
Power-switch output, IN-OUT1
OUT2
6
6
O
Power-switch output, IN-OUT2
PowerPAD™
-
-
Ground
Internally connected to GND; used to heat-sink the part to the circuit board traces.
Should be connected to GND pin.
Functional Block Diagram
OC1
Thermal
Sense
GND
Deglitch
EN1
(See Note B)
Driver
Current
Limit
Charge
Pump
(See Note A)
CS
OUT1
UVLO
(See Note A)
IN
OUT2
CS
Charge
Pump
Driver
Current
Limit
OC2
EN2
(See Note B)
Thermal
Sense
Deglitch
Note A: Current sense
Note B: Active low (ENx) for TPS2062. Active high (ENx) for TPS2066.
6
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Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067
TPS2061, TPS2062, TPS2063
TPS2065, TPS2066, TPS2067
www.ti.com
SLVS490I – DECEMBER 2003 – REVISED OCTOBER 2009
Pin Functions (TPS2063 and TPS2067)
PINS
NAME
I/O
DESCRIPTION
TPS2063
TPS2067
EN1
3
–
I
Enable input, logic low turns on power switch IN1-OUT1
EN2
4
–
I
Enable input, logic low turns on power switch IN1-OUT2
EN3
7
–
I
Enable input, logic low turns on power switch IN2-OUT3
EN1
–
3
I
Enable input, logic high turns on power switch IN1-OUT1
EN2
–
4
I
Enable input, logic high turns on power switch IN1-OUT2
I
Enable input, logic high turns on power switch IN2-OUT3
EN3
–
7
GND
1, 5
1, 5
IN1
2
2
I
Input voltage for OUT1 and OUT2
IN2
6
6
I
Input voltage for OUT3
NC
Ground
8, 9, 10
8, 9, 10
OC1
16
16
O
No connection
Overcurrent, open-drain output, active low, IN1-OUT1
OC2
13
13
O
Overcurrent, open-drain output, active low, IN1-OUT2
OC3
12
12
O
Overcurrent, open-drain output, active low, IN2-OUT3
OUT1
15
15
O
Power-switch output, IN1-OUT1
OUT2
14
14
O
Power-switch output, IN1-OUT2
OUT3
11
11
O
Power-switch output, IN2-OUT3
Copyright © 2003–2009, Texas Instruments Incorporated
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Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067
7
TPS2061, TPS2062, TPS2063
TPS2065, TPS2066, TPS2067
SLVS490I – DECEMBER 2003 – REVISED OCTOBER 2009
www.ti.com
Functional Block Diagram
OC1
Thermal
Sense
GND
Deglitch
EN1
(See Note B)
Driver
Current
Limit
(See Note A)
CS
OUT1
UVLO
(See Note A)
CS
IN1
Driver
OUT2
Current
Limit
OC2
EN2
(See Note B)
VCC
Selector
Thermal
Sense
Deglitch
Charge
Pump
(See Note A)
IN2
CS
EN3
Driver
OUT3
Current
Limit
(See Note B)
OC3
UVLO
Thermal
Sense
GND
Deglitch
Note A: Current sense
Note B: Active low (ENx) for TPS2063; Active high (ENx) for TPS2067
8
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Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067
TPS2061, TPS2062, TPS2063
TPS2065, TPS2066, TPS2067
www.ti.com
SLVS490I – DECEMBER 2003 – REVISED OCTOBER 2009
PARAMETER MEASUREMENT INFORMATION
OUT
RL
tf
tr
CL
VO(OUT)
90%
90%
10%
10%
TEST CIRCUIT
50%
VI(EN)
50%
toff
ton
VO(OUT)
50%
VI(EN)
90%
50%
toff
ton
90%
VO(OUT)
10%
10%
VOLTAGE WAVEFORMS
Figure 1. Test Circuit and Voltage Waveforms
VI(EN)
5 V/div
RL = 5 W,
CL = 1 mF
TA = 255C
VI(EN)
5 V/div
RL = 5 W,
CL = 1 mF
TA = 255C
VO(OUT)
2 V/div
VO(OUT)
2 V/div
t − Time − 500 ms/div
Figure 2. Turnon Delay and Rise Time With 1-μF
Load
Copyright © 2003–2009, Texas Instruments Incorporated
t − Time − 500 ms/div
Figure 3. Turnoff Delay and Fall Time With 1-μF
Load
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9
TPS2061, TPS2062, TPS2063
TPS2065, TPS2066, TPS2067
SLVS490I – DECEMBER 2003 – REVISED OCTOBER 2009
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
RL = 5 W,
CL = 100 mF
TA = 255C
VI(EN)
5 V/div
VI(EN)
5 V/div
RL = 5 W,
CL = 100 mF
TA = 255C
VO(OUT)
2 V/div
VO(OUT)
2 V/div
t − Time − 500 ms/div
t − Time − 500 ms/div
Figure 4. Turnon Delay and Rise Time With 100-μF
Load
VI(EN)
5 V/div
Figure 5. Turnoff Delay and Fall Time With 100-μF
Load
VIN = 5 V
RL = 5 W,
TA = 255C
VI(EN)
5 V/div
220 mF
470 mF
IO(OUT)
500 mA/div
IO(OUT)
500 mA/div
t − Time − 500 ms/div
Figure 6. Short-Circuit Current,
Device Enabled Into Short
10
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100 mF
t − Time − 1 ms/div
Figure 7. Inrush Current With Different
Load Capacitance
Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067
TPS2061, TPS2062, TPS2063
TPS2065, TPS2066, TPS2067
www.ti.com
SLVS490I – DECEMBER 2003 – REVISED OCTOBER 2009
PARAMETER MEASUREMENT INFORMATION (continued)
VO(OC)
2 V/div
VO(OC)
2 V/div
IO(OUT)
1 A/div
IO(OUT)
1 A/div
t − Time − 2 ms/div
t − Time − 2 ms/div
Figure 8. 2-Ω Load Connected to Enabled Device
Figure 9. 1-Ω Load Connected to Enabled Device
TYPICAL CHARACTERISTICS
TURNON TIME
vs
INPUT VOLTAGE
TURNOFF TIME
vs
INPUT VOLTAGE
1.0
2
CL = 100 mF,
RL = 5 W,
TA = 255C
0.9
0.8
CL = 100 mF,
RL = 5 W,
TA = 255C
1.9
Turnoff Time − mS
Turnon Time − ms
0.7
0.6
0.5
0.4
1.8
1.7
0.3
0.2
1.6
0.1
0
2
3
4
5
VI − Input Voltage − V
Figure 10.
Copyright © 2003–2009, Texas Instruments Incorporated
6
1.5
2
3
4
5
VI − Input Voltage − V
6
Figure 11.
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TYPICAL CHARACTERISTICS (continued)
RISE TIME
vs
INPUT VOLTAGE
FALL TIME
vs
INPUT VOLTAGE
0.25
0.6
0.5
0.2
0.4
Fall Time − ms
Rise Time − ms
CL = 1 mF,
RL = 5 W,
TA = 255C
CL = 1 mF,
RL = 5 W,
TA = 255C
0.3
0.15
0.1
0.2
0.05
0.1
0
2
3
4
5
VI − Input Voltage − V
0
6
2
Figure 13.
TPS2061, TPS2065
SUPPLY CURRENT, OUTPUT ENABLED
vs
JUNCTION TEMPERATURE
TPS2062, TPS2066
SUPPLY CURRENT, OUTPUT ENABLED
vs
JUNCTION TEMPERATURE
VI = 5.5 V
50
VI = 5 V
40
30
VI = 2.7 V
20
VI = 3.3 V
10
0
−50
6
70
I I (IN) − Supply Current, Output Enabled − µ A
I I (IN) − Supply Current, Output Enabled − µ A
4
5
VI − Input Voltage − V
Figure 12.
60
0
50
100
TJ − Junction Temperature − 5C
Figure 14.
12
3
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150
VI = 5.5 V
60
50
VI = 5 V
VI = 3.3 V
40
30
VI = 2.7 V
20
10
0
−50
0
50
100
150
TJ − Junction Temperature − 5C
Figure 15.
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TPS2065, TPS2066, TPS2067
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SLVS490I – DECEMBER 2003 – REVISED OCTOBER 2009
TYPICAL CHARACTERISTICS (continued)
TPS2063, TPS2067
SUPPLY CURRENT, OUTPUT ENABLED
vs
JUNCTION TEMPERATURE
TPS2061, TPS2065
SUPPLY CURRENT, OUTPUT DISABLED
vs
JUNCTION TEMPERATURE
80
VI = 5.5 V
70
VI = 5 V
60
VI = 3.3 V
50
40
VI = 2.7 V
30
20
10
0
−50
I I (IN) − Supply Current, Output Disabled − µ A
I I (IN) − Supply Current, Output Disabled − µ A
0.5
0
50
100
TJ − Junction Temperature − 5C
VI = 5.5 V
0.45
VI = 5 V
0.4
0.35
0.3
VI = 2.7 V
VI = 3.3 V
0.25
0.2
0.15
0.1
0.05
0
−50
150
0
50
100
Figure 16.
Figure 17.
TPS2062, TPS2066
SUPPLY CURRENT, OUTPUT DISABLED
vs
JUNCTION TEMPERATURE
TPS2063, TPS2067
SUPPLY CURRENT, OUTPUT DISABLED
vs
JUNCTION TEMPERATURE
0.5
0.5
0.45
VI = 5.5 V
VI = 5 V
0.4
0.35
0.3
VI = 2.7 V
VI = 3.3 V
0.25
0.2
0.15
0.1
0.05
0
−50
150
TJ − Junction Temperature − 5C
I I (IN) − Supply Current, Output Disabled − µ A
I I (IN) − Supply Current, Output Enabled − µ A
90
0
50
100
TJ − Junction Temperature − 5C
Figure 18.
Copyright © 2003–2009, Texas Instruments Incorporated
150
0.45
VI = 5.5 V
VI = 5 V
0.4
0.35
0.3
VI = 3.3 V
VI = 2.7 V
0.25
0.2
0.15
0.1
0.05
0
−50
0
50
100
TJ − Junction Temperature − 5C
150
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
SHORT-CIRCUIT OUTPUT CURRENT
vs
JUNCTION TEMPERATURE
1.56
120
IO = 0.5 A
I OS − Short-Circuit Output Current − A
On-State Resistance − mΩ
100
r DS(on) − Static Drain-Source
VI = 2.7 V
1.54
Out1 = 5 V
Out1 = 3.3 V
80
Out1 = 2.7 V
60
40
20
1.52
VI = 3.3 V
1.5
1.48
1.46
1.44
VI = 5 V
1.42
VI = 5.5 V
1.4
1.38
1.36
1.34
0
−50
0
50
100
−50
150
TJ − Junction Temperature − 5C
100
Figure 21.
THRESHOLD TRIP CURRENT
vs
INPUT VOLTAGE
UNDERVOLTAGE LOCKOUT
vs
JUNCTION TEMPERATURE
150
2.3
UVLO Rising
UVOL − Undervoltage Lockout − V
TA = 255C
Load Ramp = 1A/10 ms
2.3
Threshold Trip Current − A
50
Figure 20.
2.5
2.1
1.9
1.7
1.5
2.5
3
3.5
4
4.5
5
VI − Input Voltage − V
Figure 22.
14
0
TJ − Junction Temperature − 5C
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5.5
6
2.26
2.22
UVLO Falling
2.18
2.14
2.1
−50
0
50
100
150
TJ − Junction Temperature − 5C
Figure 23.
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SLVS490I – DECEMBER 2003 – REVISED OCTOBER 2009
TYPICAL CHARACTERISTICS (continued)
CURRENT-LIMIT RESPONSE
vs
PEAK CURRENT
200
Current-Limit Response − µ s
VI = 5 V,
TA = 255C
150
100
50
0
0
Copyright © 2003–2009, Texas Instruments Incorporated
2.5
5
7.5
Peak Current − A
Figure 24.
10
12.5
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APPLICATION INFORMATION
POWER-SUPPLY CONSIDERATIONS
TPS2062
2
Power Supply
2.7 V to 5.5 V
IN
OUT1
0.1 µF
8
3
5
4
7
Load
0.1 µF
22 µF
0.1 µF
22 µF
OC1
EN1
OUT2
6
OC2
Load
EN2
GND
1
Figure 25. Typical Application
A 0.01-μF to 0.1-μF ceramic bypass capacitor between IN and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy.
This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing the
output with a 0.01-μF to 0.1-μF ceramic capacitor improves the immunity of the device to short-circuit transients.
OVERCURRENT
A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do not
increase the series resistance of the current path. When an overcurrent condition is detected, the device
maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only
if the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before VI(IN) has been applied (see Figure 15). The TPS206x senses the short and
immediately switches into a constant-current output.
In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload
occurs, high currents may flow for a short period of time before the current-limit circuit can react. After the
current-limit circuit has tripped (reached the overcurrent trip threshold), the device switches into constant-current
mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figure 18). The TPS206x is capable of delivering current up to the current-limit threshold without
damaging the device. Once the threshold has been reached, the device switches into its constant-current mode.
OC RESPONSE
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature shutdown condition
is encountered after a 10-ms deglitch timeout. The output remains asserted until the overcurrent or
overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause a
momentary overcurrent condition; however, no false reporting on OCx occurs due to the 10-ms deglitch circuit.
The TPS206x is designed to eliminate false overcurrent reporting. The internal overcurrent deglitch eliminates
the need for external components to remove unwanted pulses. OCx is not deglitched when the switch is turned
off due to an overtemperature shutdown.
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SLVS490I – DECEMBER 2003 – REVISED OCTOBER 2009
V+
TPS2062
GND
Rpullup
OC1
IN
OUT1
EN1
OUT2
EN2
OC2
Figure 26. Typical Circuit for the OC Pin
POWER DISSIPATION AND JUNCTION TEMPERATURE
The low on-resistance on the N-channel MOSFET allows the small surface-mount packages to pass large
currents. The thermal resistances of these packages are high compared to those of power packages; it is good
design practice to check power dissipation and junction temperature. Begin by determining the rDS(on) of the
N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the
highest operating ambient temperature of interest and read rDS(on) from Figure 20. Using this value, the power
dissipation per switch can be calculated by:
• PD = rDS(on)× I2
Multiply this number by the number of switches being used. This step renders the total power dissipation from
the N-channel MOSFETs.
The thermal resistance, RθJA = 1 / (DERATING FACTOR), where DERATING FACTOR is obtained from the
Dissipation Ratings Table. Thermal resistance is a strong function of the printed circuit board construction , and
the copper trace area connecting the integrated circuit.
Finally, calculate the junction temperature:
• TJ = PD x RθJA + TA
Where:
• TA= Ambient temperature °C
• RθJA = Thermal resistance
• PD = Total power dissipation based on number of switches being used.
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.
THERMAL PROTECTION
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The TPS206x implements a thermal sensing to monitor the operating junction
temperature of the power distribution switch. In an overcurrent or short-circuit condition, the junction temperature
rises due to excessive power dissipation. Once the die temperature rises above a minimum of 135°C due to
overcurrent conditions, the internal thermal sense circuitry turns the power switch off, thus preventing the power
switch from damage. Hysteresis is built into the thermal sense circuit, and after the device has cooled
approximately 10°C, the switch turns back on. The switch continues to cycle in this manner until the load fault or
input power is removed. The OCx open-drain output is asserted (active low) when an overtemperature shutdown
or overcurrent occurs.
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UNDERVOLTAGE LOCKOUT (UVLO)
An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input
voltage falls below approximately 2 V, the power switch is quickly turned off. This facilitates the design of
hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The
UVLO also keeps the switch from being turned on until the power supply has reached at least 2 V, even if the
switch is enabled. On reinsertion, the power switch is turned on, with a controlled rise time to reduce EMI and
voltage overshoots.
UNIVERSAL SERIAL BUS (USB) APPLICATIONS
The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for
low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB
interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for
differential data, and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply.
The USB specification defines the following five classes of devices, each differentiated by power-consumption
requirements:
• Hosts/self-powered hubs (SPH)
• Bus-powered hubs (BPH)
• Low-power, bus-powered functions
• High-power, bus-powered functions
• Self-powered functions
SPHs and BPHs distribute data and power to downstream functions. The TPS206x has higher current capability
than required by one USB port; so, it can be used on the host side and supplies power to multiple downstream
ports or functions.
HOST/SELF-POWERED AND BUS-POWERED HUBS
Hosts and SPHs have a local power supply that powers the embedded functions and the downstream ports (see
Figure 27). This power supply must provide from 5.25 V to 4.75 V to the board side of the downstream
connection under full-load and no-load conditions. Hosts and SPHs are required to have current-limit protection
and must report overcurrent conditions to the USB controller. Typical SPHs are desktop PCs, monitors, printers,
and stand-alone hubs.
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SLVS490I – DECEMBER 2003 – REVISED OCTOBER 2009
Downstream
USB Ports
D+
D−
VBUS
0.1 µF
33 µF
GND
Power Supply
3.3 V
5V
D+
TPS2062
2
IN
OUT1
0.1 µF
VBUS
0.1 µF
8
3
USB
Controller
D−
7
5
4
33 µF
GND
OC1
EN1
D+
OC2
EN2
OUT2
GND
D−
6
VBUS
0.1 µF
33 µF
GND
1
D+
D−
VBUS
0.1 µF
33 µF
GND
Figure 27. Typical Four-Port USB Host / Self-Powered Hub
BPHs obtain all power from upstream ports and often contain an embedded function. The hubs are required to
power up with less than one unit load. The BPH usually has one embedded function, and power is always
available to the controller of the hub. If the embedded function and hub require more than 100 mA on power up,
the power to the embedded function may need to be kept off until enumeration is completed. This can be
accomplished by removing power or by shutting off the clock to the embedded function. Power switching the
embedded function is not necessary if the aggregate power draw for the function and controller is less than one
unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the
embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.
LOW-POWER BUS-POWERED AND HIGH-POWER BUS-POWERED FUNCTIONS
Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power
functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and can
draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω
and 10 μF at power up, the device must implement inrush current limiting (see Figure 28). With TPS206x, the
internal functions could draw more than 500 mA, which fits the needs of some applications such as motor driving
circuits.
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SLVS490I – DECEMBER 2003 – REVISED OCTOBER 2009
Power Supply
3.3 V
D+
D−
VBUS
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TPS2062
2
10 µF
0.1 µF
IN
OUT1
GND
8
3
USB
Control
5
4
7
0.1 µF
10 µF
Internal
Function
0.1 µF
10 µF
Internal
Function
OC1
EN1
OC2
EN2
OUT2
GND
1
6
Figure 28. High-Power Bus-Powered Function
USB POWER-DISTRIBUTION REQUIREMENTS
USB can be implemented in several ways, and, regardless of the type of USB device being developed, several
power-distribution features must be implemented.
• Hosts/SPHs must:
– Current-limit downstream ports
– Report overcurrent conditions on USB VBUS
• BPHs must:
– Enable/disable power to downstream ports
– Power up at <100 mA
– Limit inrush current (<44 Ω and 10 μF)
• Functions must:
– Limit inrush currents
– Power up at <100 mA
The feature set of the TPS206x allows them to meet each of these requirements. The integrated current-limiting
and overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable and controlled rise
times meet the need of both input and output ports on bus-powered hubs, as well as the input ports for
bus-powered functions (see Figure 29).
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SLVS490I – DECEMBER 2003 – REVISED OCTOBER 2009
TUSB2040
Hub Controller
Upstream
Port
SN75240
BUSPWR
A C
B D
GANGED
D+
D−
DP0
DP1
DM0
DM1
Tie to TPS2041 EN Input
D+
5V
IN
DM2
5-V Power
Supply
EN
33 µF†
DM3
D+
A C
B D
1 µF
TPS76333
4.7 µF
5V
DP3
OUT
0.1 µF
D−
SN75240
Ferrite Beads
GND
DP4
IN
3.3 V
4.7 µF
VCC
DM4
5V
TPS2062
GND
PWRON1
GND
OVRCUR1
48-MHz
Crystal
XTAL1
33 µF†
EN1 OUT1
OC1 OUT2
PWRON2
EN2
OVRCUR2
OC2
D+
IN
0.1 µF
Tuning
Circuit
D−
GND
SN75240
DP2
OC
Ferrite Beads
A C
B D
GND
TPS2041B
Downstream
Ports
D−
Ferrite Beads
GND
XTAL2
5V
OCSOFF
33 µF†
GND
D+
Ferrite Beads
D−
GND
5V
†
33 µF†
USB rev 1.1 requires 120 µF per hub.
Figure 29. Hybrid Self / Bus-Powered Hub Implementation
GENERIC HOT-PLUG APPLICATIONS
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen by
the main power supply and the card being inserted. The most effective way to control these surges is to limit and
slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Due to the controlled rise times and fall times of the TPS206x, these devices can be used to
provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of the TPS206x
also ensures that the switch is off after the card has been removed, and that the switch is off during the next
insertion. The UVLO feature insures a soft start with a controlled rise time for every insertion of the card or
module.
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PC Board
TPS2062
OC1
GND
Power
Supply
2.7 V to 5.5 V
1000 µF
Optimum
0.1 µF
IN
EN1
EN2
Block of
Circuitry
OUT1
OUT2
OC2
Block of
Circuitry
Overcurrent Response
Figure 30. Typical Hot-Plug Implementation
By placing the TPS206x between the VCC input and the rest of the circuitry, the input power reaches these
devices first after insertion. The typical rise time of the switch is approximately 1 ms, providing a slow voltage
ramp at the output of the device. This implementation controls system surge currents and provides a
hot-plugging mechanism for any device.
DETAILED DESCRIPTION
Power Switch
The power switch is an N-channel MOSFET with a low on-state resistance. Configured as a high-side switch, the
power switch prevents current flow from OUT to IN and IN to OUT when disabled. The power switch supplies a
minimum current of 1 A.
Charge Pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
little supply current.
Driver
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall
times of the output voltage.
Enable (ENx or ENx)
The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce
the supply current. The supply current is reduced to less than 1 μA when a logic high is present on ENx, or when
a logic low is present on ENx. A logic zero input on ENx, or a logic high input on ENx restores bias to the drive
and control circuits and turns the switch on. The enable input is compatible with both TTL and CMOS logic
levels.
Overcurrent (OCx)
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output remains asserted until the overcurrent or overtemperature condition is removed. A
10-ms deglitch circuit prevents the OCx signal from oscillation or false triggering. If an overtemperature shutdown
occurs, the OCx is asserted instantaneously.
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SLVS490I – DECEMBER 2003 – REVISED OCTOBER 2009
Current Sense
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its
saturation region, which switches the output into a constant-current mode and holds the current constant while
varying the voltage on the load.
Thermal Sense
The TPS206x implements a thermal sensing to monitor the operating temperature of the power distribution
switch. In an overcurrent or short-circuit condition the junction temperature rises. When the die temperature rises
to approximately 140°C due to overcurrent conditions, the internal thermal sense circuitry turns off the switch,
thus preventing the device from damage. Hysteresis is built into the thermal sense, and after the device has
cooled approximately 10 degrees, the switch turns back on. The switch continues to cycle off and on until the
fault is removed. The open-drain false reporting output (OCx) is asserted (active low) when an overtemperature
shutdown or overcurrent occurs.
Undervoltage Lockout
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control
signal turns off the power switch.
spacer
REVISION HISTORY
Changes from Original (December 2003) to Revision A
Page
•
Added devices to the data sheet- TPS2063, TPS2065, TPS2066, TPS2067 ...................................................................... 1
•
Added the General Switch Catalog ....................................................................................................................................... 1
Changes from Revision A (July 2004) to Revision B
Page
•
Changed Features Bullet From: UL Pending To: UL Listed - File No. E169910 .................................................................. 1
•
Changed Electrical Characteristics - CURRENT LIMIT information. .................................................................................... 4
Changes from Revision C (January 2006) to Revision D
•
Page
Changed ORDERING INFORMATION table ........................................................................................................................ 2
Changes from Revision D (Februaty 2007) to Revision E
•
Page
Changed General Switch Catalog information. ..................................................................................................................... 1
Changes from Revision E (September 2007) to Revision F
Page
•
Added the DBV-5 package. .................................................................................................................................................. 1
•
Added the DBV-5 package option. ....................................................................................................................................... 1
•
Added the DBV-5 package option to the Dissipation Ratings table. .................................................................................... 3
•
Changed Thermal Sense paragraph: From: Once the die temperature rises to approximately 140°C To: Once the
die temperature rises above a minimum of 135°C ............................................................................................................. 17
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Changes from Revision F (April 2008) to Revision G
•
Page
Changed DBV-5 to Product Preview. ................................................................................................................................... 1
Changes from Revision G (July 2008) to Revision H
Page
•
Deleted Product Preview from the DBV package ................................................................................................................. 1
•
Changed TPS2061DBV status From Preview to Active ....................................................................................................... 2
•
Changed TPS2065DBV status From Preview to Active ....................................................................................................... 2
Changes from Revision H (December 2008) to Revision I
Page
•
Changed the ESD statement ................................................................................................................................................ 2
•
Deleted temp range of 0°C to 70°C from the Available Option table. .................................................................................. 2
•
Added Note to the Available Options table - The printed circuit board layout is important for control of temperature
rise when operated at high ambient temperatures ............................................................................................................... 2
•
Deleted temp range of 0°C to 70°C from the Ordering Information table. ............................................................................ 2
•
Added Note to the Ordering Information table - The printed circuit board layout is important for control of
temperature rise when operated at high ambient temperatures ........................................................................................... 2
•
Changed the Abs Max Ratings table - Operating virtual junction temperature range From: -40°C to 125°C To: -40°C
to 150°C ................................................................................................................................................................................ 3
•
Deleted Storage temperature range, Tstg from the Abs Max Ratings table .......................................................................... 3
•
Deleted MIL-STD-883C reference from ESD in the Abs Max table ..................................................................................... 3
•
Added 3 table notes to the Dissipation Ratings table. .......................................................................................................... 3
•
Added Addition values for the DBV-5 option in the Dissipation Ratings table. .................................................................... 3
•
Deleted Note - Not tested in production, specified by design from rDS(on) in the Electrical Characteristics table. ................ 3
•
Deleted Note - Not tested in production, specified by design from tr in the Electrical Characteristics table. ....................... 3
•
Deleted Note - Not tested in production, specified by design from tf in the Electrical Characteristics table. ....................... 3
•
Added text to the POWER DISSIPATION section - The thermal resistance, RθJA ............................................................. 17
24
Submit Documentation Feedback
Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067
PACKAGE OPTION ADDENDUM
www.ti.com
27-Oct-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS2061D
ACTIVE
SOIC
D
8
TPS2061DBVR
ACTIVE
SOT-23
DBV
TPS2061DBVT
ACTIVE
SOT-23
TPS2061DG4
ACTIVE
TPS2061DGN
75
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
MSOPPower
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2061DGNG4
ACTIVE
MSOPPower
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2061DGNR
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2061DGNRG4
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2061DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2061DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2062D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2062DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2062DGN
ACTIVE
MSOPPower
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2062DGNG4
ACTIVE
MSOPPower
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2062DGNR
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2062DGNRG4
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2062DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2062DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2063D
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2063DG4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2063DR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2063DRG4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
27-Oct-2009
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS2065D
ACTIVE
SOIC
D
8
TPS2065DBVR
ACTIVE
SOT-23
DBV
TPS2065DBVT
ACTIVE
SOT-23
TPS2065DG4
ACTIVE
TPS2065DGN
Lead/Ball Finish
MSL Peak Temp (3)
no Sb/Br)
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
MSOPPower
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2065DGNG4
ACTIVE
MSOPPower
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2065DGNR
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2065DGNRG4
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2065DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2065DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2066D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2066DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2066DGN
ACTIVE
MSOPPower
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2066DGNG4
ACTIVE
MSOPPower
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2066DGNR
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2066DGNRG4
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2066DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2066DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2066ID
PREVIEW
SOIC
D
8
TPS2066IDR
PREVIEW
SOIC
D
8
TPS2067D
ACTIVE
SOIC
D
16
40
TPS2067DG4
ACTIVE
SOIC
D
16
40
TPS2067DR
ACTIVE
SOIC
D
16
TBD
Call TI
Call TI
TBD
Call TI
Call TI
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2500 Green (RoHS &
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
27-Oct-2009
Orderable Device
Status (1)
Package
Type
Package
Drawing
TPS2067DRG4
ACTIVE
SOIC
D
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
no Sb/Br)
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS2062 :
• Automotive: TPS2062-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Oct-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TPS2061DBVR
SOT-23
3000
179.0
TPS2061DBVT
TPS2061DGNR
DBV
5
SOT-23
DBV
5
250
MSOPPower
PAD
DGN
8
2500
B0
(mm)
K0
(mm)
P1
(mm)
8.4
3.2
3.2
1.4
4.0
179.0
8.4
3.2
3.2
1.4
330.0
12.4
5.3
3.3
1.3
W
Pin1
(mm) Quadrant
8.0
Q3
4.0
8.0
Q3
8.0
12.0
Q1
TPS2061DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TPS2062DGNR
MSOPPower
PAD
DGN
8
2500
330.0
12.4
5.3
3.3
1.3
8.0
12.0
Q1
TPS2062DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TPS2063DR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
TPS2065DBVR
SOT-23
DBV
5
3000
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS2065DBVT
SOT-23
DBV
5
250
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS2065DGNR
MSOPPower
PAD
DGN
8
2500
330.0
12.4
5.3
3.3
1.3
8.0
12.0
Q1
TPS2065DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TPS2066DGNR
MSOPPower
PAD
DGN
8
2500
330.0
12.4
5.3
3.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Oct-2009
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS2066DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TPS2067DR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
TPS2067DR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS2061DBVR
SOT-23
DBV
5
3000
195.0
200.0
45.0
TPS2061DBVT
SOT-23
DBV
5
250
195.0
200.0
45.0
TPS2061DGNR
MSOP-PowerPAD
DGN
8
2500
370.0
355.0
55.0
TPS2061DR
SOIC
D
8
2500
340.5
338.1
20.6
TPS2062DGNR
MSOP-PowerPAD
DGN
8
2500
370.0
355.0
55.0
TPS2062DR
SOIC
D
8
2500
340.5
338.1
20.6
TPS2063DR
SOIC
D
16
2500
346.0
346.0
33.0
TPS2065DBVR
SOT-23
DBV
5
3000
195.0
200.0
45.0
TPS2065DBVT
SOT-23
DBV
5
250
195.0
200.0
45.0
TPS2065DGNR
MSOP-PowerPAD
DGN
8
2500
370.0
355.0
55.0
TPS2065DR
SOIC
D
8
2500
340.5
338.1
20.6
TPS2066DGNR
MSOP-PowerPAD
DGN
8
2500
370.0
355.0
55.0
TPS2066DR
SOIC
D
8
2500
340.5
338.1
20.6
TPS2067DR
SOIC
D
16
2500
346.0
346.0
33.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Oct-2009
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS2067DR
SOIC
D
16
2500
333.2
345.9
28.6
Pack Materials-Page 3
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