D−8 D−16 TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067 DBV−5 DGN−8 DRB−8 www.ti.com ................................................................................................................................................... SLVS490G – DECEMBER 2003 – REVISED JULY 2008 CURRENT-LIMITED, POWER-DISTRIBUTION SWITCHES FEATURES APPLICATIONS • • • • • • 1 2 • • • • • • • • • • 70-mΩ High-Side MOSFET 1-A Continuous Current Thermal and Short-Circuit Protection Accurate Current Limit (1.1 A min, 1.9 A max) Operating Range: 2.7 V to 5.5 V 0.6-ms Typical Rise Time Undervoltage Lockout Deglitched Fault Report (OC) No OC Glitch During Power Up 1-µA Maximum Standby Supply Current Bidirectional Switch Ambient Temperature Range: -40°C to 85°C Built-in Soft-Start UL Listed - File No. E169910 Heavy Capacitive Loads Short-Circuit Protections TPS2062/TPS2066 D AND DGN PACKAGE (TOP VIEW) TPS2061/TPS2065 D AND DGN PACKAGE (TOP VIEW) GND IN IN EN 1 2 3 4 † OUT OUT OUT 8 7 6 5 OC GND IN † EN1 † EN2 GND IN IN1 GND OC † EN 8 7 6 5 OC1 OUT1 OUT2 OC2 TPS2063/TPS2067 D PACKAGE (TOP VIEW) TPS2061/TPS2065 DBV PACKAGE (TOP VIEW) OUT 1 2 3 4 † EN1 † EN2 GND IN2 † EN3 NC 1 2 3 4 5 6 7 8 16 15 14 OC1 OUT1 OUT2 13 12 11 10 9 OC2 OC3 OUT3 NC NC † All Enable Inputs Are Active High For TPS2065, TPS2066, and TPS2067 DESCRIPTION The TPS206x power-distribution switches are intended for applications where heavy capacitive loads and short-circuits are likely to be encountered. This device incorporates 70-mΩ N-channel MOSFET power switches for power-distribution systems that require multiple power switches in a single package. Each switch is controlled by a logic enable input. Gate drive is provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize current surges during switching. The charge pump requires no external components and allows operation from supplies as low as 2.7 V. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2008, Texas Instruments Incorporated TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067 SLVS490G – DECEMBER 2003 – REVISED JULY 2008 ................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) When the output load exceeds the current-limit threshold or a short is present, the device limits the output current to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic output low. When continuous heavy overloads and short-circuits increase the power dissipation in the switch, causing the junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures that the switch remains off until valid input voltage is present. This power-distribution switch is designed to set current limit at 1.5 A typically. AVAILABLE OPTION AND ORDERING INFORMATION TA ENABLE RECOMMEND ED MAXIMUM CONTINUOUS LOAD CURRENT TYPICAL SHORTCIRCUIT CURRENT LIMIT AT 25°C PACKAGED DEVICES (1) NUMBER OF SWITCHES Active low Single Active high -40°C to 85°C Active low Active high Active low Dual 1A 1.5 A (1) SOIC (D) SOT23 (DBV) TPS2061DGN TPS2061D - TPS2065DGN TPS2065D - TPS2062DGN TPS2062D - TPS2066DGN TPS2066D - - TPS2063D - - TPS2067D - - - TPS2061DBV - - TPS2065DBV Triple Active high 0°C to 70°C MSOP (DGN) Active low Single Active high The package is available taped and reeled. Add an R suffix to device types (e.g., TPS2062DR). ORDERING INFORMATION TA -40°C to 85°C 0°C to 70°C (1) 2 SOIC(D) (1) STATUS MSOP (DGN) (1) STATUS SOT23 (DBV) STATUS TPS2061DG4 Active TPS2061DGNG4 Active - - TPS2062DG4 Active TPS2062DGNG4 Active - - TPS2065DG4 Active TPS2065DGNG4 Active - - TPS2066DG4 Active TPS2066DGNG4 Active - - - - - - TPS2061DBV Preview - - - - TPS2065DBV Preview For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067 TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067 www.ti.com ................................................................................................................................................... SLVS490G – DECEMBER 2003 – REVISED JULY 2008 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) UNIT Input voltage range, VI(IN) (2) -0.3 V to 6 V Output voltage range, VO(OUT) (2), VO(OUTx) -0.3 V to 6 V Input voltage range, VI(EN), VI(EN), VI(ENx), VI(ENx) -0.3 V to 6 V Voltage range, VI(OC), VI(OCx) -0.3 V to 6 V Continuous output current, IO(OUT), IO(OUTx) Internally limited Continuous total power dissipation See Dissipation Rating Table Operating virtual junction temperature range, TJ -40°C to 125°C Storage temperature range, Tstg -65°C to 150°C Electrostatic discharge (ESD) protection (1) (2) Human body model MIL-STD-883C 2 kV Charge device model (CDM) 500 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. DISSIPATING RATING TABLE (1) PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING D-8 585.82 mW 5.8582 mW/°C 322.20 mW 234.32 mW DGN-8 1712.3 mW 17.123 mW/°C 941.78 mW 684.33 mW D-16 898.47 mW 8.9847 mW/°C 494.15 mW 359.38 mW DBV-5 (1) 285 mW 2.85 mW/°C 155 mW 114 mW Product Preview RECOMMENDED OPERATING CONDITIONS Input voltage, VI(IN) Input voltage, VI(EN), VI(EN), VI(ENx), VI(ENx) Continuous output current, IO(OUT), IO(OUTx) Operating virtual junction temperature, TJ MIN MAX 2.7 5.5 UNIT V 0 5.5 V 0 1 A -40 125 °C ELECTRICAL CHARACTERISTICS over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = 1 A, VI(ENx) = 0 V, or VI(ENx) = 5.5 V (unless otherwise noted) TEST CONDITIONS (1) PARAMETER MIN TYP MAX UNIT POWER SWITCH rDS(on) tr (2) tf (2) (1) (2) Static drain-source on-state resistance, 5-V operation and 3.3-V operation VI(IN) = 5 V or 3.3 V, IO = 1 A, -40°C ≤ TJ ≤ 125°C 70 135 mΩ Static drain-source on-state resistance, 2.7-V operation (2) VI(IN) = 2.7 V, IO = 1 A, -40°C ≤ TJ ≤ 125°C 75 150 mΩ VI(IN) = 5.5 V 0.6 1.5 VI(IN) = 2.7 V 0.4 1 Rise time, output Fall time, output VI(IN) = 5.5 V VI(IN) = 2.7 V CL = 1 µF, RL = 5 Ω, TJ = 25°C 0.05 0.5 0.05 0.5 ms Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. Not tested in production, specified by design. Copyright © 2003–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067 3 TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067 SLVS490G – DECEMBER 2003 – REVISED JULY 2008 ................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = 1 A, VI(ENx) = 0 V, or VI(ENx) = 5.5 V (unless otherwise noted) TEST CONDITIONS (1) PARAMETER MIN TYP MAX UNIT ENABLE INPUT EN OR EN VIH High-level input voltage 2.7 V ≤ VI(IN) ≤ 5.5 V VIL Low-level input voltage 2.7 V ≤ VI(IN) ≤ 5.5 V II Input current VI(ENx) = 0 V or 5.5 V, VI(ENx) = 0 V or 5.5 V ton Turnon time CL = 100 µF, RL = 5 Ω 3 toff Turnoff time CL = 100 µF, RL = 5 Ω 10 2 0.8 -0.5 0.5 V µA ms CURRENT LIMIT IOS Short-circuit output current VI(IN) = 5 V, OUT connected to GND, device enabled into short-circuit IOC_TRIP Overcurrent trip threshold VI(IN) = 5 V, current ramp (≤ 100 A/s) on OUT TJ = 25°C 1.1 1.5 1.9 -40°C ≤ TJ ≤ 125°C 1.1 1.5 2.1 TPS2061, TPS2062, TPS2065, TPS2066 1.6 2.3 2.7 TPS2063, TPS2067 1.6 2.4 3.0 A A SUPPLY CURRENT (TPS2061, TPS2065) Supply current, low-level output No load on OUT, VI(ENx) = 5.5 V, or VI(ENx) = 0 V TJ = 25°C 0.5 1 -40°C ≤ TJ ≤ 125°C 0.5 5 Supply current, high-level output No load on OUT, VI(ENx) = 0 V, or VI(ENx) = 5.5 V TJ = 25°C 43 60 -40°C ≤ TJ ≤ 125°C 43 70 Leakage current OUT connected to ground, VI(EN) = 5.5 V, or VI(EN) = 0 V -40°C ≤ TJ ≤ 125°C 1 µA Reverse leakage current VI(OUTx) = 5.5 V, IN = ground TJ = 25°C 0 µA Supply current, low-level output No load on OUT, VI(ENx) = 5.5 V, or VI(ENx) = 0 V TJ = 25°C 0.5 1 -40°C ≤ TJ ≤ 125°C 0.5 5 Supply current, high-level output No load on OUT, VI(ENx) = 0 V, or VI(ENx) = 5.5 V TJ = 25°C 50 70 -40°C ≤ TJ ≤ 125°C 50 90 Leakage current OUT connected to ground, VI(/ENx) = 5.5 V, or VI(ENx) = 0 V -40°C ≤ TJ ≤ 125°C 1 µA Reverse leakage current VI(OUTx) = 5.5 V, IN = ground TJ = 25°C 0.2 µA TJ = 25°C 0.5 2 -40°C ≤ TJ ≤ 125°C 0.5 10 TJ = 25°C 65 90 -40°C ≤ TJ ≤ 125°C 65 110 1 µA 0.2 µA µA µA SUPPLY CURRENT (TPS2062, TPS2066) µA µA SUPPLY CURRENT (TPS2063, TPS2067) Supply current, low-level output No load on OUT, VI(ENx) = 0 V Supply current, high-level output No load on OUT, VI(ENx) = 5.5 V Leakage current OUT connected to ground, VI(ENx) = 5.5 V, or VI(ENx) = 0 V -40°C ≤ TJ ≤ 125°C Reverse leakage current VI(OUTx) = 5.5 V, INx = ground TJ = 25°C µA µA UNDERVOLTAGE LOCKOUT Low-level input voltage, IN 2 Hysteresis, IN TJ = 25°C 2.5 75 V mV OVERCURRENT OC1 and OC2 Output low voltage, VOL(OCx) IO(OCx) = 5 mA Off-state current VO(OCx) = 5 V or 3.3 V OC deglitch OCx assertion or deassertion 4 8 0.4 V 1 µA 15 ms THERMAL SHUTDOWN (3) Thermal shutdown threshold 135 Recovery from thermal shutdown 125 Hysteresis (3) 4 °C °C 10 °C The thermal shutdown only reacts under overcurrent conditions. Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067 TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067 www.ti.com ................................................................................................................................................... SLVS490G – DECEMBER 2003 – REVISED JULY 2008 DEVICE INFORMATION Pin Functions (TPS2061 and TPS2065) PINS D or DGN Package NAME TPS2061 DBV Package TPS2065 TPS2061 I/O DESCRIPTION TPS2065 EN 4 - 4 - I Enable input, logic low turns on power switch EN - 4 - 4 I Enable input, logic high turns on power switch GND 1 1 2 2 IN 2, 3 2,3 5 5 I Input voltage OC 5 5 3 3 O Overcurrent, open-drain output, active-low 6, 7, 8 6, 7, 8 1 1 O Power-switch output - - - - OUT PowerPAD™ Ground Internally connected to GND; used to heat-sink the part to the circuit board traces. Should be connected to GND pin. Functional Block Diagram (See Note A) CS IN OUT Charge Pump EN (See Note B) Driver Current Limit OC UVLO Thermal Sense GND Deglitch Note A: Current sense Note B: Active low (EN) for TPS2061. Active high (EN) for TPS2065. Copyright © 2003–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067 5 TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067 SLVS490G – DECEMBER 2003 – REVISED JULY 2008 ................................................................................................................................................... www.ti.com Pin Functions (TPS2062 and TPS2066) PINS NAME I/O NO. DESCRIPTION TPS2062 TPS2066 EN1 3 - I Enable input, logic low turns on power switch IN-OUT1 EN2 4 - I Enable input, logic low turns on power switch IN-OUT2 EN1 - 3 I Enable input, logic high turns on power switch IN-OUT1 EN2 - 4 I Enable input, logic high turns on power switch IN-OUT2 GND 1 1 IN 2 2 I Input voltage OC1 8 8 O Overcurrent, open-drain output, active low, IN-OUT1 OC2 5 5 O Overcurrent, open-drain output, active low, IN-OUT2 OUT1 7 7 O Power-switch output, IN-OUT1 OUT2 6 6 O Power-switch output, IN-OUT2 PowerPAD™ - - Ground Internally connected to GND; used to heat-sink the part to the circuit board traces. Should be connected to GND pin. Functional Block Diagram OC1 Thermal Sense GND Deglitch EN1 (See Note B) Driver Current Limit Charge Pump (See Note A) CS OUT1 UVLO (See Note A) IN CS OUT2 Charge Pump Driver Current Limit OC2 EN2 (See Note B) Thermal Sense Deglitch Note A: Current sense Note B: Active low (ENx) for TPS2062. Active high (ENx) for TPS2066. 6 Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067 TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067 www.ti.com ................................................................................................................................................... SLVS490G – DECEMBER 2003 – REVISED JULY 2008 Pin Functions (TPS2063 and TPS2067) PINS NAME I/O DESCRIPTION TPS2063 TPS2067 EN1 3 – I Enable input, logic low turns on power switch IN1-OUT1 EN2 4 – I Enable input, logic low turns on power switch IN1-OUT2 EN3 7 – I Enable input, logic low turns on power switch IN2-OUT3 EN1 – 3 I Enable input, logic high turns on power switch IN1-OUT1 EN2 – 4 I Enable input, logic high turns on power switch IN1-OUT2 EN3 – 7 I Enable input, logic high turns on power switch IN2-OUT3 GND 1, 5 1, 5 IN1 2 2 I Ground Input voltage for OUT1 and OUT2 IN2 6 6 I Input voltage for OUT3 NC 8, 9, 10 8, 9, 10 OC1 16 16 O No connection Overcurrent, open-drain output, active low, IN1-OUT1 OC2 13 13 O Overcurrent, open-drain output, active low, IN1-OUT2 OC3 12 12 O Overcurrent, open-drain output, active low, IN2-OUT3 OUT1 15 15 O Power-switch output, IN1-OUT1 OUT2 14 14 O Power-switch output, IN1-OUT2 OUT3 11 11 O Power-switch output, IN2-OUT3 Copyright © 2003–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067 7 TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067 SLVS490G – DECEMBER 2003 – REVISED JULY 2008 ................................................................................................................................................... www.ti.com Functional Block Diagram OC1 Thermal Sense GND Deglitch EN1 (See Note B) Driver Current Limit (See Note A) CS OUT1 UVLO (See Note A) IN1 OUT2 CS Driver Current Limit OC2 EN2 (See Note B) VCC Selector Thermal Sense Deglitch Charge Pump (See Note A) IN2 CS EN3 Driver OUT3 Current Limit (See Note B) OC3 UVLO Thermal Sense GND Deglitch Note A: Current sense Note B: Active low (ENx) for TPS2063; Active high (ENx) for TPS2067 8 Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067 TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067 www.ti.com ................................................................................................................................................... SLVS490G – DECEMBER 2003 – REVISED JULY 2008 PARAMETER MEASUREMENT INFORMATION OUT RL tf tr CL VO(OUT) 90% 90% 10% 10% TEST CIRCUIT 50% VI(EN) 50% toff ton VO(OUT) 50% VI(EN) 90% 50% toff ton 90% VO(OUT) 10% 10% VOLTAGE WAVEFORMS Figure 1. Test Circuit and Voltage Waveforms VI(EN) 5 V/div RL = 5 W, CL = 1 mF TA = 255C VI(EN) 5 V/div RL = 5 W, CL = 1 mF TA = 255C VO(OUT) 2 V/div VO(OUT) 2 V/div t − Time − 500 ms/div Figure 2. Turnon Delay and Rise Time With 1-µF Load Copyright © 2003–2008, Texas Instruments Incorporated t − Time − 500 ms/div Figure 3. Turnoff Delay and Fall Time With 1-µF Load Submit Documentation Feedback Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067 9 TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067 SLVS490G – DECEMBER 2003 – REVISED JULY 2008 ................................................................................................................................................... www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) RL = 5 W, CL = 100 mF TA = 255C VI(EN) 5 V/div VI(EN) 5 V/div RL = 5 W, CL = 100 mF TA = 255C VO(OUT) 2 V/div VO(OUT) 2 V/div t − Time − 500 ms/div t − Time − 500 ms/div Figure 4. Turnon Delay and Rise Time With 100-µF Load VI(EN) 5 V/div Figure 5. Turnoff Delay and Fall Time With 100-µF Load VIN = 5 V RL = 5 W, TA = 255C VI(EN) 5 V/div 220 mF 470 mF IO(OUT) 500 mA/div IO(OUT) 500 mA/div t − Time − 500 ms/div Figure 6. Short-Circuit Current, Device Enabled Into Short 10 Submit Documentation Feedback 100 mF t − Time − 1 ms/div Figure 7. Inrush Current With Different Load Capacitance Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067 TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067 www.ti.com ................................................................................................................................................... SLVS490G – DECEMBER 2003 – REVISED JULY 2008 PARAMETER MEASUREMENT INFORMATION (continued) VO(OC) 2 V/div VO(OC) 2 V/div IO(OUT) 1 A/div IO(OUT) 1 A/div t − Time − 2 ms/div t − Time − 2 ms/div Figure 8. 2-Ω Load Connected to Enabled Device Figure 9. 1-Ω Load Connected to Enabled Device TYPICAL CHARACTERISTICS TURNON TIME vs INPUT VOLTAGE TURNOFF TIME vs INPUT VOLTAGE 1.0 2 CL = 100 mF, RL = 5 W, TA = 255C 0.9 0.8 CL = 100 mF, RL = 5 W, TA = 255C 1.9 Turnoff Time − mS Turnon Time − ms 0.7 0.6 0.5 0.4 0.3 0.2 1.8 1.7 1.6 0.1 0 2 3 4 5 VI − Input Voltage − V Figure 10. Copyright © 2003–2008, Texas Instruments Incorporated 6 1.5 2 3 4 5 VI − Input Voltage − V 6 Figure 11. Submit Documentation Feedback Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067 11 TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067 SLVS490G – DECEMBER 2003 – REVISED JULY 2008 ................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) RISE TIME vs INPUT VOLTAGE FALL TIME vs INPUT VOLTAGE 0.25 0.6 0.5 0.2 0.4 Fall Time − ms Rise Time − ms CL = 1 mF, RL = 5 W, TA = 255C CL = 1 mF, RL = 5 W, TA = 255C 0.3 0.15 0.1 0.2 0.05 0.1 0 2 3 4 5 VI − Input Voltage − V 0 6 2 Figure 13. TPS2061, TPS2065 SUPPLY CURRENT, OUTPUT ENABLED vs JUNCTION TEMPERATURE TPS2062, TPS2066 SUPPLY CURRENT, OUTPUT ENABLED vs JUNCTION TEMPERATURE I I (IN) − Supply Current, Output Enabled − µ A I I (IN) − Supply Current, Output Enabled − µ A 6 70 VI = 5.5 V 50 VI = 5 V 40 30 VI = 2.7 V 20 VI = 3.3 V 10 0 50 100 TJ − Junction Temperature − 5C Figure 14. 12 4 5 VI − Input Voltage − V Figure 12. 60 0 −50 3 Submit Documentation Feedback 150 VI = 5.5 V 60 50 VI = 5 V VI = 3.3 V 40 30 VI = 2.7 V 20 10 0 −50 0 50 100 150 TJ − Junction Temperature − 5C Figure 15. Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067 TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067 www.ti.com ................................................................................................................................................... SLVS490G – DECEMBER 2003 – REVISED JULY 2008 TYPICAL CHARACTERISTICS (continued) TPS2063, TPS2067 SUPPLY CURRENT, OUTPUT ENABLED vs JUNCTION TEMPERATURE TPS2061, TPS2065 SUPPLY CURRENT, OUTPUT DISABLED vs JUNCTION TEMPERATURE I I (IN) − Supply Current, Output Disabled − µ A 80 VI = 5.5 V 70 VI = 5 V 60 VI = 3.3 V 50 40 VI = 2.7 V 30 20 10 0 −50 I I (IN) − Supply Current, Output Disabled − µ A 0.5 0 50 100 TJ − Junction Temperature − 5C 0.3 VI = 2.7 V VI = 3.3 V 0.25 0.2 0.15 0.1 0.05 0 50 100 Figure 17. TPS2062, TPS2066 SUPPLY CURRENT, OUTPUT DISABLED vs JUNCTION TEMPERATURE TPS2063, TPS2067 SUPPLY CURRENT, OUTPUT DISABLED vs JUNCTION TEMPERATURE 150 0.5 VI = 5.5 V 0.4 0.35 VI = 2.7 V VI = 3.3 V 0.25 0.2 0.15 0.1 0.05 0 −50 0.35 TJ − Junction Temperature − 5C VI = 5 V 0.3 VI = 5 V 0.4 Figure 16. 0.5 0.45 VI = 5.5 V 0.45 0 −50 150 I I (IN) − Supply Current, Output Disabled − µ A I I (IN) − Supply Current, Output Enabled − µ A 90 0 50 100 TJ − Junction Temperature − 5C Figure 18. Copyright © 2003–2008, Texas Instruments Incorporated 150 0.45 VI = 5.5 V VI = 5 V 0.4 0.35 0.3 VI = 3.3 V VI = 2.7 V 0.25 0.2 0.15 0.1 0.05 0 −50 0 50 100 TJ − Junction Temperature − 5C 150 Figure 19. Submit Documentation Feedback Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067 13 TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067 SLVS490G – DECEMBER 2003 – REVISED JULY 2008 ................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 120 IO = 0.5 A SHORT-CIRCUIT OUTPUT CURRENT vs JUNCTION TEMPERATURE 1.56 I OS − Short-Circuit Output Current − A On-State Resistance − mΩ 100 r DS(on) − Static Drain-Source VI = 2.7 V 1.54 Out1 = 5 V Out1 = 3.3 V 80 Out1 = 2.7 V 60 40 20 1.52 VI = 3.3 V 1.5 1.48 1.46 1.44 VI = 5 V 1.42 VI = 5.5 V 1.4 1.38 1.36 1.34 0 −50 0 50 100 −50 150 100 150 UNDERVOLTAGE LOCKOUT vs JUNCTION TEMPERATURE 2.3 2.5 UVLO Rising UVOL − Undervoltage Lockout − V TA = 255C Load Ramp = 1A/10 ms 2.3 Threshold Trip Current − A 50 Figure 21. THRESHOLD TRIP CURRENT vs INPUT VOLTAGE 2.1 1.9 1.7 1.5 2.5 3 3.5 4 4.5 5 VI − Input Voltage − V Figure 22. 14 0 TJ − Junction Temperature − 5C TJ − Junction Temperature − 5C Figure 20. Submit Documentation Feedback 5.5 6 2.26 2.22 UVLO Falling 2.18 2.14 2.1 −50 0 50 100 150 TJ − Junction Temperature − 5C Figure 23. Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067 TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067 www.ti.com ................................................................................................................................................... SLVS490G – DECEMBER 2003 – REVISED JULY 2008 TYPICAL CHARACTERISTICS (continued) CURRENT-LIMIT RESPONSE vs PEAK CURRENT 200 Current-Limit Response − µ s VI = 5 V, TA = 255C 150 100 50 0 0 Copyright © 2003–2008, Texas Instruments Incorporated 2.5 5 7.5 Peak Current − A Figure 24. 10 12.5 Submit Documentation Feedback Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067 15 TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067 SLVS490G – DECEMBER 2003 – REVISED JULY 2008 ................................................................................................................................................... www.ti.com APPLICATION INFORMATION POWER-SUPPLY CONSIDERATIONS TPS2062 2 Power Supply 2.7 V to 5.5 V IN OUT1 0.1 µF 8 3 5 4 7 Load 0.1 µF 22 µF 0.1 µF 22 µF OC1 EN1 OUT2 6 OC2 Load EN2 GND 1 Figure 25. Typical Application A 0.01-µF to 0.1-µF ceramic bypass capacitor between IN and GND, close to the device, is recommended. Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy. This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing the output with a 0.01-µF to 0.1-µF ceramic capacitor improves the immunity of the device to short-circuit transients. OVERCURRENT A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do not increase the series resistance of the current path. When an overcurrent condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault is present long enough to activate thermal limiting. Three possible overload conditions can occur. In the first condition, the output has been shorted before the device is enabled or before VI(IN) has been applied (see Figure 15). The TPS206x senses the short and immediately switches into a constant-current output. In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload occurs, high currents may flow for a short period of time before the current-limit circuit can react. After the current-limit circuit has tripped (reached the overcurrent trip threshold), the device switches into constant-current mode. In the third condition, the load has been gradually increased beyond the recommended operating current. The current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is exceeded (see Figure 18). The TPS206x is capable of delivering current up to the current-limit threshold without damaging the device. Once the threshold has been reached, the device switches into its constant-current mode. OC RESPONSE The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature shutdown condition is encountered after a 10-ms deglitch timeout. The output remains asserted until the overcurrent or overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause a momentary overcurrent condition; however, no false reporting on OCx occurs due to the 10-ms deglitch circuit. The TPS206x is designed to eliminate false overcurrent reporting. The internal overcurrent deglitch eliminates the need for external components to remove unwanted pulses. OCx is not deglitched when the switch is turned off due to an overtemperature shutdown. 16 Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067 TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067 www.ti.com ................................................................................................................................................... SLVS490G – DECEMBER 2003 – REVISED JULY 2008 V+ TPS2062 GND Rpullup OC1 IN OUT1 EN1 OUT2 EN2 OC2 Figure 26. Typical Circuit for the OC Pin POWER DISSIPATION AND JUNCTION TEMPERATURE The low on-resistance on the N-channel MOSFET allows the small surface-mount packages to pass large currents. The thermal resistances of these packages are high compared to those of power packages; it is good design practice to check power dissipation and junction temperature. Begin by determining the rDS(on) of the N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and read rDS(on) from Figure 20. Using this value, the power dissipation per switch can be calculated by: • PD = rDS(on)× I2 Multiply this number by the number of switches being used. This step renders the total power dissipation from the N-channel MOSFETs. Finally, calculate the junction temperature: • TJ = PD x RθJA + TA Where: • TA= Ambient temperature °C • RθJA = Thermal resistance • PD = Total power dissipation based on number of switches being used. Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees, repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally sufficient to get a reasonable answer. THERMAL PROTECTION Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for extended periods of time. The TPS206x implements a thermal sensing to monitor the operating junction temperature of the power distribution switch. In an overcurrent or short-circuit condition, the junction temperature rises due to excessive power dissipation. Once the die temperature rises above a minimum of 135°C due to overcurrent conditions, the internal thermal sense circuitry turns the power switch off, thus preventing the power switch from damage. Hysteresis is built into the thermal sense circuit, and after the device has cooled approximately 10°C, the switch turns back on. The switch continues to cycle in this manner until the load fault or input power is removed. The OCx open-drain output is asserted (active low) when an overtemperature shutdown or overcurrent occurs. UNDERVOLTAGE LOCKOUT (UVLO) An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input voltage falls below approximately 2 V, the power switch is quickly turned off. This facilitates the design of hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The UVLO also keeps the switch from being turned on until the power supply has reached at least 2 V, even if the switch is enabled. On reinsertion, the power switch is turned on, with a controlled rise time to reduce EMI and voltage overshoots. Copyright © 2003–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067 17 TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067 SLVS490G – DECEMBER 2003 – REVISED JULY 2008 ................................................................................................................................................... www.ti.com UNIVERSAL SERIAL BUS (USB) APPLICATIONS The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data, and two lines are provided for 5-V power distribution. USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V from the 5-V input or its own internal power supply. The USB specification defines the following five classes of devices, each differentiated by power-consumption requirements: • Hosts/self-powered hubs (SPH) • Bus-powered hubs (BPH) • Low-power, bus-powered functions • High-power, bus-powered functions • Self-powered functions SPHs and BPHs distribute data and power to downstream functions. The TPS206x has higher current capability than required by one USB port; so, it can be used on the host side and supplies power to multiple downstream ports or functions. HOST/SELF-POWERED AND BUS-POWERED HUBS Hosts and SPHs have a local power supply that powers the embedded functions and the downstream ports (see Figure 27). This power supply must provide from 5.25 V to 4.75 V to the board side of the downstream connection under full-load and no-load conditions. Hosts and SPHs are required to have current-limit protection and must report overcurrent conditions to the USB controller. Typical SPHs are desktop PCs, monitors, printers, and stand-alone hubs. 18 Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067 TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067 www.ti.com ................................................................................................................................................... SLVS490G – DECEMBER 2003 – REVISED JULY 2008 Downstream USB Ports D+ D− VBUS 0.1 µF 33 µF GND Power Supply 3.3 V 5V D+ TPS2062 2 IN OUT1 0.1 µF VBUS 0.1 µF 8 3 USB Controller D− 7 5 4 33 µF GND OC1 EN1 D+ OC2 EN2 OUT2 GND D− 6 VBUS 0.1 µF 33 µF GND 1 D+ D− VBUS 0.1 µF 33 µF GND Figure 27. Typical Four-Port USB Host / Self-Powered Hub BPHs obtain all power from upstream ports and often contain an embedded function. The hubs are required to power up with less than one unit load. The BPH usually has one embedded function, and power is always available to the controller of the hub. If the embedded function and hub require more than 100 mA on power up, the power to the embedded function may need to be kept off until enumeration is completed. This can be accomplished by removing power or by shutting off the clock to the embedded function. Power switching the embedded function is not necessary if the aggregate power draw for the function and controller is less than one unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port. LOW-POWER BUS-POWERED AND HIGH-POWER BUS-POWERED FUNCTIONS Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and can draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω and 10 µF at power up, the device must implement inrush current limiting (see Figure 28). With TPS206x, the internal functions could draw more than 500 mA, which fits the needs of some applications such as motor driving circuits. Copyright © 2003–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067 19 TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067 SLVS490G – DECEMBER 2003 – REVISED JULY 2008 ................................................................................................................................................... www.ti.com Power Supply 3.3 V D+ D− VBUS TPS2062 2 10 µF 0.1 µF IN OUT1 GND 8 3 USB Control 5 4 7 0.1 µF 10 µF Internal Function 0.1 µF 10 µF Internal Function OC1 EN1 OC2 EN2 OUT2 GND 1 6 Figure 28. High-Power Bus-Powered Function USB POWER-DISTRIBUTION REQUIREMENTS USB can be implemented in several ways, and, regardless of the type of USB device being developed, several power-distribution features must be implemented. • Hosts/SPHs must: – Current-limit downstream ports – Report overcurrent conditions on USB VBUS • BPHs must: – Enable/disable power to downstream ports – Power up at <100 mA – Limit inrush current (<44 Ω and 10 µF) • Functions must: – Limit inrush currents – Power up at <100 mA The feature set of the TPS206x allows them to meet each of these requirements. The integrated current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable and controlled rise times meet the need of both input and output ports on bus-powered hubs, as well as the input ports for bus-powered functions (see Figure 29). 20 Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067 TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067 www.ti.com ................................................................................................................................................... SLVS490G – DECEMBER 2003 – REVISED JULY 2008 TUSB2040 Hub Controller Upstream Port SN75240 BUSPWR A C B D GANGED D+ D− DP0 DP1 DM0 DM1 Tie to TPS2041 EN Input D+ A C B D GND OC 5V IN DM2 5-V Power Supply EN GND 5V 33 µF† DM3 A C B D 1 µF TPS76333 4.7 µF SN75240 D+ D− Ferrite Beads GND DP4 IN 3.3 V 4.7 µF VCC DM4 5V TPS2062 GND PWRON1 GND OVRCUR1 48-MHz Crystal XTAL1 33 µF† EN1 OUT1 OC1 OUT2 PWRON2 EN2 OVRCUR2 OC2 D+ IN 0.1 µF Tuning Circuit D− DP3 OUT 0.1 µF Ferrite Beads SN75240 DP2 TPS2041B Downstream Ports D− Ferrite Beads GND XTAL2 5V OCSOFF 33 µF† GND D+ Ferrite Beads D− GND 5V † 33 µF† USB rev 1.1 requires 120 µF per hub. Figure 29. Hybrid Self / Bus-Powered Hub Implementation GENERIC HOT-PLUG APPLICATIONS In many applications it may be necessary to remove modules or pc boards while the main unit is still operating. These are considered hot-plug applications. Such implementations require the control of current surges seen by the main power supply and the card being inserted. The most effective way to control these surges is to limit and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply normally turns on. Due to the controlled rise times and fall times of the TPS206x, these devices can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of the TPS206x also ensures that the switch is off after the card has been removed, and that the switch is off during the next insertion. The UVLO feature insures a soft start with a controlled rise time for every insertion of the card or module. Copyright © 2003–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067 21 TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067 SLVS490G – DECEMBER 2003 – REVISED JULY 2008 ................................................................................................................................................... www.ti.com PC Board TPS2062 OC1 GND Power Supply 2.7 V to 5.5 V 1000 µF Optimum 0.1 µF IN EN1 EN2 Block of Circuitry OUT1 OUT2 OC2 Block of Circuitry Overcurrent Response Figure 30. Typical Hot-Plug Implementation By placing the TPS206x between the VCC input and the rest of the circuitry, the input power reaches these devices first after insertion. The typical rise time of the switch is approximately 1 ms, providing a slow voltage ramp at the output of the device. This implementation controls system surge currents and provides a hot-plugging mechanism for any device. DETAILED DESCRIPTION Power Switch The power switch is an N-channel MOSFET with a low on-state resistance. Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when disabled. The power switch supplies a minimum current of 1 A. Charge Pump An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires little supply current. Driver The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall times of the output voltage. Enable (ENx or ENx) The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce the supply current. The supply current is reduced to less than 1 µA when a logic high is present on ENx, or when a logic low is present on ENx. A logic zero input on ENx, or a logic high input on ENx restores bias to the drive and control circuits and turns the switch on. The enable input is compatible with both TTL and CMOS logic levels. Overcurrent (OCx) The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature condition is encountered. The output remains asserted until the overcurrent or overtemperature condition is removed. A 10-ms deglitch circuit prevents the OCx signal from oscillation or false triggering. If an overtemperature shutdown occurs, the OCx is asserted instantaneously. 22 Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067 TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067 www.ti.com ................................................................................................................................................... SLVS490G – DECEMBER 2003 – REVISED JULY 2008 Current Sense A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its saturation region, which switches the output into a constant-current mode and holds the current constant while varying the voltage on the load. Thermal Sense The TPS206x implements a thermal sensing to monitor the operating temperature of the power distribution switch. In an overcurrent or short-circuit condition the junction temperature rises. When the die temperature rises to approximately 140°C due to overcurrent conditions, the internal thermal sense circuitry turns off the switch, thus preventing the device from damage. Hysteresis is built into the thermal sense, and after the device has cooled approximately 10 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is removed. The open-drain false reporting output (OCx) is asserted (active low) when an overtemperature shutdown or overcurrent occurs. Undervoltage Lockout A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control signal turns off the power switch. Copyright © 2003–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067 23 PACKAGE OPTION ADDENDUM www.ti.com 15-Jul-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS2061D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2061DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2061DGN ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2061DGNG4 ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2061DGNR ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2061DGNRG4 ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2061DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2061DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2062D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2062DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2062DGN ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2062DGNG4 ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2062DGNR ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2062DGNRG4 ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2062DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2062DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2063D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2063DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2063DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2063DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2065D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2065DG4 ACTIVE SOIC D 8 75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 15-Jul-2008 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS2065DGN ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2065DGNG4 ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2065DGNR ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2065DGNRG4 ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2065DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2065DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2066D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2066DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2066DGN ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2066DGNG4 ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2066DGNR ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2066DGNRG4 ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2066DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2066DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) no Sb/Br) TPS2066ID PREVIEW SOIC D 8 75 TBD Call TI Call TI TPS2066IDR PREVIEW SOIC D 8 2500 TBD Call TI Call TI TPS2067D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2067DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2067DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2067DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 15-Jul-2008 PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS2061DGNR Package Package Pins Type Drawing MSOPPower PAD SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 TPS2061DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS2062DGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 TPS2062DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS2063DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TPS2065DGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 TPS2065DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS2065DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS2066DGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 TPS2066DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS2067DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TPS2067DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2061DGNR MSOP-PowerPAD DGN 8 2500 370.0 355.0 55.0 TPS2061DR SOIC D 8 2500 340.5 338.1 20.6 TPS2062DGNR MSOP-PowerPAD DGN 8 2500 370.0 355.0 55.0 TPS2062DR SOIC D 8 2500 340.5 338.1 20.6 TPS2063DR SOIC D 16 2500 346.0 346.0 33.0 TPS2065DGNR MSOP-PowerPAD DGN 8 2500 370.0 355.0 55.0 TPS2065DR SOIC D 8 2500 340.5 338.1 20.6 TPS2065DR SOIC D 8 2500 346.0 346.0 29.0 TPS2066DGNR MSOP-PowerPAD DGN 8 2500 370.0 355.0 55.0 TPS2066DR SOIC D 8 2500 340.5 338.1 20.6 TPS2067DR SOIC D 16 2500 333.2 345.9 28.6 TPS2067DR SOIC D 16 2500 346.0 346.0 33.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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