TI TPS659102A1RSLR

TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Integrated Power Management Unit Top Specification
Check for
Samples: TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103, TPS659104, TPS659105, TPS659106,
TPS659107, TPS659108, TPS659109
FEATURES
1
The purpose of the TPS65910 device is to
provide the following resources:
•
•
•
•
•
•
•
•
•
•
•
•
•
Embedded power controller
Two efficient step-down dc-dc converters for
processor cores
One efficient step-down dc-dc converter for I/O
power
One efficient step-up 5-V dc-dc converter
SmartReflex™ compliant dynamic voltage
management for processor cores
8 LDO voltage regulators and one RTC LDO
(internal purpose)
One high-speed I2C interface for generalpurpose control commands (CTL-I2C)
One high-speed I2C interface for SmartReflex
Class 3 control and command (SR-I2C)
Two enable signals multiplexed with SR-I2C,
configurable to control any supply state and
processor cores supply voltage
Thermal shutdown protection and hot-die
detection
A real-time clock (RTC) resource with:
– Oscillator for 32.768-kHz crystal or 32-kHz
built-in RC oscillator
– Date, time and calendar
– Alarm capability
One configurable GPIO
DC-DC switching synchronization through
internal or external 3-MHz clock
APPLICATIONS
•
•
Portable and handheld systems
OMAP3 power management
DESCRIPTION
The TPS65910 is an integrated power-management
IC available in 48-QFN package and dedicated to
applications powered by one Li-Ion or Li-Ion polymer
battery cell or 3-series Ni-MH cells, or by a 5-V input;
it requires multiple power rails. The device provides
three step-down converters, one step-up converter,
and eight LDOs and is designed to support the
specific power requirements of OMAP-based
applications.
Two of the step-down converters provide power for
dual processor cores and are controllable by a
dedicated class-3 SmartReflex interface for optimum
power savings. The third converter provides power for
the I/Os and memory in the system.
The device includes eight general-purpose LDOs
providing a wide range of voltage and current
capabilities; they are fully controllable by the I2C
interface. The use of the LDOs is flexible; they are
intended to be used as follows: Two LDOs are
designated to power the PLL and video DAC supply
rails on the OMAP based processors, four generalpurpose auxiliary LDOs are available to provide
power to other devices in the system, and two LDOs
are provided to power DDR memory supplies in
applications requiring these memories.
In addition to the power resources, the device
contains an embedded power controller (EPC) to
manage the power sequencing requirements of the
OMAP systems and an (RTC).
Figure 1 shows the top-level diagram of the device.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2012, Texas Instruments Incorporated
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
VBACKUP
SWCS046N – MARCH 2010 – REVISED APRIL 2012
CBB
VBAT
VCC7
VBAT
Ci(VCC7)
VRTC
VRTC (LDO)
and POR
Co(VRTC)
VAUX33 VCC7
Backup
management
Ci(VDD3)
SW3
GNDA
GNDA
GND3
VDD3
(SMPS)
OSC32KIN
OSC
32-kHz
OSC32KOUT
VFB3
Real-time
clock
Co(VDD3)
AGND
VCC7
REFGND
VDDIO
SDA_SDI
SCL_SCK
VBAT
VCC1
CLK32KOUT
Ci(VCC1)
SW1
GND1
2
I C
VDD1
(SMPS)
Bus
control
GPIO_CKSYNC
Co(VDD1)
VFB1
AGND
VCC4
VBAT
VCC2
Ci(VCC2)
SW2
SDASR_EN2
GND2
2
I C
SCLSR_EN1
VDD2
(SMPS)
Co(VDD2)
VFB2
AGND
VCC7
INT1
SLEEP
PWRON
BOOT1
BOOT0
PWRHOLD
NRESPWRON
Power
control
statemachine
Co(VREF)
TESTV
REFGND
VIO
(SMPS)
VCC 7
Analog
references
and comparators
VDAC
Co(VDAC)
VBAT
VDIG1
(LDO)
VDDIO
VDIG1
Co(VDIG1)
DGND
AGND2
VCC7
VCC5
Co(VIO)
VFBIO
VCC7
Test interface
VDAC
(LDO)
Ci(VCCIO)
SWIO
GNDIO
AGND2
VREF
VBAT
VCCIO
VCC6
AGND
Ci(VCC5)
VDIG2
VPLL
VDIG2
(LDO)
VPLL
(LDO)
Co(VPLL)
Co(VDIG2)
AGND2
AGND
VAUX1
VAUX33
(LDO)
VAUX1
(LDO)
VAUX33
Co(VAUX33)
Co(VAUX1)
VBAT
VBAT
AGND2
VCC4
AGND2
VCC3
Ci(VCC4)
VAUX2
Co(VAUX2)
DGND AGND AGND2 GND3
VAUX2
(LDO)
Ci(VCC4)
VMMC
VMMC
(LDO)
Co(VMMC)
AGND2
GNDP
AGND2
GNDP: Power pad ground
SWCS046-001
Figure 1. 48-QFN Top-Level Diagram
2
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Table 1. SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERS
(1)
Compatible Processor (1)
Part Number (1)
TI processor - AM335x with DDR2
TPS65910AA1RSL
TI processor - AM335x with DDR3
TPS65910A3A1RSL
TI processors - AM1705/07, AM1806/08, AM3505/17, AM3703/15, DM3730/25,
OMAP-L137/38, OMAP3503/15/25/30, TMS320C6742/6/8
TPS65910A1RSL
Samsung - S5PV210, S5PC110
TPS659101A1RSL
Rockchip - RK29xx
TPS659102A1RSL
Samsung - S5PC100
TPS659103A1RSL
Samsung - S5P6440
TPS659104A1RSL
TI processors - DM643x, DM644x
TPS659105A1RSL
Reserved
TPS659106A1RSL
Freescale - i.MX27, Freescale - i.MX35
TPS659107A1RSL
Freescale - i.MX508
TPS659108A1RSL
Freescale - i.MX51
TPS659109A1RSL
The RSL package is available in tape and reel. See for details for corresponding part numbers, quantities and ordering information.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
Stresses beyond those listed under below may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated below are not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
The absolute maximum ratings for the TPS65910 device are listed below:
MIN
MAX
UNIT
Voltage range on pins/balls VCC1, VCC2, VCCIO, VCC3, VCC4,
VCC5, VCC6, VCC7
PARAMETER
–0.3
7
V
Voltage range on pins/balls VDDIO
–0.3
3.6
V
Voltage range on pins/balls OSC32KIN, OSC32KOUT, BOOT1,
BOOT0
–0.3
VRTCMAX + 0.3
V
Voltage range on pins/balls SDA_SDI, SCL_SCK, SDASR_EN2,
SCLSR_EN1, SLEEP, INT1, CLK32KOUT, NRESPWRON
–0.3
VDDIOMAX + 0.3
V
Voltage range on pins/balls PWRON
–0.3
7
V
Voltage range on pins/balls PWRHOLD (1) GPIO_CKSYNC (2)
–0.3
7
V
Functional junction temperature range
–45
150
°C
Peak output current on all other terminals than power resources
–5
5
mA
(1)
(2)
I/O supplied from VDDIO but which can be driven from to a VBAT voltage level
I/O supplied from VRTC but can be driven to a VBAT voltage level
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
Package
Rθja (°C/W)
TA < 25°C Power
Rating (W)
DERATING
FACTOR ABOVE
25 °C
(mW/°C)
TA = 70°C Power
(W)
TA = 85°C Power
Rating (W)
RSL 48-QFN
37
2.6
37
1.48
1
The thermal resistance RθJP junction-to-power PAD of the RSL package is 1.1°C/W
The value of thermal resistance RθJA junction-to-ambient was measured on a high K.
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
3
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
Lists of the recommended operating maximum ratings for the TPS65910 device are given below.
Note1: VCC7 should be connected to the highest supply that is connected to the device VCCx pin. The exception is that
VCC2 and VCC4 can be higher than VCC7.
Note2: VCC2 and VCC4 must be connected together (to the same voltage).
Note3: If VDD3 boost is used, VAUX33 must be set to 2.8 V or higher and enabled before VDD3.
PARAMETER
TEST CONDITIONS
VCC: Input voltage range on pins/balls VCC1, VCC2, VCCIO, VCC3, VCC4, VCC5,
VCC7
MIN
NOM
MAX
UNIT
2.7
3.6
5.5
V
VCCP: Input voltage range on pins/balls VCC6
1.7
3.6
5.5
V
Input voltage range on pins/balls VDDIO
1.65
1.8/3.3
3.45
V
0
3.6
5.5
V
Input voltage range on pins/balls SDA_SDI, SCL_SCK, SDASR_EN2, SCLSR_EN1,
SLEEP
1.65
VDDIO
3.45
V
Input voltage range on pins/balls PWRHOLD, GPIO_CKSYNC
1.65
VDDIO
5.5
V
Input voltage range on balls BOOT1, BOOT0, OSC32KIN
1.65
VRTC
1.95
V
Operating free-air temperature, TA
–40
27
85
°C
Junction temperature TJ
–40
27
125
°C
Storage temperature range
–65
27
150
°C
Input voltage range on pins/balls PWRON
Lead temperature (soldering, 10 s)
260
°C
100
nF
Power References
VREF filtering capacitor CO(VREF)
Connected from VREF to REFGND
Input capacitor CI(VCC1)
X5R or X7R dielectric
Filter capacitor CO(VDD1)
X5R or X7R dielectric
CO filter capacitor ESR
f = 3 MHz
VDD1 SMPS
10
4
Inductor LO(VDD1)
µF
10
12
µF
10
300
mΩ
125
mΩ
2.2
LO inductor dc resistor DCRL
µH
VDD2 SMPS
Input capacitor CI(VCC2)
X5R or X7R dielectric
Filter capacitor CO(VDD2)
X5R or X7R dielectric
CO filter capacitor ESR
f = 3 MHz
10
4
Inductor LO(VDD2)
µF
10
12
µF
10
300
mΩ
125
mΩ
2.2
LO inductor dc resistor DCRL
µH
VIO SMPS
Input capacitor CI(VIO)
X5R or X7R dielectric
Filter capacitor CO(VIO)
X5R or X7R dielectric
CO filter capacitor ESR
f = 3 MHz
10
4
Inductor LO(VIO)
µF
10
12
µF
10
300
mΩ
2.2
LO inductor dc resistor DCRL
µH
125
mΩ
VDIG1 LDO
Input capacitor CI(VCC6)
X5R or X7R dielectric
4.7
Filtering capacitor CO(VDIG1)
0.8
CO filtering capacitor ESR
2.2
0
µF
2.64
µF
500
mΩ
VDIG2 LDO
Filtering capacitor CO(VDIG2)
0.8
CO filtering capacitor ESR
2.2
0
2.64
µF
500
mΩ
VPLL LDO
Input capacitor CI(VCC5)
X5R or X7R dielectric
Filtering capacitor CO(VPLL)
4
Submit Documentation Feedback
4.7
0.8
2.2
µF
2.64
µF
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
Lists of the recommended operating maximum ratings for the TPS65910 device are given below.
Note1: VCC7 should be connected to the highest supply that is connected to the device VCCx pin. The exception is that
VCC2 and VCC4 can be higher than VCC7.
Note2: VCC2 and VCC4 must be connected together (to the same voltage).
Note3: If VDD3 boost is used, VAUX33 must be set to 2.8 V or higher and enabled before VDD3.
PARAMETER
TEST CONDITIONS
CO filtering capacitor ESR
MIN
NOM
0
MAX
UNIT
500
mΩ
VDAC LDO
Filtering capacitor CO(VDAC)
0.8
CO filtering capacitor ESR
0
2.2
2.64
µF
500
mΩ
VMMC LDO
Input capacitor CI(VCC4)
X5R or X7R dielectric
4.7
Filtering capacitor CO(VMMC)
0.8
CO filtering capacitor ESR
2.2
0
µF
2.64
µF
500
mΩ
VAUX33 LDO
Filtering capacitor CO(VAUX33)
0.8
CO filtering capacitor ESR
2.2
0
2.64
µF
500
mΩ
VAUX1 LDO
Input capacitor CI(VCC3)
X5R or X7R dielectric
4.7
Filtering capacitor CO(VAUX1)
0.8
CO filtering capacitor ESR
2.2
0
µF
2.64
µF
500
mΩ
VAUX2 LDO
Filtering capacitor CO(VAUX2)
0.8
CO filtering capacitor ESR
2.2
0
2.64
µF
500
mΩ
VRTC LDO
Input capacitor CI(VCC7)
X5R or X7R dielectric
4.7
Filtering capacitor CO(VRTC)
0.8
CO filtering capacitor ESR
2.2
0
µF
2.64
µF
500
mΩ
VDD3 SMPS
Input capacitor CI(VDD3)
X5R or X7R dielectric
Filter capacitor CO(VDD3)
X5R or X7R dielectric
CO filter capacitor ESR
f = 1 MHz
4.7
Inductor LO(VDD3)
µF
4
10
12
µF
10
300
mΩ
2.8
4.7
6.6
µH
50
500
mΩ
10
LO inductor DC resistor DCRL
Backup Battery
Backup battery capacitor CBB
Series resistors
Battery or superCap supplying VBACKUP
5
2000
mF
Capacitor supplying VBACKUP
1
40
µF
5 to 15 mF
10
1500
100 to 2000 mF
5
15
Ω
I2C Interfaces
SDA_SDI, SCL_SCK, SDASR_EN2,
SCLSR_EN1 external pull-up resistor
Connected to VDDIO
1.2
kΩ
32.768
kHz
Crystal Oscillator (connected from OSC32KIN to OSC32KOUT)
Crystal frequency
@ specified load cap value
Crystal tolerance
@ 27°C
–20
Frequency Temperature coefficient.
Oscillator contribution (not including crystal
variation)
–0.5
Secondary temperature coefficient
Voltage coefficient
Copyright © 2010–2012, Texas Instruments Incorporated
–0.04
–2
0
–0.035
20
ppm
0.5
ppm/°C
–0.03
ppm/°C2
2
ppm/V
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
5
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
Lists of the recommended operating maximum ratings for the TPS65910 device are given below.
Note1: VCC7 should be connected to the highest supply that is connected to the device VCCx pin. The exception is that
VCC2 and VCC4 can be higher than VCC7.
Note2: VCC2 and VCC4 must be connected together (to the same voltage).
Note3: If VDD3 boost is used, VAUX33 must be set to 2.8 V or higher and enabled before VDD3.
PARAMETER
TEST CONDITIONS
MIN
Max crystal series resistor
@ Fundamental frequency
Crystal load capacitor
According to crystal data sheet
Load crystal oscillator Coscin
,Coscout
parallel mode Including parasitic PCB capacitor
Quality factor
NOM
MAX
UNIT
90
kΩ
6
12.5
pF
12
25
pF
8000
80000
ESD SPECIFICATIONS
over operating free-air temperature range (unless otherwise noted)
STANDARD REFERENCE
PERFORMANCE
TI STANDARD
REQUIREMENTS
Human body model (HBM)
EIA/JESD22-A114D
2000 V
2000 V
Charge device model (CDM)
EIA/JESD22-C101C
500 V
500 V
ESD METHOD
6
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
I/O PULLUP AND PULLDOWN CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
–45%
8
+45%
kΩ
µA
SDA_SDI, SCL_SCK, SDASR_EN2,
SCLSR_EN1 Programmable pullup (DFT, default
inactive)
Grounded, VDDIO = 1.8 V
SLEEP programmable pulldown (default active)
@ 1.8 V, VRTC = 1.8 V
2
4.5
10
@ 1.8 V, VRTC = 1.8 V, VCC7 = 2.7
V
2
4.5
10
@ 5.5 V, VRTC = 1.8 V, VCC7 = 5.5
V
7
14
30
BOOT0, BOOT1 programmable pulldown (default
@ 1.8 V, VRTC = 1.8 V
active)
2
4.5
10
µA
NRESPWRON pulldown
@ 1.8 V, VCC7 = 5.5 V, OFF state
2
4.5
10
µA
32KCLKOUT pulldown (disabled in Active-sleep
state)
@ 1.8 V, VRTC = 1.8 V, OFF state
2
4.5
10
µA
PWRON programmable pullup (default active)
Grounded, VCC7 = 5.5 V
–40
–31
–15
µA
GPIO_CKSYNC programmable pullup (default
active)
Grounded, VRTC = 1.8 V
–27
–18
–9
µA
PWRHOLD programmable pulldown (default
active)
(1)
µA
The internal pullups on the CTL-I2C and SR-I2C balls are used for test purposes or when the SR-I2C interface is not used. Discrete
pullups to the VIO supply must be mounted on the board in order to use the I2C interfaces. The internal I2C pullups must not be used for
functional applications
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
7
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
DIGITAL I/O VOLTAGE ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
0.3 x VCC7
V
Related I/O: PWRON
Low-level input voltage VIL
High-level input voltage VIH
0.7 x VCC7
V
Related I/Os: PWRHOLD, GPIO_CKSYNC
Low-level input voltage VIL
High-level input voltage VIH
VDDIO/V
CC7
1.3
0.45
V
VCC7
V
0.35 x VRTC
V
Related I/Os: BOOT0, BOOT1, OSC32KIN
Low-level input voltage VIL
High-level input voltage VIH
0.65 x VRTC
V
Related I/Os: SLEEP
Low-level input voltage VIL
0.35 x VDDIO
High-level input voltage VIH
0.65 x VDDIO
V
V
Related I/Os: NRESPWRON, INT1, 32KCLKOUT
Low-level output voltage VOL
High-level output voltage VOH
IOL = 100 µA
0.2
V
IOL = 2 mA
0.45
V
IOH = 100 µA
VDDIO – 0.2
V
IOH = 2 mA
VDDIO – 0.45
V
Related Open-Drain I/Os: GPIO0
Low-level output voltage VOL
IOL = 100 µA
0.2
V
IOL = 2 mA
0.45
V
0.3 x VDDIO
V
2
I C-Specific Related I/Os: SCL, SDA, SCLSR_EN1, SDASR_EN2
Low-level input voltage VIL
–0.5
High-level input voltage VIH
0.7 x VDDIO
Hysteresis
0.1 x VDDIO
V
V
Low-level output voltage VOL @ 3mA (sink current), VDDIO = 1.8 V
0.2 × VDDIO
V
Low-level output voltage VOL @ 3mA (sink current), VDDIO = 3.3 V
0.4 x VDDIO
V
8
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
I2C INTERFACE AND CONTROL SIGNALS
over operating free-air temperature range (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
INT1 rise and fall times, CL = 5 to 35 pF
5
10
ns
NRESPWRON rise and fall times, CL = 5 to 35 pF
5
10
ns
10
80
ns
3.4
Mbps
SLAVE HIGH–SPEED MODE
SCL/SCLSR_EN1 and SDA/SDASR_EN2 rise and fall
time, CL = 10 to 100 pF
Data rate
I3
tsu(SDA-SCLH)
Setup time, SDA valid to SCL high
10
I4
th(SCLL-SDA)
Hold time, SDA valid from SCL low
I7
tsu(SCLH-SDAL)
Setup time, SCL high to SDA low
160
ns
I8
th(SDAL-SCLL)
Hold time, SCL low from SDA low
160
ns
I9
tsu(SDAH-SCLH)
Setup time, SDA high to SCL high
160
ns
0
ns
70
ns
SLAVE FAST MODE
SCL/SCLSR_EN1 and SDA/SDASR_EN2 rise and fall
time, CL = 10 to 400 pF
20 +
0.1 × CL
Data rate
250
ns
400
Kbps
0.9
µs
I3
tsu(SDA-SCLH)
Setup time, SDA valid to SCL high
100
I4
th(SCLL-SDA)
Hold time, SDA valid from SCL low
0
ns
I7
tsu(SCLH-SDAL)
Setup time, SCL high to SDA low
0.6
µs
I8
th(SDAL-SCLL)
Hold time, SCL low from SDA low
0.6
µs
I9
tsu(SDAH-SCLH)
Setup time, SDA high to SCL high
0.6
µs
SLAVE STANDARD MODE
SCL/SCLSR_EN1 and SDA/SDASR_EN2 rise and fall
time, CL = 10 to 400 pF
250
ns
Data rate
100
Kbps
I3
tsu(SDA-SCLH)
Setup time, SDA valid to SCL high
250
ns
I4
th(SCLL-SDA)
Hold time, SDA valid from SCL low
0
µs
I7
tsu(SCLH-SDAL)
Setup time, SCL high to SDA low
4.7
µs
I8
th(SDAL-SCLL)
Hold time, SCL low from SDA low
4
µs
I9
tsu(SDAH-SCLH)
Setup time, SDA high to SCL high
4
µs
SWITCHING CHARACTERISTICS
SLAVE HIGH–SPEED MODE
I1
tw(SCLL)
Pulse duration, SCL low
160
ns
I2
tw(SCLH)
Pulse duration, SCL high
60
ns
SLAVE FAST MODE
I1
tw(SCLL)
Pulse duration, SCL low
1.3
µs
I2
tw(SCLH)
Pulse duration, SCL high
0.6
µs
SLAVE STANDARD MODE
I1
tw(SCLL)
Pulse duration, SCL low
4.7
µs
I2
tw(SCLH)
Pulse duration, SCL high
4
µs
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
9
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
POWER CONSUMPTION
over operating free-air temperature range (unless otherwise noted)
All current consumption measurements are relative to the FULL chip, all VCC inputs set to VBAT voltage.
PARAMETER
Device BACKUP state
Device OFF state
TYP
MAX
VBAT = 2.4 V, VBACKUP = 0 V,
TEST CONDITIONS
MIN
11
16
VBAT = 0 V, VBACKUP = 3.2 V
6
9
UNIT
µA
VBAT = 3.6 V, CK32K clock running
BOOT[1:0] = 00: 32-kHz RC oscillator
16.5
23
BOOT[1:0] = 01: 32-kHz quartz or bypass oscillator, BOOT0P
=0
15
20
BOOT[1:0] = 01, Backup Battery Charger on, VBACKUP = 3.2
V
32
42
VBAT = 5 V, CK32K clock running:
20
28
µA
BOOT[1:0] = 00: RC oscillator
Device SLEEP state
Device ACTIVE state
VBAT = 3.6 V, CK32K clock running, PWRHOLDP = 0
BOOT[1:0] = 00, 3 DC-DCs on, 5 LDOs and VRTC on, no load
295
BOOT[1:0] = 01, 3 DC-DCs on, 3 LDOs and VRTC on, no load,
BOOT0P = 0
279
µA
VBAT = 3.6 V, CK32K clock running, PWRHOLDP = 0
BOOT[1:0] = 00, 3 DC-DCs on, 5 LDOs and VRTC on, no load
1
BOOT[1:0] = 01, 3 DC-DCs on, 3 LDOs and VRTC on, no load,
BOOT0P = 0
0.9
BOOT[1:0] = 00, 3 DC-DCs on PWM mode (VDD1_PSKIP =
VDD2_PSKIP = VIO_PSKIP = 0), 5 LDOs and VRTC on, no
load
21
mA
POWER REFERENCES AND THRESHOLDS
over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output reference voltage (VREF
terminal)
PARAMETER
Device in active or low-power mode
–1%
0.85
+1%
V
Main battery charged
threshold VMBCH (programmable)
Measured on VCC7 terminal
Triggering monitored through NRESPRWON
VMBCH_VSEL = 11, BOOT[1:0] = 11 or 00
3
VMBCH_VSEL = 10
2.9
VMBCH_VSEL = 01
2.8
VMBCH_VSEL = 00
V
bypassed
Main battery discharged
Measured on VCC7 terminal (MTL prg)
threshold VMBDCH (programmable) Triggering monitored through INT1
VMBCH –
100 mV
V
Main battery low threshold VMBLO
(MB comparator)
Measured on VCC7 terminal (Triggering
monitored on terminal NRESPWRON)
2.5
2.6
2.7
Main battery high threshold VMBHI
VBACKUP = 0 V, measured on terminal VCC7
(MB comparator)
2.6
2.75
3
VBACKUP = 3.2 V, measured on terminal VCC7
2.5
2.55
3
Measured on terminal VCC7
(Triggering monitored on terminal VRTC)
1.9
2.1
2.2
Main battery not present threshold
VBNPR
Ground current (analog references
+ comparators + backup battery
switch)
10
V
V
V
VCC = 3.6 V
Device in OFF state
8
Device in ACTIVE or SLEEP state
20
Submit Documentation Feedback
µA
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
THERMAL MONITORING AND SHUTDOWN
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Hot-die temperature rising threshold
MIN
TYP
THERM_HDSEL[1:0] = 00
121
113
125
THERM_HDSEL[1:0] = 11
°C
136
130
Hot-die temperature hysteresis
10
Thermal shutdown temperature rising
threshold
136
148
Thermal shutdown temperature hysteresis
Device in ACTIVE state, Temp = 27°C,
VCC7 = 3.6 V
Ground current
UNIT
117
THERM_HDSEL[1:0] = 01
THERM_HDSEL[1:0] = 10
MAX
°C
160
°C
10
°C
6
µA
32-kHz RTC CLOCK
over operating free-air temperature range (unless otherwise noted)
PARAMETER
CLK32KOUT rise and fall time
TEST CONDITIONS
MIN
TYP
CL = 35 pF
MAX
UNIT
10
ns
Bypass Clock (OSC32KIN: input, OSC32KOUT floating)
Input bypass clock frequency
OSCKIN input
Input bypass clock duty cycle
OSCKIN input
Input bypass clock rise and fall time
10% – 90%, OSC32KIN input,
CLK32KOUT duty cycle
Logic output signal
Bypass clock setup time
32KCLKOUT output
Ground current
Bypass mode
32
40%
kHz
60%
10
40%
20
ns
60%
1
ms
1.5
µA
Crystal oscillator (connected from OSC32KIN to OSC32KOUT)
Output frequency
CK32KOUT output
Oscillator startup time
On power on
32.768
kHz
2
Ground current
1.5
s
µA
RC oscillator (OSC32KIN: grounded, OSC32KOUT floating)
Output frequency
CK32KOUT output
Output frequency accuracy
@ 25°C
Cycle jitter (RMS)
Oscillator contribution
Output duty cycle
32
–15%
0%
+40%
+50%
kHz
+15%
+10%
Settling time
+60%
150
Ground current
Active @ fundamental frequency
Copyright © 2010–2012, Texas Instruments Incorporated
4
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
µs
µA
11
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
BACKUP BATTERY CHARGER
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Backup battery charging current VBACKUP = 0 to 2.4 V, BBCHEN = 1
350
500
700
µA
End-of-charge backup battery
voltage (1)
VCC7 = 3.6 V, BBSEL = 10
–3%
3.15
+3%
VCC7 = 3.6 V, BBSEL = 00
–3%
3
+3%
VCC7 = 3.6 V, BBSEL = 01
–3%
2.52
+3%
VCC7 = 3.6 V, BBSEL = 11
VBAT –
0.3 V
Ground current
(1)
On mode
V
VBAT
10
µA
Note:
(a) BBSEL = 10, 00, or 01 intended to charge battery or superCap
(b) BBSEL = 11 intended to charge capacitor
VRTC LDO
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Input voltage VIN
DC output voltage VOUT
Rated output current IOUTmax
DC load regulation
DC line regulation
Transient load regulation
TEST CONDITIONS
MIN
TYP
MAX
On mode
2.5
5.5
Back-up mode
1.9
3
On mode, 3.0 V < VIN < 5.5 V
1.78
1.83
1.88
Back-up mode, 2.3 V ≤ VIN ≤ 2.6 V
1.72
1.78
1.84
On mode
20
Back-up mode
0.1
UNIT
V
V
mA
On mode, IOUT = IOUTmax to 0
50
Back-up mode, IOUT = IOUTmax to 0
50
On mode, VIN = 3.0 V to VINmax @ IOUT = IOUTmax
2.5
Back-up mode, VIN = 2.3 V to 5.5 V @ IOUT =
IOUTmax
25
On mode, VIN = VINmin + 0.2 V to VINmax
mV
mV
50
(1)
mV
25
(1)
mV
IOUT = IOUTmax/2 to IOUTmax in 5 µs
and IOUT = IOUTmax to IOUTmax/2 in 5 µs
Transient line regulation
On mode, VIN = VINmin + 0.5 V to VINmin in 30 µs
And VIN = VINmin to VINmin + 0.5 V in 30 µs, IOUT =
IOUTmax/2
Turn-on time
IOUT = 0, VIN rising from 0 up to 3.6 V, @ VOUT =
0.1 V up to VOUTmin
Ripple rejection
VIN = VINDC + 100 mVpp tone, VINDC+ = VINmin +
0.1 V to VINmax @ IOUT = IOUTmax/2
Ground current
(1)
12
2.2
f = 217 Hz
55
f = 50 kHz
35
Device in ACTIVE state
23
Device in BACKUP or OFF state
3
ms
dB
µA
These parameters are not tested. They are used for design specification only.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
VIO SMPS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Input voltage (VCCIO and VCC7) VIN
DC output voltage (VOUT)
TEST CONDITIONS
MIN
2.7
5.5
VOUT = 1.5 V or 1.8 V, IOUT > 800 mA
3.2
5.5
VOUT = 2.5 V, IOUT > 800 mA
4.0
5.5
VOUT = 3.3 V, IOUT > 800 mA
4.4
5.5
UNIT
V
PWM mode (VIO_PSKIP = 0) or pulse skip
mode IOUT to IMAX
VSEL=00
–3%
1.5
+3%
VSEL = 01, default BOOT[1:0] = 00 and 01
–3%
1.8
+3%
VSEL = 10
–3%
2.5
+3%
VSEL = 11
–3%
3.3
+3%
V
0
ILMAX[1:0] = 00, default
500
ILMAX[1:0] = 01
1000
mA
P-channel MOSFET
VIN = VINmin
300
On-resistance RDS(ON)_PMOS
VIN = 3.8 V
250
P-channel leakage current ILK_PMOS
VIN = VINMAX, SWIO = 0 V
N-channel MOSFET
VIN = VMIN
300
On-resistance RDS(ON)_NMOS
VIN = 3.8 V
250
N-channel leakage current ILK_NMOS
VIN = VINmax, SWIO = VINmax
PMOS current limit (high-side)
VIN = VINmin to VINmax, ILMAX[1:0] = 00
650
VIN = VINmin to VINmax, ILMAX[1:0] = 01
1200
VIN = VINmin to VINmax, ILMAX[1:0] = 10
1700
NMOS current limit (low-side)
MAX
IOUT ≤ 800 mA
Power down
Rated output current IOUTmax
TYP
mΩ
400
2
µA
mΩ
400
2
µA
mA
Source current load:
VIN = VINmin to VINmax, ILMAX[1:0] = 00
650
VIN = VINmin to VINmax, ILMAX[1:0] = 01
1200
VIN = VINmin to VINmax, ILMAX[1:0] = 10
1700
mA
Sink current load:
VIN = VINmin to VINmax, ILMAX[1:0] = 00
800
VIN = VINmin to VINmax, ILMAX[1:0] = 01
1200
VIN = VINmin to VINmax, ILMAX[1:0] = 10
1700
DC load regulation
On mode, IOUT = 0 to IOUTmax
20
mV
DC line regulation
On mode, VIN = VINmin to VINmax
20
mV
50
mV
VIN = 3.8 V, VOUT = 1.8 V
Transient load regulation
IOUT = 0 to 500 mA , Max slew = 100 mA/µs
IOUT = 700 to 1200 mA , Max slew = 100 mA/µs
t on, off to on
IOUT = 200 mA
350
Overshoot
SMPS turned on
3%
Power-save mode Ripple voltage
Pulse skipping mode, IOUT = 1 mA
µs
0.025 ×
VOUT
Switching frequency
VPP
3
Duty cycle
MHz
100
Minimum On Time TON(MIN)
%
35
ns
1
MΩ
P-channel MOSFET
VFBIO internal resistance
Discharge resistor for power-down
sequence RDIS
0.5
During device switch-off sequence
30
50
Ω
Note: No discharge resistor is applied if VIO is
turned off while the device is on.
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
13
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
VIO SMPS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Ground current (IQ)
TEST CONDITIONS
MIN
TYP
Off
MAX
UNIT
1
PWM mode, IOUT = 0 mA, VIN = 3.8 V,
VIO_PSKIP = 0
7500
Pulse skipping mode, no switching, 3-MHz clock
on
250
µA
Low-power (pulse skipping) mode, no switching
ST[1:0]=11
Conversion efficiency
63
PWM mode, DCRL < 50 mΩ, VOUT = 1.8 V, VIN
= 3.6 V:
IOUT = 10 mA
44%
IOUT = 100 mA
87%
IOUT = 400 mA
86%
IOUT = 800 mA
76%
IOUT = 1000 mA
72%
Pulse Skipping mode, DCRL < 50 mΩ, VOUT =
1.8 V, VIN = 3.6 V:
14
IOUT = 1 mA
71%
IOUT = 10 mA
80%
IOUT = 200 mA
87%
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
VDD1 SMPS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Input voltage (VCC1 and VCC7) VIN
TEST CONDITIONS
IOUT ≤ 1200 mA
VOUT = 0.6 V to 1.5 V, VGAIN_SEL = 00,
IOUT > 1200 mA
2.5 V ≤ VOUT ≤ 3.3 V, VGAIN_SEL = 10 or 11,
IOUT > 1200 mA
DC output voltage (VOUT)
MIN
TYP
MAX
2.7
5.5
VOUT + 2
V
5.5
4.5
5.5
UNIT
V
VGAIN_SEL = 00, IOUT = 0 to IOUTmax:
max programmable voltage, SEL[6:0] = 1001011
1.5
default voltage, BOOT[1:0] = 00
–3%
1.2
+3%
default voltage, BOOT[1:0] = 01
–3%
1.2
+3%
V
min programmable voltage, SEL[6:0] = 0000011
0.6
SEL[6:0] = 000000: power down
0
VGAIN_SEL = 10, SEL = 0101011 = 43, IOUT = 0
to IOUTmax
–3%
2.2
+3%
V
VGAIN_SEL = 11, SEL = 0101000 = 40, IOUT = 0
to IOUTmax
–3%
3.2
+3%
V
DC output voltage programmable
step (VOUTSTEP)
VGAIN_SEL = 00, 72 steps
Rated output current IOUTmax
ILMAX = 0, default
1000
ILMAX = 1
1500
12.5
mV
mA
P-channel MOSFET
VIN = VINmin
300
On-resistance RDS(ON)_PMOS
VIN = 3.8 V
250
P-channel leakage current
VIN = VINmax, SW1 = 0 V
mΩ
400
2
µA
ILK_PMOS
N-channel MOSFET
VIN = VMIN
300
On-resistance RDS(ON)_NMOS
VIN = 3.8 V
250
N-channel leakage current ILK_NMOS
VIN = VINmax, SW1 = VINmax
PMOS current limit (high-side)
VIN = VINmin to VINmax, ILMAX = 0
1150
VIN = VINmin to VINmax, ILMAX = 1
2000
NMOS current limit (low-side)
mΩ
400
2
µA
mA
Source current load:
VIN = VINmin to VINmax, ILMAX = 0
1150
VIN = VINmin to VINmax, ILMAX = 1
2000
mA
Sink current load:
VIN = VINmin to VINmax, ILMAX = 0
1200
VIN = VINmin to VINmax, ILMAX = 1
2000
DC load regulation
On mode, IOUT = 0 to IOUTmax
20
mV
DC line regulation
On mode, VIN = VINmin to VINmax
20
mV
Transient load regulation
VIN = 3.8 V, VOUT = 1.2 V
50
mV
IOUT = 0 to 500 mA , Max slew = 100 mA/µs
IOUT = 700 mA to 1.2A , Max slew = 100 mA/µs
t on, off to on
IOUT = 200 mA
Output voltage transition rate
From VOUT = 0.6 V to 1.5 V and VOUT = 1.5 V to
0.6 V IOUT = 500 mA
Overshoot
TSTEP[2:0] = 001
12.5
TSTEP[2:0] = 011 (default)
7.5
TSTEP[2:0] = 111
2.5
SMPS turned on
Power-save mode ripple voltage
350
Pulse skipping mode, IOUT = 1 mA
Switching frequency
Copyright © 2010–2012, Texas Instruments Incorporated
µs
mV/µs
3%
0.025 ×
VOUT
VPP
3
MHz
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
15
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
VDD1 SMPS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Duty cycle
MAX
100
Minimum on time tON(MIN)
UNIT
%
35
ns
1
MΩ
P-channel MOSFET
VFB1 internal resistance
0.5
Discharge resistor for power-down
sequence RDIS
Ground current (IQ)
30
Off
PWM mode, IOUT = 0 mA, VIN = 3.8 V,
VDD1_PSKIP = 0
Pulse skipping mode, no switching
50
Ω
1
7500
78
µA
Low-power (pulse skipping) mode, no switching
ST[1:0] = 11
Conversion efficiency
63
PWM mode, DCRL < 0.1 Ω, VOUT = 1.2 V, VIN =
3.6 V:
IOUT = 10 mA
35%
IOUT = 200 mA
82%
IOUT = 400 mA
81%
IOUT = 800 mA
74%
IOUT = 1500 mA
62%
Pulse skipping mode, DCRL < 0.1Ω, VOUT = 1.2
V, VIN = 3.6 V:
16
IOUT = 1 mA
59%
IOUT = 10 mA
70%
IOUT = 200 mA
82%
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
VDD2 SMPS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Input voltage (VCC2 and VCC4) VIN IOUT ≤ 1200 mA
VOUT = 0.6 V to 1.5 V, VGAIN_SEL = 00,
IOUT > 1200 mA
2.5 V ≤ VOUT ≤ 3.3 V, VGAIN_SEL = 10 or 11,
IOUT > 1200 mA
DC output voltage (VOUT)
MIN
TYP
2.7
5.5
VOUT + 2
V
5.5
4.5
5.5
UNIT
V
VGAIN_SEL = 00, IOUT = 0 to IOUTmax:
max programmable voltage, SEL[6:0] = 1001011
default, BOOT[1:0] = 01
1.5
–3%
min programmable voltage, SEL[6:0] = 0000011
1.2
+3%
0.6
SEL[6:0] = 000000: power down
V
0
VGAIN_SEL = 10, SEL = 0101011 = 43
–3%
2.2
+3%
VGAIN_SEL = 11, default, BOOT[1:0] = 00
–3%
3.3
+3%
DC output voltage programmable
step (VOUTSTEP)
VGAIN_SEL = 00, 72 steps
Rated output current IOUTmax
ILMAX = 0, default
1000
ILMAX = 1
1500
12.5
mV
mA
P-channel MOSFET
VIN = VINmin
300
On-resistance RDS(ON)_PMOS
VIN = 3.8 V
250
P-channel leakage current ILK_PMOS
VIN = VINmax, SW2 = 0 V
N-channel MOSFET
VIN = VMIN
300
On-resistance RDS(ON)_NMOS
VIN = 3.8 V
250
N-channel leakage current ILK_NMOS
VIN = VINmax, SW2 = VINmax
PMOS current limit (high-side)
VIN = VINmin to VINmax, ILMAX = 0
1150
VIN = VINmin to VINmax, ILMAX = 1
2200
Source current load:
1150
VIN = VINmin to VINmax, ILMAX = 0
2000
NMOS current limit (low-side)
MAX
mΩ
400
2
µA
mΩ
400
2
µA
mA
VIN = VINmin to VINmax, ILMAX = 1
mA
Sink current load:
VIN = VINmin to VINmax, ILMAX = 0
1200
VIN = VINmin to VINmax, ILMAX = 1
2000
DC load regulation
On mode, IOUT = 0 to IOUTmax
20
mV
DC line regulation
On mode, VIN = VINmin to VINmax @ IOUT = IOUTmax
20
mV
Transient load regulation
VIN = 3.8 V, VOUT = 1.2 V
50
mV
IOUT = 0 to 500 mA , Max slew = 100 mA/µs
IOUT = 700 mA to 1.2 A , Max slew = 100 mA/µs
t on, Off to on
IOUT = 200 mA
Output voltage transition rate
From VOUT = 0.6 V to 1.5 V and VOUT = 1.5 V to
0.6 V IOUT = 500 mA
Power-save mode ripple voltage
350
TSTEP[2:0] = 001
12.5
TSTEP[2:0] = 011 (default)
7.5
TSTEP[2:0] = 111
2.5
Pulse skipping mode, IOUT = 1 mA
Overshoot
µs
µs
0.025
VOUT
VPP
3%
Switching frequency
3
Duty cycle
MHz
100
Minimum On time
P-Channel MOSFET
Copyright © 2010–2012, Texas Instruments Incorporated
35
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
%
ns
17
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
VDD2 SMPS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VFB2 internal resistance
Discharge resistor for power-down
sequence RDIS
Ground current (IQ)
MIN
TYP
0.5
1
30
Off
PWM mode, IOUT = 0 mA, VIN = 3.8 V,
VDD2_PSKIP = 0
Pulse skipping mode, no switching
MAX
UNIT
MΩ
50
Ω
1
7500
78
µA
Low-power (pulse skipping) mode, no switching
ST[1:0] = 11
Conversion efficiency
63
PWM mode, DCRL < 50 mΩ, VOUT = 1.2 V, VIN =
3.6 V:
IOUT = 10 mA
35%
IOUT = 200 mA
82%
IOUT = 400 mA
81%
IOUT = 800 mA
74%
IOUT = 1200 mA
66%
IOUT = 1500 mA
62%
Pulse skipping mode mode, DCRL < 50 mΩ, VOUT
= 1.2 V, VIN = 3.6 V:
IOUT = 1 mA
59%
IOUT = 10 mA
70%
IOUT = 200 mA
82%
PWM mode, DCRL < 50 mΩ, VOUT = 3.3 V, VIN =
5 V:
IOUT = 10 mA
44%
IOUT = 200 mA
90%
IOUT = 400 mA
91%
IOUT = 800 mA
88%
IOUT = 1200 mA
84%
IOUT = 1500 mA
81%
Pulse skipping mode mode, DCRL < 50 mΩ, VOUT
= 3.3 V, VIN = 5 V:
18
IOUT = 1 mA
75%
IOUT = 10 mA
83%
IOUT = 200 mA
90%
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
VDD3 SMPS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Input voltage VIN
MIN
MAX
UNIT
5.5
V
5
5.25
3
DC output voltage (VOUT)
4.65
Rated output current IOUTmax
100
N-channel MOSFET
TYP
VIN = 3.6 V
V
mA
500
mΩ
On-resistance RDS(ON)_NMOS
N-channel MOSFET leakage
current ILK_NMOS
VIN = VINmax, SW3 = VINmax
N-channel MOSFET DC current
limit
VIN = VINmin to VINmax, sink current load
Turn-on inrush current
VIN = VINmin to VINmax
Ripple voltage
2
430
µA
550
mA
850
mA
20
mV
DC load regulation
On mode, IOUT = 0 to IOUTmax
100
mV
DC line regulation
On mode, VIN = VINmin to 5 V @ IOUT = IOUTmax
100
mV
Turn-on time
IOUT = 8 mA, VOUT = 0 to 4.4 V
Overshoot
200
µs
3%
Switching frequency
VFB3 internal resistance
Ground current (IQ)
MHz
MΩ
Off
IOUT = 0 mA to IOUTmax, VIN = 3.6 V
Conversion efficiency
1
088
1
360
µA
VIN = 3.6 V:
IOUT = 10 mA
81%
IOUT = 50 mA
85%
IOUT = 100 mA
85%
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
19
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
VDIG1 AND VDIG2 LDO
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Input voltage (VCC6) VIN
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOUT (VDIG1) = 1.2 V @ 300 mA / 1.5 V @ 100
mA and
VOUT (VDIG2) = 1.2 V / 1.1 V / 1.0 V @ 300 mA
1.7
5.5
VOUT (VDIG1) = 1.5 V and VOUT (VDIG2) = 1.8 V
@ 200mA
2.1
5.5
VOUT (VDIG1) = 1.8 V and VOUT (VDIG2) = 1.8 V
2.7
5.5
VOUT (VDIG1) = 2.7 V
3.2
5
V
VDIG1
DC output voltage VOUT
Rated output current IOUTmax
ON and Low-power mode, VIN = VINmin to VINmax
SEL = 11, IOUT = 0 to IOUTmax
–3%
2.7
+3%
SEL = 10 IOUT = 0 to IOUTmax
–3%
1.8
+3%
SEL = 01 IOUT = 0 to 100 mA/IOUTmax
–3%
1.5
+3%
SEL = 00, IOUT = 0 to IOUTmax, VIN = VINmin to 4 V,
default BOOT[1:0] = 00 or 01
–3%
1.2
+3%
On mode
300
Low-power mode
Dropout voltage VDO
mA
1
Load current limitation (short-circuit
On mode, VOUT = VOUTmin – 100 mV
protection)
350
V
600
mA
ON mode, VDO = VIN – VOUT
VOUTtyp = 2.7 V, VIN = 2.8 V, IOUT = IOUTmax, T =
25°C
150
VOUTtyp = 1.5 V, VIN = 1.7 V, IOUT = IOUTmax, T =
25°C
300
mV
DC load regulation
On mode, IOUT = IOUTmax to 0
25
mV
DC line regulation
On mode, VIN = VINmin to VINmax @ IOUT = IOUTmax
3
mV
Transient load regulation
ON mode, VIN = 3.8 V
10
mV
2
mV
100
µs
300
mA
IOUT = 20 mA to 180 mA in 5µs and
IOUT = 180 mA to 20 mA in 5 µs
Transient line regulation
On mode, VIN = 2.7 + 0.5 V to 2.7 in 30 µs,
And VIN = 2.7 to 2.7 + 0.5 V in 30 µs, IOUT =
IOUTmax/2
Turn-on time
IOUT = 0, @ VOUT = 0.1 V up to VOUTmin
Turn-on inrush current
Ripple rejection
VIN = VINDC + 100 mVpp tone, VINDC+= 3.8 V, IOUT =
IOUTmax/2
f = 217 Hz
70
f = 50 kHz
40
VDIG1 internal resistance
LDO off
400
Ground current
On mode, IOUT = 0, VCC6 = VBAT, VOUT = 2.7 V
54
On mode, IOUT = 0, VCC6 = 1.8 V, VOUT = 1.2 V
67
On mode, IOUT = IOUTmax, VCC6 = VBAT, VOUT =
2.7 V
1870
On mode, IOUT = IOUTmax, VCC6 = 1.8 V, VOUT =
1.2 V
1300
Low-power mode, VCC6 = VBAT, VOUT = 2.7 V
13
Low-power mode, VCC6 = 1.8 V, VOUT = 1.2 V
10
Off mode
dB
Ω
µA
1
VDIG2
DC output voltage VOUT
20
On and low-power mode, VIN = VINmin to VINmax
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
VDIG1 AND VDIG2 LDO (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Rated output current IOUTmax
TEST CONDITIONS
MIN
TYP
MAX
SEL = 11, IOUT = 0 to IOUTmax
–3%
1.8
+3%
SEL = 10 IOUT = 0 to IOUTmax, VIN = VINmin to 4 V
–3%
1.2
+3%
SEL = 01 IOUT = 0 to 100 mA/IOUTmax, VIN= VINmin
to 4 V
–3%
1.1
+3%
SEL = 00, IOUT = 0 to IOUTmax, VIN = VINmin to 4 V,
default BOOT[1:0] = 00 or 01
–3%
1
+3%
On mode
300
Low-power mode
Load current limitation (short-circuit
On mode, VOUT = VOUTmin – 100 mV
protection)
Dropout voltage VDO
UNIT
V
mA
1
350
600
mA
250
mV
ON mode, VDO = VIN – VOUT,
VOUTtyp = 1.8 V, VIN = 2.1 V, IOUT=IOUTmax, T =
25°C
DC load regulation
On mode, IOUT = IOUTmax to 0
DC line regulation
On mode, VIN = VINmin to VINmax @ IOUT = IOUTmax
Transient load regulation
ON mode, VIN = 3.8 V
25
mV
3
mV
10
mV
2
mV
IOUT = 20 mA to 180 mA in 5µs and
IOUT = 180 mA to 20 mA in 5 µs
Transient line regulation
On mode, VIN = 2.7 + 0.5 V to 2.7 in 30 µs,
And VIN = 2.7 to 2.7 + 0.5 V in 30 µs, IOUT =
IOUTmax/2
Turn-on time
IOUT = 0, @ VOUT = 0.1 V up to VOUTmin
Turn-on inrush current
Ripple rejection
100
µs
300
mA
VIN = VINDC + 100 mVpp tone, VINDC+= 3.8 V, IOUT =
IOUTmax/2
f = 217 Hz
70
f = 50 kHz
40
VDIG2 internal resistance
LDO off
400
Ground current
On mode, IOUT = 0, VCC6 = VBAT, VOUT = 1.8 V
52
On mode, IOUT = 0, VCC6 = 1.8 V, VOUT = 1.0 V
67
On mode, IOUT = IOUTmax, VCC6 = VBAT, VOUT =
1.8 V
1750
On mode, IOUT = IOUTmax, VCC6 = 1.8 V, VOUT =
1.0 V
1300
Low-power mode, VCC6 = VBAT, VOUT = 1.8 V
11
Low-power mode, VCC6 = 1.8 V, VOUT = 1.0 V
10
Off mode
Copyright © 2010–2012, Texas Instruments Incorporated
dB
Ω
µA
1
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
21
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
VAUX33 AND VMMC LDO
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Input voltage (VCC3) VIN
TEST CONDITIONS
MIN
TYP
MAX
VOUT (VAUX33) = 1.8 V / 2 V and VOUT (VMMC) =
1.8 V
2.7
5.5
VOUT (VAUX33) = 2.8 V
3.2
5.5
VOUT (VAUX33) = 3.3 V
3.6
5.5
VOUT (VMMC) = 2.8 V @ 200 mA
3.2
5.5
VOUT (VMMC) = 3.0 V
3.6
5.5
VOUT (VMMC) = 3.3 V @ 200 mA
3.6
5.5
UNIT
V
VAUX33
DC output voltage VOUT
Rated output current IOUTmax
On and low-power mode, VIN = VINmin to VINmax
SEL = 11, IOUT = 0 to IOUTmax, Default BOOT[1:0] =
01
–3%
3.3
+3%
SEL = 10, IOUT = 0 to IOUTmax
–3%
2.8
+3%
SEL = 01, IOUT = 0 to IOUTmax
–3%
2.0
+3%
SEL = 00, IOUT = 0 to IOUTmax, default BOOT[1:0] =
00
–3%
1.8
+3%
On mode
150
Low-power mode
mA
1
Load current limitation (shortcircuit protection)
On mode, VOUT = VOUTmin – 100 mV
Dropout Voltage VDO
On mode, VOUTtyp = 2.8 V, VDO = VIN – VOUT,
350
VIN = 2.9 V, IOUT = IOUTmax, T = 25°C
V
500
mA
150
mV
DC load regulation
On mode, IOUT = IOUTmax to 0
20
mV
DC line regulation
On mode, IOUT = IOUTmax
3
mV
Transient load regulation
On mode, VIN = 3.8 V
12
mV
2
mV
IOUT = 0.1 × IOUTmax to 0.9 × IOUTmax in 5 µs and
IOUT = 0.9 × IOUTmax to 0.1 × IOUTmax in 5 µs
Transient line regulation
On mode, IOUT = IOUTmax,VIN = VINmin + 0.5 V to
VINmin in 30 µs
and VIN = VINmin to VINmin + 0.5 V in 30 µs, IOUT =
IOUTmax/2
Turn-on time
IOUT = 0, @ VOUT = 0.1 V up to VOUTmin
Turn-on inrush current
Ripple Rejection
100
µs
600
mA
VIN = VINDC + 100 mVpp tone, VINDC+ = 3.8 V, IOUT
= IOUTmax/2
f = 217 Hz
70
f = 50 kHz
40
VAUX33 internal resistance
LDO off
70
Ground current
On mode, IOUT = 0
55
On mode, IOUT = IOUTmax
dB
Ω
1600
Low-power mode
µA
15
Off mode
1
VMMC
DC output voltage VOUT
22
On and low-power mode, VIN = VINmin to VINmax
SEL = 11, IOUT = 0 to 200 mA, default BOOT[1:0] =
00
–3%
3.3
+3%
SEL = 10, IOUT = 0 to IOUTmax
–3%
3.0
+3%
SEL = 01, IOUT = 0 to 200 mA
–3%
2.8
+3%
SEL = 00, IOUT = 0 to IOUTmax, default BOOT[1:0] =
01
–3%
1.8
+3%
Submit Documentation Feedback
V
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
VAUX33 AND VMMC LDO (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Rated output current IOUTmax
TEST CONDITIONS
On mode
Low-power mode
Load current limitation (shortcircuit protection)
On mode, VOUT = VOUTmin – 100 mV
Dropout voltage VDO
Dropout voltage VDO
VIN = 3.0 V, IOUT = 200 mA, T = 25°C
DC load regulation
On mode, IOUT = IOUTmax to 0
DC line regulation
On mode, VIN = VINmin to VINmax @ IOUT = IOUTmax
Transient load regulation
On mode, VIN = 3.8 V
MIN
TYP
MAX
UNIT
300
mA
1
350
500
mA
200
mV
25
mV
3
mV
12
mV
2
mV
100
µs
IOUT = 20 mA to 180 mA in 5 µs and IOUT = 180 mA
to 20 mA in 5 µs
Transient line regulation
On mode, IOUT = 200 mA, VIN = VINmin + 0.5 V to
VINmin in 30 µs
And VIN = VINmin to VINmin + 0.5 V in 30 µs, IOUT =
IOUTmax/2
Turn-on time
IOUT = 0, @ VOUT = 0.1 V up to VOUTmin
Ripple rejection
VIN = VINDC + 100 mVpp tone, VINDC+= 3.8 V, IOUT =
IOUTmax/2
f = 217 Hz
70
f = 50 kHz
40
VMMC internal resistance
LDO Off
70
Ground current
On mode, IOUT = 0
On mode, IOUT = IOUTmax
Low-power mode
Off mode
Copyright © 2010–2012, Texas Instruments Incorporated
dB
Ω
55
2700
µA
15
1
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
23
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
VAUX1 AND VAUX2 LDO
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Input voltage (VCC4) VIN
TEST CONDITIONS
MIN
TYP
MAX
VOUT (VAUX1) = 1.8 V and VOUT (AUX2) = 1.8 V
2.7
5.5
VOUT (VAUX1) = 2.5 V
3.2
5.5
VOUT (VAUX1) = 2.8 V @ Iload = 200 mA and 2.85 V
@ Iload = 200mA
3.2
5.5
VOUT (VAUX2) = 2.8 V
3.2
5.5
VOUT (VAUX2) = 2.9 V @ Iload = 100mA
3.2
5.5
VOUT (VAUX2) = 3.3 V
3.6
5.5
UNIT
V
VAUX1
DC output voltage VOUT
Rated output current IOUTmax
On and low-power mode, VIN = VINmin to VINmax
SEL = 11, IOUT = 0 to 200 mA
–3%
2.85
+3%
SEL = 10, IOUT = 0 to 200 mA
–3%
2.8
+3%
SEL = 01, IOUT = 0 to IOUTmax
–3%
2.5
+3%
SEL = 00, IOUT = 0 to IOUTmax, default BOOT[1:0] =
00 or 01
–3%
1.8
+3%
On mode
300
Low-power mode
mA
1
Load current limitation (shortcircuit protection)
On mode, VOUT = VOUTmin – 100 mV
Dropout voltage VDO
On mode, VOUTtyp = 2.8 V, VDO = VIN – VOUT,
350
VIN = 3.0 V, IOUT = 200 mA, T = 25°C
V
500
mA
200
mV
DC load regulation
On mode, IOUT = 200 mA to 0
15
mA
DC line regulation
On mode, IOUT = 200 mA
5
V
Transient load regulation
On mode, VIN = 3.8 V, IOUT = 20 mA to 180 mA in 5
µs
15
mV
2
mV
and IOUT = 180 mA to 20 mA in 5µs
Transient line regulation
On mode, IOUT = 200 mA, VIN= VINmin + 0.5 V to
VINmin in 30 µs
and VIN = VINmin to VINmin + 0.5v in 30 µs, IOUT =
IOUTmax/2
Turn-on time
IOUT = 0, @ VOUT = 0.1 V up to VOUTmin, no load
Turn-on inrush current
Ripple Rejection
100
µs
600
mA
VIN = VINDC + 100 mVpp tone, VINDC+ = 3.8 V, IOUT =
IOUTmax/2
f = 217 Hz
70
f = 50 kHz
40
VAUX1 internal resistance
LDO Off
80
Ground current
On mode, IOUT = 0
60
On mode, IOUT = IOUTmax
dB
Ω
2700
Low-power mode
µA
12
Off mode
1
VAUX2
On and low-power mode, VIN = VINmin to VINmax
Rated output current IOUTmax
SEL = 11, IOUT = 0 to IOUTmax
–3%
3.3
+3%
SEL = 10, IOUT = 0 to 100 mA
–3%
2.9
+3%
SEL = 01, IOUT = 0 to IOUTmax
–3%
2.8
+3%
SEL = 00, IOUT = 0 to IOUTmax, default BOOT[1:0] =
00 or 01
–3%
1.8
+3%
On mode
150
Low-power mode
24
Submit Documentation Feedback
1
V
mA
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
VAUX1 AND VAUX2 LDO (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Load current limitation (shortcircuit protection)
On mode, VOUT = VOUTmin – 100 mV
350
500
mA
Dropout voltage VDO
On mode, VOUTtyp = 2.8 V, VDO = VIN – VOUT
150
mV
VIN = 2.9 V, IOUT = IOUTmax, T = 25°C
DC load regulation
On mode, IOUT = IOUTmax to 0
15
mV
DC line regulation
On mode, VIN = VINmin to VINmax @ IOUT = IOUTmax
2
mV
Transient load regulation
On mode, VIN = 3.8 V, IOUT = 0.1 × IOUTmax to 0.9 ×
IOUTmax in 5µs
12
mV
2
mV
100
µs
600
mA
And IOUT = 0.9 × IOUTmax to 0.1 × IOUTmax in 5us
Transient line regulation
On mode, IOUT = IOUTmax, VIN = VINmin + 0.5 V to
VINmin in 30 µs
And VIN= VINmin to VINmin + 0.5 V in 30 µs, IOUT =
IOUTmax/2
Turn-on time
IOUT = 0, @ VOUT = 0.1 V up to VOUTmin
Turn-on Inrush current
Ripple rejection
VIN = VINDC + 100 mVpp tone, VINDC+ = 3.8 V, IOUT =
IOUTmax/2
f = 217 Hz
70
f = 50 kHz
40
VAUX2 internal resistance
LDO off
80
Ground current
On mode, IOUT = 0
60
On mode, IOUT = IOUTmax
Low-power mode
Off mode
Copyright © 2010–2012, Texas Instruments Incorporated
dB
Ω
1600
µA
12
1
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
25
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
VDAC AND VPLL LDO
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Input voltage (VCC5) VIN
TEST CONDITIONS
MIN
TYP
MAX
VOUT(VDAC) = 1.8 V and VOUT(VPLL) = 1.8 V / 1.1 V
/ 1.0 V
2.7
5.5
VOUT(VDAC) = 2.6 V and VOUT(VPLL) = 2.5 V
3.0
5.5
VOUT(VDAC) = 2.8 V / 2.85 V
3.2
5.5
UNIT
V
VDAC
DC Output voltage VOUT
Rated output current IOUTmax
On and low-power mode, VIN = VINmin to VINmax
SEL = 11, IOUT = 0 to IOUTmax
–3%
2.85
+3%
SEL = 10, IOUT = 0 to IOUTmax
–3%
2.8
+3%
SEL = 01, IOUT = 0 to IOUTmax
–3%
2.6
+3%
SEL = 00, IOUT = 0 to IOUTmax, default BOOT[1:0] =
00 or 01
–3%
1.8
+3%
On mode
150
Low-power mode
mA
1
Load current limitation (shortcircuit protection)
On mode, VOUT = VOUTmin – 100 mV
Dropout Voltage VDO
On mode, VOUTtyp = 2.8 V, VDO = VIN – VOUT,
350
V
500
mA
150
mV
VIN = 2.9 V, IOUT = IOUTmax, T = 25°C
DC load regulation
On mode, VOUT = VOUTmin – 100 mV
15
mV
DC line regulation
On mode, VOUT = 1.8 V, IOUT = IOUTmax
2
mV
Transient load regulation
On mode, VIN = 3.8 V, IOUT = 0.1 × IOUTmax to 0.9 ×
IOUTmax in 5 µs
15
mV
0.5
mV
And IOUT = 0.9 × IOUTmax to 0.1 × IOUTmax in 5 µs
Transient line regulation
On mode, IOUT = IOUTmax, VIN = VINmin + 0.5 V to
VINmin in 30 µs
And VIN = VINmin to VINmin + 0.5 V in 30 µs, IOUT =
IOUTmax/2
Turn-on time
IOUT = 0, @ VOUT = 0.1 V up to VOUTmin
Turn-on Inrush current
Ripple Rejection
100
µs
600
mA
VIN = VINDC + 100 mVpp tone, VINDC+ = 3.8 V, IOUT =
IOUTmax/2
f = 217 Hz
70
f = 50 kHz
40
VDAC internal resistance
LDO off
360
Ground current
On mode, IOUT = 0
60
On mode, IOUT = IOUTmax
dB
kΩ
1600
Low-power mode
µA
12
Off mode
1
VPLL
DC output voltage VOUT
Rated output current IOUTmax
On and low-power mode, VIN = VINmin to VINmax
SEL = 11, IOUT = 0 to IOUTmax
–3%
2.5
+3%
SEL = 10, IOUT = 0 to IOUTmax, default BOOT[1:0 = 00
or 01
–3%
1.8
+3%
SEL = 01, IOUT = 0 to IOUTmax
–3%
1.1
+3%
SEL = 00, IOUT = 0 to IOUTmax
–3%
1.0
+3%
On mode
50
Low-power mode
1
Load current limitation (shortcircuit protection)
On mode, VOUT = VOUTmin – 100 mV
Dropout voltage VDO
On mode, VOUTtyp = 2.5 V, VDO = VIN – VOUT,
26
Submit Documentation Feedback
200
V
mA
400
mA
100
mV
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
VDAC AND VPLL LDO (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN = 2.5 V, IOUT = IOUTmax, T = 25°C
DC load regulation
On mode, IOUT = IOUTmax to 0
10
mV
DC line regulation
On mode, VIN = VINmin to VINmax @ IOUT = IOUTmax
1
mV
Transient load regulation
On mode, VIN = 3.8 V, IOUT = 0.1 × IOUTmax to 0.9 ×
IOUTmax in 5 µs
9
mV
0.5
mV
And IOUT = 0.9 × IOUTmax to 0.1 × IOUTmax in 5 µs
Transient line regulation
On mode, VIN = VINmin + 0.5 V to VINmin in 30 µs
And VIN = VINmin to VINmin + 0.5 V in 30 µs, IOUT =
IOUTmax/2
Turn-on time
IOUT = 0, @ VOUT = 0.1 V up to VOUTmin
Turn-on inrush current
Ripple rejection
100
µs
300
mA
VIN = VINDC + 100 mVpp tone, VINDC+ = 3.8 V, IOUT =
IOUTmax/2
f = 217 Hz
70
f = 50 kHz
40
VPLL internal resistance
LDO off
535
Ground current
On mode, IOUT = 0
60
On mode, IOUT = IOUTmax
dB
kΩ
1600
Low-power mode
µA
12
Off mode
1
SWITCH-ON/-OFF SEQUENCES AND TIMING
Time slot length can be selected to be 0.5 ms or 2 ms through the EEPROM for an OFF-to-ACTIVE transition or
through the value programmed in the register DEVCTRL2_REG for a SLEEP-to-ACTIVE transition.
BOOT1 = 0, BOOT0 = 0
Table 2 provides details about the EEPROM setting for the BOOT modes. The power-up sequence for this boot
mode is provided in Figure 2.
Table 2. Fixed Boot Mode: 00
Register
VDD1_OP_REG
VDD1_REG
Bit
SEL
VGAIN_SEL
EEPROM
Description
TPS65910
Boot 00
VDD1 voltage level selection for boot
1.2 V
VDD1 Gain selection, x1 or x2
x1
VDD1 time slot selection
DCDCCTRL_REG
VDD2_OP_REG/VDD2_SR_REG
VDD2_REG
VDD1_PSKIP
SEL
VGAIN_SEL
EEPROM
VDD1 pulse skip mode enable
3
skip enabled
VDD2 voltage level selection for boot
1.1 V
VDD2 Gain selection, x1 or x3
x3
VDD2 time slot selection
DCDCCTRL_REG
VIO_REG
VDD2_PSKIP
SEL
EEPROM
VDD2 pulse skip mode enable
2
skip enabled
VIO voltage selection
1.8 V
VIO time slot selection
DCDCCTRL_REG
VIO_PSKIP
EEPROM
VDIG1_REG
SEL
EEPROM
VDIG2_REG
SEL
Copyright © 2010–2012, Texas Instruments Incorporated
VIO pulse skip mode enable
1
skip enabled
VDD3 time slot
OFF
LDO voltage selection
1.2 V
LDO time slot
OFF
LDO voltage selection
1.0 V
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
27
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
SWITCH-ON/-OFF SEQUENCES AND TIMING (continued)
Table 2. Fixed Boot Mode: 00 (continued)
EEPROM
VDAC_REG
SEL
EEPROM
LDO time slot
OFF
LDO voltage selection
1.8 V
LDO time slot
VPLL_REG
SEL
EEPROM
5
LDO voltage selection
1.8 V
LDO time slot
VAUX1_REG
SEL
EEPROM
4
LDO voltage selection
1.8 V
LDO time slot
VMMC_REG
SEL
EEPROM
1
LDO voltage selection
3.3 V
LDO time slot
VAUX33_REG
SEL
EEPROM
VAUX2_REG
SEL
LDO voltage selection
OFF
LDO voltage selection
1.8 V
LDO time slot
CLK32KOUT pin
CLK32KOUT time slot
NRESPWRON pin
NRESPWRON time slot
VRTC_OFFMAS
K
DEVCTRL_REG
RTC_PWDN
DEVCTRL_REG
CK32K_CTRL
DEVCTRL2_REG
DEVCTRL2_REG
INT_MSK_REG
1.8 V
LDO time slot
EEPROM
VRTC_REG
6
5
7
7+1
0: VRTC LDO will be in low-power mode during OFF state
1: VRC LDO will be in full-power mode during OFF state
0: RTC in normal power mode
28
Submit Documentation Feedback
1
1: Clock gating of RTC register and logic, low-power mode
0: Clock source is crystal/external clock
RC
1: Clock source is internal RC oscillator
Boot sequence time slot duration:
TSLOT_LENGTH
0: 0.5 ms
[0]
1: 2 ms
IT_POL
VMBHI_IT_MSK
0: INT1 signal will be active-low
1: INT1 signal will be active-high
0: Device will automatically switch-on at NOSUPPLY to
OFF or BACKUP to OFF transition
1: Startup reason required before switch-on
VMBCH_REG
Low-power mode
VMBCH_SEL[1:0]
2 ms
Active-low
0: Automatic
switch-on from
supply insertion
Select threshold for main battery comparator threshold
VMBCH.
3V
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Figure 2 shows the 00 Boot mode timing characteristics.
tdSOFF2
PWRHOLD
tdSON1
1.8 V
VIO/VFBIO
VAUX1
1.8 V
tdSON2
VDD2/VFB2
3.3 V
tdSON3
1.2 V
VDD1/VFB1
tdSON4
1.8 V
VPLL
tdSON5
VDAC
1.8 V
VAUX2
1.8 V
tdSON6
3.3 V
VMMC
tdSON7
tdSOFF1
CLK32KOUT
tdSON8
NRESPWRON
tdSONT: Switch-on sequence
Switch-off sequence
SWCS046-018
Figure 2. Boot Mode: BOOT1 = 0, BOOT0 = 0
Table 3 lists the 00 Boot mode timing characteristics.
Table 3. Boot Mode: BOOT1 = 0, BOOT0 = 0 Timing Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tdSON1
PWRHOLD rising edge to VIO, VAUX1 enable delay
66 × tCK32k = 2060
µs
tdSON2
VIO to VDD2 enable delay
64 × tCK32k = 2000
µs
tdSON3
VDD2 to VDD1 enable delay
64 × tCK32k = 2000
µs
tdSON4
VDD1 to VPLL enable delay
64 × tCK32k = 2000
µs
tdSON5
VPLL to VDAC,VAUX2 enable delay
64 × tCK32k = 2000
µs
tdSON6
VDAC to VMMC enable delay
64 × tCK32k = 2000
µs
VMMC to CLK32KOUT rising edge delay
64 × tCK32k = 2000
µs
64 × tCK32k = 2000
µs
16
ms
tdSON8
CLK32KOUT to NRESPWRON rising edge delay
tdSONT
Total switch-on delay
tdSOFF1
PWRHOLD falling edge to NRESPWRON falling edge
delay
2 × tCK32k = 62.5
µs
tdSOFF1B
NRESPWRON falling edge to CLK32KOUT low delay
3 × tCK32k = 92
µs
tdSOFF2
PWRHOLD falling edge to supplies and reference
disable delay
5 × tCK32k = 154
µs
Registers default setting: CK32K_CTRL = 1 (32-kHz RC oscillator is used), RTC_PWDN = 1 (RTC domain off),
IT_POL = 0 (INt2 interrupt flag active low), VMBHI_IT_MSK = 0 (automatic switch-on on Battery plug),
VMBCH_SEL = 11.
BOOT1 = 0, BOOT0 = 1
Table 4 provides details about the EEPROM setting for the BOOT modes. The power-up sequence for this boot
mode is provided in Figure 3.
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
29
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
Table 4. Fixed Boot Mode: 01
Register
VDD1_OP_REG
VDD1_REG
Bit
SEL
VGAIN_SEL
EEPROM
Description
VDD1 voltage level selection for boot
1.2 V
VDD1 Gain selection, x1 or x2
x1
VDD1 time slot selection
DCDCCTRL_REG
VDD2_OP_REG/VDD2_SR_REG
VDD2_REG
VDD1_PSKIP
SEL
VGAIN_SEL
EEPROM
DCDCCTRL_REG
VIO_REG
VDD2_PSKIP
SEL
EEPROM
3
VDD1 pulse skip mode enable
Skip enabled
VDD2 voltage level selection for boot
1.2 V
VDD2 Gain selection, x1 or x3
x1
VDD2 time slot selection
4
VDD2 pulse skip mode enable
Skip enabled
VIO voltage selection
1.8 V
VIO time slot selection
DCDCCTRL_REG
VIO_PSKIP
EEPROM
VDIG1_REG
SEL
EEPROM
VDIG2_REG
SEL
EEPROM
VDAC_REG
SEL
EEPROM
VPLL_REG
SEL
EEPROM
1
VIO pulse skip mode enable
Skip enabled
VDD3 time slot
OFF
LDO voltage selection
1.2 V
LDO time slot
OFF
LDO voltage selection
1.0 V
LDO time slot
OFF
LDO voltage selection
1.8 V
LDO time slot
OFF
LDO voltage selection
1.8 V
LDO time slot
VAUX1_REG
SEL
EEPROM
VMMC_REG
SEL
EEPROM
VAUX33_REG
SEL
EEPROM
2
LDO voltage selection
1.8 V
LDO time slot
OFF
LDO voltage selection
1.8 V
LDO time slot
OFF
LDO voltage selection
3.3 V
LDO time slot
VAUX2_REG
SEL
LDO time slot
CLK32KOUT pin
CLK32KOUT time slot
NRESPWRON pin
NRESPWRON time slot
VRTC_OFFMAS
K
VRTC_REG
DEVCTRL_REG
RTC_PWDN
DEVCTRL_REG
CK32K_CTRL
DEVCTRL2_REG
DEVCTRL2_REG
INT_MSK_REG
6
LDO voltage selection
EEPROM
1.8 V
5
7
7+1
0: VRTC LDO will be in low-power mode during OFF state
1: VRC LDO will be in full-power mode during OFF state
VMBCH_REG
Submit Documentation Feedback
low-power mode
0: RTC in normal power mode
1
1: Clock gating of RTC register and logic, low-power mode
0: Clock source is crystal/external clock
Crystal
1: Clock source is internal RC oscillator
Boot sequence time slot duration:
TSLOT_LENGTH
0: 0.5 ms
[0]
1: 2 ms
IT_POL
VMBHI_IT_MSK
0: INT1 signal will be active-low
1: INT1 signal will be active-high
0: Device will automatically switch-on at NOSUPPLY to
OFF or BACKUP to OFF transition
1: Startup reason required before switch-on
30
TPS65910
Boot 01
VMBCH_SEL[1:0]
2 ms
Active-low
0: Automatic
switch-on from
supply insertion
Select threshold for main battery comparator threshold
VMBCH.
3V
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Figure 3 shows the 01 Boot mode timing characteristics.
tdSOFF2
PWRHOLD
tdSON1
VIO/VFBIO
1.8 V
tdSON2
VPLL
1.8 V
tdSON3
1.2 V
VDD1/VFB1
tdSON4
1.2 V
VDD2/VFB2
tdSON5
VAUX2
1.8 V
tdSON6
VAUX33
3.3 V
tdSON7
tdSOFF1
CLK32KOUT
tdSON8
NRESPWRON
tdSONT: Switch-on sequence
Switch-off sequence
SWCS046-019
Figure 3. Boot Mode: BOOT1 = 0, BOOT0 = 1
Table 5 lists the 01 Boot mode timing characteristics.
Table 5. Boot Mode: BOOT1 = 0, BOOT0 = 1 Timing Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tdSON1
PWRHOLD rising edge to VIO enable delay
66 × tCK32k = 2060
µs
tdSON2
VIO to VPLL enable delay
64 × tCK32k = 2000
µs
tdSON3
VPLL to VDD1 enable delay
64 × tCK32k = 2000
µs
tdSON4
VDD1 to VDD2 enable delay
64 × tCK32k = 2000
µs
tdSON5
VDD2 to VAUX2 enable delay
64 × tCK32k = 2000
µs
VAUX2 to VAUX33 enable delay
64 × tCK32k = 2000
µs
tdSON7
VAUX33 to CLK32KOUT enable delay
64 × tCK32k = 2000
µs
tdSON8
CLK32KOUT to NRESPWRON enable delay
64 × tCK32k = 2000
µs
tdSONT
Total switch-on delay
16
ms
tdSOFF1
PWRHOLD falling edge to NRESPWRON falling edge
2 × tCK32k = 62.5
µs
tdSOFF1B
NRESPWRON falling edge to CLK32KOUT low delay
3 × tCK32k = 92
µs
tdSOFF2
PWRHOLD falling edge to supplies disable delay
5 × tCK32k = 154
µs
Registers default setting: CK32K_CTRL = 0 (32-kHz quartz or external bypass clock is used), RTC_PWDN = 1
(RTC domain off), IT_POL = 0 (INt2 interrupt flag active low), VMBHI_IT_MSK = 0 (automatic switch-on on
battery plug), VMBCH_SEL = 11.
POWER CONTROL TIMING
Device Turn-On/Off With Rising/Falling Input Voltage
Figure 4 shows the device turn-on/-off with rising/falling input voltage.
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
31
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
POWER CONTROL TIMING (continued)
VMBCH threshold
VMBDCH threshold
VMBLO threshold
VMBHI threshold
VBNPR threshold
VCC7
VRTC
1.8V
VBACKUP > VBNPR
VIO
1.8V
CLK33KOUT
t dOINT1
NRESPWRON
t dbVMBLO
(1)
Interrupt aknowledge
INT1
t dbVMBDCH
VMBHI_IT=1
PWRHOLD
t d32KON
t dbVMBHI
t dSONT
Switch-on sequence
Switch-off sequence
t dONVMBHI
SWCS046-022
NOTE: (1) The DEV_ON control bit (set to 1) or the PWRHOLD signal (set high) can be used to maintain supplies on after
the switch-on sequence. If none of these devce Power On enable conditions is set, the supplies will be turned off after
tdOINT1 delay.
Figure 4. Device Turn-On/Off with Rising/Falling Input Voltage
Device State Control Through PWRON Signal
Figure 5 shows the device state control through PWRON signal.
PWRON
VIO
1.8 V
CLK33KOUT
t dOINT1
NRESPWRON
(1)
Interrupt acknowledge
INT1
PWRON_IT=1
Interrupt acknowledge
PWRON_IT=1
PWRHOLD
t dbPWRHOLDF
t dbPWRONF
t dSONT
Switch-on sequence
t dONPWHOLD
t dbPWRONF
Switch-off
sequence
SWCS046-009
NOTE: (1) The DEV_ON control bit (set to 1) or the PWRHOLD signal (set high) can be used to maintain supplies on after
switch-on sequence, If none of these device POWER ON enable condition is set the supplies will be turned off after
TdOINT1 delay.
Figure 5. PWRON Turn-On/Turn-Off
Figure 6 shows the long-press turn-off timing characteristics.
32
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
POWER CONTROL TIMING (continued)
PWRON
VIO
NRESPWRON
INT1
PWRON_IT=1
PWRON_LP_IT=1
PWRON_IT=1
PWRHOLD
t dPWRONLP
Switch-off
sequence
t dPWRONLPTO
t dbPWRONF
SWCS046-010
NOTE: If the DEV_ON control bit is set to 1 or PWRHOLD is kept high, the device will be turned on again after PWRON long
press turn-off and PWRON released.
Figure 6. PWRON Long-Press Turn-Off
Table 6 lists the power control timing characteristics.
Table 6. Power Control Timing Characteristics
PARAMETER
td32KON: 32-kHz Oscillator turn-on time
TEST CONDITIONS
MIN
TYP
BOOT[1:0] = 00, RC oscillator
0.1
BOOT[1:0] = 01, Quartz
oscillator
400
BOOT[1:0] = 01, Bypass clock
MAX
UNIT
2000
ms
4 × tCK32k
= 125
µs
0.1
3×
tdbVMBHI: VMBHI rising-edge debouncing delay
tCK32k =
94
tdbVMBDCH: Main Battery voltage = VMBDCH threshold to INT1
falling-edge delay
3×
tCK32k =
94
4 × tCK32k
= 125
s
tdbVMBLO: Main Battery voltage = VMBLO threshold to
NRESPWRON falling-edge delay
3×
tCK32k =
94
4 × tCK32k
= 125
s
500
550
µs
4 × tCK32k
= 125
µs
3×
tCK32k=
94
µs
tdbPWRONF: PWRON falling-edge debouncing delay
3×
tdbPWRONR: PWRON rising-edge debouncing delay
tCK32k=
94
tdbPWRHOLD: PWRON rising-edge debouncing delay
2×
tCK32k =
63
tdOINT: INT1 (internal) Power-on pulse duration after PWRON
low-level (debounced) event
tdONPWHOLD: delay to set high PWRHOLD signal or DEV_ON
control bit after NRESPWRON released to keep on the supplies
1
s
984
ms
tdPWRONLP: PWRON long-press delay to interrupt
PWRON falling edge to
PWON_LP_IT = 1
6
s
tdPWRONLPTO: PWRON long-press delay to turn-off
PWRON falling edge to
NRESPWRON falling edge
8
s
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
33
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
Device SLEEP State Control
Figure 7 shows the device SLEEP state control timing characteristics.
tACT2SLP
tSLP2ACT
SLEEP
1.8 V
PWM mode
1.8 V
Low-power mode
1.8 V
PWM mode
1.8 V
Active mode
1.8 V
Low-power mode
1.8 V
Active mode
3.3 V
Pulse skip mode
3.3 V
Low-power mode
3.3 V
Pulse skip mode
VIO/VFBIO
SWIO
VAUX1
VDD2/VFB2
SW2
1.2 V
PWM mode
Off
VPLL
1.8 V
Active mode
Off
VDAC
1.8 V
Active mode
Off
VAUX2
1.8 V
Active mode
1.8 V
Active mode
VMMC
3.3 V
Active mode
3.3 V
Low-power mode
VDD1/VFB1
tdONDCDCSLP
1.2 V
PWM mode
SW1
1.8 V
Active mode
1.8 V
Active mode
1.8 V
Active mode
3.3 V
Active mode
tSLP2ACTCK32K
CLK32KOUT
tACT2SLPCK32K
tdSLPON1
tdSLPONST
tdSLPONST
SWCS046-024
NOTE: Registers programming: VIO_PSKIP = 0, VDD1_PSKIP = 0, VDD1_SETOFF = 1, VDAC_SETOFF = 1,
VPLL_SETOFF = 1, VAUX2_KEEPON = 1
Figure 7. Device SLEEP State Control
Table 7. Device SLEEP State Control Timing Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3 × tCK32k =
94
µs
188
µs
9 × tCK32k =
281
µs
tACT2SLP
SLEEP falling edge to supply in low power
mode
(SLEEP resynchronization delay)
tACT2SLP
SLEEP falling edge to CLK32KOUT low
tSLP2ACT
SLEEP rising edge to supply in high power
mode
8 × tCK32k =
250
tSLP2ACTCK32K
SLEEP rising edge to CLK32KOUT running
344
tSLP2ACT + 3 ×
tCK32k
375
µs
tdSLPON1
SLEEP rising edge to time step 1 of the tun-on
sequence from SLEEP state
281
tSLP2ACT + 1 ×
tCK32k
312
µs
2 × tCK32k =
62
tACT2SLP + 3 ×
tCK32k
156
turn-on sequence step duration, from SLEEP
state
tdSLPONST
tdSLPONDCDC
34
TSLOT_LENGTH[1:0] = 00
0
TSLOT_LENGTH[1:0] = 01
200
TSLOT_LENGTH[1:0] = 10
500
TSLOT_LENGTH[1:0] = 11
2000
VDD1, VDD2 or VIO tun-on delay from tun-on
sequence time step
Submit Documentation Feedback
2 × tCK32k =
62
µs
us
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Power Supplies State Control Through the SCLSR_EN1 and SDASR_EN2 Signals
Figure 8 andFigure 9 show the power supplies state control through the SCLSR_EN1 and SDASR_EN2 signals
timing characteristics.
Switch-on sequence
Switch-off sequence
Device on
NRESPWRON
tdEN
SCLSR_EN1
tdVEN
VDIG1
tdEN
1.2 V
tdSOFF2
tdEN
SCLSR_EN2
VPLL
tdEN
Low-power mode
1.8 V
SWCS046-016
NOTE: Register setting: VDIG1_EN1 = 1, VPLL_EN2 = 1, and VPLL_KEEPON = 1
Figure 8. LDO Type Supplies State Control Through SCLSR_EN1 and SCLSR_EN2
Switch-on sequence
Switch-off sequence
Device on
NRESPWRON
tdEN
SCLSR_EN2
VDD2/VFB2
tdOEN
tdVDDEN
tdVDDEN
0V
3.3 V
tdSOFF2
SCLSR_EN1
VDD1/VFB1
1.2 V
PWM mode
tdEN
tdEN
Low-power mode
PFM (pulse skipping) mode
SW1
SWCS046-017
NOTE: Register setting: VDD2_EN2 = 1, VDD1_EN1 = 1, VDD1_KEEPON = 1, VDD1_PSKIP = 0, and SEL[6:0] = hex00 in
VDD2_SR_REG
Figure 9. VDD1 and VDD2 Supplies State Control Through SCLSR_EN1 and SCLSR_EN2
Table 8. Supplies State Control Though SCLSR_EN1 and SCLSR_EN2 Timing Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tdEN: NREPSWON to supply state
change delay, SCLSR_EN1 or
SCLSR_EN2 driven
0
ms
tdEN: SCLSR_EN1 or
SCLSR_EN2 edge to supply state
change delay
1 × tCK32k = 31
µs
tdVDDEN: SCLSR_EN1 or
SCLSR_EN2 edge to VDD1 or
VDD2 dc-dc turn on delay
3 × tCK32k = 63
µs
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
35
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
VDD1 and VDD2 Voltage Control Through SCLSR_EN1 and SDASR_EN2 Signals
Figure 10 shows the VDD1 and VDD2 voltage control through the SCLSR_EN1 and SDASR_EN2 signals timing
characteristics.
SCLSR_EN2
tdDVSEN
tdDVSENL
1.2 V
VDD1/VFB1
tdDVSEN
tdDVSENL
0.8 V
TSTEP[2:0]=001
TSTEP[2:0]=011
SW1
PFM (pulse skipping) mode
PWM mode
PFM (pulse
skipping) mode
PWM mode
PFM (pulse
skipping) mode
SWCS046-021
NOTE: Register setting: VDD1_EN1 = 1, SEL[6:0] = hex13 in VDD1_SR_REG
Figure 10. VDD1 Supply Voltage Control Though SCLSR_EN1
Table 9. VDD1 Supply Voltage Control Through SCLSR_EN1 Timing Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
tdDVSEN: SCLSR_EN1 or SCLSR_EN2 edge to
VDD1 or VDD2 voltage change delay
tdDVSENL: VDD1 or VDD2 voltage settling delay
MAX
UNIT
2 × tCK32k = 62
µs
32
µs
TSTEP[2:0] = 001
TSTEP[2:0] = 011 (default)
0.4/7.5 = 53
TSTEP[2:0] = 111
160
SMPS Switching Synchronization
Figure 11 shows the SMPS switching synchronization timing characteristics.
SWIO
SW1
tdswio2sw1
tdviosync
tdswio2sw2
SW2
tdswio2sw3
SW3
SWCS046-025
NOTE: VDD1 or VDD2 switching synchronization is available in PWM mode (VDD1_PSKIP = 0 or VDD2_PSKIP = 0). SMPS
external clock (GPIO_CKSYNC) synchronization is available when VIO PWM mode is set (VIO_PSKIP = 0).
Figure 11. SMPS Switching Synchronization
Table 10. SMPS Switching Synchronization Timing Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD1_PSKIP = 0,
tdSWIO2SW1: delay from SWIO rising edge to SW1
rising edge
DCDCCKSYNC[1:0] = 11
160
DCDCCKSYNC[1:0] = 01
220
ns
VDD2_PSKIP = 0,
tdSWIO2SW2: delay from SWIO rising edge to SW1
rising edge
36
Submit Documentation Feedback
DCDCCKSYNC[1:0] = 11
160
DCDCCKSYNC[1:0] = 01
290
ns
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Table 10. SMPS Switching Synchronization Timing Characteristics (continued)
PARAMETER
tdSWIO2SW3: delay from SWIO rising edge to SW3
rising edge
Copyright © 2010–2012, Texas Instruments Incorporated
TEST CONDITIONS
MIN
TYP
MAX
206
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
UNIT
ns
37
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
DEVICE INFORMATION
Table 11. Terminal Functions
NAME
QFN PIN
VDDIO
SUPPLIES
TYPE
I/O
VDDIO/DGND
Power
I
DESCRIPTION
PU/PD
Digital I/Os supply
No
SDA_SDI
VDDIO/DGND
Digital
I/O
I2C bidirectional data signal/serial
peripheral interface data input
(multiplexed)
SCL_SCK
VDDIO/DGND
Digital
I/O
I2C bidirectional clock signal/serial
peripheral interface Clock Input
(multiplexed)
External PU
SDASR_EN2
VDDIO/DGND
Digital
I/O
I2C SmartReflex bidirectional data
signal/enable of supplies (multiplexed)
External PU
SCLSR_EN1
VDDIO/DGND
Digital
I/O
I2C SmartReflex bidirectional clock
signal/enable of supplies (multiplexed)
External PU
SLEEP
VDDIO/DGND
Digital
I
Active-sleep state transition control
signal
Programmable PD
(default active)
GPIO_CKSYNC
VDDIO/DGND
Digital
I/O
Configurable general-purpose I/O or
DC-DCs synchronization clock input
signal
Programmable PD
(default active)
PWRHOLD
VRTC/DGND
Digital
I
Switch-on/-off control signal
Programmable PD
(default active)
PWRON
VBAT/DGND
Digital
I
External switch-on control (ON button)
Programmable PU
(default active)
NRESPWRON
VDDIO/DGND
Digital
O
Power off reset
PD active during
device OFF state
INT1
VDDIO/DGND
Digital
O
Interrupt flag
External PU
No
BOOT0
VRTC/DGND
Digital
I
Power-up sequence selection
Programmable PD
(default active)
BOOT1
VRTC/DGND
Digital
I
Power-up sequence selection
Programmable PD
(default active)
CLK32KOUT
VDDIO/DGND
Digital
O
32-kHz clock output
PD disable in
ACTIVE or SLEEP
state
OSC32KIN
VRTC/REFGND
Analog
I
32-kHz crystal oscillator
No
OSC32KOUT
VRTC/REFGND
Analog
I
32-kHz crystal oscillator
No
VREF
VCC7/REFGND
Analog
O
Bandgap voltage
No
REFGND
Analog
I/O
Reference ground
No
VCC7/AGND
Analog
O
Analog test output (DFT)
No
VBACKUP/AGND
Power
I
Backup battery input (short to VCC5 if
not used)
No
VCC1
VCC1/GND1
Power
I
VDD1 dc-dc power input
No
GND1
VCC1/GND1
Power
I/O
VDD1 dc-dc power ground
No
SW1
VCC1/GND1
Power
O
VDD1 dc-dc switched output
No
VFB1
VCC7/AGND
Analog
I
VDD1 feedback voltage
PD
VCC2
VCC2/GND2
Power
I
VDD2 dc-dc power input
No
GND2
VCC2/GND2
Power
I/O
VDD2 dc-dc power ground
No
SW2
VCC2/GND2
Power
O
VDD2 dc-dc switched output
No
VFB2
VCC4/AGND2
Analog
I
VDD2 dc-dc feedback voltage
PD
VCCIO
VCCIO/GNDIO
Power
I
VIO dc-dc power input
No
GNDIO
VCCIO/GNDIO
Power
I/O
VIO dc-dc power ground
No
SWIO
VCCIO/GNDIO
Power
O
VIO dc-dc switched output
No
VFBIO
VCC7/AGND
Analog
I
VIO feedback voltage
PD
VCC3
VCC3/AGND2
Power
I
VMMC VAUX33 power input
No
VMMC
VCC3/REFGND
Power
O
LDO regulator output
PD
REFGND
TESTV
VBACKUP
38
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Table 11. Terminal Functions (continued)
NAME
QFN PIN
VAUX33
VCC4
SUPPLIES
TYPE
VCC3/REFGND
Power
I/O
DESCRIPTION
O
LDO regulator output, VDD3 internal
regulated supply
PU/PD
PD
VCC4/AGND2
Power
I
VAUX1, VAUX2 power input
No
VAUX1
VCC4/REFGND
Power
O
LDO regulator output
PD
VAUX2
PD
VCC4/REFGND
Power
O
LDO regulator output
VCC5
VCC5/AGND
Power
I
VDAC, VPLL power input
No
VDAC
VCC5/REFGND
Power
O
LDO regulator output
PD
VPLL
VCC5/REFGND
Power
O
LDO regulator output
PD
VRTC
VCC7/REFGND
Power
O
LDO regulator output
PD
VCC6
VCC6/AGND2
Power
I
VDIG1, VDIG2 power input
No
VDIG1
VCC6/REFGND
Power
O
LDO regulator output
No
VDIG2
VCC6/REFGND
Power
O
LDO regulator output
No
I
VRTC power input, VDD3 internal and
analog references supply
No
VCC7
VCC7/REFGND
Power
VFB3
VCC7/AGND
Analog
I
VDD3 feedback voltage
No
SW3
VCC7/GND3
Power
O
VDD3 dc-dc switched output
No
GND3
Power
PAD
AGND
Power
I/O
VDD3 dc-dc power ground
No
AGND
Power
PAD
AGND
Power
I/O
Analog ground
No
AGND2
Power
PAD
AGND
Power
I/O
Analog ground
No
DGND
Power
PAD
DGND
Power
I/O
Digital ground
No
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
39
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
25 TESTV
26 BOOT0
27 VBACKUP
28 VCC7
29 VRRTC
30 VFB3
31 SW3
32 VFB1
33 PWRON
34 GND1
35 SW1
36 VCC1
PIN ASSIGNMENT (TOP VIEW)
SLEEP 37
24 VPLL
CLK32KOUT 38
23 VCC5
GPIO/CKSYN 39
22 VDAC
21 OSC32KOUT
NRESPWRON 40
20 OSC32KIN
VCC2 41
19 BOOT1
SW2 42
PowerPad
GND2 43
18 VREF
VFB2 44
17 REFGND
INT1 45
16 VFBIO
VAUX1 46
15 GNDIO
VDDIO 12
SCLSR/EN1 11
SDASR/EN2 10
SCL 9
SDA 8
VDIG1 7
VCC6 6
VDIG2 5
VAUX33 4
13 VCCIO
VCC3 3
VAUX2 48
VMMC 2
14 SWIO
PWRHOLD 1
VCC4 47
SWCS046-004
Figure 12. 48-QFN Top View Pin Assignment
40
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
DETAILED DESCRIPTION
POWER REFERENCE
The bandgap voltage reference is filtered by using an external capacitor connected across the VREF output and
the analog ground REFGND (see RECOMMENDED OPERATING CONDITIONS, Recommended Operating
Conditions). The VREF voltage is distributed and buffered inside the device.
POWER SOURCES
The power resources provided by the TPS65910 device include inductor-based switched mode power supplies
(SMPS) and linear low drop-out voltage regulators (LDOs). These supply resources provide the required power
to the external processor cores and external components, and to modules embedded in the TPS65910 device.
Two of these SMPS have DVS capability SmartReflex Class 3 compatible. These SMPS provide independent
core voltage domains to the host processor. The remaining SMPS provides supply voltage for the host processor
I/Os.
Table 12 lists the power sources provided by the TPS65910 device.
Table 12. Power Sources
RESOURCE
TYPE
VOLTAGES
POWER
VIO
SMPS
1.5 V / 1.8 V / 2.5 V / 3.3 V
1000 mA
VDD1
SMPS
0.6 ... 1.5 in 12.5-mV steps
1500 mA
Programmable multiplication factor: x2, x3
VDD2
SMPS
0.6 ... 1.5 in 12.5-mV steps
1500 mA
Programmable multiplication factor: x2, x3
VDD3
SMPS
5V
100 mA
VDIG1
VDIG2
LDO
1.2 V, 1.5 V, 1.8 V, 2.7 V
300 mA
LDO
1 V, 1.1 V, 1.2 V, 1.8 V
300 mA
VPLL
LDO
1.0 V, 1.1 V, 1.8 V, 2.5 V
50 mA
VDAC
LDO
1.8 V, 2.6 V, 2.8 V, 2.85 V
150 mA
VAUX1
LDO
1.8 V, 2.5 V, 2.8 V, 2.85 V
300 mA
VAUX2
LDO
1.8 V, 2.8 V, 2.9 V, 3.3 V
150 mA
VAUX33
LDO
1.8 V, 2.0 V, 2.8 V, 3.3 V
150 mA
VMMC
LDO
1.8 V, 2.8 V, 3.0 V, 3.3 V
300 mA
EMBEDED POWER CONTROLLER
The embedded power controller manages the state of the device and controls the power-up sequence.
STATE-MACHINE
The EPC supports the following states:
No supply: The main battery supply voltage is not high enough to power the VRTC regulator. A global reset is
asserted in this case. Everything on the device is off.
Backup: The main battery supply voltage is high enough to enable the VRTC domain but not enough to switch
on all the resources. In this state, the VRTC regulator is in backup mode and only the 32-K oscillator and RTC
module are operating (if enabled). All other resources are off or under reset.
Off: The main battery supply voltage is high enough to start the power-up sequence but device power on is not
enabled. All power supplies are in OFF state except VRTC.
Active: Device power-on enable conditions are met and regulated power supplies are on or can be enabled with
full current capability.
Sleep: Device SLEEP enable conditions are met and some selected regulated power supplies are in low-power
mode.
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
41
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
Figure 13 shows the transitions of the state-machine.
PWRHOLD
NRESPWRON
Pulse
generator
INT1
DEV_ON
POWER ON
enable
tDOINT
PWRON
PWRON_LP_IT
tD
THERM_TS
DEV_OFF
NO SUPPLY
DEV_OFF_RST
SLEEPSIG_POL
MB and BB<VBNPR
SLEEP
SLEEP
enable
DEV_SLP
INT1
MB>VMBHI
MB<VMBLO
MB and BB<VBNPR
OFF
MB>VMBHI
MB and BB<VBNPR
POWER ON
enabled and
MB>VMBCH
POWER ON
disabled
Backup
MB or BB>VBNPR and
MB<VMBLO
ACTIVE
POWER ON
disabled
MB<VMBLO
SLEEP
enabled
SLEEP
disabled
MB: Main battery voltage
BB: Backup battery voltage
MB<VMBLO
SLEEP
SWCS046-011
Figure 13. Embebded Power Control State-Machine
Device power-on enable conditions:
If none of the device power-on disable conditions is met, the following conditions are available to turn on
and/or maintain the ON state of the device:
• PWRON signal low level.
• Or PWRHOLD signal high level.
• Or DEV_ON control bit set to 1 (default inactive).
42
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
•
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Or interrupt flag active (default INT1 low) while the device is off (NRESPWRON = 0) generates a poweron enable condition during a fixed delay (TDOINT1 pulse duration defined in POWER CONTROL TIMING,
Power Control Timing).
The power-on enable condition pulse occurs only if the interrupt status bit is initially low (no previous
identical interrupt pending in the status register).
The Interrupt sources expected when the device is off are:
• PWRON low-level interrupt (PWRON_IT = 1 in INT_STS_REG register)
• PWRHOLD rising-edge interrupt (PWRHOLD_IT = 1 in INT_STS_REG register)
The Interrupt sources expected if enabled when the device is off are:
• RTC Alarm interrupt (RTC_ALARM_IT = 1 or RTC_PERIOD_IT = 1 in INT_STS_REG register)
• First-time input voltage rising above VMBHI threshold (Boot mode or EEPROM dependent) and input
voltage > VMBCH threshold (VMBCH_IT = 1 in INT_STS_REG register).
GPIO_CKSYNC cannot be used to turn on the device (OFF-to-ACTIVE state transition), even if its associated
interrupt is not masked, but can be used as an interrupt source to wake up the device from SLEEP-to-ACTIVE
state.
Device power-on disable conditions:
• PWRON signal low level during more than the long-press delay: tdPWRONLP (can be disabled though register
programming). The interrupt corresponding to this condtion is PWRON_LP_IT in the INT_STS_REG register.
• Or Die temperature has reached the thermal shutdown threshold.
• Or DEV_OFF or DEV_OFF_RST control bit set to 1 (value of DEV_OFF is cleared when the device is in OFF
state).
Device SLEEP enable conditions:
• SLEEP signal low level (default, or high level depending on the programmed polarity)
• And DEV_SLP control bit set to 1
• And interrupt flag inactive (default INT1 high): no nonmasked interrupt pending
The SLEEP state can be controlled by programming DEV_SLP and keeping the SLEEP signal in the active
polarity state, or it can be controlled through the SLEEP signal setting the DEV_SLP bit to 1 once, after device
turn-on.
SWITCH-ON/-OFF SEQUENCES
The power sequence is the automated switching on of the device resources when an off-to-active transition takes
place.
The device supports three embedded power sequences selectable by the device BOOT pins.
BOOT0
BOOT1
Processor Supported
0
0
AM3517, AM3505
1
0
OMAP3 Family, AM3715/03, DM3730/25
0
1
EEPROM sequence
Details of the boot sequence timing are given in SWITCH-ON/-OFF SEQUENCES AND TIMING. EEPROM
sequences can be used for specific power up sequence for corresponding application processor. For details of
EEPROM
sequence
refer
to
the
user
guides
on
the
product
folder:
http://focus.ti.com/docs/prod/folders/print/tps65910.html.
CONTROL SIGNALS
SLEEP
When none of the device sleep-disable conditions are met, a falling edge (default, or rising edge, depending on
the programmed polarity) of this signal causes an ACTIVE-to-SLEEP state transition of the device. A rising edge
(default, or falling edge, depending on the programmed polarity) causes a transition back to ACTIVE state. This
input signal is level sensitive and no debouncing is applied.
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
43
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
While the device is in SLEEP state, predefined resources are automatically set in their low-power mode or off.
Resources can be kept in their active mode: (full-load capability), programming the SLEEP_KEEP_LDO_ON and
the SLEEP_KEEP_RES_ON registers. These registers contain 1 bit per power resource. If the bit is set to 1,
then that resource stays in active mode when the device is in SLEEP state. 32KCLKOUT is also included in the
SLEEP_KEEP_RES_ON register and the 32-kHz clock output is maintained in SLEEP state if the corresponding
mask bit is set.
PWRHOLD
When none of the device power-on disable conditions are met, a rising edge of this signal causes an OFF-toACTIVE state transition of the device and a falling edge causes a transition back to OFF state. Typically, this
signal is used to control the device in a slave configuration. It can be connected to the SYSEN output signal from
other TPS659xx devices, or the NRESPWRON signal of another TPS65910 device. This input signal is level
sensitive and no debouncing is applied.
A rising edge of PWRHOLD is highlighted though an associated interrupt.
BOOT0/BOOT1
These signals determine which processor the device is working with and hence which power-up sequence is
needed. See SWITCH-ON/-OFF SEQUENCES AND TIMING for more details. There is no debouncing on this
input signal.
NRESPWRON
This signal is used as the reset to the processor. It is held low until the ACTIVE state is reached. See POWER
CONTROL TIMING to get detailed timing.
CLK32KOUT
This signal is the output of the 32K oscillator, which can be enabled or not during the power-on sequence,
depending on the Boot mode. It can be enabled and disabled by register bit, during ACTIVE state of the device.
CLK32KOUT output can also be enabled or not during SLEEP state of the device depending on the
SLEEPMASK register programming.
PWRON
A falling edge on this signal causes after tdbPWRONF debouncing delay (defined in Figure 5 and Table 6) an OFFto-ACTIVE state or SLEEP-to-ACTIVE state transition of the device and makes the corresponding interrupt
(PWRON_IT) active. The PWRON input is connected to an external push-button. The built-in debouncing time
defines a minimum button press duration that is required for button press detection. Any button press duration
which is lower than this value is ignored, considered an accidental touch.
After an OFF-to-ACTIVE state transition, the PMIC maintains ACTIVE during tdOINT delay, if the button is
released. After this delay if none of the device enabling conditions is set by the processor supplied, the PMIC
automatically turns off. If the button is not released, the PMIC maintains ACTIVE up to tdPWRONLPTO, because
PWRON low is a device enabling condition. After a SLEEP-to-ACTIVE state transition, the PMIC maintains
ACTIVE as long as an interrupt is pending.
If the device is already in ACTIVE state, a PWRON low level makes the corresponding interrupt (PWRON_IT)
active.
When the PMIC is in ACTIVE mode, if the button is pressed for longer time than tdPWRONLP, the PMIC generates
the PWON_LP_IT interrupt. If the processor does not acknowledge the long press interrupt within a period of
tdPWRONLPTO – tdPWRONLP, the PMIC goes to OFF mode and shuts down the DCDCs and LDOs.
INT1
INT1 signal (default active low) warns the host processor of any event that occurred on the TPS65910 device.
The host processor can then poll the interrupt from the interrupt status register through I2C to identify the
interrupt source. A low level (default setting) indicates an active interrupt, highlighted in the INT_STS_REG
register. The polarity of INT1 can be set by programming the IT_POL control bit.
44
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Any (not masked or masked) interrupt detection causes a POWER ON enable condition during a fixed delay
tDOINT1 (only) when the device is in OFF state (when NRESPWON signal is low). Any (not masked) interrupt
detection is causing a device wakeup from SLEEP state up to acknowledge of the pending interrupt. Any of the
interrupt sources can be masked by programming the INT_MSK_REG register. When an interrupt is masked, its
corresponding interrupt status bit is still updated, but the INT1 flag is not activated.
Interrupt source masking can be used to mask a device switch-on event. Because interrupt flag active is a
POWER ON enable condition during tDOINT1 delay, any interrupt not masked must be cleared to allow turn off of
the device after the tDOINT1 POWER ON enable pulse duration.. See section: Interrupts, for interrupt sources
definition.
SDASR_EN2 and SCLSR_EN1
SDASR_EN2 and SCLSR_EN1 are the data and clock signals of the serial control interface (SR-I2C) dedicated
to SmartReflex applications. These signals can also be programmed to be used as enable signals of one or
several supplies, when the device is on (NRESPWRON high). A resource assigned to SDASR_EN2 or
SCLSR_EN1 control automatically disables the serial control interface.
Programming EN1_LDO_ASS_REG, EN2_LDO_REG, and SLEEP_KEEP_LDO_ON_REG registers:
SCLSR_EN1 and SDASR_EN2 signals can be used to control the turn on/off or sleep state of any LDO type
supplies.
Programming EN1_SMPS_ASS_REG, EN2_SMPS_ASS_REG, and SLEEP_KEEP_RES_ON registers:
SCLSR_EN1 and SDASR_EN2 signals can be used to control the turn on/off or low-power state (PFM mode) of
SMPS type supplies.
SDASR_EN2 and SCLSR_EN1 can be used to set output voltage of VDD1 and VDD2 SMPS from a roof to a
floor value, preprogrammed in the VDD1_OP_REG, VDD2_OP_REG, and teh VDD1_SR_REG, VDD2_SR_REG
registers. Tun-off of VDD1 and VDD2 can also be programmed either in VDD1_OP_REG, VDD2_OP_REG or in
VDD1_SR_REG, VDD2_SR_REG registers.
When a supply is controlled through SCLSR_EN1 or SCLSR_EN2 signals, its state is no longer driven by the
device SLEEP state.
GPIO_CKSYNC
GPIO_CKSYNC is a configurable open-drain digital I/O: directivity, debouncing delay and internal pullup can be
programmed in the GPIO0_REG register. GPIO_CKSYNC cannot be used to turn on the device (OFF-to-ACTIVE
state transition), even if its associated interrupt is not masked, but can be used as an interrupt source to wake up
the device from SLEEP-to-ACTIVE state.
Programming DCDCCKEXT = 1, VDD1, VDD2, VIO, and VDD3 dc-dc switching can be synchronized using a 3MHz clock set though the GPIO_CKSYNC pin.
DYNAMIC VOLTAGE FREQUENCY SCALING AND ADAPTIVE VOLTAGE SCALING OPERATION
Dynamic voltage frequency scaling (DVFS) operation: a supply voltage value corresponding to a targeted
frequency of the digital core supplied is programmed in VDD1_OP_REG or VDD2_OP_REG registers.
The slew rate of the voltage supply reaching a new VDD1_OP_REG or VDD2_OP_REG programmed value is
limited to 12.5 mV/µs, fixed value. Adaptative voltage scaling (AVS) operation: a supply voltage value
corresponding to a supply voltage adjustment is programmed in VDD1_SR_REG or VDD2_SR_REG registers.
The supply voltage is then intended to be tuned by the digital core supplied, based its performance selfevaluation. The slew rate of VDD1 or VDD2 voltage supply reaching a new programmed value is programmable
though the VDD1_REG or VDD2_REG register, respectively.
A serial control interface (SR-I2C) is dedicated to SmartReflex applications such as DVFS and class 3 AVS, and
thus gives access to the VDD1_OP_REG, VDD1_SR_REG, and VDD2_OP_REG, VDD2_SR_REG register.
A general-purpose serial control interface (CTL-I2C) also gives access to these registers, if SR_CTL_I2C_SEL
control bit is set to 1 in the DEVCTRL_REG register (default inactive).
Both control interfaces are compliant with HS-I2C specification (100 kbps, 400 kbps, or 3.4 Mbps).
Figure 14 shows an example of a SmartReflex operation. To optimize power efficiency, the voltage domains of
the host processor uses the DVFS and AVS features provided by SmartReflex.
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
45
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
OPP5
Coarse steps (DVFS)
Fine steps (AVS)
OPP4
OPP Change end
OPP3
OPP2
OPP Change start
OPP1
TSR TI2C
TSMPS
TSR TI2C
TSMPS
TSR TI2C
TSMPS
TSR TI2C
TSMPS
SWCS046-012
(1)
TSR: Time used by the SmartReflex controller
(2)
TI2C: Time used for data transfer through the I2C interface
(3)
TSMPS: Time required by the SMPS to converge to new voltage value
Figure 14. SmartReflex Operation Example
32-kHz RTC CLOCK
The TPS65910 device can provide a 32-kHz clock to the platform through the CLK32KOUT output, the source of
this 32-kHz clock can be:
• 32-kHz crystal connected from OSC32IN to OSC32KOUT pins
• A square-wave 32-kHz clock signal applied to OSC32IN input (OSC32KOUT kept floating).
• Internal 32-kHz RC oscillator, to reduce the BOM, if an accurate clock is not needed by the system.
Default selection of a 32-kHz RC oscillator versus 32-kHz crystal oscillator or external square-wave 32-kHz clock
depends on the Boot mode or device version (EEPROM programming):
• BOOT1 = 0, BOOT0 = 1: quartz oscillator or external square wave 32-kHz clock default
• BOOT1 = 0, BOOT0 = 0: 32-kHz RC oscillator default
Switching from the 32-kHz RC oscillator to the 32-kHz crystal oscillator or external square-wave 32-kHz clock
can also be programmed though DEVCTRL_REG register, taking benefit of the shorter turn-on time of the
internal RC oscillator.
Switching from the 32-kHz crystal oscillator or external square-wave clock to the RC oscillator is not supported.
46
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
VRTC
32 kHz to
digital block
Biasing
and
amplitude
control
OSC32KIN
REFGND
OSC32KOUT
Q
Coscin
Coscout
SWCS046-013
Figure 15. Crystal Oscillator 32-kHz Clock
RTC
The RTC, which is driven by the 32-kHz clock, provides the alarm and timekeeping functions. The RTC is kept
supplied when the device is in the OFF or the BACKUP state.
The main functionalities of the RTC block are:
• Time information (seconds/minutes/hours) directly in binary-coded decimal (BCD) format
• Calendar information (Day/Month/Year/Day of the week) directly in BCD code up to year 2099
• Programmable interrupts generation: The RTC can generate two interrupts: a timer interrupt
RTC_PERIOD_IT periodically (1s/1m/1h/1d period) and an alarm interrupt RTC_ALARM_IT at a precise time
of the day (alarm function). These interrupts are enabled using IT_ALARM and IT_TIMER control bits.
Periodically interrupts can be masked during the SLEEP period to avoid host interruption and are
automatically unmasked after SLEEP wakeup (using the IT_SLEEP_MASK_EN control bit).
• Oscillator frequency calibration and time correction
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
47
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
32-kHz clock
input
Seconds
Week
Days
Frequency
compensation
32-kHz
counter
Minutes
Hours
Days
Interrupt
Control
Months
Alarm
Years
INT_ALARM
INT_TIMER
SWCS046-014
Figure 16. RTC Digital Section Block Diagram
NOTE
INT_ALARM can generate a wakeup of the platform.
INT_TIMER cannot generate a wakeup of the platform.
TIME CALENDAR REGISTERS
All the time and calendar information are available in these dedicated registers, called TC registers. Values of the
TC registers are written in BCD format.
1. Year data ranges from 00 to 99
– Leap year = Year divisible by four (2000, 2004, 2008, 2012...)
– Common year = other years
2. Month data ranges from 01 to 12
3. Day value ranges from:
– 1 to 31 when months are 1, 3, 5, 7, 8, 10, 12
– 1 to 30 when months are 4, 6, 9, 11
– 1 to 29 when month is 2 and year is a leap year
– 1 to 28 when month is 2 and year is a common year
4. Week value ranges from 0 to 6
5. Hour value ranges from 00 to 23 in 24-hour mode and ranges from 1 to 12 in AM/PM mode
6. Minutes value ranges from 0 to 59
7. Seconds value ranges from 0 to 59
To modify the current time, software writes the new time into TC registers to fix the time/calendar information.
The DBB can write into TC registers without stopping the RTC. In addition, software can stop the RTC by
clearing the STOP_RTC bit of the control register and check the RUN bit of the status to be sure that the RTC is
frozen. Then update TC values, and then restart the RTC by setting the STOP_RTC bit.
Example: Time is 10H54M36S PM (PM_AM mode set), 2008 September 5, previous register values are:
48
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Register
Value
SECONDS_REG
0x36
MINUTES_REG
0x54
HOURS_REG
0x90
DAYS_REG
0x05
MONTHS_REG
0x09
YEARS_REG
0x08
The user can round to the closest minute, by setting the ROUND_30S register bit. TC values are set to the
closest minute value at the next second. The ROUND_30S bit is automatically cleared when the rounding time is
performed.
Example:
• If current time is 10H59M45S, a round operation changes time to 11H00M00S.
• if current time is 10H59M29S, a round operation changes time to 10H59M00S.
GENERAL REGISTERS
Software can access the RTC_STATUS_REG and RTC_CTRL_REG registers at any time (except for the
RTC_CTRL_REG[5] bit, which must be changed only when the RTC is stopped).
COMPENSATION REGISTERS
The RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers must respect the available access period.
These registers must be updated before each compensation process. For example, software can load the
compensation value into these registers after each hour event, during an available access period.
Hours
Seconds
4
3
58
59
0
1
6
58
2
59
0
1
2
Compensation event
Hours
3
Seconds
59
4
0
1
Compensation event
swcs046-015
Figure 17. RTC Compensation Scheduling
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
49
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
This drift can be balanced to compensate for any inaccuracy of the 32-kHz oscillator. Software must calibrate the
oscillator frequency, calculate the drift compensation versus one time hour period; and then load the
compensation registers with the drift compensation value. Indeed, if the AUTO_COMP_EN bit in the
RTC_CTRL_REG is enabled, the value of COMP_REG (in twos-complement) is added to the RTC 32-kHz
counter at each hour and one second. When COMP_REG is added to the RTC 32-kHz counter, the duration of
the current second becomes (32768 - COMP_REG)/32768s; so, the RTC can be compensated with a 1/32768
s/hour time unit accuracy.
NOTE
The compensation is considered once written into the registers.
BACKUP BATTERY MANAGEMENT
The device includes a back-up battery switch connecting the VRTC regulator input to a main battery (VCC7) or to
a back-up battery (VBACKUP), depending on the batteries voltage value.
The VRTC supply can then be maintained during a BACKUP state as far as the input voltage is high enough
(>VBNPR threshold). Below the VBNPR voltage threshold the digital core of the device is set under reset by
internal signal POR (PowerOnReset).
The back-up domain functions which are always supplied from VRTC comprehend:
• The internal 32-kHz oscillator
• Backup registers
The back-up battery can be charged from the main battery through an embedded charger. The back-up battery
charge voltage and enable is controlled through BBCH_REG register programming. This register content is
maintained during the device Backup state.
Hence enabled the back-up battery charge is maintained as far as the main battery voltage is higher than the
VMBLO threshold and the back-up battery voltage.
BACKUP REGISTERS
As part of the RTC the device contains five 8-bit registers which can be used for storage by the application
firmware when the external host is powered down. These registers retain their content as long as the VRTC is
active.
I2C INTERFACE
A general-purpose serial control interface (CTL-I2C) allows read and write access to the configuration registers of
all resources of the system.
A second serial control interface (SR-I2C) is dedicated to SmartReflex applications such as DVFS or AVS.
Both control interfaces are compliant with HS-I2C specification.
These interfaces support the standard slave mode (100 Kbps), Fast mode (400 Kbps), and high-speed mode
(3.4 Mbps). The general-purpose I2C module using one slave hard-coded addresse (ID1 = 2Dh). The
SmartReflex I2C module uses one slave hard-coded address (ID0 = 12h). The master mode is not supported.
Addressing: Seven-bit mode addressing device
They do not support the following features:
• 10-bit addressing
• General call
THERMAL MONITORING AND SHUTDOWN
A thermal protection module monitors the junction temperature of the device versus two thesholds:
• Hot-die temperature threshold
• Thermal shutdown temperature theshold
50
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
When the hot-die temperature threshold is reached an interrupt is sent to software to close the noncritical running
tasks.
When the thermal shutdown temperature theshold is reached, the TPS65910 device is set under reset and a
transition to OFF state is initiated. Then the power-on enable conditions of the device is not considered until the
die temperature has decreased below the hot-die threshold. An hysteresis is applied to the hot-die and shutdown
threshold, when detecting a falling edge of temperature, and both detection are debounced to avoid any parasitic
detection. The TPS65910 device allows programming of four hot-die temperature thresholds to increase the
flexibility of the system.
By default, the thermal protection is enabled in ACTIVE state, but can be disabled through programming register
THERM_REG. The thermal protection can be enabled in SLEEP state programming register
SLEEP_KEEP_RES_ON. The thermal protection is automatically enabled during an OFF-to-ACTIVE state
transition and is kept enabled in OFF state after a switch-off sequence caused by a thermal shutdown event.
Transition to OFF state sequence caused by a thermal shutdown event is highlighted in the INT_STS_REG
status register. Recovery from this OFF state is initiated (switch-on sequence) when the die temperature falls
below the hot-die temperature threshold.
Hot-die and thermal shutdown temperature threshold detections state can be monitored or masked by reading or
programming the THERM_REG register. Hot-die interrupt can be masked by programming the INT_MSK_REG
register.
INTERRUPTS
Table 13. Interrupt Sources
Interrupt
Description
RTC_ALARM_IT
RTC alarm event: Occurs at programmed determinate date and time
(running in ACTIVE, OFF, and SLEEP state, default inactive)
RTC_PERIOD_IT
RTC periodic event: Occurs at programmed regular period of time (every second or minute)
(running in ACTIVE, OFF, and SLEEP state, default inactive)
HOT_DIE_IT
The embedded thermal monitoring module has detected a die temperature above the hot-die
detection threshold (running in ACTIVE and SLEEP state)
Level sensitive interrupt.
PWRHOLD_IT
PWRHOLD signal rising edge
PWRON_LP_IT
PWRON is low during more than the long-press delay: tdPWRONLP (can be disable though
register programming).
PWRON_IT
PWRON is low while the device is on (running in ACTIVE and SLEEP state) or PWON was
low while the device was off (causing a device turn-on). Level-sensitive interrupt
VMBHI_IT
The battery voltage rise above the VMBHI threshold: NOSUPPLY to Off or Backup-to-Off
device states transition (first battery plug or battery voltage bounce detection). This interrupt
source can be disabled through EEPROM programming (VMBHI_IT_DIS). Edge-sensitive
interrupt
VMBDCH_IT
The battery voltage falls down below the VMBDCH threshold(running in ACTIVE and SLEEP
state, if enabled programming VMBCH_VSEL). Edge-sensitive interrupt
GPIO0_R_IT
GPIO_CKSYNC rising-edge detection (available in ACTIVE and SLEEP state)
GPIO0_F_IT
GPIO_CKSYNC falling-edge detection (available in ACTIVE and SLEEP state)
INT1 signal (active low) warns the host processor of any event that occurred on the TPS65910 device. The host
processor can then poll the interrupt from the interrupt status register via I2C to identify the interrupt source. Each
interrupt source can be individually masked via the interrupt mask register.
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
51
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
PACKAGE DESCRIPTION
The following are the package descriptions of the TPS65910 PMU devices:
• Package type:
Package
TPS65910
Type
RSL QFN-N48
Size (mm)
6x6
Substrate layers
1 layer
Pitch ball array (mm)
0.4 mm
ViP (via-in-pad)
No
Number of balls
48
Thickness (mm) (max. height including balls)
1
Others
•
Green, ROHS-compliant
Moisture sensitivity level target: JEDEC MSL3 @ 260°C
APPENDIX A: FUNCTIONAL REGISTERS
TPS65910_FUNC_REG REGISTERS MAPPING SUMMARY
Table 14. TPS65910_FUNC_REG Register Summary
Register Name
Type
Register Width (Bits)
Register Reset
Address Offset
SECONDS_REG
RW
8
0x00
0x00
MINUTES_REG
RW
8
0x00
0x01
HOURS_REG
RW
8
0x00
0x02
DAYS_REG
RW
8
0x01
0x03
MONTHS_REG
RW
8
0x01
0x04
YEARS_REG
RW
8
0x00
0x05
WEEKS_REG
RW
8
0x00
0x06
ALARM_SECONDS_REG
RW
8
0x00
0x08
ALARM_MINUTES_REG
RW
8
0x00
0x09
ALARM_HOURS_REG
RW
8
0x00
0x0A
ALARM_DAYS_REG
RW
8
0x01
0x0B
ALARM_MONTHS_REG
RW
8
0x01
0x0C
ALARM_YEARS_REG
RW
8
0x00
0x0D
RTC_CTRL_REG
RW
8
0x00
0x10
RTC_STATUS_REG
RW
8
0x80
0x11
RTC_INTERRUPTS_REG
RW
8
0x00
0x12
RTC_COMP_LSB_REG
RW
8
0x00
0x13
RTC_COMP_MSB_REG
RW
8
0x00
0x14
RTC_RES_PROG_REG
RW
8
0x27
0x15
RTC_RESET_STATUS_REG
RW
8
0x00
0x16
BCK1_REG
RW
8
0x00
0x17
BCK2_REG
RW
8
0x00
0x18
BCK3_REG
RW
8
0x00
0x19
BCK4_REG
RW
8
0x00
0x1A
BCK5_REG
RW
8
0x00
0x1B
PUADEN_REG
RW
8
0x9F
0x1C
REF_REG
RW
8
0x01
0x1D
VRTC_REG
RW
8
0x01
0x1E
VIO_REG
RW
8
0x00
0x20
52
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Table 14. TPS65910_FUNC_REG Register Summary (continued)
Register Name
Type
Register Width (Bits)
Register Reset
Address Offset
VDD1_REG
RW
8
0x0C
0x21
VDD1_OP_REG
RW
8
0x00
0x22
VDD1_SR_REG
RW
8
0x00
0x23
VDD2_REG
RW
8
0x04
0x24
VDD2_OP_REG
RW
8
0x00
0x25
VDD2_SR_REG
RW
8
0x00
0x26
VDD3_REG
RW
8
0x04
0x27
VDIG1_REG
RW
8
0x00
0x30
VDIG2_REG
RW
8
0x00
0x31
VAUX1_REG
RW
8
0x00
0x32
VAUX2_REG
RW
8
0x00
0x33
VAUX33_REG
RW
8
0x00
0x34
VMMC_REG
RW
8
0x00
0x35
VPLL_REG
RW
8
0x00
0x36
VDAC_REG
RW
8
0x00
0x37
THERM_REG
RW
8
0x0D
0x38
BBCH_REG
RW
8
0x00
0x39
DCDCCTRL_REG
RW
8
0x3B
0x3E
DEVCTRL_REG
RW
8
0x40
0x3F
DEVCTRL2_REG
RW
8
0x34
0x40
SLEEP_KEEP_LDO_ON_REG
RW
8
0x00
0x41
SLEEP_KEEP_RES_ON_REG
RW
8
0x00
0x42
SLEEP_SET_LDO_OFF_REG
RW
8
0x00
0x43
SLEEP_SET_RES_OFF_REG
RW
8
0x00
0x44
EN1_LDO_ASS_REG
RW
8
0x00
0x45
EN1_SMPS_ASS_REG
RW
8
0x00
0x46
EN2_LDO_ASS_REG
RW
8
0x00
0x47
EN2_SMPS_ASS_REG
RW
8
0x00
0x48
RESERVED
RW
8
0x00
0x49
RESERVED
RW
8
0x00
0x4A
INT_STS_REG
RW
8
0x00
0x50
INT_MSK_REG
RW
8
0x02
0x51
INT_STS2_REG
RW
8
0x00
0x52
INT_MSK2_REG
RW
8
0x00
0x53
GPIO0_REG
RW
8
0x0A
0x60
JTAGVERNUM_REG
RO
8
0x00
0x80
TPS65910_FUNC_REG REGISTER DESCRIPTIONS
Table 15. SECONDS_REG
Address Offset
0x00
Physical Address
Instance
Description
RTC register for seconds
Type
RW
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
53
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
7
6
5
Reserved
Bits
www.ti.com
4
3
2
SEC1
1
0
SEC0
Field Name
Description
Type
Reset
Reserved
Reserved bit
RO
R returns
0s
0
6:4
SEC1
Second digit of seconds (range is 0 up to 5)
RW
0x0
3:0
SEC0
First digit of seconds (range is 0 up to 9)
RW
0x0
7
Table 16. MINUTES_REG
Address Offset
0x01
Physical Address
Instance
Description
RTC register for minutes
Type
RW
7
6
5
Reserved
Bits
4
3
2
MIN1
1
0
MIN0
Field Name
Description
Type
Reset
Reserved
Reserved bit
RO
R returns
0s
0
6:4
MIN1
Second digit of minutes (range is 0 up to 5)
RW
0x0
3:0
MIN0
First digit of minutes (range is 0 up to 9)
RW
0x0
7
Table 17. HOURS_REG
Address Offset
0x02
Physical Address
Instance
Description
RTC register for hours
Type
RW
7
6
PM_NAM
Reserved
Bits
5
4
3
HOUR1
2
1
0
HOUR0
Field Name
Description
7
PM_NAM
Only used in PM_AM mode (otherwise it is set to 0)
0 is AM
1 is PM
Type
Reset
RW
0
6
Reserved
Reserved bit
RO
R returns
0s
0
5:4
HOUR1
Second digit of hours(range is 0 up to 2)
RW
0x0
3:0
HOUR0
First digit of hours (range is 0 up to 9)
RW
0x0
Table 18. DAYS_REG
Address Offset
0x03
Physical Address
Instance
Description
RTC register for days
Type
RW
54
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
7
6
5
Reserved
4
3
2
DAY1
1
0
DAY0
Bits
Field Name
Description
Type
Reset
7:6
Reserved
Reserved bit
RO
R returns
0s
0x0
5:4
DAY1
Second digit of days (range is 0 up to 3)
RW
0x0
3:0
DAY0
First digit of days (range is 0 up to 9)
RW
0x1
Table 19. MONTHS_REG
Address Offset
0x04
Physical Address
Instance
Description
RTC register for months
Type
RW
7
6
5
Reserved
4
3
2
MONTH1
1
0
MONTH0
Bits
Field Name
Description
Type
Reset
7:5
Reserved
Reserved bit
RO
R returns
0s
0x0
4
MONTH1
Second digit of months (range is 0 up to 1)
RW
0
3:0
MONTH0
First digit of months (range is 0 up to 9)
RW
0x1
Table 20. YEARS_REG
Address Offset
0x05
Physical Address
Instance
Description
RTC register for day of the week
Type
RW
7
6
5
4
3
2
YEAR1
1
0
YEAR0
Bits
Field Name
Description
Type
Reset
7:4
YEAR1
Second digit of years (range is 0 up to 9)
RW
0x0
3:0
YEAR0
First digit of years (range is 0 up to 9)
RW
0x0
Table 21. WEEKS_REG
Address Offset
0x06
Physical Address
Instance
Description
RTC register for day of the week
Type
RW
7
6
5
Reserved
Copyright © 2010–2012, Texas Instruments Incorporated
4
3
2
1
0
WEEK
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
55
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
Bits
Field Name
Description
Type
Reset
7:3
Reserved
Reserved bit
RO
R returns
0s
0x00
2:0
WEEK
First digit of day of the week (range is 0 up to 6)
RW
0
1
0
Table 22. ALARM_SECONDS_REG
Address Offset
0x08
Physical Address
Instance
Description
RTC register for alarm programmation for seconds
Type
RW
7
6
5
4
3
2
Reserved
ALARM_SEC1
Bits
Field Name
Description
Type
Reset
Reserved
Reserved bit
RO
R returns
0s
0
6:4
ALARM_SEC1
Second digit of alarm programmation for seconds (range is 0 up to 5)
RW
0x0
3:0
ALARM_SEC0
First digit of alarm programmation for seconds (range is 0 up to 9)
RW
0x0
7
ALARM_SEC0
Table 23. ALARM_MINUTES_REG
Address Offset
0x09
Physical Address
Instance
Description
RTC register for alarm programmation for minutes
Type
RW
7
6
Reserved
Bits
5
4
3
2
ALARM_MIN1
1
0
ALARM_MIN0
Field Name
Description
Type
Reset
Reserved
Reserved bit
RO
R returns
0s
0
6:4
ALARM_MIN1
Second digit of alarm programmation for minutes (range is 0 up to 5)
RW
0x0
3:0
ALARM_MIN0
First digit of alarm programmation for minutes (range is 0 up to 9)
RW
0x0
7
Table 24. ALARM_HOURS_REG
Address Offset
0x0A
Physical Address
Instance
RTC register for alarm programmation for hours
Type
RW
56
7
6
ALARM_PM_NAM
Description
Reserved
Submit Documentation Feedback
5
4
ALARM_HOUR1
3
2
1
0
ALARM_HOUR0
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
Bits
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Field Name
Description
7
ALARM_PM_NAM
Only used in PM_AM mode for alarm programmation (otherwise it is set
to 0)
0 is AM
1 is PM
Type
Reset
RW
0
6
Reserved
Reserved bit
RO
R returns
0s
0
5:4
ALARM_HOUR1
3:0
ALARM_HOUR0
Second digit of alarm programmation for hours(range is 0 up to 2)
RW
0x0
First digitof alarm programmation for hours (range is 0 up to 9)
RW
0x0
Table 25. ALARM_DAYS_REG
Address Offset
0x0B
Physical Address
Instance
Description
RTC register for alarm programmation for days
Type
RW
7
6
5
Reserved
4
3
2
ALARM_DAY1
1
0
ALARM_DAY0
Bits
Field Name
Description
Type
Reset
7:6
Reserved
Reserved bit
RO
R Special
0x0
5:4
ALARM_DAY1
Second digit of alarm programmation for days (range is 0 up to 3)
RW
0x0
3:0
ALARM_DAY0
First digit of alarm programmation for days (range is 0 up to 9)
RW
0x1
Table 26. ALARM_MONTHS_REG
Address Offset
0x0C
Physical Address
Instance
Description
RTC register for alarm programmation for months
Type
RW
6
5
4
3
ALARM_MONTH1
7
Reserved
2
1
0
ALARM_MONTH0
Bits
Field Name
Description
Type
Reset
7:5
Reserved
Reserved bit
RO
R returns
0s
0x0
4
ALARM_MONTH1
Second digit of alarm programmation for months (range is 0 up to 1)
RW
0
3:0
ALARM_MONTH0
First digit of alarm programmation for months (range is 0 up to 9)
RW
0x1
Table 27. ALARM_YEARS_REG
Address Offset
0x0D
Physical Address
Instance
Description
RTC register for alarm programmation for years
Type
RW
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
57
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
7
6
www.ti.com
5
4
3
2
ALARM_YEAR1
1
0
ALARM_YEAR0
Bits
Field Name
Description
Type
Reset
7:4
ALARM_YEAR1
Second digit of alarm programmation for years (range is 0 up to 9)
RW
0x0
3:0
ALARM_YEAR0
First digit of alarm programmation for years (range is 0 up to 9)
RW
0x0
Table 28. RTC_CTRL_REG
Address Offset
0x10
Physical Address
Instance
RTC control register:
NOTES: A dummy read of this register is necessary before each I2C read in order to update the
ROUND_30S bit value.
Type
RW
7
6
5
4
3
2
1
0
RTC_V_OPT
GET_TIME
SET_32_COUNTER
Description
TEST_MODE
MODE_12_24
AUTO_COMP
ROUND_30S
STOP_RTC
58
Bits
Field Name
Description
Type
Reset
7
RTC_V_OPT
RTC date / time register selection:
0: Read access directly to dynamic registers (SECONDS_REG,
MINUTES_REG, HOURS_REG, DAYS_REG, MONTHS_REG,
YEAR_REG, WEEKS_REG)
1: Read access to static shadowed registers: (see GET_TIME bit).
RW
0
6
GET_TIME
When writing a 1 into this register, the content of the dynamic registers
(SECONDS_REG, MINUTES_REG, HOURS_REG, DAYS_REG,
MONTHS_REG, YEAR_REG and WEEKS_REG) is transferred into
static shadowed registers. Each update of the shadowed registers needs
to be done by re-asserting GET_TIME bit to 1 (i.e.: reset it to 0 and then
re-write it to 1)
RW
0
5
SET_32_COUNTER
0: No action
1: set the 32-kHz counter with COMP_REG value.
It must only be used when the RTC is frozen.
RW
0
4
TEST_MODE
0: functional mode
1: test mode (Auto compensation is enable when the 32kHz counter
reaches at its end)
RW
0
3
MODE_12_24
0: 24 hours mode
1: 12 hours mode (PM-AM mode)
It is possible to switch between the two modes at any time without
disturbed the RTC, read or write are always performed with the current
mode.
RW
0
2
AUTO_COMP
0: No auto compensation
1: Auto compensation enabled
RW
0
1
ROUND_30S
0: No update
1: When a one is written, the time is rounded to the closest minute.
This bit is a toggle bit, the micro-controller can only write one and RTC
clears it. If the micro-controller sets the ROUND_30S bit and then read it,
the micro-controller will read one until the rounded to the closet.
RW
0
0
STOP_RTC
0: RTC is frozen
1: RTC is running
RW
0
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Table 29. RTC_STATUS_REG
Address Offset
0x11
Physical Address
Instance
Description
RTC status register:
NOTES: A dummy read of this register is necessary before each I2C read in order to update the status
register value.
Type
RW
7
6
5
4
3
2
1
0
POWER_UP
ALARM
EVENT_1D
EVENT_1H
EVENT_1M
EVENT_1S
RUN
Reserved
Bits
Field Name
Description
Type
Reset
7
POWER_UP
Indicates that a reset occurred (bit cleared to 0 by writing 1).
POWER_UP is set by a reset, is cleared by writing one in this bit.
RW
1
6
ALARM
Indicates that an alarm interrupt has been generated (bit clear by writing
1).
The alarm interrupt keeps its low level, until the micro-controller write 1 in
the ALARM bit of the RTC_STATUS_REG register.
The timer interrupt is a low-level pulse (15 µs duration).
RW
0
5
EVENT_1D
One day has occurred
RO
0
4
EVENT_1H
One hour has occurred
RO
0
3
EVENT_1M
One minute has occurred
RO
0
2
EVENT_1S
One second has occurred
RO
0
1
RUN
0: RTC is frozen
1: RTC is running
This bit shows the real state of the RTC, indeed because of STOP_RTC
signal was resynchronized on 32-kHz clock, the action of this bit is
delayed.
RO
0
0
Reserved
Reserved bit
RO
R returns
0s
0
Table 30. RTC_INTERRUPTS_REG
Address Offset
0x12
Physical Address
Instance
RTC interrupt control register
Type
RW
7
6
5
Reserved
4
3
2
IT_SLEEP_MASK_EN
Description
1
IT_ALARM
IT_TIMER
0
EVERY
Bits
Field Name
Description
Type
Reset
7:5
Reserved
Reserved bit
RO
R returns
0s
0x0
IT_SLEEP_MASK_E
N
1: Mask periodic interrupt while the TPS65910 device is in SLEEP mode.
Interrupt event is back up in a register and occurred as soon as the
TPS65910 device is no more in SLEEP mode.
0: Normal mode, no interrupt masked
RW
0
4
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
59
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
Bits
Field Name
Description
Type
Reset
3
IT_ALARM
Enable one interrupt when the alarm value is reached (TC ALARM
registers) by the TC registers
RW
0
2
IT_TIMER
Enable periodic interrupt
0: interrupt disabled
1: interrupt enabled
RW
0
EVERY
Interrupt period
00: every second
01: every minute
10: every hour
11: every day
RW
0x0
1:0
Table 31. RTC_COMP_LSB_REG
Address Offset
0x13
Physical Address
Instance
Description
RTC compensation register (LSB)
Notes: This register must be written in 2-complement.
This means that to add one 32kHz oscillator period every hour, micro-controller needs to write FFFF into
RTC_COMP_MSB_REG & RTC_COMP_LSB_REG.
To remove one 32-kHz oscillator period every hour, micro-controller needs to write 0001 into
RTC_COMP_MSB_REG & RTC_COMP_LSB_REG.
The 7FFF value is forbidden.
Type
RW
7
6
5
4
3
2
1
0
RTC_COMP_LSB
Bits
Field Name
Description
7:0
RTC_COMP_LSB
This register contains the number of 32-kHz periods to be added into the
32-kHz counter every hour [LSB]
Type
Reset
RW
0x00
Table 32. RTC_COMP_MSB_REG
Address Offset
0x14
Physical Address
Instance
Description
RTC compensation register (MSB)
Notes: See RTC_COMP_LSB_REG Notes.
Type
RW
7
6
5
4
3
2
1
0
RTC_COMP_MSB
Bits
Field Name
Description
7:0
RTC_COMP_MSB
This register contains the number of 32-kHz periods to be added into the
32-kHz counter every hour [MSB]
Type
Reset
RW
0x00
Table 33. RTC_RES_PROG_REG
Address Offset
0x15
Physical Address
Instance
Description
RTC register containing oscillator resistance value
Type
RW
7
6
Reserved
60
Submit Documentation Feedback
5
4
3
2
1
0
SW_RES_PROG
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Bits
Field Name
Description
Type
Reset
7:6
Reserved
Reserved bit
RO
R returns
0s
0x0
5:0
SW_RES_PROG
Value of the oscillator resistance
RW
0x27
Table 34. RTC_RESET_STATUS_REG
Address Offset
0x16
Physical Address
Instance
Description
RTC register for reset status
Type
RW
6
5
4
3
2
1
0
RESET_STATUS
7
Reserved
Bits
Field Name
Description
Type
Reset
7:6
Reserved
Reserved bit
RO
R returns
0s
0x0
5:0
RESET_STATUS
RW
0x27
Table 35. BCK1_REG
Address Offset
0x17
Physical Address
Instance
Description
Backup register which can be used for storage by the application firmware when the external host is
powered down. These registers will retain their content as long as the VRTC is active.
Type
RW
7
6
5
4
3
2
1
0
BCKUP
Bits
Field Name
Description
7:0
BCKUP
Backup bit
Type
Reset
RW
0x00
Table 36. BCK2_REG
Address Offset
0x18
Physical Address
Instance
Description
Backup register which can be used for storage by the application firmware when the external host is
powered down. These registers will retain their content as long as the VRTC is active.
Type
RW
7
6
5
4
3
2
1
0
BCKUP
Bits
Field Name
Description
7:0
BCKUP
Backup bit
Copyright © 2010–2012, Texas Instruments Incorporated
Type
Reset
RW
0x00
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
61
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
Table 37. BCK3_REG
Address Offset
0x19
Physical Address
Instance
Description
Backup register which can be used for storage by the application firmware when the external host is
powered down. These registers will retain their content as long as the VRTC is active.
Type
RW
7
6
5
4
3
2
1
0
BCKUP
Bits
Field Name
Description
7:0
BCKUP
Backup bit
Type
Reset
RW
0x00
Table 38. BCK4_REG
Address Offset
0x1A
Physical Address
Instance
Description
Backup register which can be used for storage by the application firmware when the external host is
powered down. These registers will retain their content as long as the VRTC is active.
Type
RW
7
6
5
4
3
2
1
0
BCKUP
Bits
Field Name
Description
7:0
BCKUP
Backup bit
Type
Reset
RW
0x00
Table 39. BCK5_REG
Address Offset
0x1B
Physical Address
Instance
Description
Backup register which can be used for storage by the application firmware when the external host is
powered down. These registers will retain their content as long as the VRTC is active.
Type
RW
7
6
5
4
3
2
1
0
BCKUP
Bits
Field Name
Description
7:0
BCKUP
Backup bit
Type
Reset
RW
0x00
Table 40. PUADEN_REG
Address Offset
0x1C
Physical Address
Instance
Description
Pull-up/pull-down control register.
Type
RW
62
7
6
5
4
3
2
1
0
RESERVED
I2CCTLP
I2CSRP
PWRONP
SLEEPP
PWRHOLDP
BOOT1P
BOOT0P
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Bits
Field Name
Description
Type
Reset
7
RESERVED
Reserved bit
RW
1
6
I2CCTLP
SDACTL and SCLCTL pull-up control:
1: Pull-up is enabled
0: Pull-up is disabled
RW
0
5
I2CSRP
SDASR and SCLSR pull-up control:
1: Pull-up is enabled
0: Pull-up is disabled
RW
0
4
PWRONP
PWRON pad pull-up control:
1: Pull-up is enabled
0: Pull-up is disabled
RW
1
3
SLEEPP
SLEEP pad pull-down control:
1: Pull-down is enabled
0: Pull-down is disabled
RW
1
2
PWRHOLDP
PWRHOLD pad pull-down control:
1: Pull-down is enabled
0: Pull-down is disabled
RW
1
1
BOOT1P
BOOT1 pad control:
1: Pull-down is enabled
0: Pull-down is disabled
RW
1
0
BOOT0P
BOOT0 pad control:
1: Pull-down is enabled
0: Pull-down is disabled
RW
1
1
0
Table 41. REF_REG
Address Offset
0x1D
Physical Address
Instance
Description
Reference control register
Type
RW
7
6
5
4
3
Reserved
2
VMBCH_SEL
ST
Bits
Field Name
Description
Type
Reset
7:4
Reserved
Reserved bit
RO
R returns
0s
0x0
3:2
VMBCH_SEL
Main Battery comparator VMBCH programmable threshold (EEPROM
bits):
VMBCH_SEL[1:0] = 00 : bypass
VMBCH_SEL[1:0] = 01 : VMBCH = 2.8 V
VMBCH_SEL[1:0] = 10 : VMBCH = 2.9 V
VMBCH_SEL[1:0] = 11 : VMBCH = 3.0 V
RW
0x0
1:0
ST
Reference state:
ST[1:0] = 00 : Off
ST[1:0] = 01 : On high power (ACTIVE)
ST[1:0] = 10 : Reserved
ST[1:0] = 11 : On low power (SLEEP)
(Write access available in test mode only)
RO
0x1
Table 42. VRTC_REG
Address Offset
0x1E
Physical Address
Instance
Description
VRTC internal regulator control register
Type
RW
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
63
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
7
6
www.ti.com
5
4
Reserved
3
2
VRTC_OFFMASK
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Reserved
1
0
ST
Bits
Field Name
Description
Type
Reset
7:4
Reserved
Reserved bit
RO
R returns
0s
0x0
3
VRTC_OFFMASK
VRTC internal regulator off mask signal:
when 1, the regulator keeps its full-load capability during device OFF
state.
when 0, the regulator will enter in low-power mode during device OFF
state.(EEPROM bit)
RW
0
2
Reserved
Reserved bit
RO
R returns
0s
0
ST
Reference state:
ST[1:0] = 00 : Reserved
ST[1:0] = 01 : On high power (ACTIVE)
ST[1:0] = 10 : Reserved
ST[1:0] = 11 : On low power (SLEEP)
(Write access available in test mode only)
RO
0x1
1:0
Table 43. VIO_REG
Address Offset
0x20
Physical Address
Instance
Description
VIO control register
Type
RW
7
6
5
ILMAX
(1)
64
4
Reserved
3
2
1
SEL
0
ST
Bits
Field Name
Description
7:6
ILMAX
Select maximum load current:
when 00: 0.5 A
when 01: 1.0 A
when 10: 1.0 A
when 11: 1.0 A
Type
Reset
RW
0x0
5:4
Reserved
Reserved bit
RO
R returns
0s
0x0
3:2
SEL
Output voltage selection (EEPROM bits):
SEL[1:0] = 00 : 1.5 V
SEL[1:0] = 01 : 1.8 V
SEL[1:0] = 10 : 2.5 V
SEL[1:0] = 11 : 3.3 V
RW
1:0
ST
Supply state (EEPROM bits):
ST[1:0] = 00 : Off
ST[1:0] = 01 : On high power (ACTIVE)
ST[1:0] = 10 : Off
ST[1:0] = 11 : On low power (SLEEP)
(Write access available in test mode only)
RW
See
(1)
0x0
The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor
user guide to find the correct default value.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Table 44. VDD1_REG
Address Offset
0x21
Physical Address
Instance
Description
VDD1 control register
Type
RW
7
6
5
VGAIN_SEL
4
3
ILMAX
2
1
TSTEP
0
ST
Bits
Field Name
Description
Type
Reset
7:6
VGAIN_SEL
Select output voltage multiplication factor: G (EEPROM bits):
when 00: x1
when 01: x1
when 10: x2
when 11: x3
RW
0x0
5:4
ILMAX
Select maximum load current:
when 0: 1.0 A
when 1: 1.5 A
RW
0
3:2
TSTEP
Time step: when changing the output voltage, the new value is reached
through successive 12.5 mV voltage steps (if not bypassed). The
equivalent programmable slew rate of the output voltage is then:
TSTEP[2:0] = 000 : step duration is 0, step function is bypassed
TSTEP[2:0] = 001 : 12.5 mV/µs (sampling 3 Mhz)
TSTEP[2:0] = 010 : 9.4 mV/µs (sampling 3 Mhz × 3/4)
TSTEP[2:0] = 011 : 7.5 mV/µs (sampling 3 Mhz × 3/5) (default)
TSTEP[2:0] = 100 : 6.25 mV/µs(sampling 3 Mhz/2)
TSTEP[2:0] = 101 : 4.7 mV/µs(sampling 3 Mhz/3)
TSTEP[2:0] = 110 : 3.12 mV/µs(sampling 3 Mhz/4)
TSTEP[2:0] = 111 : 2.5 mV/µs(sampling 3 Mhz/5)
RW
0x3
1:0
ST
Supply state (EEPROM bits):
ST[1:0] = 00 : Off
ST[1:0] = 01 : On, high power mode
ST[1:0] = 10 : Off
ST[1:0] = 11 : On, low power mode
RW
0x0
Table 45. VDD1_OP_REG
Address Offset
0x22
Physical Address
Instance
Description
VDD1 voltage selection register.
This register can be accessed by both control and smartreflex I2C interfaces depending on
SR_CTL_I2C_SEL register bit value.
Type
RW
7
6
5
CMD
4
3
2
1
0
SEL
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
65
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Bits
(1)
www.ti.com
Field Name
Description
Type
Reset
7
CMD
Smart-Reflex command:
when 0: VDD1_OP_REG voltage is applied
when 1: VDD1_SR_REG voltage is applied
RW
0
6:0
SEL
Output voltage (EEPROM bits) selection with GAIN_SEL = 00 (G = 1,
12.5 mV per LSB):
SEL[6:0] = 1001011 to 1111111 : 1.5 V
...
SEL[6:0] = 0111111 : 1.35 V
...
SEL[6:0] = 0110011 : 1.2 V
...
SEL[6:0] = 0000001 to 0000011 : 0.6 V
SEL[6:0] = 0000000 : Off (0.0 V)
Note: from SEL[6:0] = 3 to 75 (dec)
Vout = (SEL[6:0] × 12.5 mV + 0.5625 mV) × G
RW
See
(1)
The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor
user guide to find the correct default value.
Table 46. VDD1_SR_REG
Address Offset
0x23
Physical Address
Instance
Description
VDD1 voltage selection register for smartreflex.
This register can be accessed by both control and smartreflex I2C interfaces depending on
SR_CTL_I2C_SEL register bit value.
Type
RW
7
6
5
4
Reserved
Bits
7
6:0
(1)
3
2
1
0
SEL
Field Name
Description
Type
Reset
Reserved
Reserved bit
RO
R returns
0s
0
SEL
Output voltage (EEPROM bits) selection with GAIN_SEL = 00 (G = 1,
12.5 mV per LSB):
SEL[6:0] = 1001011 to 1111111 : 1.5V
...
SEL[6:0] = 0111111 : 1.35V
...
SEL[6:0] = 0110011 : 1.2V
...
SEL[6:0] = 0000001 to 0000011 : 0.6V
SEL[6:0] = 0000000 : Off (0.0V)
Note: from SEL[6:0] = 3 to 75 (dec)
Vout = (SEL[6:0] × 12.5 mV + 0.5625 mV) × G
RW
See
(1)
The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor
user guide to find the correct default value.
Table 47. VDD2_REG
Address Offset
0x24
Physical Address
Instance
Description
VDD2 control register
Type
RW
7
6
VGAIN_SEL
66
5
ILMAX
Submit Documentation Feedback
4
3
TSTEP
2
1
0
ST
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Bits
Field Name
Description
Type
Reset
7:6
VGAIN_SEL
Select output voltage multiplication factor: G (EEPROM bits):
when 00: x1
when 01: x1
when 10: x2
when 11: x3
RW
0x0
5:4
ILMAX
Select maximum load current:
when 0: 1.0 A
when 1: 1.5 A
RW
0
3:2
TSTEP
Time step: when changing the output voltage, the new value is reached
through successive 12.5 mV voltage steps (if not bypassed). The
equivalent programmable slew rate of the output voltage is then:
TSTEP[2:0] = 000: step duration is 0, step function is bypassed
TSTEP[2:0] = 001: 12.5 mV/µs (sampling 3 Mhz)
TSTEP[2:0] = 010: 9.4 mV/µs (sampling 3 Mhz × 3/4)
TSTEP[2:0] = 011: 7.5 mV/µs (sampling 3 Mhz × 3/5) (default)
TSTEP[2:0] = 100: 6.25 mV/µs(sampling 3 Mhz/2)
TSTEP[2:0] = 101: 4.7 mV/µs(sampling 3 Mhz/3)
TSTEP[2:0] = 110: 3.12 mV/µs(sampling 3 Mhz/4)
TSTEP[2:0] = 111: 2.5 mV/µs(sampling 3 Mhz/5)
RW
0x1
1:0
ST
Supply state (EEPROM bits):
ST[1:0] = 00 : Off
ST[1:0] = 01 : On, high power mode
ST[1:0] = 10 : Off
ST[1:0] = 11 : On, low power mode
RW
0x0
Table 48. VDD2_OP_REG
Address Offset
0x25
Physical Address
Instance
Description
VDD2 voltage selection register.
This register can be accessed by both control and smartreflex I2C interfaces depending on
SR_CTL_I2C_SEL register bit value.
Type
RW
7
6
5
CMD
Bits
(1)
4
3
2
1
0
SEL
Field Name
Description
Type
Reset
7
CMD
Smart-Reflex command:
when 0: VDD2_OP_REG voltage is applied
when 1: VDD2_SR_REG voltage is applied
RW
0
6:0
SEL
Output voltage (EEPROM bits) selection with GAIN_SEL = 00 (G = 1,
12.5 mV per LSB):
SEL[6:0] = 1001011 to 1111111 : 1.5 V
...
SEL[6:0] = 0111111 : 1.35 V
...
SEL[6:0] = 0110011 : 1.2 V
...
SEL[6:0] = 0000001 to 0000011 : 0.6 V
SEL[6:0] = 0000000 : Off (0.0 V)
Note: from SEL[6:0] = 3 to 75 (dec)
Vout= (SEL[6:0] × 12.5 mV + 0.5625 mV) × G
RW
See
(1)
The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor
user guide to find the correct default value.
Table 49. VDD2_SR_REG
Address Offset
0x26
Physical Address
Description
Instance
VDD2 voltage selection register for smartreflex.
This register can be accessed by both control and smartreflex I2C interfaces depending on
SR_CTL_I2C_SEL register bit value.
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
67
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
Table 49. VDD2_SR_REG (continued)
Type
RW
7
6
5
4
3
Reserved
Bits
7
6:0
(1)
2
1
0
SEL
Field Name
Description
Type
Reset
Reserved
Reserved bit
RO
R returns
0s
0
SEL
Output voltage (EEPROM bits) selection with GAIN_SEL = 00 (G = 1,
12.5 mV per LSB):
SEL[6:0] = 1001011 to 1111111: 1.5 V
...
SEL[6:0] = 0111111: 1.35V
...
SEL[6:0] = 0110011: 1.2V
...
SEL[6:0] = 0000001 to 0000011: 0.6V
SEL[6:0] = 0000000: Off (0.0V)
Note: from SEL[6:0] = 3 to 75 (dec)
Vout= (SEL[6:0] × 12.5 mV + 0.5625 mV) ×G
RW
See
(1)
The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor
user guide to find the correct default value.
Table 50. VDD3_REG
Address Offset
0x27
Physical Address
Instance
Description
VDD2 voltage selection register for smartreflex.
This register can be accessed by both control and smartreflex I2C interfaces depending on
SR_CTL_I2C_SEL register bit value.
Type
RW
7
6
5
4
3
2
Reserved
1
CKINEN
0
ST
Bits
Field Name
Description
Type
Reset
7:3
Reserved
Reserved bit
RO
R returns
0s
0x00
2
CKINEN
Enable 1Mhz clock synchronization
RW
1
ST
Supply state (EEPROM bits):
ST[1:0] = 00 : Off
ST[1:0] = 01 : On high power (ACTIVE)
ST[1:0] = 10 : Off
ST[1:0] = 11 : On low power (SLEEP)
RW
0x0
1:0
Table 51. VDIG1_REG
Address Offset
0x30
Physical Address
Instance
Description
VDIG1 regulator control register
Type
RW
7
6
5
Reserved
68
Submit Documentation Feedback
4
3
2
SEL
1
0
ST
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
(1)
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Bits
Field Name
Description
Type
Reset
7:4
Reserved
Reserved bit
RO
R returns
0s
0x0
3:2
SEL
Supply voltage (EEPROM bits):
SEL[1:0] = 00 : 1.2 V
SEL[1:0] = 01 : 1.5 V
SEL[1:0] = 10 : 1.8 V
SEL[1:0] = 11 : 2.7 V
RW
1:0
ST
Supply state (EEPROM bits):
ST[1:0] = 00 : Off
ST[1:0] = 01 : On high power (ACTIVE)
ST[1:0] = 10 : Off
ST[1:0] = 11 : On low power (SLEEP)
RW
See
(1)
0x0
The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor
user guide to find the correct default value.
Table 52. VDIG2_REG
Address Offset
0x31
Physical Address
Instance
Description
VDIG2 regulator control register
Type
RW
7
6
5
4
3
Reserved
(1)
2
1
SEL
0
ST
Bits
Field Name
Description
Type
Reset
7:4
Reserved
Reserved bit
RO
R returns
0s
0x0
3:2
SEL
Supply voltage (EEPROM bits):
SEL[1:0] = 00 : 1.0 V
SEL[1:0] = 01 : 1.1 V
SEL[1:0] = 10 : 1.2 V
SEL[1:0] = 11 : 1.8 V
RW
1:0
ST
Supply state (EEPROM bits):
ST[1:0] = 00 : Off
ST[1:0] = 01 : On high power (ACTIVE)
ST[1:0] = 10 : Off
ST[1:0] = 11 : On low power (SLEEP)
RW
See
(1)
0x0
The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor
user guide to find the correct default value.
Table 53. VAUX1_REG
Address Offset
0x32
Physical Address
Instance
Description
VAUX1 regulator control register
Type
RW
7
6
5
Reserved
Copyright © 2010–2012, Texas Instruments Incorporated
4
3
2
SEL
1
0
ST
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
69
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
(1)
www.ti.com
Bits
Field Name
Description
Type
Reset
7:4
Reserved
Reserved bit
RO
R returns
0s
0x0
3:2
SEL
Supply voltage (EEPROM bits):
SEL[1:0] = 00 : 1.8 V
SEL[1:0] = 01 : 2.5 V
SEL[1:0] = 10 : 2.8 V
SEL[1:0] = 11 : 2.85 V
RW
1:0
ST
Supply state (EEPROM bits):
ST[1:0] = 00 : Off
ST[1:0] = 01 : On high power (ACTIVE)
ST[1:0] = 10 : Off
ST[1:0] = 11 : On low power (SLEEP)
RW
See
(1)
0x0
The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor
user guide to find the correct default value.
Table 54. VAUX2_REG
Address Offset
0x33
Physical Address
Instance
Description
VAUX2 regulator control register
Type
RW
7
6
5
4
3
Reserved
(1)
2
1
SEL
0
ST
Bits
Field Name
Description
Type
Reset
7:4
Reserved
Reserved bit
RO
R returns
0s
0x0
3:2
SEL
Supply voltage (EEPROM bits):
SEL[1:0] = 00 : 1.8 V
SEL[1:0] = 01 : 2.8 V
SEL[1:0] = 10 : 2.9 V
SEL[1:0] = 11 : 3.3 V
RW
1:0
ST
Supply state (EEPROM bits):
ST[1:0] = 00 : Off
ST[1:0] = 01 : On high power (ACTIVE)
ST[1:0] = 10 : Off
ST[1:0] = 11 : On low power (SLEEP)
RW
See
(1)
0x0
The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor
user guide to find the correct default value.
Table 55. VAUX33_REG
Address Offset
0x34
Physical Address
Instance
Description
VAUX33 regulator control register
Type
RW
7
6
5
Reserved
70
Submit Documentation Feedback
4
3
2
SEL
1
0
ST
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
(1)
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Bits
Field Name
Description
Type
Reset
7:4
Reserved
Reserved bit
RO
R returns
0s
0x0
3:2
SEL
Supply voltage (EEPROM bits):
SEL[1:0] = 00 : 1.8 V
SEL[1:0] = 01 : 2.0 V
SEL[1:0] = 10 : 2.8 V
SEL[1:0] = 11 : 3.3 V
RW
1:0
ST
Supply state (EEPROM bits):
ST[1:0] = 00 : Off
ST[1:0] = 01 : On high power (ACTIVE)
ST[1:0] = 10 : Off
ST[1:0] = 11 : On low power (SLEEP)
RW
See
(1)
0x0
The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor
user guide to find the correct default value.
Table 56. VMMC_REG
Address Offset
0x35
Physical Address
Instance
Description
VMMC regulator control register
Type
RW
7
6
5
4
3
Reserved
(1)
2
1
SEL
0
ST
Bits
Field Name
Description
Type
Reset
7:4
Reserved
Reserved bit
RO
R returns
0s
0x0
3:2
SEL
Supply voltage (EEPROM bits):
SEL[1:0] = 00 : 1.8 V
SEL[1:0] = 01 : 2.8 V
SEL[1:0] = 10 : 3.0 V
SEL[1:0] = 11 : 3.3 V
RW
1:0
ST
Supply state (EEPROM bits):
ST[1:0] = 00: Off
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP)
RW
See
(1)
0x0
The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor
user guide to find the correct default value.
Table 57. VPLL_REG
Address Offset
0x36
Physical Address
Instance
Description
VPLL regulator control register
Type
RW
7
6
5
Reserved
Copyright © 2010–2012, Texas Instruments Incorporated
4
3
2
SEL
1
0
ST
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
71
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
(1)
www.ti.com
Bits
Field Name
Description
Type
Reset
7:4
Reserved
Reserved bit
RO
R returns
0s
0x0
3:2
SEL
Supply voltage (EEPROM bits):
SEL[1:0] = 00 : 1.0V
SEL[1:0] = 01 : 1.1 V
SEL[1:0] = 10 : 1.8 V
SEL[1:0] = 11 : 2.5 V
RW
1:0
ST
Supply state (EEPROM bits):
ST[1:0] = 00 : Off
ST[1:0] = 01 : On high power (ACTIVE)
ST[1:0] = 10 : Off
ST[1:0] = 11 : On low power (SLEEP)
RW
See
(1)
0x0
The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor
user guide to find the correct default value.
Table 58. VDAC_REG
Address Offset
0x37
Physical Address
Instance
Description
VDAC regulator control register
Type
RW
7
6
5
4
3
Reserved
(1)
2
1
SEL
0
ST
Bits
Field Name
Description
Type
Reset
7:4
Reserved
Reserved bit
RO
R returns
0s
0x0
3:2
SEL
Supply voltage (EEPROM bits):
SEL[1:0] = 00 : 1.8 V
SEL[1:0] = 01 : 2.6 V
SEL[1:0] = 10 : 2.8 V
SEL[1:0] = 11 : 2.85 V
RW
1:0
ST
Supply state (EEPROM bits):
ST[1:0] = 00 : Off
ST[1:0] = 01 : On high power (ACTIVE)
ST[1:0] = 10 : Off
ST[1:0] = 11 : On low power (SLEEP)
RW
See
(1)
0x0
The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor
user guide to find the correct default value.
Table 59. Therm_REG
Address Offset
0x38
Instance
Description
Thermal control register
Type
RW
7
6
Reserved
72
5
4
THERM_HD
THERM_TS
Submit Documentation Feedback
3
2
THERM_HDSEL
1
0
RSVD1
THERM_STATE
Physical Address
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Bits
Field Name
Description
Type
Reset
7:6
Reserved
Reserved bit
RO
R returns
0s
0x0
5
THERM_HD
Hot die detector output:
when 0: the hot die threshold is not reached
when 1: the hot die threshold is reached
RO
0
4
THERM_TS
Thermal shutdown detector output:
when 0: the thermal shutdown threshold is not reached
when 1: the thermal shutdown threshold is reached
RO
0
THERM_HDSEL
Temperature selection for Hot Die detector:
when 00: Low temperature threshold
…
when 11: High temperature threshold
RW
0x3
1
RSVD1
Reserved bit
RW
0
0
THERM_STATE
Thermal shutdown module enable signal:
when 0: thermal shutdown module is disable
when 1: thermal shutdown module is enable
RW
1
3:2
Table 60. BBCH_REG
Address Offset
0x39
Physical Address
Instance
Description
Back-up battery charger control register
Type
RW
7
6
5
4
3
2
Reserved
1
0
BBSEL
BBCHEN
Bits
Field Name
Description
Type
Reset
7:4
Reserved
Reserved bit
RO
R returns
0s
0x00
2:1
BBSEL
Back up battery charge voltage selection:
BBSEL[1:0] = 00 : 3.0 V
BBSEL[1:0] = 01 : 2.52 V
BBSEL[1:0] = 10 : 3.15 V
BBSEL[1:0] = 11 : VBAT
RW
0x0
BBCHEN
Back up battery charge enable
RW
0
1
0
0
Table 61. DCDCCTRL_REG
Address Offset
0x3E
Physical Address
Instance
Description
DCDC control register
Type
RW
7
6
Reserved
5
4
3
2
VDD2_PSKIP
VDD1_PSKIP
VIO_PSKIP
DCDCCKEXT
DCDCCKSYNC
Bits
Field Name
Description
Type
Reset
7:6
Reserved
Reserved bit
RO
R returns
0s
0x0
5
VDD2_PSKIP
VDD2 pulse skip mode enable (EEPROM bit)
RW
1
4
VDD1_PSKIP
VDD1 pulse skip mode enable (EEPROM bit)
RW
1
3
VIO_PSKIP
VIO pulse skip mode enable (EEPROM bit)
RW
1
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
73
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Bits
2
1:0
www.ti.com
Field Name
Description
Type
Reset
DCDCCKEXT
This signal control the muxing of the GPIO0 pad:
When 0: this pad is a GPIO
When 1: this pad is used as input for an external clock used for the
synchronisation of the DCDCs
RW
0
DCDCCKSYNC
DCDC clock configuration:
DCDCCKSYNC[1:0] = 00 : no synchronization of DCDC clocks
DCDCCKSYNC[1:0] = 01 : DCDC synchronous clock with phase shift
DCDCCKSYNC[1:0] = 10 : no synchronization of DCDC clocks
DCDCCKSYNC[1:0] = 11 : DCDC synchronous clock
RW
0x3
Table 62. DEVCTRL_REG
Address Offset
0x3F
Physical Address
Instance
Type
RW
7
6
5
4
3
2
1
0
Reserved
RTC_PWDN
CK32K_CTRL
DEV_OFF_RST
Device control register
SR_CTL_I2C_SEL
Description
DEV_ON
DEV_SLP
DEV_OFF
Bits
Field Name
Description
Type
Reset
7
Reserved
Reserved bit
RO
R returns
0s
0
6
RTC_PWDN
When 1, disable the RTC digital domain (clock gating and reset of RTC
registers and logic).
This register bit is not reset in BACKUP state. (EEPROM bit)
RW
1
5
CK32K_CTRL
Internal 32-kHz clock source control bit (EEPROM bit):
when 0, the internal 32-kHz clock source is the crystal oscillator or an
external 32-kHz clock in case the crystal oscillator is used in bypass
mode
when 1, the internal 32-kHz clock source is the RC oscillator.
RW
0
4
SR_CTL_I2C_SEL
Smartreflex registers access control bit:
when 0: access to smartreflex registers by smartreflex I2C
when 1: access to smartreflex registers by control I2C The smartreflex
registers are: VDD1_OP_REG, VDD1_SR_REG, VDD2_OP_REG and
VDD2_SR_REG.
RW
0
3
DEV_OFF_RST
Write 1 will start an ACTIVE to OFF or SLEEP to OFF device state
transition (switch-off event) and activate reset of the digital core.
RW
0
2
DEV_ON
Write 1 will maintain the device on (ACTIVE or SLEEP device state) (if
DEV_OFF = 0 and DEV_OFF_RST = 0).
RW
0
1
DEV_SLP
Write 1 allows SLEEP device state (if DEV_OFF = 0 and
DEV_OFF_RST = 0).
Write ‘0’ will start an SLEEP to ACTIVE device state transition (wake-up
event) (if DEV_OFF = 0 and DEV_OFF_RST = 0). This bit is cleared in
OFF state.
RW
0
0
DEV_OFF
Write 1 will start an ACTIVE to OFF or SLEEP to OFF device state
transition (switch-off event). This bit is cleared in OFF state.
RW
0
Table 63. DEVCTRL2_REG
Address Offset
0x40
Physical Address
Description
74
Instance
Device control register
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Table 63. DEVCTRL2_REG (continued)
6
5
4
3
2
1
0
TSLOT_LENGTH
PWRON_LP_RST
7
PWRON_LP_OFF
RW
SLEEPSIG_POL
Type
IT_POL
Bits
Field Name
Description
Type
Reset
7:6
Reserved
Reserved bit
RO
R returns
0s
0x0
5:4
TSLOT_LENGTH
Time slot duration programming (EEPROM bit):
When 00 : 0 µs
When 01 : 200 µs
When 10 : 500 µs
When 11 : 2 ms
RW
0x3
3
SLEEPSIG_POL
When 1, SLEEP signal active high
When 0, SLEEP signal active low
RW
0
2
PWRON_LP_OFF
When 1, allows device turn-off after a PWRON long press (signal low).
RW
1
1
PWRON_LP_RST
When 1, allows digital core reset when the device is OFF after a
PWRON long press (signal low).
RW
0
0
IT_POL
INT1 interrupt pad polarity control signal (EEPROM bit):
When 0, active low
When 1, active high
RW
0
Reserved
Table 64. SLEEP_KEEP_LDO_ON_REG
Address Offset
0x41
Physical Address
Instance
5
4
3
2
VAUX1_KEEPON
VDIG2_KEEPON
Copyright © 2010–2012, Texas Instruments Incorporated
1
0
VMMC_KEEPON
6
VDIG1_KEEPON
7
VAUX2_KEEPON
RW
VAUX33_KEEPON
Type
VPLL_KEEPON
When corresponding control bit=0 in EN1/2_ LDO_ASS register (default setting): Configuration Register
keeping the full load capability of LDO regulator (ACTIVE mode) during the SLEEP state of the device.
When control bit=1, LDO regulator full load capability (ACTIVE mode) is maintained during device
SLEEP state.
When control bit=0, the LDO regulator is set or stay in low power mode during device SLEEP state(but
then supply state can be overwritten programming ST[1:0]). Control bit value has no effect if the LDO
regulator is off.
When corresponding control bit=1 in EN1/2_ LDO_ASS register: Configuration Register setting the LDO
regulator state driven by SCLSR_EN1/2 signal low level (when SCLSR_EN1/2 is high the regulator is
on, full power):
- the regulator is set off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register (default)
- the regulator is set in low power mode if its corresponding control bit = 1 in SLEEP_KEEP_LDO_ON
register
VDAC_KEEPON
Description
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
75
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Bits
www.ti.com
Field Name
Description
Type
Reset
7
VDAC_KEEPON
Setting supply state during device SLEEP state or when SCLSR_EN1/2
is low
RW
0
6
VPLL_KEEPON
Setting supply state during device SLEEP state or when SCLSR_EN1/2
is low
RW
0
5
VAUX33_KEEPON
Setting supply state during device SLEEP state or when SCLSR_EN1/2
is low
RW
0
4
VAUX2_KEEPON
Setting supply state during device SLEEP state or when SCLSR_EN1/2
is low
RW
0
3
VAUX1_KEEPON
Setting supply state during device SLEEP state or when SCLSR_EN1/2
is low
RW
0
2
VDIG2_KEEPON
Setting supply state during device SLEEP state or when SCLSR_EN1/2
is low
RW
0
1
VDIG1_KEEPON
Setting supply state during device SLEEP state or when SCLSR_EN1/2
is low
RW
0
0
VMMC_KEEPON
Setting supply state during device SLEEP state or when SCLSR_EN1/2
is low
RW
0
Table 65. SLEEP_KEEP_RES_ON_REG
Address Offset
0x42
Physical Address
Instance
Bits
76
7
6
5
4
3
2
1
0
I2CHS_KEEPON
VDD3_KEEPON
VDD2_KEEPON
VDD1_KEEPON
RW
VRTC_KEEPON
Type
CLKOUT32K_KEEPON
Configuration Register keeping, during the SLEEP state of the device (but then supply state can be
overwritten programming ST[1:0]):
- the full load capability of LDO regulator (ACTIVE mode),
- The PWM mode of DCDC converter
- 32KHz clock output
- Register access though I2C interface (keeping the internal high speed clock on)
- Die Thermal monitoring on
Control bit value has no effect if the resource is off.
THERM_KEEPON
Description
VIO_KEEPON
Field Name
Description
7
THERM_KEEPON
When 1, thermal monitoring is maintained during device SLEEP state.
When 0, thermal monitoring is turned off during device SLEEP state.
Type
Reset
RW
0
6
CLKOUT32K_KEEPO When 1, CLK32KOUT output is maintained during device SLEEP state.
N
When 0, CLK32KOUT output is set low during device SLEEP state.
RW
0
5
VRTC_KEEPON
When 1, LDO regulator full load capability (ACTIVE mode) is maintained
during device SLEEP state.
When 0, the LDO regulator is set or stays in low power mode during
device SLEEP state.
RW
0
4
I2CHS_KEEPON
When 1, high speed internal clock is maintained during device SLEEP
state.
When 0, high speed internal clock is turned off during device SLEEP
state.
RW
0
3
VDD3_KEEPON
When 1, VDD3 SMPS high power mode is maintained during device
SLEEP state. No effect if VDD3 working mode is low power.
When 0, VDD3 SMPS low power mode is set during device SLEEP
state.
RW
0
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
Bits
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Field Name
Description
Type
Reset
2
VDD2_KEEPON
If VDD2_EN1&2 control bit = 0 (default setting):
When 1, VDD2 SMPS PWM mode is maintained during device SLEEP
state. No effect if VDD2 working mode is PFM.
When 0, VDD2 SMPS PFM mode is set during device SLEEP state.
RW
0
1
VDD1_KEEPON
If VDD1_EN1&2 control bit=0 (default setting):
When 1, VDD1 SMPS PWM mode is maintained during device SLEEP
state. No effect if VDD1 working mode is PFM.
When 0, VDD1 SMPS PFM mode is set during device SLEEP state.
RW
0
0
VIO_KEEPON
If VIO_EN1&2 control bit=0 (default setting): When 1, VIO SMPS PWM
mode is maintained during device SLEEP state. No effect if VIO working
mode is PFM.
When 0, VIO SMPS PFM mode is set during device SLEEP state.
RW
0
Table 66. SLEEP_SET_LDO_OFF_REG
Address Offset
0x43
Physical Address
Instance
Bits
4
3
2
1
0
VMMC_SETOFF
VPLL_SETOFF
5
VDIG1_SETOFF
6
VDIG2_SETOFF
7
VAUX1_SETOFF
RW
VAUX2_SETOFF
Type
VAUX33_SETOFF
Configuration Register turning-off LDO regulator during the SLEEP state of the device.
Corresponding *_KEEP_ON control bit in SLEEP_KEEP_RES_ON register should be 0 to make this
*_SET_OFF control bit effective
VDAC_SETOFF
Description
Field Name
Description
Type
Reset
7
VDAC_SETOFF
When 1, LDO regulator is turned off during device SLEEP state.
When 0, No effect
RW
0
6
VPLL_SETOFF
When 1, LDO regulator is turned off during device SLEEP state.
When 0, No effect
RW
0
5
VAUX33_SETOFF
When 1, LDO regulator is turned off during device SLEEP state.
When 0, No effect
RW
0
4
IVAUX2_SETOFF
When 1, LDO regulator is turned off during device SLEEP state.
When 0, No effect
RW
0
3
VAUX1_SETOFF
When 1, LDO regulator is turned off during device SLEEP state.
When 0, No effect
RW
0
2
VDIG2_SETOFF
When 1, LDO regulator is turned off during device SLEEP state.
When 0, No effect
RW
0
1
VDIG1_SETOFF
When 1, LDO regulator is turned off during device SLEEP state.
When 0, No effect
RW
0
0
VMMC_SETOFF
When 1, LDO regulator is turned off during device SLEEP state.
When 0, No effect
RW
0
Table 67. SLEEP_SET_RES_OFF_REG
Address Offset
0x44
Physical Address
Instance
Description
Configuration Register turning-off SMPS regulator during the SLEEP state of the device.
Corresponding *_KEEP_ON control bit in SLEEP_KEEP_RES_ON2 register should be 0 to make this
*_SET_OFF control bit effective. Supplies voltage expected after their wake-up (SLEEP to ACTIVE state
transition) can also be programmed.
Type
RW
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
77
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
Bits
3
2
1
0
VDD1_SETOFF
RSVD
4
VDD2_SETOFF
5
VDD3_SETOFF
6
DEFAULT_VOLT
7
www.ti.com
SPARE_SETOFF
SWCS046N – MARCH 2010 – REVISED APRIL 2012
VIO_SETOFF
Field Name
Description
DEFAULT_VOLT
When 1, default voltages (registers value after switch-on) will be used to
turned-on supplies during SLEEP to ACTIVE state transition.
When 0, voltages programmed before the ACTIVE to SLEEP state
transition will be used to turned-on supplies during SLEEP to ACTIVE
state transition.
Type
Reset
RW
0
RSVD
Reserved bit
RO
R returns
0s
0x0
4
SPARE_SETOFF
3
VDD3_SETOFF
Spare bit
RW
0
When 1, SMPS is turned off during device SLEEP state.
When 0, No effect.
RW
0
2
VDD2_SETOFF
When 1, SMPS is turned off during device SLEEP state.
When 0, No effect.
RW
0
1
VDD1_SETOFF
When 1, SMPS is turned off during device SLEEP state.
When 0, No effect.
RW
0
0
VIO_SETOFF
When 1, SMPS is turned off during device SLEEP state.
When 0, No effect.
RW
0
7
6:5
Table 68. EN1_LDO_ASS_REG
Address Offset
0x45
Physical Address
Instance
Description
Configuration Register setting the LDO regulators, driven by the multiplexed SCLSR_EN1 signal.
When control bit = 1, LDO regulator state is driven by the SCLSR_EN1 control signal and is also defined
though SLEEP_KEEP_LDO_ON register setting:
When SCLSR_EN1 is high the regulator is on,
When SCLSR_EN1 is low:
- the regulator is off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register
- the regulator is working in low power mode if its corresponding control bit = 1 in
SLEEP_KEEP_LDO_ON register
When control bit = 0 no effect : LDO regulator state is driven though registers programming and the
device state
Any control bit of this register set to 1 will disable the I2C SR Interface functionality
Type
RW
78
7
6
5
4
3
2
1
0
VDAC_EN1
VPLL_EN1
VAUX33_EN1
VAUX2_EN1
VAUX1_EN1
VDIG2_EN1
VDIG1_EN1
VMMC_EN1
Bits
Field Name
Description
Type
Reset
7
VDAC_EN1
Setting supply state control though SCLSR_EN1 signal
RW
0
6
VPLL_EN1
Setting supply state control though SCLSR_EN1 signal
RW
0
5
VAUX33_EN1
Setting supply state control though SCLSR_EN1 signal
RW
0
4
VAUX2_EN1
Setting supply state control though SCLSR_EN1 signal
RW
0
3
VAUX1_EN1
Setting supply state control though SCLSR_EN1 signal
RW
0
2
VDIG2_EN1
Setting supply state control though SCLSR_EN1 signal
RW
0
1
VDIG1_EN1
Setting supply state control though SCLSR_EN1 signal
RW
0
0
VMMC_EN1
Setting supply state control though SCLSR_EN1 signal
RW
0
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Table 69. EN1_SMPS_ASS_REG
Address Offset
0x46
Physical Address
Instance
Description
Configuration Register setting the SMPS Supplies driven by the multiplexed SCLSR_EN1 signal.
When control bit = 1, SMPS Supply state and voltage is driven by the SCLSR_EN1 control signal and is
also defined though SLEEP_KEEP_RES_ON register setting.
When control bit = 0 no effect : SMPS Supply state is driven though registers programming and the
device state.
Any control bit of this register set to 1 will disable the I2C SR Interface functionality
Type
RW
7
6
5
RSVD
4
3
2
1
0
SPARE_EN1
VDD3_EN1
VDD2_EN1
VDD1_EN1
VIO_EN1
Bits
Field Name
Description
Type
Reset
7:5
RSVD
Reserved bit
RW
0
4
SPARE_EN1
Spare bit
Rw
0
3
VDD3_EN1
When 1:
When SCLSR_EN1 is high the supply is on.
When SCLSR_EN1 is low and SLEEP_KEEP_RES_ON = '0' the supply
voltage is off.
When SCLSR_EN1 is low and SLEEP_KEEP_RES_ON = '1' the SMPS
is working in low power mode.
When control bit = 0 no effect: supply state is driven though registers
programming and the device state
RW
0
2
VDD2_EN1
When control bit = 1:
When SCLSR_EN1 is high the supply voltage is programmed though
VDD2_OP_REG register, and it can also be programmed off.
When SCLSR_EN1 is low the supply voltage is programmed though
VDD2_SR_REG register, and it can also be programmed off.
When SCLSR_EN1 is low and VDD2_KEEPON = 1 the SMPS is working
in low power mode, if not tuned off through VDD2_SR_REG register.
When control bit = 0 no effect: supply state is driven though registers
programming and the device state
RW
0
1
VDD1_EN1
When 1:
When SCLSR_EN1 is high the supply voltage is programmed though
VDD1_OP_REG register, and it can also be programmed off.
When SCLSR_EN1 is low the supply voltage is programmed though
VDD1_SR_REG register, and it can also be programmed off.
When SCLSR_EN1 is low and VDD1_KEEPON = 1 the SMPS is working
in low power mode, if not tuned off though VDD1_SR_REG register.
When control bit = 0 no effect: supply state is driven though registers
programming and the device state
RW
0
0
VIO_EN1
When control bit = 1, supply state is driven by the SCLSR_EN1 control
signal and is also defined though SLEEP_KEEP_RES_ON register
setting:
When SCLSR_EN1 is high the supply is on,
When SCLSR_EN1 is low:
- the supply is off (default) or the SMPS is working in low power mode if
VIO_KEEPON = 1
When control bit = 0 no effect: SMPS state is driven though registers
programming and the device state
RW
0
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
79
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
Table 70. EN2_LDO_ASS_REG
Address Offset
0x47
Physical Address
Instance
Description
Configuration Register setting the LDO regulators, driven by the multiplexed SDASR_EN2 signal.
When control bit = 1, LDO regulator state is driven by the SDASR_EN2 control signal and is also
defined though SLEEP_KEEP_LDO_ON register setting:
When SDASR_EN2 is high the regulator is on,
When SCLSR_EN2 is low:
- the regulator is off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register
- the regulator is working in low power mode if its corresponding control bit = 1 in
SLEEP_KEEP_LDO_ON register
When control bit = 0 no effect: LDO regulator state is driven though registers programming and the
device state
Any control bit of this register set to 1 will disable the I2C SR Interface functionality
Type
RW
7
6
5
4
3
2
1
0
VDAC_EN2
VPLL_EN2
VAUX33_EN2
VAUX2_EN2
VAUX1_EN2
VDIG2_EN2
VDIG1_EN2
VMMC_EN2
Bits
Field Name
Description
Type
Reset
7
VDAC_EN2
6
VPLL_EN2
Setting supply state control though SDASR_EN2 signal
RW
0
Setting supply state control though SDASR_EN2 signal
RW
5
0
VAUX33_EN2
Setting supply state control though SDASR_EN2 signal
RW
0
4
VAUX2_EN2
Setting supply state control though SDASR_EN2 signal
RW
0
3
VAUX1_EN2
Setting supply state control though SDASR_EN2 signal
RW
0
2
VDIG2_EN2
Setting supply state control though SDASR_EN2 signal
RW
0
1
VDIG1_EN2
Setting supply state control though SDASR_EN2 signal
RW
0
0
VMMC_EN2
Setting supply state control though SDASR_EN2 signal
RW
0
Table 71. EN2_SMPS_ASS_REG
Address Offset
0x48
Physical Address
Instance
Description
Configuration Register setting the SMPS Supplies driven by the multiplexed SDASR_EN2 signal.
When control bit = 1, SMPS Supply state and voltage is driven by the SDASR_EN2 control signal and is
also defined though SLEEP_KEEP_RES_ON register setting.
When control bit = 0 no effect: SMPS Supply state is driven though registers programming and the
device state
Any control bit of this register set to 1 will disable the I2C SR Interface functionality
Type
RW
7
6
5
RSVD
80
4
3
2
1
0
SPARE_EN2
VDD3_EN2
VDD2_EN2
VDD1_EN2
VIO_EN2
Bits
Field Name
Description
Type
Reset
7:5
RSVD
Reserved bit
RO
R returns
0s
0x0
4
SPARE_EN2
Spare bit
RW
0
3
VDD3_EN2
When 1:
When SDASR_EN2 is high the supply is on.
When SDASR_EN2 is low and SLEEP_KEEP_RES_ON = 0 the supply
voltage is off.
When SDASR_EN2 is low and SLEEP_KEEP_RES_ON = 1 the SMPS
is working in low power mode.
When control bit = 0 no effect: supply state is driven though registers
programming and the device state
RW
0
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Bits
Field Name
Description
Type
Reset
2
VDD2_EN2
When control bit = 1:
When SDASR_EN2 is high the supply voltage is programmed though
VDD2_OP_REG register, and it can also be programmed off.
When SDASR_EN2 is low the supply voltage is programmed though
VDD2_SR_REG register, and it can also be programmed off.
When SDASR_EN2 is low and and VDD2_KEEPON = 1 the SMPS is
working in low power mode, if not tuned off though VDD2_SR_REG
register.
When control bit = 0 no effect: supply state is driven though registers
programming and the device state
RW
0
1
VDD1_EN2
When control bit = 1:
When SDASR_EN2 is high the supply voltage is programmed though
VDD1_OP_REG register, and it can also be programmed off.
When SDASR_EN2 is low the supply voltage is programmed though
VDD1_SR_REG register, and it can also be programmed off.
When SDASR_EN2 is low and and VDD1_KEEPON = 1 the SMPS is
working in low power mode, if not tuned off though VDD1_SR_REG
register.
When control bit = 0 no effect: supply state is driven though registers
programming and the device state
RW
0
0
VIO_EN2
When control bit = 1,
supply state is driven by the SCLSR_EN2 control signal and is also
defined though SLEEP_KEEP_RES_ON register setting:
When SDASR _EN2 is high the supply is on,
When SDASR _EN2 is low :
- the supply is off (default) or the SMPS is working in low power mode if
VIO_KEEPON = 1
When control bit = 0 no effect: SMPS state is driven though registers
programming and the device state
RW
0
1
0
Table 72. RESERVED
Address Offset
0x49
Physical Address
Instance
Description
Reserved register
Type
RW
7
6
5
4
3
2
RESERVED
Bits
Field Name
Description
Type
Reset
7:0
RESERVED
Reserved bit
RW
0
1
0
Table 73. RESERVED
Address Offset
0x4A
Physical Address
Instance
Description
Reserved register
Type
RW
7
6
5
4
3
2
RESERVED
Bits
Field Name
Description
Type
Reset
7:0
RESERVED
Reserved bit
RW
0x00
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
81
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
Table 74. INT_STS_REG
Address Offset
0x50
Physical Address
Instance
Type
RW
7
6
5
4
3
2
1
0
RTC_ALARM_IT
Interrupt status register:
The interrupt status bit is set to 1 when the associated interrupt event is detected. Interrupt status bit is
cleared by writing 1.
RTC_PERIOD_IT
Description
HOTDIE_IT
PWRHOLD_IT
PWRON_LP_IT
PWRON_IT
VMBHI_IT
VMBDCH_IT
Bits
Field Name
Description
Type
Reset
7
RTC_PERIOD_IT
RTC period event interrupt status.
RW
W1 to Clr
0
6
RTC_ALARM_IT
RTC alarm event interrupt status.
RW
W1 to Clr
0
5
HOTDIE_IT
Hot die event interrupt status.
RW
W1 to Clr
0
4
PWRHOLD_IT
PWRHOLD event interrupt status.
RW
W1 to Clr
0
3
PWRON_LP_IT
PWRON Long Press event interrupt status.
RW
W1 to Clr
0
2
PWRON_IT
PWRON event interrupt status.
RW
W1 to Clr
0
1
VMBHI_IT
VBAT > VMBHI event interrupt status
RW
W1 to Clr
0
0
VMBDCH_IT
VBAT > VMBDCH event interrupt status.
Active only if Main Battery comparator VMBCH programmable threshold
is not bypassed (VMBCH_SEL[1:0] ≠ 00)
RW
W1 to Clr
0
Table 75. INT_MSK_REG
Address Offset
0x51
Physical Address
Instance
82
4
3
PWRON_LP_IT_MSK
Submit Documentation Feedback
2
1
0
VMBDCH_IT_MSK
5
VMBHI_IT_MSK
6
PWRON_IT_MSK
7
PWRHOLD_IT_MSK
RW
HOTDIE_IT_MSK
Type
RTC_ALARM_IT_MSK
Interrupt mask register:
When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT
interrupt status bit is updated.
When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is
updated.
RTC_PERIOD_IT_MSK
Description
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
Bits
SWCS046N – MARCH 2010 – REVISED APRIL 2012
Type
Reset
7
Field Name
RTC_PERIOD_IT_MS RTC period event interrupt mask.
K
Description
RW
0
6
RTC_ALARM_IT_MS
K
RTC alarm event interrupt mask.
RW
0
5
HOTDIE_IT_MSK
Hot die event interrupt mask.
RW
0
4
PWRHOLD_IT_MSK
PWRHOLD rising edge event interrupt mask.
RW
0
3
PWRON_LP_IT_MSK PWRON Long Press event interrupt mask.
RW
0
2
PWRON_IT_MSK
PWRON event interrupt mask.
RW
0
1
VMBHI_IT_MSK
VBAT > VMBHI event interrupt mask.
When 0, enable the device automatic switch on at BACKUP to OFF or
NOSUPPLY to OFF device state transition (EEPROM bit)
RW
1
0
VMBDCH_IT_MSK
VBAT < VMBDCH event interrupt status.
Active only if the main battery comparator VMBCH programmable
threshold is not bypassed (VMBCH_SEL[1:0] ≠ 00).
RW
0
Table 76. INT_STS2_REG
Address Offset
0x52
Physical Address
Instance
Description
Interrupt status register:
The interrupt status bit is set to 1 when the associated interrupt event is detected. Interrupt status bit is
cleared by writing 1.
Type
RW
7
6
5
4
3
2
Reserved
1
0
GPIO0_F_IT
GPIO0_R_IT
Bits
Field Name
Description
Type
Reset
7:2
Reserved
Reserved bit
RW
W1 to Clr
0
1
GPIO0_F_IT
GPIO_CKSYNC falling edge detection interrupt status
RW
W1 to Clr
0
0
GPIO0_R_IT
GPIO_CKSYNC rising edge detection interrupt status
RW
W1 to Clr
0
Table 77. INT_MSK2_REG
Address Offset
0x53
Physical Address
Instance
Type
RW
7
6
5
4
Reserved
Copyright © 2010–2012, Texas Instruments Incorporated
3
2
1
0
GPIO0_R_IT_MSK
Interrupt mask register:
When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT
interrupt status bit is updated.
When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is
updated.
GPIO0_F_IT_MSK
Description
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
83
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
Bits
Field Name
Description
Type
Reset
7:2
Reserved
Reserved bit
RW
0
1
GPIO0_F_IT_MSK
GPIO_CKSYNC falling edge detection interrupt mask.
RW
0
0
GPIO0_R_IT_MSK
GPIO_CKSYNC rising edge detection interrupt mask.
RW
0
Table 78. GPIO0_REG
Address Offset
0x60
Physical Address
Instance
Description
GPIO0 configuration register
Type
RW
7
6
5
Reserved
4
3
2
1
0
GPIO_DEB
GPIO_PUEN
GPIO_CFG
GPIO_STS
GPIO_SET
Bits
Field Name
Description
Type
Reset
7:5
Reserved
Reserved bit
RO
R returns
0s
0x0
4
GPIO_DEB
GPIO_CKSYNC input debouncing time configuration:
When 0, the debouncing is 91.5 µs using a 30.5 µs clock rate
When 1, the debouncing is 150 ms using a 50 ms clock rate
RW
0
3
GPIO_PUEN
GPIO_CKSYNC pad pull-up control:
1: Pull-up is enabled
0: Pull-up is disabled
RW
1
2
GPIO_CFG
Configuration of the GPIO_CKSYNC pad direction:
When 0, the pad is configured as an input
When 1, the pad is configured as an output
RW
0
1
GPIO_STS
Status of the GPIO_CKSYNC pad
RO
1
0
GPIO_SET
Value set on the GPIO output when configured in output mode
RW
0
1
0
Table 79. JTAGVERNUM_REG
Address Offset
0x80
Physical Address
Instance
Description
Silicon version number
Type
RO
7
6
5
4
3
2
Reserved
84
VERNUM
Bits
Field Name
Description
Type
Reset
7:4
Reserved
Reserved bit
RO
R returns
0s
0x0
3:0
VERNUM
Value depending on silicon version number 0000 - Revision 1.0
RO
0x0
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N – MARCH 2010 – REVISED APRIL 2012
GLOSSARY
ACRONYMS, ABBREVIATIONS, AND DEFINITIONS
ACRONYM
DEFINITION
DDR
Dual-Data Rate (memory)
ES
Engineering Sample
ESD
Electrostatic Discharge
FET
Field Effect Transistor
EPC
Embedded Power Controller
FSM
Finite State Machine
GND
Ground
GPIO
General-Purpose I/O
HBM
Human Body Model
HD
Hot-Die
HS-I2C
High-Speed I2C
2
I C
Inter-Integrated Circuit
IC
Integrated Circuit
ID
Identification
IDDQ
Quiescent supply current
IEEE
Institute of Electrical and Electronics Engineers
IR
Instruction Register
I/O
Input/Output
JEDEC
Joint Electron Device Engineering Council
JTAG
Joint Test Action Group
LBC7
Lin Bi-CMOS 7 (360 nm)
LDO
Low Drop Output voltage linear regulator
LP
Low-Power application mode
LSB
Least Significant Bit
MMC
Multimedia Card
MOSFET
Metal Oxide Semiconductor Field Effect Transistor
NVM
Nonvolatile Memory
OMAP™
Open Multimedia Application Platform™
RTC
Real-Time Clock
SMPS
Switched Mode Power Supply
SPI
Serial Peripheral Interface
POR
Power-On Reset
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
85
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N – MARCH 2010 – REVISED APRIL 2012
www.ti.com
Table 80. REVISION HISTORY
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
86
VERSION
DATE
*
03/2010
NOTES
See
(1)
.
A
05/2010
See
(2)
B
06/2010
See
(3)
C
06/2010
See
(4)
D
11/2010
See
(5)
.
.
.
.
E
01/2011
See
(6)
F
01/2011
See
(7)
G
05/2011
See
(8)
.
.
.
H
06/2011
See
(9)
I
07/2011
See
(10)
J
10/2011
See
(11)
K
10/2011
See
(12)
L
01/2012
See
(13)
M
03/2012
See
(14)
N
04/2012
See
(15)
.
Initial release
SWCS046A: Updated register tables VMMC_REG and VDAC_REG. Added register table VPLL_REG
SWCS046B: Update Absolute Maximum Ratings, Recommended Operating Conditions, I/O Pullup and Pulldown Characteristics, DigitaL
I/Os Voltage Electrical Characteristics, Power Consumption, Power References and Thresholds, Thermal Monitoring and Shutdown, 32kHz RTC Clock, VRTC LDO, VIO SMPS, VDD1 SMPS, VDD2 SMPS, VDD3 SMPS, Switch-On/-Off Sequences and Timing
SWCS046C: Associate parts; no change.
SWCS046D: Update Recommended Operating Conditions - Backup Battery, I/O Pullup and Pulldown Characteristics, Backup Battery
Charger. Update Rated output current, PMOS current limit (High-Side), NMOS current limit (Low-Side), and Conversion Efficiency for
VIO SMPS, VDD1/VDD2/VDD3 SMPS and VDIG1/VDIG2 LDO. Update Input Voltage for VIO/VDD1/VDD2 SMPS. Update DC and
Transient Load and Line Regulatio and Internal Resistance for VDIG1/VDIG2 LDO, VAUX33/VMMC LDO, VAUX1,VAUX2, LDO, and
VDAC/VPLL LDO. Update DC Load Regulation for VAUX3/VMMC/VDAC. Update Power Control Timing. Add Device SLEEP State
Control. Add SMPS Switching Synchronization. Update VIO_REG, VDD1_REG, and VDD2_REG.
SWCS046E: Manually added Thermal Pad Mechanical Data.
SWCS046F: UpdateTable 1, SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERS.
SWCS046G: Update PACKAGE DESCRIPTION, RECOMMENDED OPERATING CONDITIONS, DIGITAL I/O VOLTAGE ELECTRICAL
CHARACTERISTICS, and PWRON.
SWCS046H: Update Table 40, PUADEN_REG, Table 72, RESERVED, and Table 73, RESERVED.
SWCS046I: Update DC Output voltage VOUT in VAUX1 AND VAUX2 LDO.
SWCS046J: UpdateTable 1, SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERS.
SWCS046K: UpdateTable 1, SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERS - Add AM335x.
SWCS046L: Update Table 1, SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERS - Add AM335x with DDR2 and
AM335x with DDR3.
SWCS046M: Update STATE-MACHINE, - Update Device Sleep enable conditions control information.
SWCS046N:
(a) VIO SMPS - Update PMOS current limit (high side) conditions
(b) Table 74 - Update INT_STS_REG register - VMBHI_IT description
(c) Update Input voltage: VDIG1 AND VDIG2 LDO
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
WARNING: EXPORT NOTICE
Recipient agrees to not knowingly export or re-export, directly or
indirectly, any product or technical data (as defined by the U.S., EU, and
other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations,
received from Disclosing party under this Agreement, or any direct
product of such technology, to any destination to which such export or
re-export is restricted or prohibited by U.S. or other applicable laws,
without obtaining prior authorisation from U.S. Department of Commerce
and other competent Government authorities to the extent required by
those laws. This provision shall survive termination or expiration of this
Agreement.
According to our best knowledge of the state and end-use of this
product or technology, and in compliance with the export control
regulations of dual-use goods in force in the origin and exporting
countries, this technology is classified as follows:
US ECCN: EAR99
EU ECCN: EAR99
And may require export or re-export license for shipping it in compliance
with the applicable regulations of certain countries.
PACKAGE OPTION ADDENDUM
www.ti.com
19-May-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
(Requires Login)
TPS659101A1RSL
ACTIVE
VQFN
RSL
48
60
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TPS659101A1RSLR
ACTIVE
VQFN
RSL
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TPS659102A1RSL
ACTIVE
VQFN
RSL
48
60
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TPS659102A1RSLR
ACTIVE
VQFN
RSL
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TPS659103A1RSL
PREVIEW
VQFN
RSL
48
60
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TPS659103A1RSLR
PREVIEW
VQFN
RSL
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TPS659104A1RSL
PREVIEW
VQFN
RSL
48
60
TBD
TPS659104A1RSLR
PREVIEW
VQFN
RSL
48
2500
TBD
TPS659105A1RSL
PREVIEW
VQFN
RSL
48
60
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TPS659105A1RSLR
PREVIEW
VQFN
RSL
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TPS659106A1RSL
ACTIVE
VQFN
RSL
48
60
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TPS659106A1RSLR
ACTIVE
VQFN
RSL
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TPS659107A1RSL
PREVIEW
VQFN
RSL
48
60
TBD
TPS659107A1RSLR
PREVIEW
VQFN
RSL
48
2500
TBD
TPS659108A1RSL
ACTIVE
VQFN
RSL
48
60
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TPS659108A1RSLR
ACTIVE
VQFN
RSL
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TPS659109A1RSL
ACTIVE
VQFN
RSL
48
60
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TPS659109A1RSLR
ACTIVE
VQFN
RSL
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Addendum-Page 1
Samples
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
19-May-2012
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
TPS65910A1RSL
ACTIVE
VQFN
RSL
48
60
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TPS65910A1RSLR
ACTIVE
VQFN
RSL
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TPS65910A3A1RSL
ACTIVE
VQFN
RSL
48
60
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TPS65910A3A1RSLR
ACTIVE
VQFN
RSL
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TPS65910AA1RSL
ACTIVE
VQFN
RSL
48
60
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TPS65910AA1RSLR
ACTIVE
VQFN
RSL
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
19-May-2012
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
19-May-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS659101A1RSLR
VQFN
RSL
48
2500
330.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
TPS659102A1RSLR
VQFN
RSL
48
2500
330.0
16.4
6.3
6.3
1.5
12.0
16.0
Q2
TPS659102A1RSLR
VQFN
RSL
48
2500
330.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
TPS659106A1RSLR
VQFN
RSL
48
2500
330.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
TPS659108A1RSLR
VQFN
RSL
48
2500
330.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
TPS65910A3A1RSLR
VQFN
RSL
48
2500
330.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
TPS65910AA1RSLR
VQFN
RSL
48
2500
330.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-May-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS659101A1RSLR
VQFN
RSL
48
2500
346.0
346.0
33.0
TPS659102A1RSLR
VQFN
RSL
48
2500
346.0
346.0
33.0
TPS659102A1RSLR
VQFN
RSL
48
2500
346.0
346.0
33.0
TPS659106A1RSLR
VQFN
RSL
48
2500
346.0
346.0
33.0
TPS659108A1RSLR
VQFN
RSL
48
2500
346.0
346.0
33.0
TPS65910A3A1RSLR
VQFN
RSL
48
2500
346.0
346.0
33.0
TPS65910AA1RSLR
VQFN
RSL
48
2500
346.0
346.0
33.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Mobile Processors
www.ti.com/omap
Wireless Connectivity
www.ti.com/wirelessconnectivity
TI E2E Community Home Page
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated