TI TPS65930A2ZCHR

TPS65930/TPS65920
Integrated Power Management
\Audio Codec (TPS65930 Only)
Silicon Revision 1.2
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SWCS037G
May 2008 – Revised April 2011
TPS65930/TPS65920
SWCS037G – MAY 2008 – REVISED APRIL 2011
www.ti.com
Contents
1
2
3
4
2
........................................................................................................................ 9
1.1
Features .................................................................................................................... 10
1.2
TPS65920 and TPS65930 Device Block Diagrams ................................................................... 11
Terminal Description .......................................................................................................... 13
2.1
Ball Characteristics ........................................................................................................ 13
2.2
Signal Description ......................................................................................................... 17
Electrical Characteristics .................................................................................................... 23
3.1
Absolute Maximum Ratings .............................................................................................. 23
3.2
Minimum Voltages and Associated Currents .......................................................................... 23
3.3
Recommended Operating Conditions .................................................................................. 24
3.4
Digital I/O Electrical Characteristics ..................................................................................... 24
Power Module ................................................................................................................... 27
4.1
Power Providers ........................................................................................................... 28
4.1.1
VDD1 dc-dc Regulator ......................................................................................... 29
4.1.1.1
VDD1 dc-dc Regulator Characteristics .......................................................... 29
4.1.1.2
External Components and Application Schematics ........................................... 30
4.1.2
VDD2 dc-dc Regulator ......................................................................................... 32
4.1.2.1
VDD2 dc-dc Regulator Characteristics .......................................................... 32
4.1.2.2
External Components and Application Schematics ........................................... 33
4.1.3
VIO dc-dc Regulator ............................................................................................ 35
4.1.3.1
VIO dc-dc Regulator Characteristics ............................................................ 35
4.1.3.2
External Components and Application Schematics ........................................... 36
4.1.4
VDAC LDO Regulator .......................................................................................... 38
4.1.5
VPLL1 LDO Regulator ......................................................................................... 39
4.1.6
VMMC1 LDO Regulator ....................................................................................... 40
4.1.7
VAUX2 LDO Regulator ........................................................................................ 41
4.1.8
Output Load Conditions ........................................................................................ 42
4.1.9
Charge Pump ................................................................................................... 43
4.1.10 USB LDO Short-Circuit Protection Scheme ................................................................. 44
4.2
Power References ......................................................................................................... 45
4.3
Power Control .............................................................................................................. 45
4.3.1
Backup Battery Charger ....................................................................................... 45
4.3.2
Battery Monitoring and Threshold Detection ................................................................ 46
4.3.2.1
Power On/Power Off and Backup Conditions .................................................. 46
4.3.3
VRRTC LDO Regulator ........................................................................................ 46
4.4
Power Consumption ....................................................................................................... 47
4.5
Power Management ....................................................................................................... 49
4.5.1
Boot Modes ...................................................................................................... 49
4.5.2
Process Modes .................................................................................................. 49
4.5.2.1
MC021 Mode ....................................................................................... 49
4.5.3
Power-On Sequence ........................................................................................... 49
4.5.3.1
Timing Before Sequence_Start .................................................................. 49
4.5.3.2
Power-On Sequence .............................................................................. 51
4.5.3.3
Power On in Slave_C021 Mode ................................................................. 51
4.5.4
Power-Off Sequence ........................................................................................... 53
4.5.4.1
Power-Off Sequence .............................................................................. 53
Introduction
Contents
Copyright © 2008–2011, Texas Instruments Incorporated
TPS65930/TPS65920
SWCS037G – MAY 2008 – REVISED APRIL 2011
www.ti.com
5
6
7
8
9
10
11
.................................................................
.........................................................................................................................
5.1.1
Backup Battery ..................................................................................................
5.2
EPC .........................................................................................................................
Audio/Voice Module (TPS65930 Device Only) ........................................................................
6.1
Audio/Voice Downlink (RX) Module .....................................................................................
6.1.1
Predriver for External Class-D Amplifier .....................................................................
6.1.1.1
Predriver Output Characteristics .................................................................
6.1.1.2
External Components and Application Schematics ...........................................
6.1.2
Vibrator H-Bridge ...............................................................................................
6.1.2.1
Vibrator H-Bridge Output Characteristics .......................................................
6.1.2.2
External Components and Application Schematics ...........................................
6.1.3
Carkit Output ....................................................................................................
6.1.4
Digital Audio Filter Module ....................................................................................
6.1.5
Boost Stage .....................................................................................................
6.2
Audio Uplink (TX) Module ................................................................................................
6.2.1
Microphone Bias Module ......................................................................................
6.2.1.1
Analog Microphone Bias Module Characteristics ..............................................
6.2.1.2
Silicon Microphone Module Characteristics ....................................................
6.2.2
FM Radio/Auxiliary Input .......................................................................................
6.2.2.1
External Components .............................................................................
6.2.3
Uplink Characteristics ..........................................................................................
6.2.4
Microphone Amplification Stage ..............................................................................
6.2.5
Carkit Input ......................................................................................................
6.2.6
Digital Audio Filter Module ....................................................................................
USB Transceiver ...............................................................................................................
7.1
USB Transceiver ...........................................................................................................
7.1.1
Features .........................................................................................................
7.1.2
HS USB Port Timing ...........................................................................................
7.1.3
USB-CEA Carkit Port Timing ..................................................................................
7.1.4
PHY Electrical Characteristics ................................................................................
7.1.4.1
HS Differential Receiver ...........................................................................
7.1.4.2
HS Differential Transmitter ........................................................................
7.1.4.3
CEA/UART Driver ..................................................................................
7.1.4.4
Pullup/Pulldown Resistors ........................................................................
7.1.5
OTG Electrical Characteristics ................................................................................
7.1.5.1
OTG VBUS Electrical Characteristics ...........................................................
7.1.5.2
OTG ID Electrical Characteristics ................................................................
MADC ...............................................................................................................................
8.1
General Description .......................................................................................................
8.2
MADC Electrical Characteristics .........................................................................................
8.3
Channel Voltage Input Range ...........................................................................................
8.3.1
Sequence Conversion Time (Real-Time or Nonaborted Asynchronous) ................................
LED Drivers ......................................................................................................................
9.1
General Description .......................................................................................................
Keyboard ..........................................................................................................................
10.1 Keyboard Connection .....................................................................................................
Clock Specifications ..........................................................................................................
Real-Time Clock and Embedded Power Controller
54
5.1
54
RTC
Copyright © 2008–2011, Texas Instruments Incorporated
Contents
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57
57
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58
59
59
61
61
61
63
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81
81
82
82
83
3
TPS65930/TPS65920
SWCS037G – MAY 2008 – REVISED APRIL 2011
11.1
11.2
www.ti.com
Clock Features ............................................................................................................. 83
Input Clock Specifications ................................................................................................ 84
16
.................................................................................. 84
11.2.2 HFCLKIN ......................................................................................................... 84
11.2.3 32-kHz Input Clock ............................................................................................. 86
11.2.3.1 External Crystal Description ...................................................................... 87
11.2.3.2 External Clock Description ........................................................................ 88
11.3 Output Clock Specifications .............................................................................................. 91
11.3.1 32KCLKOUT Output Clock .................................................................................... 91
11.3.2 HFCLKOUT Output Clock ..................................................................................... 92
11.3.3 Output Clock Stabilization Time .............................................................................. 93
Timing Requirements and Switching Characteristics ............................................................. 94
12.1 Timing Parameters ........................................................................................................ 94
12.2 Target Frequencies ........................................................................................................ 95
12.3 I2C Timing .................................................................................................................. 96
12.4 Audio Interface: TDM/I2S Protocol ...................................................................................... 97
12.4.1 I2S Right- and Left-Justified Data Format ................................................................... 98
12.4.2 TDM Data Format ............................................................................................. 100
12.5 JTAG Interfaces .......................................................................................................... 101
Debouncing Time ............................................................................................................. 103
External Components ....................................................................................................... 104
TPS65920/TPS65930 Package ............................................................................................ 107
15.1 TPS65920/TPS65930 Standard Package Symbols ................................................................. 107
15.2 Package Thermal Resistance Characteristics ....................................................................... 107
15.3 Mechanical Data ......................................................................................................... 108
15.4 ESD Specifications ...................................................................................................... 109
Glossary ......................................................................................................................... 110
4
Contents
11.2.1
12
13
14
15
Clock Source Requirements
Copyright © 2008–2011, Texas Instruments Incorporated
TPS65930/TPS65920
SWCS037G – MAY 2008 – REVISED APRIL 2011
www.ti.com
List of Figures
1-1
TPS65920 Block Diagram ....................................................................................................... 12
1-2
TPS65930 Block Diagram ....................................................................................................... 12
2-1
PBGA Bottom View .............................................................................................................. 13
4-1
Power Provider Block Diagram ................................................................................................. 27
4-2
VDD1 dc-dc Regulator Efficiency .............................................................................................. 30
4-3
VDD1 dc-dc Application Schematic ............................................................................................ 31
4-4
VDD2 dc-dc Regulator Efficiency .............................................................................................. 33
4-5
VDD2 dc-dc Application Schematic ............................................................................................ 34
4-6
VIO dc-dc Regulator Efficiency ................................................................................................. 36
4-7
VIO dc-dc Application Schematic .............................................................................................. 37
4-8
Timing Before Sequence Start
4-9
Timings–Power On in OMAP3 Mode .......................................................................................... 51
.................................................................................................
50
4-10
Timings—Power On in Slave_C021 Mode .................................................................................... 52
4-11
Power-Off Sequence in Master Modes
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
7-1
7-2
7-3
7-4
7-5
8-1
9-1
10-1
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
11-11
11-12
11-13
.......................................................................................
Audio/Voice Module Block Diagram ...........................................................................................
Predriver for External Class D ..................................................................................................
Vibrator H-Bridge .................................................................................................................
Carkit Output Downlink Path Characteristics .................................................................................
Digital Audio Filter Downlink Path Characteristics ...........................................................................
Analog Microphone Pseudodifferential ........................................................................................
Analog Microphone Differential .................................................................................................
Silicon Microphone ...............................................................................................................
Audio Auxiliary Input .............................................................................................................
Uplink Amplifier ...................................................................................................................
Carkit Input Uplink Path Characteristics ......................................................................................
Digital Audio Filter Uplink Path Characteristics ..............................................................................
USB 2.0 PHY Block Diagram ...................................................................................................
USB System Application Schematic ...........................................................................................
HS-USB Interface—Transmit and Receive Modes (ULPI 8-bit) ............................................................
USB-CEA Carkit UART Data Flow .............................................................................................
USB-CEA Carkit UART Timings................................................................................................
Conversion Sequence General Timing Diagram .............................................................................
LED Driver Block Diagram ......................................................................................................
Keyboard Connection ............................................................................................................
Clock Overview ...................................................................................................................
HFCLKIN Clock Distribution ....................................................................................................
Example of Wired-OR Clock Request .........................................................................................
HFCLKIN Squared Input Clock .................................................................................................
32-kHz Oscillator Block Diagram In Master Mode With Crystal ............................................................
32-kHz Crystal Input .............................................................................................................
32-kHz Oscillator Block Diagram Without Crystal Option 1.................................................................
32-kHz Oscillator Block Diagram Without Crystal Option 2.................................................................
32-kHz Oscillator in Bypass Mode Block Diagram Without Crystal Option 3 ............................................
32-kHz Square- or Sine-Wave Input Clock ...................................................................................
32.768-kHz Clock Output Block Diagram .....................................................................................
32KCLKOUT Output Clock......................................................................................................
HFCLKOUT Output Clock .......................................................................................................
Copyright © 2008–2011, Texas Instruments Incorporated
List of Figures
53
55
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59
62
63
64
65
65
67
68
69
70
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80
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5
TPS65930/TPS65920
SWCS037G – MAY 2008 – REVISED APRIL 2011
www.ti.com
11-14
32KCLKOUT and HFCLKOUT Clock Stabilization Time .................................................................... 93
11-15
...........................................................................................................
I C Interface—Transmit and Receive in Slave Mode ........................................................................
I2S Interface—I2S Master ModeI ..............................................................................................
I2S Interface—I2S Slave Mode.................................................................................................
TDM Interface—TDM Master Mode ..........................................................................................
JTAG Interface Timing .........................................................................................................
Debouncing Sequence Chronogram Example ..............................................................................
Printed Device Reference .....................................................................................................
TPS65920/TPS65930 Mechanical Package Bottom View ................................................................
Ball Size ..........................................................................................................................
12-1
12-2
12-3
12-4
12-5
13-1
15-1
15-2
15-3
6
HFCLKOUT Behavior
2
List of Figures
93
96
98
98
100
102
103
107
108
108
Copyright © 2008–2011, Texas Instruments Incorporated
TPS65930/TPS65920
SWCS037G – MAY 2008 – REVISED APRIL 2011
www.ti.com
List of Tables
2-1
Ball Characteristics ............................................................................................................... 13
2-2
Signal Description ................................................................................................................ 17
3-1
Absolute Maximum Ratings ..................................................................................................... 23
3-2
VBAT Minimum Required Per VBAT Ball and Associated Maximum Current
3-3
3-4
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
5-1
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
...........................................
Recommended Operating Maximum Ratings ................................................................................
Digital I/O Electrical Characteristics ...........................................................................................
Summary of the Power Providers ..............................................................................................
Part Names With Corresponding VDD1 Current Support ...................................................................
VDD1 dc-dc Regulator Characteristics ........................................................................................
VDD2 dc-dc Regulator Characteristics ........................................................................................
VIO dc-dc Regulator Characteristics...........................................................................................
VDAC LDO Regulator Characteristics .........................................................................................
VPLL1 LDO Regulator Characteristics ........................................................................................
VMMC1 LDO Regulator Characteristics.......................................................................................
VAUX2 LDO Regulator Characteristics .......................................................................................
Output Load Conditions .........................................................................................................
Charge Pump Output Load Conditions ........................................................................................
Voltage Reference Characteristics .............................................................................................
Backup Battery Charger Characteristics ......................................................................................
Battery Threshold Levels ........................................................................................................
VRRTC LDO Regulator Characteristics .......................................................................................
Power Consumption .............................................................................................................
Regulator State Depending on Use Case .....................................................................................
BOOT Mode Description ........................................................................................................
MC021 Mode......................................................................................................................
System States ....................................................................................................................
Predriver Output Characteristics ...............................................................................................
Vibrator H-Bridge Output Characteristics .....................................................................................
USB-CEA Carkit Audio Downlink Electrical Characteristics ................................................................
Digital Audio Filter RX Electrical Characteristics .............................................................................
Boost Electrical Characteristics Versus FS Frequency (FS ≤ 22.05 kHz) .................................................
Boost Electrical Characteristics Versus FS Frequency (FS ≥ 24 kHz) .....................................................
Analog Microphone Bias Module Characteristics With Bias Resistor .....................................................
Analog Microphone Bias Module Characteristics With Bias Resistor .....................................................
Silicon Microphone Module Characteristics ...................................................................................
Uplink Characteristics ............................................................................................................
USB-CEA Carkit Audio Uplink Electrical Characteristics....................................................................
Digital Audio Filter TX Electrical Characteristics .............................................................................
HS-USB Interface Timing Requirements ......................................................................................
HS-USB Interface Switching Requirements ..................................................................................
USB-CEA Carkit Interface Timing Parameters ...............................................................................
USB-CEA Carkit UART Timings................................................................................................
HS Differential Receiver .........................................................................................................
HS Differential Transmitter ......................................................................................................
CEA/UART Driver ................................................................................................................
Pullup/Pulldown Resistors.......................................................................................................
OTG VBUS Electrical Characteristics .........................................................................................
Copyright © 2008–2011, Texas Instruments Incorporated
List of Tables
23
24
24
28
29
29
32
35
38
39
40
41
42
43
45
45
46
46
47
48
49
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58
59
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60
61
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64
65
67
68
71
71
72
73
74
74
75
75
76
7
TPS65930/TPS65920
SWCS037G – MAY 2008 – REVISED APRIL 2011
www.ti.com
7-10
OTG ID Electrical Characteristics .............................................................................................. 76
8-1
MADC Electrical Characteristics
8-2
8-3
9-1
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
11-11
11-12
12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
12-9
12-10
13-1
14-1
15-1
15-2
15-3
8
...............................................................................................
Analog Input Voltage Range ....................................................................................................
Sequence Conversion Timing Characteristics ................................................................................
LED Driver Electrical Characteristics ..........................................................................................
TPS65920/TPS65930 Input Clock Source Requirements ..................................................................
HFCLKIN Input Clock Electrical Characteristics .............................................................................
HFCLKIN Square Input Clock Timing Requirements with Slicer in Bypass ..............................................
Crystal Electrical Characteristics ...............................................................................................
Base Oscillator Switching Characteristics.....................................................................................
32-kHz Crystal Input Clock Timing Requirements ...........................................................................
32-kHz Input Square- or Sine-Wave Clock Source Electrical Characteristics............................................
32-kHz Square-Wave Input Clock Source Timing Requirements ..........................................................
32KCLKOUT Output Clock Electrical Characteristics .......................................................................
32KCLKOUT Output Clock Switching Characteristics.......................................................................
HFCLKOUT Output Clock Electrical Characteristics ........................................................................
HFCLKOUT Output Clock Switching Characteristics ........................................................................
Timing Parameters ...............................................................................................................
TPS65920/TPS65930 Interface Target Frequencies ........................................................................
I2C Interface—Timing Requirements ..........................................................................................
I2C Interface—Switching Requirements ......................................................................................
I2S Interface—Timing Requirements ..........................................................................................
I2S Interface—Switching Characteristics......................................................................................
TDM Interface Master Mode—Timing Requirements ......................................................................
TDM Interface Master Mode—Switching Characteristics .................................................................
JTAG Interface—Timing Requirements ......................................................................................
JTAG Interface—Switching Characteristics .................................................................................
Debouncing ......................................................................................................................
TPS65920/TPS65930 External Components ...............................................................................
TPS65920/TPS65930 Nomenclature Description ..........................................................................
TPS65920 Thermal Resistance Characteristics ............................................................................
TPS65930 Thermal Resistance Characteristics ............................................................................
List of Tables
78
79
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81
84
86
86
87
88
88
90
90
92
92
92
92
94
95
96
97
99
99
101
101
102
102
103
104
107
107
107
Copyright © 2008–2011, Texas Instruments Incorporated
TPS65930/TPS65920
SWCS037G – MAY 2008 – REVISED APRIL 2011
www.ti.com
Integrated Power Management
\Audio Codec (TPS65930 Only)
Check for Samples: TPS65930/TPS65920
1
Introduction
The TPS65920/TPS65930 devices are power-management ICs for OMAP™ and other mobile
applications. The devices include power-management, a universal serial bus (USB) high-speed (HS)
transceiver, light -emitting diode (LED) drivers, an analog-to-digital converter (ADC), a real-time clock
(RTC), and embedded power control (EPC). In addition, the TPS65930 includes a full audio codec with
two digital-to-analog converters (DACs) and two ADCs to implement dual voice channels, and a stereo
downlink channel that can play all standard audio sample rates through a multiple format inter-integrated
sound (I2S™)/time division multiplexing (TDM) interface.
These optimized devices support the power and peripheral requirements of the OMAP application
processors. The power portion of the devices contains three buck converters, two controllable by a
dedicated SmartReflex™ class-3 interface, multiple low dropout (LDO) regulators, an EPC to manage the
power sequencing requirements of OMAP, and an RTC and backup module. The RTC can be powered by
a backup battery when the main supply is not present, and the devices include a coin-cell charger to
recharge the backup battery as needed.
The USB module provides a HS 2.0 OTG transceiver suitable for direct connection to the OMAP UTMI+
low pin interface (ULPI), with an integrated charge pump and full support for the carkit CEA-936A
specification. An ADC is provided for monitoring signals, such as supply voltage, entering the device, and
two additional external ADC inputs are provided for system use.
The devices provide driver circuitry to power two LED circuits that can illuminate a panel or provide user
indicators. The drivers also provide pulse width modulation (PWM) circuits to control the illumination levels
of the LEDs. A keypad interface implements a built-in scanning algorithm to decode hardware-based key
presses and reduce software use, with multiple additional general-purpose input/output devices (GPIOs)
that can be used as interrupts when configured as inputs.
This TPS65920/TPS65930 data manual presents the electrical and mechanical specifications for the
TPS65920 and TPS65930 devices
. It covers the following topics:
• TPS65920/TPS65930 terminals: Assignment, multiplexing, electrical characteristics, and functional
description (see Section 2, Terminal Description)
• Electrical characteristic requirements: Maximum and recommended operating conditions, digital
input/output (I/O) characteristics (see Section 3, Electrical Characteristics)
• Power module: Power provider, power references, power control, power consumption, and power
management, with the on and off sequence (see Section 4, Power Module)
• RTC and EPC (see Section 5, Real-Time Clock and Embedded Power Controller)
• Audio/voice module (TPS65930 device only): Electrical characteristics and application schematics for
the downlink and uplink paths (see Section 6, Audio/Voice Module (TPS65930 Device Only))
• Various modules: USB transceiver, monitoring analog-to-digital converter (MADC), LED drivers, and
keyboard (see Section 8, MADC, Section 9, LED Driver, and Section 10, Keyboard)
• Clock specifications: Clock slicer; input and output clocks (see Section 11, Clock Specifications)
• Timing requirements and switching characteristics (ac timings) of the interfaces (see Section 12,
Timing Requirements and Switching Characteristics)
• Debouncing time (see Section 13, Debouncing Time)
• External components for the application schematics (see Section 14, External Components)
• Thermal resistance characteristics, device nomenclature, and mechanical data about the available
packaging (see Section 15, TPS65920/TPS65930 Package
)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2011, Texas Instruments Incorporated
TPS65930/TPS65920
SWCS037G – MAY 2008 – REVISED APRIL 2011
•
1.1
1
www.ti.com
Glossary of acronyms and abbreviations used in this data manual (see Section 16, Glossary)
Features
The TPS65930 and TPS65920 devices offer the following features:
• Power:
– Three efficient stepdown converters
– Four external linear LDOs for clocks and peripherals
– SmartReflex dynamic voltage management
• Audio (TPS65930 device only):
– Differential input main microphones
– Mono auxiliary/FM input
– External predrivers for class D (stereo)
– TDM interface
– Automatic level control (ALC)
– Digital and analog mixing
– 16-bit linear audio stereo DAC (96, 48, 44.1, and 32 kHz and derivatives)
– 16-bit linear audio stereo ADC (48, 44.1, and 32 kHz and derivatives)
– Carkit
• USB:
– USB 2.0 on-the-go (OTG)-compliant HS transceivers
– 12-bit universal transceiver macro interface ULPI
– USB power supply (5-V charge pump for VBUS)
– Consumer Electronics Association (CEA)-2011: OTG transceiver interface specification
– CEA-936A: Mini-USB analog carkit specification
• Additional Features:
– LED driver circuit for two external LEDs
– Two external 10-bit MADC inputs
– Real-time clock (RTC) and retention modules
– HS I2C serial control
– Thermal shutdown and hot-die detection
– Keypad Interface (up to 6 × 6)
– External vibrator control
– 15 GPIOs
– 0.65 mm pitch, 139 pin, 10 × 10 mm package
• Charger:
– Backup battery charger
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
10
Introduction
Copyright © 2008–2011, Texas Instruments Incorporated
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TPS65930/TPS65920
SWCS037G – MAY 2008 – REVISED APRIL 2011
www.ti.com
1.2
TPS65920 and TPS65930 Device Block Diagrams
TPS65920
Interface subchip (D)
Digital signal(s)
Analog signal(s)
PIH
I2C A pad
Clock
generator
I2C B pad
TAP
OCP
Clk In/Out
Card Det1
GPIO pad
GPIO
SIH
Card Det2
TAP
SIH_INT
TAP
Clocks
OCP
OCP SR
TAP
OCP
Clocks
Clocks
SIH_INT
OCP
PMC slave
Smart
Reflex
RFIDEN
Vibrator
control (D)
Clock slicer
Power control
(BBS-backup
VRRTC-UVLO)
USB power
supply
USB subchip (A-D)
ULPI(12)
UART(2)
BERCLK
BERDATA
Auxiliary subchip (A-D)
Power digital
Keypad
(D)
Power analog
RTC
32 kHz
TAP
Shundan
RTC
Clocks
SIH
OCP
PMC master
SIH_INT
SIH_INT
OTG
module
USB 2.0
transceiver
USB
digital
(ULPI
regist
ers,
interr
upts,
Thermal monitor
system
MADC
digital
state-machine
MADC analog
(SAR-Vref)
MADCTOP
Rc oscillator
LEDTOP
Power provider
(LDOs-DcDcs)
Power references
(Vref-Iref-bandgap)
LED digital
LED analog
Power subchip (A-D)
LedSync
Figure 1-1. TPS65920 Block Diagram
Introduction
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TPS65930
Digital signal(s)
Interface subchip (D)
Audio
PLL
I2C A pad
PIH
AUDIO
analog
Audio RX amplifiers
Mic amplifiers
Analog volume control
D/A converters
A/D converters
Differential vibrator
Carkit preamplifiers
Analog signal(s)
Analog and
mic bias
Clocks
Clock
generator
I2C B pad
Clk In/
Out
GPIO
pad
TAP
OCP
Wrapper
digital
Card Det1
GPIO
SIH
Audio filters
(RX and TX paths)
and
vibrator control
TDM/I2S
interface
TDM
Card Det2
AUDIO digital
TAP
Audio subchip (A-D)
TAP
Clocks
OCP
OCP SR
SIH_INT
TAP
TAP
OCP
Clocks
Clocks
SIH_INT
OCP
RFIDEN
Vibrator
control (D)
PMC slave
Smart
Reflex
Clock slicer
Power control
(BBS-backup
VRRTC-UVLO)
USB power
supply
USB subchip (A-D)
ULPI(12)
UART(2)
BERCLK
BERDATA
Auxiliary subchip (A-D)
Power digital
Keypad
(D)
Power analog
RTC
32 kHz
TAP
Shundan
RTC
Clocks
SIH
OCP
PMC master
SIH_INT
SIH_INT
USB
digital
ULPI/
registers
interrupts
CEA and
carkit
Analog
carkit
interfaces
OTG
module
USB 2.0
transceiver
Thermal monitor
system
MADC
digital
state-machine
MADC analog
(SAR-Vref)
MADCTOP
Rc oscillator
LEDTOP
Power provider
(LDOs-DcDcs)
Power references
(Vref-Iref-bandgap)
LED digital
LED analog
Power subchip (A-D)
LedSync
037-002
Figure 1-2. TPS65930 Block Diagram
12
Introduction
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2
Terminal Description
Figure 2-1 shows the ball locations for the 139 -ball plastic ball grid array (PBGA) package. Use this array
with Table 2-1 to locate signal names and ball grid numbers.
037-003
Figure 2-1. PBGA Bottom View
2.1
Ball Characteristics
Table 2-1 describes the terminal characteristics and the signals multiplexed on each pin. The following list
describes the table column headers:
1. Ball: Ball number(s) associated with each signal(s)
2. Pin Name: The names of all the signals that are multiplexed on each ball
3. A/D: Analog or digital signal
4. Type: The terminal type when a particular signal is multiplexed on the terminal:
– I = Input
– O = Output
5. Reference Level: See the power module chapter for values.
6. PU/PD: Denotes the presence of an internal pullup or pulldown. Pullups and pulldowns can be enabled
or disabled by software.
7. Buffer Strength: Drive strength of the associated output buffer
Table 2-1. Ball Characteristics
TPS65920
Ball[1]
TPS65930
Ball[1]
H2
H2
F2
F2
M5
A/D
[3]
Type[4]
ADCIN0
A
I/O
VINTANA1.OUT
ADCIN2
A
I
VINTANA2.OUT
M5
PCHGAC
A
I
VACCHARGER
N1
N1
VPRECH
A
O
VPRECH
N5
N5
VBAT
A
Power
VBAT
GPIO0/CD1
D
I/O
IO_1P8
JTAG.TDO
D
I/O
IO_1P8
F7
Pin
Name[2]
Reference Level
RL[5]
F7
PU[6] (kΩ)
PD[6] (kΩ)
Min
Typ
Max
Min
Typ
Max
75
100
202
59
100
144
Buffer
Strength
(mA)[7]
8
8
Terminal Description
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Table 2-1. Ball Characteristics (continued)
TPS65920
Ball[1]
TPS65930
Ball[1]
E7
E7
P2
Pin
Name[2]
Reference Level
RL[5]
L5
J7
Buffer
Strength
(mA)[7]
GPIO1
D
I/O
IO_1P8
JTAG.TMS
D
I
IO_1P8
GPIO2
D
I/O
IO_1P8
TEST1
D
I/O
IO_1P8
GPIO15
D
I/O
IO_1P8
TEST2
D
I/O
IO_1P8
GPIO6
D
I/O
IO_1P8
PWM0
D
O
IO_1P8
TEST3
D
I/O
IO_1P8
2
GPIO7
D
I/O
IO_1P8
2
VIBRA.SYNC
D
I
IO_1P8
PWM1
D
O
IO_1P8
TEST4
D
I/O
IO_1P8
P13
L5
PD[6] (kΩ)
Type[4]
P2
P13
PU[6] (kΩ)
A/D
[3]
Min
Typ
Max
Min
Typ
Max
75
100
202
59
100
144
156
220
450
59
100
144
2
2
2
2
156
J7
220
450
59
100
144
2
2
75
75
100
100
202
202
59
59
100
100
144
4
144
4
2
D8
D8
SYSEN
D
Open drain/I
IO_1P8
A4
A4
CLKEN
D
O
IO_1P8
B13
B13
CLKREQ
D
I
IO_1P8
C10
C10
INT1
D
O
IO_1P8
2
C8
C8
NRESPWRON
D
O
IO_1P8
2
B9
B9
NRESWARM
D
I
IO_1P8
2
D10
D10
PWRON
D
I
VBAT
G5
G5
NSLEEP1
D
I
IO_1P8
E10
E10
CLK256FS (1)
D
O
IO_1P8
E4
E4
VMODE1
D
I
IO_1P8
E8
E8
BOOT0
A/D
I/O
VBAT
D7
D7
BOOT1
A/D
I/O
VBAT
B8
B8
REGEN
D
Open drain
VBAT
H4
H4
MSECURE
D
I
IO_1P8
L13
L13
VREF
A
Power
VREF
A
Power
ground
(GND)
GND
I2C.SR.SDA
D
I/O
IO_1P8
VMODE2
D
I
IO_1P8
I2C.SR.SCL
D
I/O
K13
K13
B3
B3
AGND
4.7
7.35
10
2
2
60
100
146
2
5.5
8
12
2
2.5
3.4
12
IO_1P8
2.5
3.4
12
N.C.
C5
C3
C3
I2C.CNTL.SDA
D
I/O
IO_1P8
2.5
3.4
12
B4
B4
I2C.CNTL.SCL
D
I
IO_1P8
2.5
3.4
12
See
(2)
H3
I2S.CLK
D
I/O
IO_1P8
2
See
(2)
K2
I2S.SYNC
D
I/O
IO_1P8
2
See
(2)
K4
I2S.DIN
D
I
IO_1P8
2
See
(2)
K3
I2S.DOUT
D
O
IO_1P8
2
See
(2)
D1
MIC.MAIN.P
A
I
MICBIAS1.OUT
See
(2)
E1
MIC.MAIN.M
A
I
MICBIAS1.OUT
A10
VBAT.RIGHT
A
Power
VBAT
PreDriv.LEFT
A
O
VINTANA2.OUT
VMID
A
Power
VINTANA2.OUT
PreDriv.RIGHT
A
O
VINTANA2.OUT
ADCIN7
A
I
VINTANA2.OUT
AUXR
A
I
VINTANA2.OUT
MICBIAS1.OUT
A
Power
VINTANA2.OUT
VMIC1.OUT
A
Power
VINTANA2.OUT
Power GND
GND
A10
See
(2)
See
(2)
See
See
See
(1)
(2)
14
2
C5
(2)
(2)
(2)
A7
A8
G1
E2
D2
MICBIAS.GND
To avoid reflection on this pin as a result of impedance mismatch, a serial resistance of 33 Ω must be added. This clock output is
available in TPS65920 also. Can be used as a clock source, if required.
Balls A7, A8, D1, D2, E1, E2, G1, H3, K2, K3, and K4 are present on TPS65920 package. However, there is no function associated with
these pins. These can be left floating.
Terminal Description
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Table 2-1. Ball Characteristics (continued)
TPS65920
Ball[1]
TPS65930
Ball[1]
G2
G2
L7
L7
N14
Pin
Name[2]
A/D
[3]
Type[4]
Reference Level
RL[5]
AVSS1
A
Power GND
GND
AVSS2
A
Power GND
GND
N14
AVSS3
A
Power GND
GND
C7
C7
AVSS4
A
Power GND
GND
M10
M10
32KCLKOUT
D
O
IO_1P8
PU[6] (kΩ)
Min
Typ
PD[6] (kΩ)
Max
Min
Typ
Max
Buffer
Strength
(mA)[7]
L14
L14
32KXIN
A
I
IO_1P8
K14
K14
32KXOUT
A
O
IO_1P8
A11
A11
HFCLKIN
A
I
IO_1P8
M11
M11
HFCLKOUT
D
O
IO_1P8
P8
P8
VBUS
A
Power
VBUS
N10
N10
DP/UART3.RXD
A
I/O
VBUS
2
P10
P10
DN/UART3.TXD
A
I/O
VBUS
2
G6
G6
ID
A
I/O
VBUS
2
K11
K11
UCLK
D
I
IO_1P8
16
STP
D
I
IO_1P8
H12
H12
GPIO9
D
I/O
IO_1P8
2
DIR
D
O
IO_1P8
16
GPIO10
D
I/O
IO_1P8
2
NXT
D
O
IO_1P8
16
GPIO11
D
I/O
IO_1P8
2
DATA0
D
I/O
IO_1P8
16
UART4.TXD
D
I
IO_1P8
DATA1
D
I/O
IO_1P8
UART4.RXD
D
O
IO_1P8
2
DATA2
D
I/O
IO_1P8
16
UART4.RTSI
D
I
IO_1P8
DATA3
D
I/O
IO_1P8
UART4.CTSO
D
O
IO_1P8
GPIO12
D
I/O
IO_1P8
DATA4
D
I/O
IO_1P8
GPIO14
D
I/O
IO_1P8
2
DATA5
D
I/O
IO_1P8
16
GPIO3
D
I/O
IO_1P8
2
DATA6
D
I/O
IO_1P8
16
GPIO4
D
I/O
IO_1P8
2
DATA7
D
I/O
IO_1P8
16
GPIO5
D
I/O
IO_1P8
A/D
I
VBAT
H11
J8
L10
K10
G11
G10
E12
G9
G12
E11
P14
H11
75
J8
75
100
100
202
202
202
59
59
59
100
100
100
144
144
144
16
K10
G11
G10
E12
G9
16
60
100
140
60
100
140
75
100
202
59
100
144
75
100
202
59
100
144
16
G12
75
E11
75
P14
TEST.RESET
P1
TESTV1
A
I/O
VBAT
A14
TESTV2
A
I/O
VINTANA2.OUT
A1
A1
TEST
D
I
IO_1P8
A13
JTAG.TDI/
BERDATA
D
I
IO_1P8
B14
JTAG.TCK/
BERCLK
D
I
IO_1P8
VBAT/VBUS
P7
P7
CP.IN
A
Power
N7
N7
CP.CAPP
A
O
CP.CAPP
N6
N6
CP.CAPM
A
O
CP.CAPM
P5
P5
CP.GND
A
Power GND
GND
N9
N9
VBAT.USB
A
Power
VBAT
M8
M8
VUSB.3P1
A
Power
VUSB.3P1
L1
L1
VAUX12S.IN
A
Power
VBAT
N2
N2
VAUX2.OUT
A
Power
VAUX2.OUT
H14
H14
VPLLA3R.IN
A
Power
VBAT
K12
K12
VRTC.OUT
A
Power
VRTC.OUT
16
16
75
P1
B14
100
L10
A14
A13
16
75
100
100
100
202
202
202
59
59
100
100
144
144
59
100
144
30
50
70
60
100
146
2
Terminal Description
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Table 2-1. Ball Characteristics (continued)
TPS65920
Ball[1]
TPS65930
Ball[1]
G14
G14
A2
A2
B1
A/D
[3]
Type[4]
VPLL1.OUT
A
Power
VMMC1.IN
A
Power
VBAT
B1
VMMC1.OUT
A
Power
VMMC1.OUT
M7
M7
VINTUSB1P5.
OUT
A
Power
VINTUSB1P5.OUT
N8
N8
VINTUSB1P8.
OUT
A
Power
VINTUSB1P8.OUT
K1
K1
VDAC.IN
A
Power
VBAT
L2
L2
VDAC.OUT
A
Power
VDAC.OUT
H13
H13
VINT.IN
A
Power
VBAT
H1
H1
VINTANA1.OUT
A
Power
VINTANA1.OUT
Reference Level
RL[5]
J2
J2
VINTANA2.OUT
A
Power
VINTANA2.OUT
A5
VINTANA2.OUT
A
Power
VINTANA2.OUT
J13
J13
VINTDIG.OUT
A
Power
VINTDIG.OUT
D13
D13
VDD1.IN
A
Power
VBAT
D12
D12
VDD1.IN
A
Power
VBAT
D14
D14
VDD1.IN
A
Power
VBAT
C11
C11
VDD1.SW
A
O
VBAT
C12
C12
VDD1.SW
A
O
VBAT
C13
C13
VDD1.SW
A
O
VBAT
E14
E14
VDD1.FB
A
I
A12
A12
VDD1.GND
A
Power GND
GND
B11
B11
VDD1.GND
A
Power GND
GND
B12
B12
VDD1.GND
A
Power GND
GND
M13
M13
VDD2.IN
A
Power
VBAT
M12
M12
VDD2.IN
A
Power
VBAT
N13
N13
VDD2.FB
A
I
N11
N11
VDD2.SW
A
O
VBAT
P11
P11
VDD2.SW
A
O
VBAT
N12
N12
VDD2.GND
A
Power GND
GND
P12
P12
VDD2.GND
A
Power GND
GND
M2
M2
VIO.IN
A
Power
VBAT
M3
M3
VIO.IN
A
Power
VBAT
M4
M4
VIO.FB
A
I
N4
N4
VIO.SW
A
O
VBAT
P4
P4
VIO.SW
A
O
VBAT
N3
N3
VIO.GND
A
Power GND
GND
P3
P3
VIO.GND
A
Power GND
GND
H9
H9
BKBAT
A
Power
VBACK
B7
B7
IO.1P8
A
Power
IO_1P8
H10
H10
DGND
A
Power GND
GND
F13
F13
LEDGND
A
Power GND
GND
GPIO13
D
I/O
IO_1P8
LEDSYNC
D
I
IO_1P8
LEDA
A
Open drain
VBAT
VIBRA.P
A
Open drain
VBAT
LEDB
A
Open drain
VBAT
VIBRA.M
A
Open drain
VBAT
E13
G13
PU[6] (kΩ)
PD[6] (kΩ)
Min
Typ
Max
Min
Typ
Max
75
100
202
59
100
144
8
10
12
Buffer
Strength
(mA)[7]
VPLL1.OUT
A5
B10
16
Pin
Name[2]
B10
E13
G13
G4
G4
KPD.C0
D
Open drain
IO_1P8
G3
G3
KPD.C1
D
Open drain
IO_1P8
E5
E5
KPD.C2
D
Open drain
IO_1P8
B2
B2
KPD.C3
D
Open drain
IO_1P8
E3
E3
KPD.C4
D
Open drain
IO_1P8
D5
D5
KPD.C5
D
Open drain
IO_1P8
K7
K7
KPD.R0
D
I
IO_1P8
Terminal Description
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Table 2-1. Ball Characteristics (continued)
TPS65920
Ball[1]
TPS65930
Ball[1]
H5
H5
K5
K5
H6
A/D
[3]
Type[4]
KPD.R1
D
KPD.R2
D
H6
KPD.R3
K8
K8
L8
L8
2.2
Pin
Name[2]
PU[6] (kΩ)
PD[6] (kΩ)
Reference Level
RL[5]
Min
Typ
Max
I
IO_1P8
8
10
12
I
IO_1P8
8
10
12
D
I
IO_1P8
8
10
12
KPD.R4
D
I
IO_1P8
8
10
12
KPD.R5
D
I
IO_1P8
8
10
12
Min
Typ
Max
Buffer
Strength
(mA)[7]
Signal Description
Table 2-2 describes the signals on the TPS65920 and TPS65930 devices; some signals are available on
multiple pins.
Table 2-2. Signal Description
Module
ADC
Charger
GPIOs/
JTAG
Signal
Name
Description
Type
TPS65920
Ball
TPS65930
Ball
Default Configuration After Reset
Released
Signal
Internal
Pull or
Not
Type
Features
Not Used (1)
ADCIN0
Battery type
I/O
H2
H2
ADCIN0
ADCIN2
General-purpose ADC input
I
F2
F2
ADCIN2
I
GND
PCHGAC
AC precharge sense signal. Also
used for EEPROM.
I
M5
M5
PCHGAC
I
GND
VPRECH
Precharge regulator output
O
N1
N1
VPRECH
O
Cap to GND(2)
VBAT
Battery voltage sensing
Power
N5
N5
VBAT
Power
VBAT
GPIO0/CD1
GPIO0/card detection 1
I/O
JTAG.TDO
JTAG test data output
I/O
F7
F7
GPIO0
I
PD
Floating
GPIO1
GPIO1
I/O
JTAG.TMS
JTAG test mode state
E7
E7
GPIO1
I
PD
Floating
GPIO2
GPIO2
I/O
TEST1
TEST1 pin used in test mode
only
I/O
P2
P2
GPIO2
I
PD
Floating
GPIO15
GPIO15
I/O
TEST2
TEST2 pin used in test mode
only
I/O
P13
P13
GPIO15
I
PD
Floating
GPIO6
GPIO6
I/O
PWM0
Pulse width driver 0
O
L5
L5
GPIO6
I
PD
Floating
TEST3
TEST3 pin used in test mode
only (controlled by JTAG)
I/O
GPIO7
GPIO7
I/O
VIBRA.SYNC
Vibrator on-off synchronization
I
PWM1
Pulse width driver
O
J7
J7
GPIO7
I
PD
Floating
TEST4
TEST4 pin used in test mode
only (controlled by JTAG)
I/O
I
GND
Terminal Description
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Table 2-2. Signal Description (continued)
Signal
Name
Module
CONTROL
Description
Type
Open
drain/I
2
IC
Smart
Reflex
I2C
TDM
ANA.MIC
HandsFree
AUX Input
18
D8
D8
Default Configuration After Reset
Released
Type
Internal
Pull or
Not
SYSEN
OD
PU
Signal
Features
Not Used (1)
System enable output
CLKEN
Clock enable
O
A4
A4
CLKEN
O
CLKREQ
Clock request
I
B13
B13
CLKREQ
I
INT1
Output interrupt line 1
O
C10
C10
INT1
O
Floating
NRESPWRON
Output control the NRESPWRON
of the application processor
O
C8
C8
NRESPWRON
O
Floating
NRESWARM
Input; detect user action on the
reset button
I
B9
B9
NRESWARM
I
GND
PWRON
Input; detect a control command
to start or stop the system
I
D10
D10
PWRON
I
VBAT
NSLEEP1
Sleep request from device 1
Floating
Floating
PD
GND
I
G5
G5
NSLEEP1
I
GND
O
E10
E10
CLK256FS
O
Floating
E4
E4
VMODE1
I
GND
VMODE1
Digital voltage scaling linked with
VDD1
I
BOOT0
Boot pin 0
I
E8
E8
BOOT0
I
PD
N/A
BOOT1
Boot pin 1
I
D7
D7
BOOT1
I
PD
N/A
Open
drain
B8
B8
REGEN
OD
PU
Floating
I
H4
H4
MSECURE
L13
L13
REGEN
Enable signal for external LDO
MSECURE
Security and digital rights
management
VREF
Reference voltage
Power
AGND
Analog ground for reference
voltage
Power
GND
N.C.
Not connected
I2C.SR.SDA
SmartReflex I2C data
VMODE2
Digital voltage scaling linked with
VDD2
I2C.SR.SCL
SmartReflex I2C data
I/O
I2C.CNTL.SDA
General-purpose I2C data
I2C.CNTL.SCL
General-purpose I2C clock
I2S.CLK
Clock signal (audio port)
I2S.SYNC
Synchronization signal (audio
port)
I2S.DIN
I2S.DOUT
I
N/A
VREF
Power
N/A
Power
GND
GND
K13
K13
AGND
B3
B3
Signal not
functional(3)
C5
C5
VMODE2
I/O
C3
C3
I2C.CNTL.SDA
I/O
PU
I/O
B4
B4
I2C.CNTL.SCL
I/O
PU
I/O
H3
I2S.CLK
I/O
Floating
I/O
K2
I2S.SYNC
I/O
Floating
Data receive (audio port)
I
K4
I2S.DIN
I
GND
Data transmit (audio port)
O
K3
I2S.DOUT
O
Floating
MIC.MAIN.P
Main microphone left input (P)
I
D1
MIC.MAIN.P
I
Cap to GND
MIC.MAIN.M
Main microphone left input (M)
I
E1
MIC.MAIN.M
I
Cap to GND
VBAT.RIGHT
Battery voltage input
A10
VBAT.RIGHT
Power
VBAT
PreDriv.LEFT
Predriver output left P for
external class-D amplifier
A7
VMID
Power
Floating
A8
ADCIN7
I
GND
G1
AUXR
I
Cap to GND
I/O
Floating
I
Power
O
VMID
Headset
TPS65930
Ball
SYSEN
CLK256FS
VREF
TPS65920
Ball
A10
I
GND
N/A
N/A
Power
PreDriv.RIGHT
Predriver output right P for
external class-D amplifier
O
ADCIN7
General-purpose ADC input 7
I
AUXR
Auxiliary audio input right
I
Terminal Description
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Table 2-2. Signal Description (continued)
Signal
Name
Module
VMIC
BIAS
Description
Type
MICBIAS1.
OUT
Analog microphone bias 1
Power
VMIC1.OUT
Digital microphone power supply
1
Power
MICBIAS.GND
Dedicated ground for
microphones
Power
GND
Default Configuration After Reset
Released
E2
MICBIAS1.OUT
Power
Floating
D2
MICBIAS.GND
Power
GND
GND
Power
GND
GND
O
Floating
G2
AVSS1
L7
L7
AVSS2
N14
N14
AVSS3
C7
C7
AVSS4
M10
M10
32KCLKOUT
Power
GND
Features
Not Used (1)
Type
G2
Analog ground
Internal
Pull or
Not
Signal
AVSS2
AVSS4
32KCLKOUT
Buffered output of the 32-kHz
digital clock
32KXIN
Input of the 32-kHz oscillator
I
L14
L14
32KXIN
I
N/A
32KXOUT
Output of the 32-kHz oscillator
O
K14
K14
32KXOUT
O
Floating
HFCLKIN
Input of the digital (or sine) HS
clock
I
A11
A11
HFCLKIN
I
N/A
HFCLKOUT
HS clock output
O
M11
M11
HFCLKOUT
VBUS
VBUS power rail
Power
P8
P8
DP/
UART3.RXD
USB data P/USB carkit receive
data/universal asynchronous
receiver/transmitter (UART)3
receive data
I/O
N10
N10
DN/
UART3.TXD
USB data N/USB carkit transmit
data/UART3 transmit data
I/O
P10
ID
USB ID
I/O
UCLK
HS USB clock
I
STP
HS USB stop
I
GPIO9
GPIO9
DIR
HS USB direction
O
GPIO10
GPIO10
I/O
NXT
HS USB next
O
GPIO11
GPIO11
I/O
DATA0
HS USB Data0
I/O
UART4.TXD
UART4.TXD
DATA1
HS USB Data1
I/O
UART4.RXD
UART4.RXD
O
DATA2
HS USB Data2
I/O
UART4.RTSI
UART4.RTSI
DATA3
HS USB Data3
UART4.CTSO
UART4.CTSO
O
GPIO12
GPIO12
I/O
DATA4
HS USB Data4
I/O
GPIO14
GPIO14
I/O
DATA5
HS USB Data5
I/O
GPIO3
GPIO3
I/O
DATA6
HS USB Data6
I/O
GPIO4
GPIO4
I/O
DATA7
HS USB Data7
I/O
GPIO5
GPIO5
I/O
USB PHY
ULPI
TPS65930
Ball
AVSS1
AVSS3
CLOCK
TPS65920
Ball
O
I/O
I
I
O
Floating
Power
N/A
DP/UART3.RX
D
I/O
N/A
P10
DN/UART3.TX
D
I/O
N/A
G6
G6
ID
I/O
Connected to
VRUSB3V1
K11
K11
UCLK
O
Floating
H12
H12
STP
I
H11
H11
DIR
O
Floating
J8
J8
NXT
O
Floating
L10
L10
DATA0
O
Floating
K10
K10
DATA1
O
Floating
G11
G11
DATA2
O
Floating
G10
G10
DATA3
O
Floating
E12
E12
DATA4
O
Floating
G9
G9
DATA5
O
Floating
G12
G12
DATA6
O
Floating
E11
E11
DATA7
O
Floating
VBUS
PU
Floating
I/O
Terminal Description
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Table 2-2. Signal Description (continued)
Module
TEST
USB CP
Signal
Name
Description
Type
Default Configuration After Reset
Released
TPS65920
Ball
TPS65930
Ball
P14
P14
TEST.RESET
Signal
Type
Internal
Pull or
Not
I
PD
Features
Not Used (1)
TEST.RESET
Reset T2 device (except power
state-machine)
TESTV1
Analog test
I/O
P1
P1
TESTV1
I/O
Floating
TESTV2
Analog test
I/O
A14
A14
TESTV2
I/O
Floating
TEST
Selection between JTAG mode
and application mode for
JTAG/GPIOs (with PU or PD)
I
A1
A1
TEST
I
JTAG.TDI/
BERDATA
JTAG.TDI/BERDATA
I
A13
A13
JTAG.TDI/
BERDATA
I
GND
JTAG.TCK/
BERCLK
JTAG.TCK/BERCLK
I
B14
B14
JTAG.TCK/
BERCLK
I
GND
CP.IN
Charge pump input voltage
CP.CAPP
Charge pump flying capacitor P
CP.CAPM
Charge pump flying capacitor M
I
Power
P7
P7
CP.IN
O
N7
N7
CP.CAPP
O
N6
N6
CP.CAPM
PD
GND
Floating
Power
VBAT
O
Floating
O
Floating
CP.GND
Power
GND
GND
CP.GND
Charge pump ground
Power
GND
VBAT.US
B
VBAT.USB
USB LDOs (VINTUSB1P5,
VINTUSB1P8, VUSB.3P1) VBAT
Power
N9
N9
VBAT.USB
Power
VBAT
USB.LDO
VUSB.3P1
USB LDO output
Power
M8
M8
VUSB.3P1
Power
N/A
VAUX1
VAUX12S.IN
VAUX1/VAUX2/VSIM LDO input
voltage
Power
L1
L1
VAUX12S.IN
Power
VBAT
VAUX2
VAUX2.OUT
VAUX2 LDO output voltage
Power
N2
N2
VAUX2.OUT
Power
Floating
VPLLA3R
VPLLA3R.IN
Input for VPLL1, VPLL2, VAUX3,
and VRTC LDOs
Power
H14
H14
VPLLA3R.IN
Power
VBAT
VRTC
VRTC.OUT
VRTC internal LDO output
(internal use only)
Power
K12
K12
VRTC.OUT
Power
N/A
VPLL1
VPLL1.OUT
LDO output voltage
Power
G14
G14
VPLL1.OUT
Power
Floating
VMMC1.IN
VMMC1 LDO input voltage
Power
A2
A2
VMMC1.IN
Power
VBAT
VMMC1.OUT
VMMC1 LDO output voltage
Power
B1
B1
VMMC1.OUT
Power
Floating
VINTUSB1 VINTUSB1P5.
P5
OUT
VINTUSB1P5 internal LDO
output (internal use only)
Power
M7
M7
VINTUSB1P5.
OUT
Power
Floating
VINTUSB1 VINTUSB1P8.
P8
OUT
VINTUSB1P8 internal LDO
output (internal use only)
Power
N8
N8
VINTUSB1P8.
OUT
Power
Floating
K1
K1
VDAC.IN
Power
VBAT
VMMC1
P5
P5
Video
DAC
VDAC.IN
Input for VDAC, VINTANA1, and
VINTANA2 LDOs
Power
VDAC.OUT
Output voltage of the regulator
Power
L2
L2
VDAC.OUT
Power
Floating
VINT
VINT.IN
Input for VINTDIG LDO
Power
H13
H13
VINT.IN
Power
VBAT
Power
N/A
VINTANA1.
VINTANA1
OUT
VINTANA1 internal LDO output
(internal use only)
Power
H1
H1
VINTANA1.OU
T
VINTANA2.
OUT
VINTANA2 internal LDO output
(internal use only)
Power
J2
J2
VINTANA2.OU
T
Power
N/A
VINTANA2.
OUT
VINTANA2 internal LDO output
(internal use only)
Power
A5
A5
VINTANA2.OU
T
Power
N/A
VINTDIG.OUT
VINTDIG internal LDO output
(internal use only)
Power
J13
J13
VINTDIG.OUT
Power
N/A
VINTANA2
VINTDIG
20
Terminal Description
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Table 2-2. Signal Description (continued)
Module
Signal
Name
Description
Type
TPS65920
Ball
TPS65930
Ball
Default Configuration After Reset
Released
Signal
Internal
Pull or
Not
Type
Features
Not Used (1)
VDD1.IN
VDD1 dc-dc input voltage
Power
D13
D13
VDD1.IN
Power
VBAT
VDD1.IN
VDD1 dc-dc input voltage
Power
D12
D12
VDD1.IN
Power
VBAT
VDD1.IN
VDD1 dc-dc input voltage
Power
D14
D14
VDD1.IN
Power
VBAT
VDD1.SW
VDD1 dc-dc switch
O
C11
C11
VDD1.SW
O
Floating
VDD1.SW
VDD1 dc-dc switch
O
C12
C12
VDD1.SW
O
Floating
VDD1.SW
VDD1 dc-dc switch
O
C13
C13
VDD1.SW
O
Floating
VDD1.FB
VDD1 dc-dc output voltage
(feedback)
I
E14
E14
VDD1.FB
I
GND
VDD1.GND
VDD1 dc-dc ground
Power
GND
A12
A12
VDD1.GND
Power
GND
GND
VDD1.GND
VDD1 dc-dc ground
Power
GND
B11
B11
VDD1.GND
Power
GND
GND
VDD1.GND
VDD1 dc-dc ground
Power
GND
B12
B12
VDD1.GND
Power
GND
GND
VDD2.IN
VDD2 dc-dc input voltage
Power
M13
M13
VDD2.IN
Power
VBAT
VDD2.IN
VDD2 dc-dc input voltage
Power
M12
M12
VDD2.IN
Power
VBAT
VDD2.FB
VDD2 dc-dc output voltage
(feedback)
I
N13
N13
VDD2.FB
I
GND
VDD2.SW
VDD2 dc-dc switch
O
N11
N11
VDD2.SW
O
Floating
VDD2.SW
VDD2 dc-dc switch
O
P11
P11
VDD2.SW
O
Floating
VDD2.GND
VDD2 dc-dc ground
Power
GND
N12
N12
VDD2.GND
Power
GND
GND
VDD2.GND
VDD2 dc-dc ground
Power
GND
P12
P12
VDD2.GND
Power
GND
GND
VIO.IN
VIO dc-dc input voltage
Power
M2
M2
VIO.IN
Power
VBAT
VIO.IN
VIO dc-dc input voltage
Power
M3
M3
VIO.IN
Power
VBAT
VIO.FB
VIO dc-dc output voltage
(feedback)
I
M4
M4
VIO.FB
I
GND
VIO.SW
VIO dc-dc switch
O
N4
N4
VIO.SW
O
Floating
VIO.SW
VIO dc-dc switch
O
P4
P4
VIO.SW
O
Floating
VIO.GND
VIO dc-dc ground
Power
GND
N3
N3
VIO.GND
Power
GND
GND
VIO.GND
VIO dc-dc ground
Power
GND
P3
P3
VIO.GND
Power
GND
GND
Backup
battery
BKBAT
Backup battery
Power
H9
H9
BKBAT
Power
GND
Digital
VDD
IO.1P8
TPS65920/TPS65930 device I/O
input
Power
B7
B7
IO.1P8
Power
N/A
Digital
ground
DGND
Digital ground
Power
GND
H10
H10
DGND
Power
GND
GND
LEDGND
LED driver ground
Power
GND
F13
F13
LEDGND
Power
GND
GND
GPIO13
GPIO13
LEDSYNC
LED synchronization input
B10
B10
GPIO13
I
LEDA
LED leg A
VIBRA.P
H-bridge vibrator P
Open
drain
E13
E13
Signal not
functional(3)
Floating
LEDB
LED leg B
VIBRA.M
H-bridge vibrator M
Open
drain
G13
G13
Signal not
functional(3)
Floating
VDD1
VDD2
VIO
LED driver
I/O
I
PD
Floating
Terminal Description
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Table 2-2. Signal Description (continued)
Module
Keypad
Signal
Name
Description
Type
TPS65920
Ball
TPS65930
Ball
Default Configuration After Reset
Released
Signal
Type
Internal
Pull or
Not
Features
Not Used (1)
KPD.C0
Keypad column 0
Open
drain
G4
G4
KPD.C0
OD
Floating
KPD.C1
Keypad column 1
Open
drain
G3
G3
KPD.C1
OD
Floating
KPD.C2
Keypad column 2
Open
drain
E5
E5
KPD.C2
OD
Floating
KPD.C3
Keypad column 3
Open
drain
B2
B2
KPD.C3
OD
Floating
KPD.C4
Keypad column 4
Open
drain
E3
E3
KPD.C4
OD
Floating
KPD.C5
Keypad column 5
Open
drain
D5
D5
KPD.C5
OD
Floating
KPD.R0
Keypad row 0
I
K7
K7
KPD.R0
I
PU
Floating
KPD.R1
Keypad row 1
I
H5
H5
KPD.R1
I
PU
Floating
KPD.R2
Keypad row 2
I
K5
K5
KPD.R2
I
PU
Floating
KPD.R3
Keypad row 3
I
H6
H6
KPD.R3
I
PU
Floating
KPD.R4
Keypad row 4
I
K8
K8
KPD.R4
I
PU
Floating
KPD.R5
Keypad row 5
I
L8
L8
KPD.R5
I
PU
Floating
(1) This column provides the connection when the associated feature is not used or not connected. When there is a pin muxing, not all
functions on the muxed pin are used. But even if a function is not used, the Default Configuration After Reset Released column still
applies.
Connection criteria:
– Analog pins:
– For input: GND
– For output: Floating (except VPRECH is connected to GND)
– For I/O if input by default: GND (except for audio features input: capacitor to ground with a 100-nF typical value capacitor)
– Digital pins:
– For input: GND (except keypad and STP are left floating)
– For input and pullup: Floating
– For output: Floating
– For I/O and pullup: Floating
N/A (not applicable): When the associated feature is mandatory for correct functioning of the TPS65920/TPS65930 device
(2) The signal VPRECH must be connected to the CPRECH capacitor to GND.
(3) Signal not functional indicates that no signal is presented on the pad after a release reset.
22
Terminal Description
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3
Electrical Characteristics
3.1
Absolute Maximum Ratings
Table 3-1 lists the absolute maximum ratings.
Table 3-1. Absolute Maximum Ratings
Parameter
Main battery supply voltage
Test Conditions
(1)
Voltage on any input
Supply represents the voltage applied to the
power supply pin associated with the input
Storage temperature range
3.2
Max
Unit
2.1
4.5
V
0.0
1.0*Supply
V
–55
125
°C
At 1.4 W (Theta JB 11°C/W 2S2P board)
–40
Junction temperature (TJ) for parametric
compliance
(1)
Typ
–40
Ambient temperature range
Junction temperature (TJ)
Min
85
°C
105
°C
105
°C
The product has negligible reliability impact if voltage spikes of 5.2 V occur for a total duration of 10 milliseconds.
Minimum Voltages and Associated Currents
Table 3-2 lists the VBAT minimum and maximum currents per VBAT ball.
Table 3-2. VBAT Minimum Required Per VBAT Ball and Associated Maximum Current
Category
Pin and Module
Maximum Current
Specified (mA)
VBAT pin name
VDD_VPLLA3R_IN_6POV
340
VPLL1 (LDO)
40
VDD1 core (DCDC)
<1
2.7
VDD2 core (DCDC)
<1
2.7
SYSPOR (power ref)
<1
2.7
PBIAS (power ref)
<1
2.7
VDD_VDAC_IN_6POV
370
VDAC (LDO)
70
1.2 / 1.3 / 1.8
Maximum
(2.7, output voltage selected + 250 mV)
VINTANA1 (LDO)
50
1.5
Maximum
(2.7, output voltage selected + 250 mV)
VINTANA2 (LDO)
250
2.5 / 2.75
Maximum
(2.7, output voltage selected +250 mV)
Internal module
supplied
VBAT pin name
Internal module
supplied
VIO core (DCDC)
<1
VDD_VAUXI2S_IN_6POV
350
VAUX2 (LDO)
100
VBAT pin name
VDD_VMMC1_IN_6POV
220
Internal module
supplied
VMMC1 (LDO)
220
VBAT pin name
Internal module
supplied
Power_REGBATT
VBAT pin name
VDD_VINT_IN_6POV
Output Voltage (V)
VBAT Minimum (V)
1.0 / 1.2 / 1.3 / 1.8 / 2.8 /
3.0
Maximum
(2.7, output voltage selected + 250 mV)
2.7
1.3 / 1.5 / 1.6 / 1.7 / 1.8 /
1.9 / 2.0 / 2.1 / 2.2 / 2.3 /
2.4 / 2.5 / 2.8
Maximum
(2.7, output voltage selected + 250 mV)
1.85 / 2.85 / 3.0 / 3.15
Maximum
(2.7, output voltage selected + 250 mV)
0.001
2.7
131
Electrical Characteristics
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Table 3-2. VBAT Minimum Required Per VBAT Ball and Associated Maximum Current (continued)
Category
Internal module
supplied
3.3
Pin and Module
Maximum Current
Specified (mA)
Output Voltage (V)
VBAT Minimum (V)
VINTDIG (LDO)
80
1.0 / 1.2 / 1.3 / 1.5
Maximum
(2.7, output voltage selected + 250 mV)
VRRTC (LDO)
30
1.5
Maximum
(2.7, output voltage selected + 250 mV)
VBACKUP (LDO)
1
2.5 / 3.0 / 3.1 / 3.2
Maximum
(2.7, output voltage selected + 250 mV)
Recommended Operating Conditions
Table 3-3 lists the recommended operating maximum ratings.
Table 3-3. Recommended Operating Maximum Ratings
Parameter
Test Conditions
Min
Typ
Max
Unit
2.7 (1)
3.6
4.5
V
Backup battery supply voltage
1.8
3.2
3.3
V
Ambient temperature range
–40
85
°C
Main battery supply voltage
(1)
2.7 V is the minimum threshold for the battery at which the device will turn OFF. However, the minimum voltage at which the device will
power ON is 3.2 V ±100 mV (if PWRON does not have a switch and is connected to VBAT) considering battery plug as the device
switch on event. If PWRON has a switch then 3.2 V is the minimum for the device to turn ON.
3.4
Digital I/O Electrical Characteristics
Table 3-4 describes the digital I/O electrical characteristics. The following list defines abbreviations used in
the table:
• RL: Reference level voltage applied to the I/O cell
• VOL: Low-level output voltage
• VOH: High-level output voltage
• VIL: Low-level input voltage
• VIH: High-level input voltage
• Min: Minimum value
• Max: Maximum value
Table 3-4. Digital I/O Electrical Characteristics
VOL (V)
VOH (V)
VIL (V)
VIL (V)
Min
Max
Min
Max
Min
Max
Min
Max
Max Freq
(MHz)
0
0.45
RL–0.45
RL
0
0.35xRL
0.65xRL
RL
33
30
5.2
5.2
0
0.45
RL–0.45
RL
0
0.35xRL
0.65xRL
RL
33
30
5.2
5.2
0
0.45
RL–0.45
RL
0
0.35xRL
0.65xRL
RL
3
30
5.2
5.2
0
0.45
RL–0.45
RL
0
0.35xRL
0.65xRL
RL
3
30
5.2
5.2
0
0.45
RL–0.45
RL
0
0.35xRL
0.65xRL
RL
3
30
5.2
5.2
0
0.45
RL–0.45
RL
0
0.35xRL
0.65xRL
RL
3
30
5.2
5.2
Pin Name
Load (pF)
Rise
Fall Time (ns)
Output Mode Time (ns)
GPIO0/CD1
JTAG.TDO
GPIO0
JTAG.TMS
GPIO2
TEST1
GPIO15
TEST2
GPIO6
PWM0
TEST3
GPIO7
VIBRA.SYNC
PWM1
TEST4
24
Electrical Characteristics
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Table 3-4. Digital I/O Electrical Characteristics (continued)
VOL (V)
VOH (V)
VIL (V)
VIL (V)
Pin Name
Max Freq
(MHz)
Load (pF)
Rise
Fall Time (ns)
Output Mode Time (ns)
Min
Max
Min
Max
Min
Max
Min
Max
SYSEN
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
CLKEN
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
3
CLKREQ
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
3
INT1
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
3
30
NRESPWRON
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
3
NRESWARM
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
3
0
0.35×1.8V
0.65×1.8V
VBAT
PWRON
5.2
5.2
33.3
33.3
33.3
33.3
33.3
33.3
30
33.3
33.3
30
33.3
33.3
3
33.3
33.3
33.3
33.3
16.3
16.3
30
NSLEEP1
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
3
CLK256FS
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
12.288
VMODE1
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
3
33.3
33.3
BOOT0
0
RL
3
33.3
33.3
BOOT1
0
RL
3
33.3
33.3
REGEN
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
3
33.3
33.3
MSECURE
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
3
33.3
33.3
I2C.SR.SDA
0
0.4
–0.5
0.3×RL
0.7×RL
RL+0.5
3.4
VMODE2
0
0.45
0
0.35×RL
0.65×RL
RL
3.4
29.4
29.4
I2C.SR.SCL
0
0.4
–0.5
0.3×RL
0.7×RL
RL+0.5
3.4
10.0
10.0
I2C.CNTL.SDA
0
0.4
–0.5
0.3×RL
0.7×RL
RL+0.5
3.4
I2C.CNTL.SCL
0
0.4
–0.5
0.3×RL
0.7×RL
RL+0.5
3.4
10.0
10.0
I2S.CLK
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
6.5
30
33.0
33.0
I2S.SYNC
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
6.5
30
33.0
33.0
I2S.DIN
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
3.25
30
33.0
33.0
I2S.DOUT
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
3.25
30
29.0
29.0
32KCLKOUT
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
0.032
30
16
16
HFCLKOUT
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
38.4
30
2.6
2.6
UCLK
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
60
10
1.0
1.0
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
30
10
1.0
1.0
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
30
10
1.0
1.0
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
30
10
1.0
1.0
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
30
10
1.0
1.0
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
30
10
1.0
1.0
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
30
10
1.0
1.0
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
30
10
1.0
1.0
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
30
10
1.0
1.0
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
30
10
1.0
1.0
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
30
10
1.0
1.0
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
30
10
1.0
1.0
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
30
10
1.0
1.0
TEST.RESET
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
3
33.0
33.0
TEST
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
3
29.0
29.0
JTAG.TDI/
BERDATA
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
3
33.0
33.0
JTAG.TCK/
BERDATA
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
3
33.0
33.0
RL–0.45
RL
30
30
Up to 400
Up to 400
STP
GPIO9
DIR
GPIO10
NXT
GPIO11
DATA0
UART4.TXD
DATA1
UART4.RXD
DATA2
UART4.RTSI
DATA3
UART4.CTSO
GPIO12
DATA4
GPIO14
DATA5
GPIO3
DATA6
GPIO4
DATA7
GPIO5
30
Electrical Characteristics
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Table 3-4. Digital I/O Electrical Characteristics (continued)
VOL (V)
VOH (V)
VIL (V)
VIL (V)
Pin Name
Min
Max
Min
Max
Min
Max
Min
0
0.45
RL–0.45
RL
0
0.35×RL
0.35×RL
KPD.C0
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
KPD.C1
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
KPD.C2
0
0.45
RL–0.45
RL
0
0.35×RL
KPD.C3
0
0.45
RL–0.45
RL
0
KPD.C4
0
0.45
RL–0.45
RL
KPD.C5
0
0.45
RL–0.45
KPD.C6
0
0.45
KPD.C7
0
KPD.R0
Max
Max Freq
(MHz)
Load (pF)
Rise
Fall Time (ns)
Output Mode Time (ns)
GPIO13
3
30
33.3
33.3
RL
0.033
30
29.0
29.0
RL
0.033
30
29.0
29.0
0.65×RL
RL
0.033
30
29.0
29.0
0.35×RL
0.65×RL
RL
0.033
30
29.0
29.0
0
0.35×RL
0.65×RL
RL
0.033
30
29.0
29.0
RL
0
0.35×RL
0.65×RL
RL
0.033
30
29.0
29.0
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
0.033
30
29.0
29.0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
0.033
30
29.0
29.0
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
0.033
3051.8
3051.8
KPD.R1
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
0.033
3051.8
3051.8
KPD.R2
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
0.033
3051.8
3051.8
KPD.R3
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
0.033
3051.8
3051.8
KPD.R4
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
0.033
3051.8
3051.8
KPD.R5
0
0.45
RL–0.45
RL
0
0.35×RL
0.65×RL
RL
0.033
3051.8
3051.8
KPD.R6
0
0.45
0.45
RL
0
0.35×RL
0.65×RL
RL
0.033
3051.8
3051.8
KPD.R7
0
0.45
0.45
RL
0
0.35×RL
0.65×RL
RL
0.033
3051.8
3051.8
LEDSYNC
26
Electrical Characteristics
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4
Power Module
This section describes the electrical characteristics of the voltage regulators and timing characteristics of
the supplies digitally controlled in the TPS65920 and TPS65930 devices
.
Figure 4-1 is the power provider block diagram.
Main battery
VPLL1.OUT
VPLLA3R.IN
VPLL1
VINT.IN
1.0/1.2/1.3/1.8 V
40 mA
CVPLL1.OUT
VMMC1.OUT
CVMMC1.OUT
VAUX2.OUT
CVAUX2.OUT
VMMC1
1.85/2.85
/3.0/3.15 V
220 mA
VAUX2
1.3/1.5/1.7/1.8/1.9/2.0/
2.1/2.2/2.3/2.4/2.5/2.8 V
100 mA
VMMC1.IN
VDAC.IN
VDAC.IN
VAUX12S.IN
VDAC.IN
VUSB.3P1
VRUSB_3V1
VBAT.USB
3.1 V
15 mA
CVUSB.3P1
VINTDIG
VINTDIG.OUT
1.0/1.2/1.3/1.5 V
80 mA
VINTANA1
CVINTDIG.OUT
VINTANA.OUT
1.5 V
50 mA
VINTANA2
2.5/2.75 V
250 mA
VDAC
CVINTANA1.OUT
VINTANA2.OUT
CVINTANA2.OUT
VDAC.OUT
1.2/1.3/1.8 V
70 mA
CVDAC.OUT
LVDD1
VDD1.L
VINTUSB1P8.OUT
VRUSB_1V8
VBAT.USB
VDD1.IN x 3
1.81 V
30 mA
CVINTUSB1P8.OUT
VDD1
(DC-DC)
(3)
VDD1.OUT
0.6 V to 1.45 V
1200 mA
VDD1.GND
CVDD1.OUT
(3)
VINTUSB1P5.OUT
CVINTUSB1P5.OUT
VRUSB_1V5
LVDD2
VDD2.L
VBAT.USB
1.525 V
30 mA
VDD2.IN x 2
VDD2
(DC-DC)
0.6 V to 1.5 V
600 mA
(2)
VDD2.OUT
CVDD2.OUT
VDD2.GND
(2)
LVIO
VIO.L
VIO.IN x 2
VIO
(DC-DC)
1.8 V/1.85 V
700 mA
(2)
VIO.OUT
CVIO.OUT
VIO.GND
(2)
037-010
Two internal regulators, VRRTC and VBRTC, are not shown. VRRTC provides power to the RTC, and VBRTC is not
used in this configuration.
Figure 4-1. Power Provider Block Diagram
NOTE
For the component values, see Table 14-1.
Power Module
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4.1
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Power Providers
Table 4-1 summarizes the power providers.
Table 4-1. Summary of the Power Providers
Usage
Type
Voltage Range (V)
Default Voltage
Maximum
Current
VAUX2
External
LDO
1.3, 1.5, 1.7, 1.8, 1.9, 2.0, 2.1, 2.2, 2.3, 2.4, 2.5, 2.8
1.8 V
100 mA
VMMC1
External
LDO
1.85, 2.85, 3.0, 3.15
3.0 V
220 mA
VPLL1
External
LDO
1.0, 1.2, 1.3, 1.8, 2.8, 3.0
1.8 V
40 mA
VDAC
External
LDO
1.2, 1.3, 1.8
1.8 V
70 mA
VIO
External
SMPS
1.8, 1.85
1.8 V
700 mA
VDD1
External
SMPS
0.6 ... 1.45
1.2 V
1200 mA
VDD2
External
SMPS
0.6 ... 1.5
1.2 V
600 mA
VINTANA1
Internal
LDO
1.5
1.5 V
50 mA
VINTANA2
Internal
LDO
2.5, 2.75
2.75 V
250 mA
VINTDIG
Internal
LDO
1.0, 1.2, 1.3, 1.5
1.5 V
80 mA
USBCP
Internal
Charge pump
5
5V
100 mA
VUSB1V5
Internal
LDO
1.5
1.5 V
30 mA
VUSB1V8
Internal
LDO
1.8
1.8 V
30 mA
VUSB3V1
Internal
LDO
3.1
3.1 V
15 mA
VRRTC
Internal
LDO
1.5
1.5 V
30 mA
VBRTC
Internal
LDO
1.3
1.3 V
100 μA
Name
28
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4.1.1
VDD1 dc-dc Regulator
4.1.1.1
VDD1 dc-dc Regulator Characteristics
The VDD1 dc-dc regulator is a stepdown dc-dc converter with a configurable output voltage. The
programming of the output voltage and the characteristics of the dc-dc converter are
SmartReflex-compatible. The regulator can be put in sleep mode to reduce its leakage (PFM) or in
power-down mode when it is not in use. Table 4-3 describes the regulator characteristics.
Table 4-2. Part Names With Corresponding VDD1 Current Support
Device Name
VDD1 Current Support
TPS65920A2ZCH (some bug fixes, see errata)
1.2 A
TPS65920A2ZCHR (some bug fixes, see errata)
1.2 A
TPS65930A2ZCH (some bug fixes, see errata)
1.2 A
TPS65930A2ZCHR (some bug fixes, see errata)
1.2 A
Table 4-3. VDD1 dc-dc Regulator Characteristics
Min
Typ
Max
Unit
Input voltage range
Parameter
Comments
2.7
3.6
4.5
V
Output voltage
0.6
1.45
V
Output voltage step
Covering the 0.6-V to 1.45-V range
Output accuracy (1)
0.6 V to < 0.8 V
–6%
12.5
6%
0.8 V to 1.45 V
–4%
4%
Switching frequency
Conversion efficiency (2), Figure 4-2 in active
mode
Output current
Ground current (IQ)
3.2
IO = 10 mA, sleep
82%
100 mA < IO < 400 mA
85%
400 mA < IO < 600 mA
80%
600 mA < IO < 800 mA
75%
1.2
A
Sleep mode
10
mA
3
μA
Off at 30°C
30
Active, unloaded, not switching
Short-circuit current
VIN = VMax
Load regulation
0 < IO < IMax
Transient load regulation (3)
IO = 10 mA to (IMax/2) + 10 mA,
Maximum slew rate is IMax/2/100 ns
2.2
mV
50
mV
10
mV
10
mV
0.25
1
ms
<10
100
μs
8
16
mV/μs
500
700
Ω
1
1.3
μH
0.1
Ω
–65
Start-up time
From sleep mode to on mode with constant
load
4
Output shunt resistor (pulldown)
Value
External coil
Data capture record (DCR)
Saturation current
(1)
(2)
(3)
(4)
0.7
A
20
300 mVPP ac input, 10-μs rise and fall time
Slew rate (rising or falling) (4)
50
300
Line regulation
Recovery time
MHz
Active mode
Sleep, unloaded
Transient line regulation
mV
1.8
A
Accuracy includes all variations (line and load regulations, line and load transients, temperature, and process)
VBAT = 3.8 V, VDD1 = 1.3 V, Fs = 3.2 MHz, L = 1 μH, LDCR = 100 mΩ, C = 10 μF, ESR = 10 mΩ
Output voltage must discharge the load current completely and settle to its final value within 100 μs.
Load current varies proportionally with the output voltage. The slew rate is for increasing and decreasing voltages, and the maximum
load current is 1.1 A.
Power Module
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Table 4-3. VDD1 dc-dc Regulator Characteristics (continued)
Parameter
Comments
External capacitor (5)
(5)
Min
Typ
Max
Value
8
10
12
Unit
μF
Equivalent series resistance (ESR) at
switching frequency
0
20
mΩ
Under current load condition step:
Imax/2 (550 mA) in 100 ns with a ±20% external capacitor accuracy or
Imax/3 (367 mA) in 100 ns with a ±50% external capacitor accuracy
See Table 2-2 for how to connect the VDD1/2 dc-dc converter when it is not in use.
Figure 4-2 shows the efficiency of the VDD1 dc-dc regulator in active mode and sleep mode.
VDD1 EFFICIENCY vs OUTPUT CURRENT
Output voltage = 1.3 V, Vbat = 3.6 V
90
80
70
Effciency (%)
60
50
40
30
20
10
0
0.0001
0.001
0.01
0.1
1
ILOAD (A)
SWCS037-018
Figure 4-2. VDD1 dc-dc Regulator Efficiency
4.1.1.2
External Components and Application Schematics
Figure 4-3 is an application schematic with the external components on the VDD1 dc-dc regulator.
30
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Device
VDD1.IN (D14)
VDD1.IN (D13)
VDD1.IN (D12)
VDD1.SW (C11)
LVDD1
VDD1.SW (C12)
VDD1.SW (C13)
CVDD1.OUT
VDD1.GND (A12)
VDD1.GND (B11)
VDD1.GND (B12)
030-009
Figure 4-3. VDD1 dc-dc Application Schematic
NOTE
For the component values, see Table 14-1.
Power Module
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4.1.2
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VDD2 dc-dc Regulator
4.1.2.1
VDD2 dc-dc Regulator Characteristics
The VDD2 dc-dc regulator is a programmable output stepdown dc-dc converter with an internal field effect
transistor (FET). Like the VDD1 regulator, the VDD2 regulator can be placed in sleep or power-down
mode and is SmartReflex-compatible. The VDD2 regulator differs from VDD1 in its current load capability.
Table 4-4 describes the regulator characteristics.
Table 4-4. VDD2 dc-dc Regulator Characteristics
Parameter
Comments
Input voltage range
Output voltage
Min
Typ
Max
Unit
2.7
3.6
4.5
V
1
1.5
0.6
Output voltage step
Covering the 0.6-V to 1.45-V range,
1.5 V is a single programmable value
12.5
Output accuracy (1)
0.6 V to < 0.8 V
–6%
0.8 V to 1.5 V
–4%
Switching frequency
Conversion efficiency (2), Figure 4-4 in active mode
Output current
Ground current (IQ)
6%
4%
3.2
IO = 10 mA, sleep
82%
100 mA < IO < 300 mA
85%
300 mA < IO < 500 mA
80%
MHz
Active mode
600
mA
Sleep mode
10
mA
Off at 30°C
1
μA
Sleep, unloaded
50
Active, unloaded, not switching
Short-circuit current
VIN = VMax
Load regulation
0 < IO < IMax
Transient load regulation (3)
IO = 10 mA to (IMax/2) + 10 mA,
Maximum slew rate is IMax/2/100 ns
300
1.2
–65
Line regulation
Transient line regulation
V
mV
300 mVPP ac input, 10-μs rise and fall
time
A
20
mV
50
mV
10
mV
10
mV
Output shunt resistor (internal pulldown)
500
700
Ω
Start-up time
0.25
1
ms
25
100
μs
Recovery time
From sleep mode to on mode with
constant load
Slew rate (rising or falling) (4)
Value
External coil
(1)
(2)
(3)
(4)
(5)
32
8
16
mV/μs
1
1.3
μH
DCR
Saturation current
External capacitor (5)
4
0.7
0.1
900
Value
8
ESR at switching frequency
0
Ω
mA
10
12
μF
20
mΩ
Accuracy includes all variations (line and load regulations, line and load transients, temperature, and process)
VBAT = 3.8 V, VDD2 = 1.3 V, Fs = 3.2 MHz, L = 1 μH, LDCR = 100 mΩ, C = 10 μF, ESR = 10 mΩ
Output voltage needs to discharge the load current completely and settle to its final value within 100 μs.
Load current varies proportionally with the output voltage. The slew rate is for both increasing and decreasing voltages and the
maximum load current is 600 mA.
Under current load condition step:
Imax/2 (300 mA) in 100 ns with a ±20% external capacitor accuracy or
Imax/3 (200 mA) in 100 ns with a ±50% external capacitor accuracy
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See Table 2-2 for how to connect the VDD1/2 dc-dc converter when it is not in use.
Figure 4-4 shows the efficiency of the VDD2 dc-dc regulator in active mode and sleep mode.
VDD2 EFFICIENCY vs OUTPUT CURRENT
Output voltage = 1.3 V, Vbat = 3.6 V
90
80
70
Effciency (%)
60
50
40
30
20
10
0
0.0001
0.001
0.01
0.1
1
ILOAD (A)
SWCS037-019
Figure 4-4. VDD2 dc-dc Regulator Efficiency
4.1.2.2
External Components and Application Schematics
Figure 4-5 is an application schematic with the external components on the VDD2 dc-dc regulator.
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Device
VDD2.IN (M12)
VDD2.IN (M13)
LVDD2
VDD2.SW (N11)
VDD2.SW (P11)
CVDD2.OUT
VDD2.GND (N12)
VDD2.GND (P12)
030-010
Figure 4-5. VDD2 dc-dc Application Schematic
NOTE
For the component values, see Table 14-1.
34
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4.1.3
VIO dc-dc Regulator
4.1.3.1
VIO dc-dc Regulator Characteristics
The I/O and memory dc-dc regulator is a 600-mA stepdown dc-dc converter (internal FET) with two output
voltage settings. It supplies the memories and all I/O ports in the application and is one of the first power
providers to switch on in the power-up sequence. This dc-dc regulator can be placed in sleep or
power-down mode; however, care must be taken in the sequencing of this power provider, because
numerous ESD blocks are connected to this supply. Table 4-5 describes the regulator characteristics.
Table 4-5. VIO dc-dc Regulator Characteristics
Parameter
Comments
Input voltage range
Min
Typ
Max
Unit
2.7
3.6
4.5
V
1.8
1.85
Output voltage (1)
Output accuracy
(2)
–4%
4%
–3%
3%
Switching frequency
Conversion efficiency (3) Figure 4-6 in active mode
Output current
Ground current (IQ)
V
3.2
IO = 10 mA, sleep
85%
100 mA < IO < 400 mA
85%
400 mA < IO < 600 mA
80%
MHz
On mode
700
Sleep mode
Off at 30°C
1
Sleep, unloaded
Active, unloaded, not switching
300
300 mVPP ac, input rise and fall time 10 μs
Start-up time
Recovery time
From sleep mode to on mode with constant
load
Output shunt resistor (internal pulldown)
Value
External coil
External capacitor
(1)
(2)
(3)
(4)
0.7
50
mV
10
mV
0.25
1
ms
<10
100
μs
500
700
Ω
1
1.3
μH
DCR
Saturation current
μA
50
Load transient (4)
Line transient
mA
10
0.1
900
Value
8
ESR at switching frequency
1
Ω
mA
10
12
μF
20
mΩ
This voltage is tuned according to the platform and transient requirements.
±4% accuracy includes all the variation (line and load regulation, line and load transient, temperature, process)
±3% accuracy is dc accuracy only.
VBAT = 3.8 V, VIO = 1.8 V, Fs = 3.2 MHz, L = 1 μH, LDCR = 100 mΩ, C = 10 μF, ESR = 10 mΩ
Load transient can also be specified as 0 < IO < IOUTmax/2, Δt = 1 μs, 100 mV but this is not included in ±4% accuracy.
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Figure 4-6 shows the efficiency of the VIO dc-dc regulator in active mode and sleep mode.
VIO EFFICIENCY vs OUTPUT CURRENT
Output voltage = 1.2 V, Vbat = 3.8 V
100
90
80
70
Effciency (%)
60
50
40
30
20
10
0
0.0001
0.001
0.01
0.1
1
ILOAD (A)
SWCS037-020
Figure 4-6. VIO dc-dc Regulator Efficiency
4.1.3.2
External Components and Application Schematics
Figure 4-7 is an application schematic with the external components on the VIO dc-dc regulator.
36
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Device
VIO.IN (M2)
VIO.IN (M3)
VIO.SW (N4)
LVIO
VIO.SW (P4)
CVIO.OUT
VIO.GND (N3)
VIO.GND (P3)
030-011
Figure 4-7. VIO dc-dc Application Schematic
NOTE
For the component values, see Table 14-1.
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VDAC LDO Regulator
The VDAC programmable LDO regulator is a high-PSRR, low-noise linear regulator that powers the host
processor dual-video DAC. It is controllable with registers through I2C and can be powered down.
Table 4-6 describes the regulator characteristics.
Table 4-6. VDAC LDO Regulator Characteristics
Parameter
Test Conditions
Min
Typ
0.3
1
Max
Unit
Output Load Conditions
Filtering capacitor
Connected from VDAC.OUT to analog ground
Filtering capacitor ESR
20
2.7
μF
600
mΩ
Electrical Characteristics
VIN
Input voltage
VOUT
Output voltage
IOUT
Rated output current
On mode
2.7
3.6
4.5
V
1.164
1.2
1.236
V
1.261
1.3
1.339
1.746
1.8
1.854
On mode
70
Low-power mode
mA
5
dc load regulation
On mode: 0 < IO < IMax
dc line regulation
On mode, VIN = VINmin to VINmax at IOUT = IOUTmax
Turn-on time
IOUT = 0, CL = 1 μF (within 10% of VOUT)
Wake-up time
Full load capability
Ripple rejection
f < 20 kHz
65
20 kHz < f < 100 kHz
45
f = 1 MHz
40
20
mV
3
mV
100
μs
10
μs
dB
VIN = VOUT + 1 V, IO = IMax
Output noise
100 Hz < f < 5 kHz
400 nV/√Hz
5 kHz < f < 400 kHz
125
400 kHz < f < 10 MHz
Ground current
50
On mode, IOUT = 0
150
On mode, IOUT = IOUTmax
350
Low-power mode, IOUT = 0
15
Low-power mode, IOUT = 1 mA
25
Off mode at 55°C
VDO
38
Dropout voltage
On mode, IOUT = IOUTmax
Transient load regulation
ILoad: IMin – IMax
Slew: 60 mA/μs
Transient line regulation
VIN drops 500 mV
Slew: 40 mV/μs
Power Module
μA
1
–40
250
mV
40
mV
10
mV
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4.1.5
VPLL1 LDO Regulator
The VPLL1 programmable LDO regulator is a high-PSRR, low-noise, linear regulator used for the host
processor PLL supply. Table 4-7 describes the regulator characteristics.
Table 4-7. VPLL1 LDO Regulator Characteristics
Parameter
Test Conditions
Min
Typ
0.3
1
Max
Unit
Output Load Conditions
Filtering capacitor
Connected from VPLL1.OUT to analog ground
Filtering capacitor ESR
20
2.7
μF
600
mΩ
Electrical Characteristics
VIN
Input voltage
VOUT
Output voltage
IOUT
Rated output current
On mode and low-power mode
2.7
3.6
4.5
V
0.97
1.0
1.03
V
1.164
1.2
1.236
1.261
1.3
1.339
1.746
1.8
1.854
2.716
2.8
2.884
2.91
3.0
3.090
On mode
40
Low-power mode
mA
5
dc load regulation
On mode: 0 < IO < IMax
dc line regulation
On mode, VIN = VINmin to VINmax at IOUT = IOUTmax
Turn-on time
IOUT = 0, CL = 1 μF (within 10% of VOUT)
Wake-up time
Full load capability
Ripple rejection
f < 10 kHz
50
10 kHz < f < 100 kHz
40
f = 1 MHz
30
20
mV
3
mV
100
μs
10
μs
dB
VIN = VOUT + 1 V, IO = IMax
Ground current
On mode, IOUT = 0
70
On mode, IOUT = IOUTmax
Low-power mode, IOUT = 0
15
Low-power mode, IOUT = 1 mA
16
Off mode at 55°C
VDO
Dropout voltage
On mode, IOUT = IOUTmax
Transient load regulation
ILoad: IMin – IMax
Slew: 60 mA/μs
Transient line regulation
VIN drops 500 mV
Slew: 40 mV/μs
1
–40
250
mV
40
mV
10
mV
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VMMC1 LDO Regulator
The VMMC1 LDO regulator is a programmable linear voltage converter that powers the multimedia card
(MMC) slot. It includes a discharge resistor and overcurrent protection (short-circuit). This LDO regulator
can also be turned off automatically when MMC card extraction is detected. The VMMC1 LDO can be
powered through an independent supply other than the battery; for example, a charge pump. In this case,
the input from the VMMC1 LDO can be higher than the battery voltage. Table 4-8 describes the regulator
characteristics.
Table 4-8. VMMC1 LDO Regulator Characteristics
Parameter
Test Conditions
Min
Typ
0.3
1
Max
Unit
Output Load Conditions
Filtering capacitor
Connected from VMMC1.OUT to analog ground
Filtering capacitor ESR
2.7
μF
600
mΩ
5.5
V
1.85 1.9055
2.85 2.9355
3.0
3.09
3.15 3.2445
V
20
Electrical Characteristics
VIN
Input voltage
2.7
1.7945
2.7645
2.91
3.0555
3.6
VOUT
Output voltage
On mode and low-power mode
IOUT
Rated output current
On mode
Low-power mode
dc load regulation
On mode: 0 < IO < IMax
dc line regulation
On mode, VIN = VINmin to VINmax at IOUT = IOUTmax
Turn-on time
IOUT = 0, CL = 1 μF (within 10% of VOUT)
Wake-up time
Full load capability
Ripple rejection
f < 10 kHz
10 kHz < f < 100 kHz
f = 1 MHz
VIN = VOUT + 1 V, IO = IMax
Ground current
On mode, IOUT = 0
On mode, IOUT = IOUTmax
Low-power mode, IOUT = 0
Low-power mode, IOUT = 5 mA
Off mode at 55°C
70
290
17
20
1
μA
Dropout voltage
On mode, IOUT = IOUTmax
250
mV
Transient load regulation
ILoad: IMin – IMax
Slew: 40 mA/μs
40
mV
Transient line regulation
VIN drops 500 mV
Slew: 40 mV/μs
10
mV
VDO
40
Power Module
220
5
mA
20
mV
3
mV
100
μs
10
μs
50
40
25
–40
dB
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4.1.7
VAUX2 LDO Regulator
The VAUX2 general-purpose LDO regulator powers the auxiliary devices. Table 4-9 describes the
regulator characteristics.
Table 4-9. VAUX2 LDO Regulator Characteristics
Parameter
Test Conditions
Min
Typ
0.3
1
Max
Unit
Output Load Conditions
Filtering capacitor
Connected from VAUX2.OUT to analog ground
Filtering capacitor ESR
20
2.7
μF
600
mΩ
Electrical Characteristics
VIN
Input voltage
2.7
3.6
4.5
V
–3%
1.3
1.5
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.8
3%
V
100
5
mA
20
mV
3
mV
100
μs
10
μs
VOUT
Output voltage
On mode and low-power mode
IOUT
Rated output current
On mode
Low-power mode
dc load regulation
On mode: IOUT = IOUTmax to 0
dc line regulation
On mode, VIN = VINmin to VINmax at IOUT = IOUTmax
Turn-on time
IOUT = 0, CL = 1 μF (within 10% of VOUT)
Wake-up time
Full load capability
Ripple rejection
f < 10 kHz
10 kHz < f < 100 kHz
f = 1 MHz
VIN = VOUT + 1 V, IO = IMax
Ground current
On mode, IOUT = 0
On mode, IOUT = IOUTmax
Low-power mode, IOUT = 0
Low-power mode, IOUT = 5 mA
Off mode at 55°C
70
170
17
20
1
μA
Dropout voltage
On mode, IOUT = IOUTmax
250
mV
Transient load regulation
ILoad: IMin – IMax
Slew: 40 mA/μs
40
mV
Transient line regulation
VIN drops 500 mV
Slew: 40 mV/μs
10
mV
VDO
50
40
25
–40
dB
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Output Load Conditions
Table 4-10 lists the regulators that power the device, and the output loads associated with them.
Table 4-10. Output Load Conditions
Regulator
VINTDIG LDO
Parameter
Filtering capacitor
Test Conditions
Connected from VINTDIG.OUT to analog
ground
Filtering capacitor ESR
VINTANA1 LDO
Filtering capacitor
Filtering capacitor
Connected from VINTANA1.OUT to
analog ground
600
mΩ
2.7
μF
600
mΩ
2.7
μF
0.3
1
600
mΩ
Connected from VUSB.3P1 to GND
0.3
1
1
2.7
μF
0
10
600
mΩ
Connected from VINTUSB1P8.OUT to
GND
0.3
1
2.7
μF
0
10
600
mΩ
Connected from VINTUSB1P5 to GND
0.3
1
2.7
μF
0
10
600
mΩ
20
Filtering capacitor ESR
42
μF
0.3
Filtering capacitor ESR
VRUSB_1V5 LDO Filtering capacitor
Unit
2.7
Connected from VINTANA2.OUT to
analog ground
Filtering capacitor ESR
VRUSB_1V8 LDO Filtering capacitor
Max
1
20
Filtering capacitor ESR
VRUSB_3V1 LDO Filtering capacitor
Typ
0.3
20
Filtering capacitor ESR
VINTANA2 LDO
Min
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4.1.9
Charge Pump
The charge pump generates a 4.8-V (nominal) power supply voltage from the battery to the VBUS pin.
The input voltage range is 2.7 to 4.5 V for the battery voltage. The charge pump operating frequency is
1 MHz.
The charge pump tolerates 7 V on VBUS when it is in power-down mode. The charge pump integrates a
short-circuit current limitation at 450 mA. Table 4-11 lists the charge pump output load conditions.
Table 4-11. Charge Pump Output Load Conditions
Parameter
Test Conditions
Min
Typ
Max
Unit
μF
Output Load Conditions
Filtering capacitor
Connected from VBUS to VSSP
1.41
4.7
6.5
Flying capacitor
Connected from CP to CN
1.32
2.2
3.08
μF
20
mΩ
Filtering capacitor ESR
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4.1.10 USB LDO Short-Circuit Protection Scheme
The short-circuit current for the LDOs and dc-dcs in the TPS65920 and TPS65930 devices is
approximately twice the maximum load current. When the output of the block is shorted to ground, the
power dissipation can exceed the 1.2-W requirement if no action is taken. A short-circuit protection
scheme is included in the TPS65920 and TPS65930 devices to ensure that if the output of an LDO or
dc-dc is short-circuited, the power dissipation does not exceed the 1.2-W level.
The three USB LDOs, VRUSB3V1, VRUSB1V8, and VRUSB1V5, are included in this short-circuit
protection scheme, which monitors the LDO output voltage at a frequency of 1 Hz and generates an
interrupt (sc_it) when a short-circuit is detected.
The scheme compares the LDO output voltage to a reference voltage and detects a short-circuit if the
LDO voltage drops below this reference value (0.5 or 0.75 V programmable). In the case of the
VRUSB3V1 and VRUSB1V8 LDOs, the reference is compared with a divided down voltage (1.5 V typical).
If a short-circuit is detected on VRUSB3V1, the power subchip FSM switches this LDO to sleep mode.
If a short-circuit is detected on VRUSB1V8 or VRUSB1V5, the power subchip FSM switches off the
relevant LDO.
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4.2
Power References
The bandgap voltage reference is filtered (resistance/capacitance [RC] filter) using an external capacitor
connected across the VREF output and an analog ground (REFGND). The VREF voltage is scaled,
distributed, and buffered in the device. The bandgap is started in fast mode (not filtered), and is set
automatically by the power state-machine in slow mode (filtered, less noisy) when required.
Table 4-12 lists the voltage reference characteristics.
Table 4-12. Voltage Reference Characteristics
Parameter
Test Conditions
Min
Typ
Max
Unit
Connected from VREF to GNDREF
0.3
1
2.7
μF
Input voltage
On mode
2.7
3.6
4.5
V
Internal bandgap reference voltage
On mode, measured through TESTV terminal
1.272
1.285
1.298
V
Reference voltage (VREF terminal)
On mode
0.749
0.75
0.77
V
Retention mode reference
On mode
0.492
0.5
0.508
V
0.9
1
1.1
μA
25
20
15
10
10
μA
Output Load Condition
Filtering capacitor
Electrical Characteristics
VIN
IREF NMOS sink
Ground current
Bandgap
IREF block
Preregulator
VREF buffer
Retention reference buffer
Output spot noise
100 Hz
1
A-weighted noise (rms)
P-weighted noise (rms)
Integrated noise
20 to 100 kHz
nV (rms)
150
nV (rms)
<1 MHz from VBAT
4.3.1
0.1
μA
1
ms
60
dB
Start-up time
4.3
μV
2.2
IBIAS trim bit LSB
Ripple rejection
μV/√Hz
200
Power Control
Backup Battery Charger
If the backup battery is rechargeable, it can be recharged from the main battery. A programmable voltage
regulator powered by the main battery allows recharging of the backup battery. The backup battery charge
must be enabled using a control bit register. Recharging starts when two conditions are met:
• Main battery voltage > backup battery voltage
• Main battery > 3.2 V
The comparators of the backup battery system (BBS) give the two thresholds of the backup battery charge
startup. The programmed voltage for the charger gives the end-of-charge threshold. The programmed
current for the charger gives the charge current.
Overcharging is prevented by measurement of the backup battery voltage through the GP ADC.
Table 4-13 lists the characteristics of the backup battery charger.
Table 4-13. Backup Battery Charger Characteristics
Parameter
VBACKUP-to-MADC input attenuation
Test Conditions
VBACKUP from 1.8 to 3.3 V
Min
Typ
Max
0.33
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Table 4-13. Backup Battery Charger Characteristics (continued)
Parameter
Test Conditions
Backup battery charging current
End backup battery charging voltage:
VBBCHGEND
4.3.2
Min
Typ
Max
VBACKUP = 2.8 V, BBCHEN = 1, BBISEL = 00
10
25
45
Unit
μA
VBACKUP = 2.8 V, BBCHEN = 1, BBISEL = 01
105
150
270
μA
VBACKUP = 2.8 V, BBCHEN = 1, BBISEL = 10
350
500
900
μA
VBACKUP = 2.8 V, BBCHEN = 1, BBISEL = 11
0.7
1
1.8
mA
VBACKUP = 0 V, BBCHEN = 1, BBISEL = 00
17.5
25
45
μA
VBACKUP = 0 V, BBCHEN = 1, BBISEL = 01
105
150
270
μA
VBACKUP = 0 V, BBCHEN = 1, BBISEL = 10
350
500
900
μA
VBACKUP = 0 V, BBCHEN = 1, BBISEL = 11
0.7
1
1.8
mA
IVBACKUP = –10 μA, BBSEL = 00
2.4
2.5
2.6
V
IVBACKUP = –10 μA, BBSEL = 01
2.9
3.0
3.1
V
IVBACKUP = –10 μA, BBSEL = 10
3.0
3.1
3.2
V
IVBACKUP = –10 μA, BBSEL = 11
3.1
3.2
3.3
V
Min
Typ
Max
Unit
3.1
3.2
3.3
V
2.55
2.7
2.85
V
2.5
2.5
2.65
2.85
2.95
2.95
V
1.6
1.95
1.8
2.1
2.0
2.25
V
Battery Monitoring and Threshold Detection
4.3.2.1
Power On/Power Off and Backup Conditions
Table 4-14 lists the threshold levels of the battery.
Table 4-14. Battery Threshold Levels
Parameter
Test Conditions
Main battery charged threshold
VMBCH
Measured on VBAT terminal
Main battery low threshold VMBLO
VBACKUP = 3.2 V, measured on VBAT terminal (monitored
on terminal ONNOFF)
Main battery high threshold VMBHI
Measured on terminal VBAT, VBACKUP = 0 V
Measured on terminal VBAT, VBACKUP = 3.2 V
Batteries not present threshold VBNPR Measured on terminal VBACKUP with VBAT < 2.1 V
Measured on terminal VBAT with VBACKUP = 0 V
(monitored on terminal VRRTC)
4.3.3
VRRTC LDO Regulator
The VRRTC voltage regulator is a programmable, low dropout, linear voltage regulator supplying (1.5 V)
the embedded real-time clock (32.768-kHz oscillator) and dedicated I/Os of the digital host counterpart.
The VRRTC regulator is also the supply voltage of the power-management digital state-machine. The
VRRTC regulator is supplied from the UPR line, switched on by the main or backup battery, depending on
the system state. The VRRTC output is present as long as a valid energy source is present. The VRRTC
line is supplied by an LDO when VBAT > 2.7, and a clamp circuit when in backup mode. Table 4-15
describes the regulator characteristics.
Table 4-15. VRRTC LDO Regulator Characteristics
Parameter
Test Conditions
Min
Typ
0.3
1
Max
Unit
Output Load Conditions
Filtering capacitor
Connected from VRTC.OUT to analog ground
Filtering capacitor ESR
20
2.7
μF
600
mΩ
Electrical Characteristics
VIN
Input voltage
On mode
2.7
VBAT
4.5
V
VOUT
Output voltage
On mode
1.45
1.5
1.55
V
46
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Table 4-15. VRRTC LDO Regulator Characteristics (continued)
Parameter
IOUT
Test Conditions
Rated output current
Min
Typ
On mode
Max
Unit
30
mA
Sleep mode
1
DC load regulation
On mode: IOUT = IOUTmax to 0
100
mV
DC line regulation
On mode, VIN = VINmin to VINmax at IOUT = IOUTmax
100
mV
Turn-on time
IOUT = 0, at VOUT = VOUTfinal ± 3%
100
μs
Wake-up time
On mode from low power to On mode, IOUT = 0, at
VOUT = VOUTfinal ± 3%
100
μs
From backup to On mode, IOUT = 0, at VOUT =
VOUTfinal ± 3%
100
Ripple rejection (VRRTC)
f < 10 kHz
50
10 kHz < f < 100 kHz
40
f = 1 MHz
30
dB
VIN = VOUT + 1 V, IO = IMAX
Ground current
On mode, IOUT = 0
70
On mode, IOUT = IOUTmax
100
Sleep mode, IOUT = 0
10
Sleep mode, IOUT = 1 mA
11
Off mode
VDO
(1)
Dropout voltage
(1)
μA
1
On mode, IOUT = IOUTmax
Transient load regulation
ILOAD: IMIN – IMAX
Slew: 40 mA/μs
Transient line regulation
VIN drops 500 mV
Slew: 40 mV/μs
Overshoot
Softstart
Pull down resistance
Default in off mode
–40
250
mV
40
mV
10
mV
3%
250
320
450
Ω
For nominal output voltage
4.4
Power Consumption
Table 4-16 describes the power consumption depending on the use cases.
NOTE
Typical power consumption is obtained in the nominal operating conditions and with the
TPS65920 and TPS65930 devices in stand-alone configuration.
Table 4-16. Power Consumption
Mode
Description
Typical Consumption
Backup
Only the RTC date is maintained with a couple of registers in the backup
domain. No main source is connected. Consumption is on the backup
battery.
VBAT not present
2.25 * 3.2 = 7.2 μW
Wait on
The phone is apparently off for the user, a main battery is present and
well-charged. The RTC registers and registers in the backup domain are
maintained. The wake-up capabilities (such as the PWRON button) are
available.
VBAT = 3.8 V
64 × 3.8 = 243.2 μW
Active no load
The subsystem is powered by the main battery, all supplies are enabled
with full current capability, internal reset is released, and the associated
processor is running.
VBAT = 3.8 V
3291 × 3.8 = 12505 μW
Sleep no load
The main battery powers the subsystem, selected supplies are enabled but
in low-consumption mode, and the associated processor is in low-power
mode.
VBAT = 3.8 V
496 × 3.8 = 1884.4 μW
Power Module
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Table 4-17 lists the regulator states according to the mode in use.
Table 4-17. Regulator State Depending on Use Case
Regulator
48
Mode
Backup
Wait On
Sleep No Load
VAUX2
OFF
OFF
SLEEP
Active No Load
ON
VMMC1
OFF
OFF
OFF
OFF
VPLL1
OFF
OFF
SLEEP
ON
VDAC
OFF
OFF
OFF
OFF
VINTANA1
OFF
OFF
SLEEP
ON
VINTANA2
OFF
OFF
SLEEP
ON
VINTDIG
OFF
OFF
SLEEP
ON
VIO
OFF
OFF
SLEEP
ON
VDD1
OFF
OFF
SLEEP
ON
VDD2
OFF
OFF
SLEEP
ON
VUSB_1V5
OFF
OFF
OFF
OFF
VUSB_1V8
OFF
OFF
OFF
OFF
VUSB_3V1
OFF
OFF
SLEEP
SLEEP
Power Module
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4.5
Power Management
4.5.1
Boot Modes
Table 4-18 lists the modes corresponding to BOOT0–BOOT1.
Table 4-18. BOOT Mode Description
4.5.2
Name
Description
BOOT0
BOOT1
Reserved
0
0
MC027
Master_C027_Generic 01
0
1
MC021
Master_C021_Generic 10
1
0
SC021
Slave_C021_Generic 11
1
1
Process Modes
This parameter defines:
• The boot voltage for the host core
• The boot sequence associated with the process
• The dynamic voltage and frequency scaling (DVFS) protocol associated with the process
4.5.2.1
MC021 Mode
Table 4-19 lists the characteristics of MC021 mode.
Table 4-19. MC021 Mode
Boot core voltage
1.2 V
Power sequence
VIO followed by VPLL1, VDD2, VDD1
SmartReflex IF (I2C HS)
DVFS protocol
4.5.3
Power-On Sequence
4.5.3.1
Timing Before Sequence_Start
Sequence_Start is a symbolic internal signal to ease the description of the power sequences. It occurs
according to the events shown in Figure 4-8.
Power Module
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Vbkup
User_Action
Starting_Event is main battery insertion
Vbat
61 ms - 2 cycle32k
Sequence_Start
Starting_Event is charger insertion
VAC
61 ms - 2 cycle32k
Sequence_Start
Starting_Event is VBUS insertion
Vbus
61 ms - 2 cycle32k
Sequence_Start
Starting_Event is PWRON button
PWRON
Pushbutton debouncing - 30 ms
Sequence_Start
Starting_Event is PWRON rising when device is in slave mode
PWRON
0 ms
Sequence_Start
030-012
Figure 4-8. Timing Before Sequence Start
50
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4.5.3.2
Power-On Sequence
Figure 4-9 describes the timing and control that must occur in the OMAP3 mode. Sequence_Start is a
symbolic internal signal to ease the description of the power sequences. It occurs according to the events
shown in Figure 4-8.
Sequence_Start
4608 ms battery detection
REGEN
1068 ms - 3 MHz oscillator setting + clock switch
VIO
1.8 V
1179 ms for VIO stabilization
VPLL1
1.8 V
1022 ms for LDO stabilization and start dc-dc ramping
VDD2
1.2 V
1099 ms for VDD2 stabilization and VDD1 start ramping
VDD1
1.2 V
1175 ms for VDD1 stabilization
32KCLKOUT
61 ms
SYSEN
1179 ms for VIO stabilization
CLKEN
1953 ms
~ 5.3 ms
HFCLKOUT
61 ms
NRESPWRON
019-072
Figure 4-9. Timings–Power On in OMAP3 Mode
4.5.3.3
Power On in Slave_C021 Mode
Figure 4-10 describes the timing and control that must occur in the Slave_C021 mode. Sequence_Start is
a symbolic internal signal to ease the description of the power sequences and occurs according to the
different events detailed in Figure 4-8
Power Module
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PWRON
4791 ms – 3 MHz oscillator setting + internal reg
REGEN
1068 ms for external supply ramp
VIO
1.8 V
1179 ms for VIO dc-dc stablilization
VPLL1
1.8 V
1022 ms
VDD2
1.2 V
1099 ms for VDD2 stabilization
VDD1
1.2 V
1175 ms for VDD1 stabilization
32KCLKOUT
61 ms
SYSEN
1099 ms for VDD2 stabilization
CLKEN
1953 ms for digital clock setting
HFCLKOUT
64 ms
NRESPWRON
030-022
Figure 4-10. Timings—Power On in Slave_C021 Mode
52
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4.5.4
Power-Off Sequence
This section describes the signal behavior required to power down the system.
4.5.4.1
Power-Off Sequence
Figure 4-11 shows the timing and control that occur during the power-off sequence in master modes.
VBAT
DEVOFF(register)
18 ms
NRESPWRON
1.2 ms
REGEN
18 ms
32KCLKOUT
1.2 ms
DCDCs
1.2 ms
LDOs
18 ms
SYSEN
18 ms
HFCLKOUT
126 ms
CLKEN
3.42 ms before detection of starting event
NEXT_Startup_event
037-055
NOTE: All of these timings are typical values with the default setup (depending on the resynchronization between power
domains, state machinery priority, etc.).
Figure 4-11. Power-Off Sequence in Master Modes
Because of the internal frequency used by Power STM switching from 3 to 1.5 MHz when the HF clock
value is 19.2 MHz, if the HF clock value is not 19.2 MHz (with HFCLK_FREQ bit field values set
accordingly
in
the
CFG_BOOT
register),
the
delay
between
DEVOFF
and
NRESPWRON/CLK32KOUT/SYSEN/HFCLKOUT is divided by two (approximately 9 μs).
The DEVOFF event is PWRON falling edge in slave mode and DEVOFF internal register write in master
mode.
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Real-Time Clock and Embedded Power Controller
The TPS65930 and TPS65920 devices contain an RTC to provide clock and timekeeping functions and an
EPC to provide battery supervision and control.
5.1
RTC
The RTC provides the following basic functions:
• Time information (seconds/minutes/hours) directly in binary-coded decimal (BCD) code
• Calendar information (day/month/year/day of the week) directly in BCD code
• Interrupt generation periodically (1 second/1 minute/1 hour/1 day) or at a precise time (alarm function)
• 32-kHz oscillator drift compensation and time correction
• Alarm-triggered system wake-up event
5.1.1
Backup Battery
The TPS65030 and TPS65920 devices device implement a backup mode in which a backup battery can
keep the RTC running to maintain clock and time information even if the main supply is not present. If the
backup battery is rechargeable, the device also provides a backup battery charger so it can be recharged
when the main battery supply is present.
The backup domain powers the following:
• Internal 32.768-kHz crystal oscillator
• RTC
• Eight general-purpose (GP) storage registers
• Backup domain low-power regulator (VBRTC)
5.2
EPC
The EPC provides five system states for optimal power use by the system, as listed in Table 5-1.
Table 5-1. System States
System State
NO SUPPLY
Description
The system is not powered by any battery.
BACKUP
The system is powered only with the backup battery and maintains
only the VBRTC supply.
WAIT-ON
The system is powered by the main battery and maintains only the
VRRTC supply. It can accept switch-on requests.
ACTIVE
The system is powered by the main battery; all supplies can be
enabled with full current capability.
SLEEP
The main battery powers the system; selected supplies are enabled,
but in low consumption mode.
Three categories of events can trigger state transitions:
• Hardware events: Supply/battery insertion, wake-up requests, USB plug, and RTC alarm
• Software events: Switch-off commands, switch-on commands, and sleep on commands
• Monitoring events: Supply/battery level check, main battery removal, main battery fail, and thermal
shutdown
54
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6
Audio/Voice Module (TPS65930 Device Only)
NOTE
This section applies only to the TPS65930 device.
Figure 6-1 is the audio/voice module block diagram.
HFCLKIN
High-speed
2
I C
(Control)
Audio
TDM/I2S
interface
Main mic
Bias LDOs
Carkit
Speak/mic
Monaural auxiliary
input
Class-D predriver
H-bridge
vibrator
Audio/voice module
Device
037-004
Figure 6-1. Audio/Voice Module Block Diagram
6.1
Audio/Voice Downlink (RX) Module
The audio/voice module includes the following output stages:
• Predriver output signals for external class-D amplifiers (single-ended)
• Vibrator H-bridge
6.1.1
Predriver for External Class-D Amplifier
The external class-D amplifiers provide a stereo signal on terminals PreD.LEFT and PreD.RIGHT to drive
the external class-D amplifier. These terminals are available if a stereo, single-ended, ac-coupled headset
is used.
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Predriver Output Characteristics
Table 6-1 lists the predriver output characteristics.
Table 6-1. Predriver Output Characteristics
Parameter
Test Conditions
Load impedance
Min
Typ
Max
10
kΩ
50
Gain range
(1)
pF
Audio path
–92
30
Voice path
–66
30
–1
Absolute gain error
(2)
1
Peak-to-peak output voltage (0 dBFs)
Default gain
Total harmonic distortion
At 0 dBFs
–80
–75
At –6 dBFs
–74
–69
At –20 dBFs
–70
–65
At –60 dBFs
–30
–25
–90
–85
Default gain
(2)
Load > 10 kΩ // 50 pF
1.5
(3)
Idle channel noise (20 Hz to 20 kHz, A-weighted)
Default gain
Load = 10 Ω
SNR (A-weighted over 20-kHz bandwidth)
At 0 dBFs
Default gain (3)
At –60 dBFs
30
Output PSRR (for all gains)
20 Hz to 4 kHz
90
20 Hz to 20 kHz
70
(1)
(2)
(3)
83
Unit
dB
dB
VPP
88
dB
dB
dB
dB
Audio digital filter = –62 to 0 dB (1-dB steps) and 0 to 12 dB (6-dB steps)
Voice digital filter = –3 to 12 dB (1-dB steps)
ARXPGA (volume control) = –24 to 12 dB (2-dB steps)
Output driver = –6 dB, 0 dB, 6 dB
The default gain setting assumes the ARXPGA has 0-dB gain setting (volume control) and output driver at 0-dB gain setting.
The default gain setting assumes the ARXPGA has 0-dB gain setting (volume control) and output driver at 0-dB gain setting.
6.1.1.2
External Components and Application Schematics
Figure 6-2 is a simplified schematic for the external class-D predriver.
On board
RPR/RPL
Chip
CPL/CPR
PreDriverD
IN+
Class D
(TPA2010D1...)
IN–
Closed to
external
Class C
CPR.O/CPL.O
RPL.O/RPR.O
CPL.M/CPR.M
RPR.M/RPL.M
037-054
Input resistor (RPR or RPL) sets the gain of the external class D. For TPS2010D1, the gain is defined according to the
following equation:
Gain (V/V) = 2*150*103/(RPR or RPL)
RPR or RPL > 15 kΩ
Figure 6-2. Predriver for External Class D
56
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NOTE
For other component values, see Table 14-1.
6.1.2
Vibrator H-Bridge
A digital signal from the pulse width modulated generator is fed to the vibrator H-bridge driver. The vibrator
H-bridge is a differential driver that drives vibrator motors. The differential output allows dual rotation
directions.
6.1.2.1
Vibrator H-Bridge Output Characteristics
Table 6-2 lists the vibrator H-bridge output characteristics.
Table 6-2. Vibrator H-Bridge Output Characteristics
Parameter
Test Conditions
VBAT voltage
Differential output swing (16-Ω load)
Min
Typ
Max
2.8
3.6
4.8
VBAT = 2.8 V
3.6
VBAT = 3.5 V
4.3
Load capacitance
8
16
Load inductance
30
Total harmonic distortion
8
Ω
100
pF
60
Ω
300
μH
10%
Operating frequency
6.1.2.2
V
VPP
Output resistance (summed for both sides)
Load resistance
Unit
20
10k
Hz
External Components and Application Schematics
Figure 6-3 is a simplified vibrator H-bridge schematic.
On board
VBAT
Chip
VBAT.RIGHT
CV.V
Ferrite cheap bead
LV.P
VIBRA.P
CV.P
Vibrator
Ferrite cheap bead
LV.M
VIBRA.M
CV.M
VIBRA.GND (LED.GND)
037-053
Figure 6-3. Vibrator H-Bridge
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NOTE
For other component values, see Table 14-1.
Example of ferrite: BLM 18BD221SN1.
6.1.3
Carkit Output
The USB-CEA carkit uses the DP/DM pad to output audio signals (see the CEA-936–Mini-USB Analog
Carkit specification).
Figure 6-4 shows the carkit output downlink full path characteristics for audio and USB.
Digital PGA
gain = 0 dB
0 dBFs
Amp
0 dB
Analog PGA
gain = 0 dB
DAC
USB
Amp
–0.6 dB
1.35 VPP
037-052
Figure 6-4. Carkit Output Downlink Path Characteristics
Table 6-3 lists the USB-CEA carkit audio downlink electrical characteristics.
Table 6-3. USB-CEA Carkit Audio Downlink Electrical Characteristics
Parameter
Conditions
Output load
Gain range
USB-CEA (DP/DM)
(1)
Min
Typ
Max
20
kΩ
Audio path
–92
30
Voice path
–66
30
–1
1
Absolute gain error
At 1 kHz
Peak-to-peak differential output voltage (0 dBFs)
Gain = 0 dB
1.5
Total harmonic distortion
At 0 dBFs
–80
–75
At –6 dBFs
–74
–69
At –20 dBFs
–70
–65
At –60 dBFs
–30
–25
THD+N (20 Hz to 20 kHz, A-weighted)
At 0 dBFs
Idle channel noise (20 Hz to 20 kHz, A-weighted)
Default gain (2)
Output PSRR
20 Hz to 20 kHz
–90
60
1.3
Isolation between D+/D– during audio mode (20 Hz to 20 kHz)
USB-CEA stereo
Crosstalk RX/Tx (1 VPP output)
USB-CEA mono/stereo
Signal noise ratio (20 Hz to 20 kHz, A-weighted)
At 0 dBFs
Phone speaker amplifier output impedance at 1 kHz
USB-CEA (DP/DM)
(2)
58
dB
dB
dB
V
1.4
60
Crosstalk between right and left channels
(1)
1.35
dB
dB
–85
1.5
Common mode output voltage for USB-CEA
dB
VPP
60
Supply voltage (Vintana1)
Unit
V
dB
–90
dB
–60
60
dB
dB
200
Ω
Audio digital filter = –62 to 0 dB (1-dB steps) and 0 to 12 dB (6-dB steps)
Voice digital filter = –36 to 12 dB (1-dB steps)
ARXPGA (volume control) = –24 to 12 dB (2-dB steps)
Output driver (USB-CEA) = –1 dB
The default gain setting assumes the ARXPGA has 0-dB gain setting (volume control) and output driver at 0.6-dB gain setting.
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6.1.4
Digital Audio Filter Module
Figure 6-5 shows the digital audio filter downlink full path characteristics for the audio interface.
High-pass
filter
Audio interface
Low-pass
Filter
Digital
modulator
Randomizer
DAC
037-051
Figure 6-5. Digital Audio Filter Downlink Path Characteristics
The HPF can be bypassed. It is controlled by the MISC_SET_2 ARX_HPF_BYP bit set to address 0x49.
Table 6-4 lists the audio filter frequency responses relative to reference gain at 1 kHz.
Table 6-4. Digital Audio Filter RX Electrical Characteristics
Parameter
Conditions
Min
Passband
Passband ripple
0 to 0.42FS
(1)
–0.25
Stopband
Stopband attenuation
F = 0.6FS
(1)
to 0.8FS
(1)
0.1
Max
Unit
0.25
dB
FS
75
dB
15.8/FS
–1.4
Linear phase
FS
0.6
60
Group delay
(1)
Typ
0.42
(1)
μs
1.4
°
FS is the sampling frequency (8, 11.025, 12, 16, 22.05, 24, 32, 44.1, or 48 kHz).
6.1.5
Boost Stage
The boost effect adds emphasis to low frequencies. It compensates for a HPF created by the capacitor
resistor (CR) filter of the headset (in ac-coupling configuration).
There are four modes. Three effects are available, with slightly different frequency responses, and the
fourth setting disables the boost effect:
• Boost effect 1
• Boost effect 2
• Boost effect 3
• Flat equalization: The boost effect is in bypass mode.
NOTE
Boost effect modes are defined in Table 6-5.
Table 6-5 and Table 6-6 include the typical values according to the frequency response versus input
frequency and FS frequency.
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Table 6-5. Boost Electrical Characteristics Versus FS Frequency (FS ≤ 22.05 kHz)
FS = 8 kHz
FS = 11.025 kHz
FS = 12 kHz
FS = 16 kHz
FS = 22.05 kHz
Frequency
(Hz)
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
10
4.51
5.13
5.62
5.10
5.51
5.80
5.22
5.58
5.83
5.54
5.77
5.92
5.76
5.89
5.97
12
4.08
4.83
5.46
4.80
5.32
5.71
4.95
5.41
5.76
5.36
5.66
5.87
5.65
5.83
5.94
15.2
3.43
4.32
5.18
4.28
4.97
5.54
4.47
5.11
5.61
5.03
5.47
5.79
5.45
5.71
5.90
18.2
2.91
3.86
4.89
3.82
4.63
5.36
4.04
4.80
5.45
4.71
5.26
5.69
5.24
5.59
5.84
20.5
2.56
3.53
4.65
3.49
4.37
5.21
3.72
4.56
5.32
4.45
5.09
5.60
5.06
5.49
5.79
29.4
1.62
2.49
3.78
2.45
3.42
4.57
2.68
3.74
4.73
3.51
4.39
5.24
4.35
5.02
5.59
39.7
1.05
1.71
2.93
1.67
2.55
3.84
1.88
2.80
4.06
2.66
3.63
4.72
3.67
4.45
5.27
50.4
0.71
1.20
2.26
1.17
1.91
3.17
1.33
2.13
3.41
2.01
2.95
4.19
2.89
3.85
4.88
60.3
0.51
0.92
1.79
0.89
1.49
2.65
1.00
1.68
2.89
1.57
2.43
3.72
2.39
3.35
4.52
76.7
0.32
0.61
1.26
0.59
1.05
1.99
0.69
1.18
2.22
1.11
1.79
3.04
1.76
2.66
3.94
97.5
0.20
0.39
0.87
0.38
0.70
1.43
0.44
0.79
1.62
0.75
1.27
2.36
1.24
2.00
3.28
131.5
0.12
0.21
0.50
0.20
0.39
0.88
0.25
0.47
1.02
0.42
0.78
1.59
0.75
1.30
2.41
157
0.08
0.15
0.36
0.15
0.28
0.65
0.17
0.33
0.75
0.31
0.57
1.22
0.55
0.99
1.93
200
0.05
0.09
0.22
0.09
0.17
0.41
0.11
0.21
0.49
0.19
0.37
0.82
0.36
0.66
1.38
240
0.03
0.06
0.15
0.06
0.12
0.29
0.07
0.14
0.35
0.14
0.26
0.60
0.25
0.48
1.04
304
0.02
0.04
0.09
0.04
0.07
0.18
0.04
0.09
0.22
0.08
0.16
0.38
0.16
0.30
0.70
463
0.00
0.01
0.03
0.01
0.03
0.07
0.02
0.04
0.09
0.03
0.07
0.17
0.07
0.13
0.32
704
0.00
0.00
0.01
0.00
0.01
0.03
0.01
0.01
0.03
0.01
0.03
0.07
0.03
0.06
0.14
1008
0.00
0.00
0.00
0.00
0.00
0.01
0.00
0.00
0.01
0.00
0.01
0.03
0.01
0.02
0.06
1444
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.01
0.02
2070
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.01
3770
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
Unit
dB
Table 6-6. Boost Electrical Characteristics Versus FS Frequency (FS ≥ 24 kHz)
FS = 24 kHz
FS = 32 kHz
FS = 44.1 kHz
FS = 48 kHz
FS = 96 kHz
Frequency
(Hz)
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
10
5.79
5.90
5.97
5.89
5.89
5.99
5.95
5.98
6.04
5.96
5.99
6.01
5.71
5.83
5.90
12
5.70
5.85
5.95
5.84
5.84
5.98
5.92
5.97
6.03
5.94
5.98
6.00
5.54
5.68
5.81
15.2
5.53
5.76
5.91
5.73
5.73
5.96
5.87
5.94
6.02
5.89
5.95
5.99
5.40
5.57
5.73
18.2
5.35
5.65
5.87
5.62
5.62
5.93
5.80
5.90
6.00
5.83
5.93
5.98
5.28
5.48
5.68
20.5
5.19
5.56
5.83
5.52
5.52
5.91
5.74
5.87
5.99
5.78
5.90
5.97
5.19
5.42
5.64
29.4
4.55
5.18
5.64
5.10
5.07
5.79
5.51
5.75
5.94
5.57
5.79
5.92
4.87
5.18
5.48
39.7
3.81
4.62
5.37
4.52
4.52
5.64
5.12
5.53
5.85
5.26
5.59
5.84
4.47
4.91
5.30
50.4
3.14
4.06
5.02
3.94
3.95
5.43
4.69
5.27
5.72
4.88
5.37
5.73
4.08
4.63
5.11
60.3
2.62
3.51
4.69
3.46
3.54
5.21
4.30
5.00
5.59
4.49
5.13
5.62
3.72
4.37
4.95
76.7
1.97
2.90
4.15
2.76
2.76
4.78
3.68
4.52
5.34
3.91
4.70
5.40
3.18
3.92
4.67
97.5
1.41
2.22
3.51
2.10
2.09
4.27
2.99
3.94
4.99
3.24
4.15
5.07
2.59
3.41
4.33
131.5
0.88
1.49
2.65
1.40
1.40
3.49
2.15
3.10
4.35
2.38
3.35
4.51
1.86
2.69
3.75
157
0.65
1.13
2.15
1.04
1.04
2.96
1.70
2.58
3.90
1.90
2.82
4.08
1.47
2.24
3.35
200
0.41
0.76
1.55
0.70
0.70
2.28
1.19
1.93
3.23
1.35
2.15
3.44
1.03
1.68
2.77
240
0.30
0.55
1.18
0.50
0.50
1.81
0.89
1.51
2.71
1.02
1.70
2.92
0.77
1.31
2.32
304
0.18
0.35
0.80
0.33
0.32
1.27
0.58
1.04
2.05
0.68
1.19
2.24
0.51
0.90
1.75
463
0.08
0.16
0.37
0.14
0.14
0.64
0.27
0.50
1.12
0.31
0.58
1.25
0.23
0.43
0.95
60
704
0.03
0.06
0.16
0.06
0.06
0.29
0.12
0.23
0.56
0.14
0.27
0.62
0.10
0.20
0.46
1008
0.01
0.03
0.07
0.03
0.02
0.14
0.06
0.11
0.30
0.06
0.13
0.31
0.05
0.10
0.23
1444
0.00
0.01
0.03
0.01
0.01
0.06
0.03
0.05
0.16
0.03
0.06
0.15
0.02
0.05
0.11
2070
0.00
0.00
0.01
0.00
0.00
0.02
0.01
0.02
0.09
0.01
0.03
0.07
0.01
0.02
0.05
3770
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.04
0.00
0.00
0.01
0.00
0.00
0.01
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6.2
Audio Uplink (TX) Module
The audio uplink path includes two input amplification stages:
• MIC_MAIN_P, MIC_MAIN_M (differential main handset input)
• AUXR (common terminal: single-ended auxiliary)
NOTE
If two audio inputs are needed, and mic bias is not needed, the AUXR input can be used
with MIC_MAIN to provide the two inputs.
6.2.1
Microphone Bias Module
A bias generator provides an external voltage of 2.2 V to bias the analog microphones (MICBIAS1
terminal). The typical output current is 1 mA.
6.2.1.1
Analog Microphone Bias Module Characteristics
Table 6-7 lists the characteristics of the analog microphone bias module.
Table 6-7. Analog Microphone Bias Module Characteristics With Bias Resistor
Parameter
Test Conditions
Bias voltage
Min
Typ
Max
Unit
2.15
2.2
2.25
V
Load current
1
Output noise
P-weighted 20 Hz to 6.6 kHz
1.8
External capacitor
0
Internal resistance
50
60
mA
μVRMS
200
pF
70
kΩ
NOTE
If the external capacitor is higher than 200 pF, the analog microphone bias becomes
unstable. To stabilize it, add a serial resistor.
Table 6-8 lists the characteristics of the analog microphone bias module with a bias resistor.
Table 6-8. Analog Microphone Bias Module Characteristics With Bias Resistor
Parameter
RSB
RB + RSB
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Test Conditions
Min
CB < 200 pF
0
CB = 100 pF
300
CB = 1 μF
500
Typ
Max
Unit
Ω
2.2 to 2.7
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Figure 6-6 and Figure 6-7 show the external components and application schematics for the analog
microphone.
Device
On board
RMM.O
MICBIAS1.OUT
CMM.B
CMM.P
MIC.MAIN.P
RMM.MP
MIC.MAIN.M
CMM.M
CMM.O
MICBIAS.GND
037-005
Figure 6-6. Analog Microphone Pseudodifferential
NOTE
For other component values, see Table 14-1.
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ON BOARD
Device
RMM.BP
MICBIAS1.OUT
RMM.GM /2
CMM.B
CMM.P
MIC.MAIN.P
47pF
CMM.PM
Close to
Device
Close to
Device
MIC.MAIN.M
CMM.M
CMM.GM
RMM.GM /2
CMM.GP
MICBIAS.GND
037-006
Figure 6-7. Analog Microphone Differential
NOTE
For other component values, see Table 14-1.
NOTE
To improve the rejection, ensure that MICBIAS_GND is as clean as possible. This ground
must be shared with AGND of the TPS65920 or TPS65930 device and must not share with
AVSS4, which is the ground used by RX class AB output stages.
In differential mode, adding a low-pass filter (made by RSB and CB) is highly recommended if
coupling between RX output stages and the microphone is too high (and not enough
attenuation by the echo cancellation algorithm). The coupling can come from:
• The internal TPS65920/TPS65930 coupling between MICBIAS.OUT voltage and RX
output stages
• Coupling noise between MICBIAS.GND and AVSS4
In pseudodifferential mode, the dynamic resistance of the microphone improves the rejection
versus MICBIAS.OUT:
PSRR = 20*log((RB + RDyn_mic)/RB).
6.2.1.2
Silicon Microphone Module Characteristics
Based on silicon micro-electrical-mechanical system (MEMS) technology, the new microphone achieves
the same acoustic and electrical properties as conventional microphones, but is more rugged and exhibits
higher heat resistance. These properties offer designers of a wide range of products greater flexibility and
new opportunities to integrate microphones.
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The silicon microphone is the integration of mechanical elements and electronics on a common silicon
substrate through microfabrication technology.
The complementary metal oxide semiconductor (CMOS) MEMS microphone is more like an analog IC
than a classical microphone, or electric condenser microphone (ECM). It is powered as an IC with a direct
connection to the power supply. The on-chip isolation between the power input and the rest of the system
adds power supply rejection (PSR) to the component. This makes the CMOS MEMS microphone
inherently more immune to power supply noise than an ECM and eliminates the need for additional
filtering circuitry to keep the power supply line clean.
Table 6-9 lists the characteristics of the silicon microphone module.
Table 6-9. Silicon Microphone Module Characteristics
Parameter
Test Conditions
Min
Bias voltage
Typ
Max
Unit
1
mA
2.2
Load current
Output noise
P-weighted 20 Hz to 6.6 kHz
V
1.8
μVRMS
Figure 6-8 is a schematic for the silicon microphone.
Optional
depending on
dynamic of MIC
On board
1 kW
Device
RSM
MICBIAS1.OUT
CSM
CSM.P
Silicon MIC
SPM0204HE5-PB
(SPM0102ND3-C)
MIC.MAIN.P
4
1
Power Output
GND GND
3
2
CSM.PG
MIC.MAIN.M
CSM.M
MICBIAS.GND
037-007
Figure 6-8. Silicon Microphone
NOTE
For other component values, see Table 14-1.
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6.2.2
FM Radio/Auxiliary Input
The auxiliary input AUXR/FMR can be used as FM radio input. The amplification stage output is
connected to the ADC input. The FM radio input can also be output through an audio output stage.
6.2.2.1
External Components
Figure 6-9 shows the external components on the auxiliary input.
On board
Chip
CAUXR
AUXR
CAUXR.M
037-008
Figure 6-9. Audio Auxiliary Input
NOTE
For other component values, see Table 14-1.
6.2.3
Uplink Characteristics
Figure 6-10 shows the uplink amplifier. Table 6-10 lists the uplink characteristics.
Amp
0 to 30 dB
ADC
Digital PGA
gain = 0 to 31 dB
037-050
Figure 6-10. Uplink Amplifier
Table 6-10. Uplink Characteristics
Parameter
Speech delay
Test Conditions
Voice path
Gain range (1)
Absolute gain
0 dBFs at 1.02 kHz
Peak-to-peak differential input voltage (0 dBFs)
For differential input
0 dB gain setting
(1)
Min
Typ
Max
0.5
Unit
ms
0
61
–1
1
dB
dB
1.5
VPP
Gain range is defined by: Preamplifier = 0 to 30 dB; Filter = 0 to 31 dB (1-dB steps)
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Table 6-10. Uplink Characteristics (continued)
Parameter
Test Conditions
Peak-to-peak single-ended input voltage (0 dBFs)
Min
Input impedance (2)
Idle channel noise
Crosstalk A/D to D/A
Max
Unit
1.5
VPP
70k
Ω
At –1 dBFs
–80
–75
dB
At –6 dBFs
–74
–69
At –10 dBFs
–70
–65
At –20 dBFs
–60
–55
At –60 dBFs
–20
–15
20 Hz to 20 kHz, A-weighted, gain = 0 dB
–85
–78
16 kHz: < 20 Hz to 7 kHz, gain = 0 dB
–90
8 kHz: P-weighted voice, gain = 18 dB
–87
16 kHz: < 20 Hz to 7 kHz, gain = 18 dB
–82
40k
Total harmonic distortion (sine wave at 1.02 kHz)
–80
Gain = 0 dB
Intermodulation distortion
dB
–60
2-tone method
dBFs
dB
–70
Crosstalk path between two microphones
(2)
Typ
For single-ended input
0 dB gain setting
dB
Impedance varies in the specified range with gain selection.
6.2.4
Microphone Amplification Stage
The microphone amplification stages perform the single-to-differential conversion for single-ended inputs.
Two programmable gains from 0 dB to 30 dB can be set:
• Automatic level control for main microphone input. The gain step is 1 dB.
• Level control by register for line-in or carkit input. The gain step is 6 dB.
The amplification stage outputs are connected to the ADC input (ADC left and right).
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6.2.5
Carkit Input
The USB-CEA carkit uses the DP pad to input the audio signal.
Figure 6-11 shows the uplink carkit full path uplink characteristics for audio and USB.
Amp
CEA
–1.02 dB
Amp
0 to
30 dB
ADC
Digital PGA
gain = 0 to 31 dB
037-009
Figure 6-11. Carkit Input Uplink Path Characteristics
Table 6-11 lists the USB-CEA carkit audio electrical characteristics.
Table 6-11. USB-CEA Carkit Audio Uplink Electrical Characteristics
Parameter
Gain range
Test Conditions
(1)
Typ
–1
Absolute gain, 0 dBFs at 1.02 kHz
(1) (2)
USB-CEA default gain setting
Speech delay
Input common mode voltage
Min
(3)
60
–1.5
Voice path
Max
1.5
0.5
USB-CEA
1.3
Phone microphone amplifier input impedance at 1 kHz
USB-CEA
8
Peak-to-peak single-ended input voltage (0 dBFs)
Default setting
Total harmonic distortion (sine wave at 1 kHz), default gain setting
At –1 dBFs
dB
dB
ms
1.9
120
–74
Unit
V
kΩ
1.414
VPP
–60
dB
At –6 dBFs
At –10 dBFs
At –20 dBFs
At –60 dBFs
THD+N (20 Hz to 20 kHz, A-weighted)
At 0 dBFs
60
dB
Signal noise ratio (20 Hz to 20 kHz, A-weighted)
At 0 dBFs
60
dB
Idle channel noise (20 Hz to 20 kHz, A-weighted), default gain
setting
USB-CEA
–77
Output PSRR (20 Hz to 20 kHz, A-weighted)
USB-CEA
50
(1)
(2)
(3)
dBFs
dB
Gain range is defined by: CEA amplifier = 0.56 to –1.02 dB; Preamplifier = 0 to 30 dB; Filter = 0 to 31 dB (1-dB steps).
The CEA default gain setting assumes 0 dB on the preamplifier, 1 dB on digital filter, and CEA amplifier at –1.02 dB.
Full-scale input voltage is 1 V minimum.
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Digital Audio Filter Module
Figure 6-12 shows the digital audio filter uplink full path characteristics for the audio interface.
A/D output
Error
cancellation
SINC filter
differentiator
4th order
SINC filter
integrator
4th order
1st order highpass filter
Low-pass
filter
Audio
interface
037-017
Figure 6-12. Digital Audio Filter Uplink Path Characteristics
The high-pass filter (HPF) can be bypassed. It is controlled by the MISC_SET_2 ATX_HPF_BYP bit set to
address 0x49.
Table 6-12 lists the audio filter frequency responses relative to reference gain at 1 kHz.
Table 6-12. Digital Audio Filter TX Electrical Characteristics
Parameter
Test Conditions
Passband
Passband gain
In region 0.0005*FS to 0.42*FS
(1)
Stopband
Stopband attenuation
In region 0.6*FS to 1*FS
(1)
Group delay
(1)
68
Min
Typ
Max
Unit
0.0005
0.42
FS
–0.25
0.25
dB
0.6
FS
60
dB
15.8/FS
μs
FS is the sampling frequency (8, 11.025, 12, 16, 22.05, 24, 32, 44.1, or 48 kHz).
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7
USB Transceiver
7.1
USB Transceiver
The TPS65920/TPS65930 device includes a USB OTG transceiver with the CEA carkit interface that
supports USB 480 Mbps HS, 12 Mbps full-speed (FS), and USB 1.5 Mbps low-speed (LS) through a 4-pin
ULPI.
The carkit block ensures the interface between the phone and a carkit device. The TPS65920/TPS65930
USB supports the CEA carkit standard.
Figure 7-1 is a block diagram of the USB 2.0 physical layer (PHY).
USB OTG device
Free headset
UART control
Audio accessory
OMAP
(LINK)
Device
USB PHY
ULPI
Phone connector
(USB)
PC
ADC inputs
(optional)
Carkit
037-011
Figure 7-1. USB 2.0 PHY Block Diagram
7.1.1
Features
The device has a USB OTG carkit transceiver that allows system implementation that complies with the
following specifications:
• Universal Serial Bus 2.0 Specification
• On-The-Go Supplement to the USB 2.0 Specification
• CEA-2011: OTG Transceiver Interface Specification
• CEA-936A: Mini-USB Analog Carkit Specification
• UTMI+ Low Pin Interface Specification
The features of the individual specifications are:
• Universal Serial Bus 2.0 Specification (hereafter referred to as the USB 2.0 specification):
– 5-V-tolerant data line at HS/FS, FS-only, and LS-only transmission rates
– 7-V-tolerant video bus (VBUS) line
– Integrated data line serial termination resistors (factory-trimmed)
– Integrated data line pullup and pulldown resistors
– On-chip 480-MHz phase-locked loop (PLL) from the internal system clock (19.2, 26, and 38.4 MHz)
– Synchronization (SYNC)/end-of-period (EOP) generation and checking
– Data and clock recovery from the USB stream
– Bit-stuffing/unstuffing and error detection
– Resume signaling, wakeup, and suspend detection
– USB 2.0 test modes
• On-The-Go Supplement to the USB 2.0 Specification (hereafter referred to as the OTG supplement to
the USB 2.0 specification):
– 3-pin LS/FS serial mode (DAT_SE0)
– 4-pin LS/FS serial mode (VP_VM)
• CEA-936A: Mini-USB Analog Carkit Interface Specification:
– 5-pin CEA mini-USB analog carkit interface
USB Transceiver
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– UART signaling
– Audio (mono/stereo) signaling
– UART transactions during audio signaling
– Basic and smart 4-wire/5-wire carkit, chargers, and accessories
– ID CEA resistor comparators
UTMI+ Low Pin Interface Specification (hereafter referred to as the ULPI specification):
– 12-pin ULPI with 8-pin parallel data for USB signaling and register access
– 60-MHz clock generation
– Register mapping
Figure 7-2 is the USB system application schematic.
VBAT
C VBUS.FC C VINTUSB.1P8
C VBUS.IN
C VBAT.USB
.*
C VINTUSB.1P5
V U S B.3P 1
V IN TU S B.1P 5
C P.C A P N
C P.C A P P
C P.IN
C P.G N D
V IN TU S B.1P 8
C VUSB.3P1
CP.OUT
UCLK
USB CP
STP
Device
ID
DIR
DP/UART3.RXD
NXT
DATA0/RX
DATA1/TX
Host processor
DM/UART3.TXD
USB 2.0
HS-OTG
transceiver
with CEA
carkit interface
VBUS
USB-CEA
carkit
connector
GND
DATA2/RTSI
DATA3/CTSO
C VBUS1
DATA4
C VBUS2
DATA5
DATA6
DATA7
037-012
Figure 7-2. USB System Application Schematic
NOTE
For the component values, see Table 14-1.
7.1.2
HS USB Port Timing
The ULPI interface supports an 8-bit data bus and the internal clock mode. The 4-bit data bus and the
external clock mode are not supported.
The HS functional mode supports an operating rate of 480 Mbps.
Table 7-1 and Table 7-2 assume testing over the recommended operating conditions (see Figure 7-3).
70
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HSU0
HSU1
HSU1
UCLK
HSU5
HSU4
STP
HSU2
HSU2
DIR_&_NXT
HSU3
HSU6
HSU3
DATA[7:0]
Data_OUT
HSU7
Data_IN
037-049
Figure 7-3. HS-USB Interface—Transmit and Receive Modes (ULPI 8-bit)
NOTE
ULPI data [7:0] lines are set to 1 after USB PHY power up, and before the clock signal is
stable.
The input timing requirements are given by considering a rising or falling time of 1 ns (see Table 7-1).
Table 7-1. HS-USB Interface Timing Requirements
Notation
Parameter
Min
Max
Unit
HSU4
ts(STPV-CLKH)
Setup time, STP valid before UCLK rising
edge
6
ns
HSU5
th(CLKH-STPIV)
Hold time, STP valid after UCLK rising edge
0
ns
HSU6
ts(DATAV-CLKH)
Setup time, DATA[0:7] valid before UCLK
rising edge
6
HSU7
th(CLKH-DATIV)
Hold time, DATA[0:7] valid after UCLK rising
edge
0
ns
ns
Table 7-2 lists the HS-USB interface switching requirements.
Table 7-2. HS-USB Interface Switching Requirements (1)
Parameter (1)
Notation
Min
Typ
Max
Unit
HSU0
fp(CLK)
UCLK clock frequency
Steady state
58.42
60
61.67
MHz
HSU1
tW(CLK)
UCLK duty cycle
Steady state
48.3%
50%
51.7%
td(CLKH-DIR)
Delay time, UCLK rising edge to
DIR transition
Steady state
0
9
td(CLKH-NXTV)
Delay time, UCLK rising edge to
NXT transition
Steady state
0
9
td(CLKH-DATV)
Delay time, UCLK rising edge to
DATA[0:7] transition
Steady state
0
9
HSU2
HSU3
(1)
ns
ns
ns
The capacitive load for output data and control load is 10 pF (rising and falling time is 2 ns).
The capacitive load for the CLK port is 6 pF (rising and falling time is 1 ns).
The HS-USB interface has only one state: the steady state.
7.1.3
USB-CEA Carkit Port Timing
This mode allows the link for communication through the USB PHY to a remote carkit in CEA audio + data
during audio (DDA) mode as defined in the CEA-936A specification. In this mode, the ULPI data bus is
redefined as a 2-pin UART interface, which exchanges data through a direct access to the FS/LS analog
transmitter and receiver.
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UART data are sent and received on the USB D+/D– pads. D+/D– are also used in this mode to carry
audio I/O signals.
Table 7-3 assumes testing over the recommended operating conditions (see the CEA-936A specification).
Table 7-3. USB-CEA Carkit Interface Timing Parameters
Parameter
Min
Max
Unit
tPH_DP_CON
Phone D+ connect time
100
tCR_DP_CON
Carkit D+ connect time
150
ms
tPH_DM_CON
Phone D– connect time
tPH_CMD_DLY
Phone command delay
tPH_MONO_ACK
Phone mono acknowledge
tPH_DISC_DET
Phone D+ disconnect time
150
tCR_DISC_DET
Carkit D– disconnect detect
50
tPH_AUD_BIAS
Phone audio bias
tCR_AUD_DET
Carkit audio detect
400
800
tCR_UART_DET
Carkit UART detect (data-during-audio enabled)
700
1200
ns
tPH_STLO_DET
Phone stereo D+ low detect
30
100
ms
tPH_PLS_POS
Phone D– interrupt pulse width
200
600
ns
tCR_PLS_NEG
Carkit D+ interrupt pulse width
200
600
ns
tDAT_AUD_POL
Data-during-audio polarity
20
60
ms
tACC_COL_DET
Accessory ID collision detect
2
3
ms
tACC_INT_PW
Accessory ID interrupt pulse width
200
400
μs
tACC_INT_WAIT
Accessory ID interrupt wait time
10
15
ms
tACC_CMD_WAIT
Accessory ID command wait time
0
tPH_INT_PW
Phone ID interrupt pulse width
4
8
ms
tPH_INT_WAIT
Phone ID interrupt wait time
4
8
ms
tPH_CMD_WAIT
Phone ID command wait time
0
ms
tPH_UART_RPT
Phone command repeat time
50
ms
tCR_UART_RSP
Carkit UART response
tCR_INT_RPT
Carkit interrupt repeat time
fUART_DFLT
Default UART signaling rate (typical rate)
300
ms
10
ms
2
ms
10
ms
ms
150
1
ms
ms
μs
ms
30
ms
9600
bps
50
ms
Figure 7-4 shows the USB-CEA carkit UART data flow.
ULPI
Device
USB-CEA connector
DATA0: UART_TX
DP/RXD/MIC
DATA1: UART_RX
DM/TXD/SPKR
037-048
Figure 7-4. USB-CEA Carkit UART Data Flow
Table 7-4 lists the USB-CEA carkit UART timings.
72
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Table 7-4. USB-CEA Carkit UART Timings
Notation
Parameter
Min
Max
Unit
CK1
td(UART_TXH-DM)
Delay time, UART_TX rising edge to DM transition
4.0
11
ns
CK2
td(UART_TXL-DM)
Delay time, UART_TX falling edge to DM transition
4.0
11
ns
205
234
CK3
td(DPH-UART_RX)
Delay time, DP rising edge to UART_RX
transition
At 38.4 MHz
At 19.2 MHz
310
364
CK4
td(DPL-UART_RX)
Delay time, DP falling edge to UART_RX
transition
At 38.4 MHz
205
234
At 19.2 MHz
310
364
ns
ns
Figure 7-5 shows the USB-CEA carkit UART timings.
UART_TX
CK1
CK2
CK3
CK4
DM
DP
UART_RX
037-047
Figure 7-5. USB-CEA Carkit UART Timings
7.1.4
PHY Electrical Characteristics
The PHY is the physical signaling layer of the USB 2.0. It contains the drivers and receivers for physical
data and protocol signaling on the DP and DM lines.
The PHY interfaces with the USB controller through the UTMI.
The transmitters and receivers in the PHY are of two main classes:
• FS and LS transceivers (legacy USB1.x transceivers)
• HS transceivers
To bias the transistors and run the logic, the PHY also contains reference generation circuitry which
consists of:
• A DPLL that does a frequency multiplication to achieve the 480-MHz low-jitter lock necessary for USB,
and the clock required for the switched capacitor resistance block
• A switched capacitor resistance block that replicates an external resistor on chip
Built-in pullup and pulldown resistors are used as part of the protocol signaling.
The PHY also contains circuitry that protects it from an accidental 5-V short on the DP and DM lines and
from 8-kV IEC ESD strikes.
7.1.4.1
HS Differential Receiver
The HS receiver consists of the following blocks:
• A differential input comparator to receive the serial data
• A squelch detector to qualify the received data
• An oversampler-based clock data recovery scheme followed by a nonreturn to zero inverted (NRZI)
decoder, bit unstuffing, and serial-to-parallel converter to generate the UTMI DATAOUT
Table 7-5 lists the characteristics of the HS differential receiver.
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Table 7-5. HS Differential Receiver
Parameter
Comments
Min
Typ
Max
Unit
Input Levels for HS
HS squelch detection threshold
VHSSQ
(Differential signal amplitude)
100
125
150
mV
HS disconnect detection threshold
VHSDSC
(Differential signal amplitude)
525
600
625
mV
HS data signaling common mode voltage
range
VHSCM
–50
200
500
mV
HS differential input sensitivity
VDIHS
100
mV
(Differential signal amplitude)
–100
Input Impedance for HS
Internal specification for input capacitance
CHSLOAD
11
pF
Internal CHSLOAD DP/DM matching
CHSLOADM
0.2
pF
External Components With the Total Budget Combined (without USB cable load)
External capacitance on DP or DM
2
pF
External series resistance on DP or DM
1
Ω
7.1.4.2
HS Differential Transmitter
The HS transmitter is always operated on the UTMI parallel interface. The parallel data on the interface is
serialized, bit stuffed, NRZI encoded, and transmitted as a dc output current on DP or DM, depending on
the data. Each line has an effective 22.5-Ω load to ground, which generates the voltage levels for
signaling.
A disconnect detector is also part of the HS transmitter. A disconnect on the far end of the cable causes
the impedance seen by the transmitter to double, thereby doubling the differential amplitude seen on the
DP/DM lines.
Table 7-6 lists the characteristics of the HS differential transmitter.
Table 7-6. HS Differential Transmitter
Parameter
Comments
Min
Typ
Max
Unit
Output Levels for HS
HS TX idle level
VHSOI
Absolute voltage DP/DM – internal/external 45 Ω
–10
0
10
mV
HS TX data signaling high
VHSOH
Absolute voltage DP/DM – internal/external 45 Ω
360
400
440
mV
HS data signaling low
VHSOL
–10
0
10
mV
Chirp J level
VCHIRPJ
Differential voltage
700
800
1100
mV
Chirp K level
VCHIRPK
Differential voltage
–900
–800
–500
mV
HS TX disconnect threshold
VDISCOUT
Absolute voltage DP/DM – no external 45 Ω
700
mV
Driver Characteristics
Rise time
tHSR
(10%–90%)
500
ps
Fall time
tHSF
(10%–90%)
500
ps
Driver output resistance
ZHSDRV
Also serves as HS termination
40.5
74
USB Transceiver
45
49.5
Ω
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7.1.4.3
CEA/UART Driver
Table 7-7 lists the characteristics of the CEA/UART driver.
Table 7-7. CEA/UART Driver
Parameter
Comments
Min
Typ
Max
Unit
1
μs
2.4
3.3
3.6
V
0
0.1
0.4
V
UART Driver CEA
Phone UART edge rates
tPH_UART_EDGE
DP_PULLDOWN asserted
Serial interface output high
VOH_SER
ISOURCE = 4 mA
Serial interface output low
VOL_SER
ISINK = –4 mA
Pulse match tolerance
QPLS_MTCH
ZCR_SPKR_IN = 60 kΩ at f = 1 kHz
Phone D– interrupt pulse
width
tPH_PLS_POS
ZCR_SPKR_IN = 60 kΩ at f = 1 kHz
200
600
ns
Phone positive pulse voltage
VPH_PLS_POS
ZCR_SPKR_IN = 60 kΩ at f = 1 kHz
2.8
3.6
V
Unit
Carkit Pulse Driver
7.1.4.4
5%
Pullup/Pulldown Resistors
Table 7-8 lists the characteristics of pullup/pulldown resistors.
Table 7-8. Pullup/Pulldown Resistors
Parameter
Comments
Min
Typ
Max
0.9
1.1
1.575
1.425
2.2
3.09
Pullup Resistors
Bus pullup resistor on upstream
port (idle bus)
RPUI
Bus idle
Bus pullup resistor on upstream
port (receiving)
RPUA
Bus driven/driver outputs unloaded
High (floating)
VIHZ
Pullups/pulldowns on DP and DM lines
Phone D+ pullup voltage
VPH_DP_UP
Driver outputs unloaded
kΩ
2.7
3.6
V
3
3.3
3.6
V
14.25
18
24.8
kΩ
3.6
V
75
pF
0.342
V
Pulldown Resistors
Phone D+/– pulldown
High (floating)
RPH_DP_DWN
Driver outputs unloaded
RPH_DM_DWN
VIHZ
Pullups/pulldowns on DP and DM lines
2.7
D+/– Data Line
Upstream facing port
CINUB
[1.0]
OTG device leakage
VOTG_DATA_LKG
[2]
ZINP
Driver outputs unloaded (waiver from
USB.ORG Standard Committee)
Input impedance exclusive of
pullup/pulldown (1)
(1)
22
80
120
kΩ
Waiver received from usb.org standards committee on ZINP 300kmin specification
7.1.5
OTG Electrical Characteristics
The OTG block integrates three main functions:
• The USB plug detection function on VBUS and ID
• The ID resistor detection
• The VBUS level detection
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OTG VBUS Electrical Characteristics
Table 7-9 lists the electrical characteristics of the OTG VBUS.
Table 7-9. OTG VBUS Electrical Characteristics
Parameter
Comments
Min
Typ
Max
Unit
15
μs
0.5
0.6
0.7
V
VBUS Wake-Up Comparator
VBUS wake-up delay
DELVBUS_WK_UP
VBUS wake-up threshold
VVBUS_WK_UP
VBUS Comparators
A-device session valid
VA_SESS_VLD
0.8
1.1
1.4
V
A-device VBUS valid
VA_VBUS_VLD
4.4
4.5
4.6
V
B-device session end
VB_SESS_END
0.2
0.5
0.8
V
B-device session valid
VB_SESS_VLD
2.1
2.4
2.7
V
100
kΩ
VBUS Line
A-device VBUS input impedance to
ground
RA_BUS_IN
SRP (VBUS pulsing) capable A-device
not driving VBUS
B-device VBUS SRP pulldown
RB_SRP_DWN
5.25 V/8 mA, pullup voltage = 3 V
0.656
10
B-device VBUS SRP pullup
RB_SRP_UP
(5.25 V – 3 V)/8 mA, pullup voltage = 3
V
0.281
1
B-device VBUS SRP rise time
maximum for OTG-A
communication
tRISE_SRP_UP_Max
0 to 2.1 V with < 13 μF load
B-device VBUS SRP rise time
minimum for standard host
connection
tRISE_SRP_UP_Min
0.8 to 2.0 V with > 97 μF load
VBUS line maximum voltage
7.1.5.2
kΩ
2
kΩ
36
ms
60
ms
If VBUS_CHRG bit is low
7
V
OTG ID Electrical Characteristics
Table 7-10 lists the electrical characteristics of OTG ID.
Table 7-10. OTG ID Electrical Characteristics
Parameter
Comments
Min
Typ
Max
Unit
ID Wake-Up Comparator
ID wake-up comparator
RID_WK_UP
Wake-up when ID shorted to ground through a
resistor lower than 445 kΩ (±1%)
445
kΩ
ID Comparators — ID External Resistor Specifications
ID ground comparator
RID_GND
ID_GND interrupt when ID shorted to ground
through a resistor lower than 10 Ω
0
5
10
Ω
ID 100k comparators
RID_100K
ID_100K interrupt when 102 kΩ (1%) resistor
plugged in
101
102
103
kΩ
ID 200k comparators
RID_200K
ID_200K interrupt when 200 kΩ (1%) resistor
plugged in
198
200
202
kΩ
ID 440k comparators
RID_440K
ID_440K interrupt when 440 kΩ (1%) resistor
plugged in
435
440
445
kΩ
ID Float comparator
RID_FLOAT
ID_FLOAT interrupt when ID shorted to ground
through a resistor higher than 560 kΩ
Phone ID pullup to VPH_ID_UP
RPH_ID_UP
ID unloaded (VRUSB)
70
Phone ID pullup voltage
VPH_ID_UP
Connected to VRUSB
2.5
1400
kΩ
ID Line
ID line maximum voltage
76
USB Transceiver
200
286
kΩ
3.2
V
5.25
V
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8
MADC
8.1
General Description
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The TPS65920/TPS65930 device provides the MADC resource to the host processors in the system
(hardware and software conversion modes).
The MADC generates interrupt signals to the host processors. Interrupts are handled primarily by the
MADC internal secondary interrupt handler and secondly at the upper level (outside the MADC) by the
TPS65920/TPS65930 interrupt primary handler.
8.2
MADC Electrical Characteristics
Table 8-1 lists the electrical characteristics of the MADC.
Table 8-1. MADC Electrical Characteristics
Parameter
Conditions
Min
Resolution
0
MADC voltage reference
Offset
2.5
V
V
–1
1
LSB
Best fitting
–2
2
LSB
Best fitting for codes 230 to maximum
–2
2
LSB
Best fitting considering offset of 25 LSB
–3.75
3.75
LSB
Best fitting
–28.5
28.5
mV
Input bias
μA
1
Input capacitor CBANK
Maximum source input resistance Rs (for all 16
internal or external inputs)
Input current leakage (for all 16 internal or external
inputs)
78
Unit
Bit
1.5
ADIN0 differential nonlinearity
Integral nonlinearity for ADIN2
Max
10
ADIN2 input dynamic range for external input
ADIN0 integral nonlinearity
Typ
MADC
10
pF
100
kΩ
1
μA
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8.3
Channel Voltage Input Range
Table 8-2 lists the analog input voltage minimum and maximum values.
Table 8-2. Analog Input Voltage Range
Channel
Min
Typ
Max
Unit
Prescaler
ADIN0: General-purpose input
0
1.5
V
No prescaler
DC current source for battery identification through external
resistor (10 μA typical)
ADIN2: General-purpose input (1)
0
2.5
V
Prescaler in the MADC to be in range 0 to >1.5 V
(1)
General-purpose inputs must be tied to ground when TPS65920/TPS65930 internal power supplies (VINTANA1 and VINTANA2) are off.
8.3.1
Sequence Conversion Time (Real-Time or Nonaborted Asynchronous)
Table 8-3 lists the sequence conversion timing characteristics.
Table 8-3. Sequence Conversion Timing Characteristics
Parameter
Comments
Min
Typ
Max
Unit
F
Running frequency
1
T = 1/F
Clock period
1
N
Number of analog inputs to convert in a single sequence
0
2
Tstart
SW1, SW2, or USB asynchronous request or real-time STARTADC
request
3
4
μs
Tsettling time
Settling time to wait before sampling a stable analog input (capacitor
bank charge time)
20
μs
5
12
MHz
μs
Tsettling is calculated from the max((Rs + Ron)*Cbank) of the two
possible input sources (internal or external). Ron is the resistance of the
selection analog input switches (5 kΩ). This time is
software-programmable by the open-core protocol (OCP) register.
Tstartsar
The successive approximation registers ADC start time
Tadc time
The successive approximation registers ADC conversion time
Tcapture time
Tcapture time is the conversion result capture time.
Tstop
Full-conversion
sequence time
One channel (N = 1) (1)
Conversion sequence
time
Without Tstart and Tstop: One channel (N = 1) (1)
STARTADC pulse
duration
(1)
Both channels (1)
Without Tstart and Tstop: Both channels
(1)
STARTADC period is T.
1
μs
10
μs
2
μs
1
2
22
39
352
624
18
33
288
528
0.33
24
μs
μs
μs
μs
Total sequence conversion time general formula: Tstart+N*(1+Tsettling+Tadc+Tcapture) +Tstop
MADC
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Table 8-3 is illustrated in Figure 8-1, which is a conversion sequence general timing diagram. The Busy
parameter indicates that a conversion sequence is running, and the channel N result register parameter
corresponds to the result register of the RT/GP selected channel.
T one conversion
Tstart
Tstartsar
Tcapture
Tsettling
Tadc
Tstop
madc_clk
Busy
mux_sel_lowv[3:0]
channel N selected
Acquire_lowv
start_sar_lowv
out_lowv[9:0]
channel N
result register
new channel N value
channel X value
old value
new value
037-046
Figure 8-1. Conversion Sequence General Timing Diagram
80
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9
LED Drivers
9.1
General Description
Two arrays of parallel LEDs are driven (dedicated for the phone light). The parallel LEDs are supplied by
VBAT, and the external resistor value is given for each LED. The TPS65920/TPS65930 device supports
two open-drain LED drivers for the keypad backlight, having drain connections tolerant of the main battery
voltage.
Figure 9-1 is the LED driver block diagram. Table 9-1 lists the electrical characteristics of the LED driver.
BATT
120 W
*16...
LEDB
160 W
BATT
LEDSYNC
LEDGND
Device
037-045
Figure 9-1. LED Driver Block Diagram
NOTE
For the component values, see Table 14-1.
Table 9-1. LED Driver Electrical Characteristics
Parameter
SW On resistance
Conditions
Min
Typ
Max
IO = 160 mA
3
4
IO = 60 mA
10
12
LED Drivers
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Keyboard
10.1 Keyboard Connection
The keyboard is connected to the chip using:
• KBR (5
:0) input pins for row lines
• KBC (5
:0) output pins for column lines
Figure 10-1 shows the keyboard connection.
Device
VCC
Internal
pullup
Keyboard controller
6x6
Keyboard matrix
kbd_r_0
kbd_r_1
kbd_r_2
kbd_r_3
kbd_r_4
kbd_r_5
kbd_c_0
kbd_c_1
kbd_c_2
kbd_c_3
kbd_c_4
kbd_c_5
037-014
Figure 10-1. Keyboard Connection
When a key button of the keyboard matrix is pressed, the corresponding row and column lines are shorted
together. To allow key press detection, all input pins (KBR) are pulled up to VCC and all output pins (KBC)
are driven to a low level.
Any action on a button generates an interrupt to the sequencer.
The decoding sequence is written to allow detection of simultaneous press actions on several key buttons.
The keyboard interface can be used with a smaller keyboard area than 6 × 6. To use a 3 × 3 keyboard,
KBR(4) and KBR(5) must be tied high to prevent any scanning process distribution.
82
Keyboard
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11
Clock Specifications
The TPS65920/TPS65930 device includes several I/O clock pins. The TPS65920/TPS65930 device has
two sources of high-stability clock signals: the external high-frequency clock (HFCLKIN) input and an
onboard 32-kHz oscillator (an external 32-kHz signal can be provided). Figure 11-1 is the clock overview.
Device
OR
32KXIN
OR
32KCLKOUT
32KXOUT
32 kHz
OR
HFCLKIN
HFCLKOUT
030-002
Figure 11-1. Clock Overview
11.1 Clock Features
The TPS65920/TPS65930 device accepts two sources of high-stability clock signals:
• 32KXIN/32KXOUT: Onboard 32-kHz crystal oscillator (an external 32-kHz input clock can be provided)
• HFCLKIN: External high-frequency clock (19.2, 26, or 38.4 MHz).
The TPS65920/TPS65930 device can provide:
• 32KCLKOUT digital output clock
• HFCLKOUT digital output clock with the same frequency as the HFCLKIN input clock
Clock Specifications
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11.2 Input Clock Specifications
The clock system accepts two input clock sources:
• 32-kHz crystal oscillator clock or sinusoidal/squared clock
• HFCLKIN high-frequency input clock
11.2.1 Clock Source Requirements
Table 11-1 lists the input clock requirements.
Table 11-1. TPS65920/TPS65930 Input Clock Source Requirements
Pad
Clock Frequency
32KXIN
32KXOUT
HFCLKIN
(1)
32.768 kHz
19.2, 26, 38.4 MHz
Stability
Duty Cycle
Crystal
±30 ppm
40%/60%
Square wave
–
45%/55%
Sine wave
–
Square wave
±150 PPM
Sine wave
–
–
See
(1)
–
HFCLK duty cycle and frequency is not altered by the internal circuit. The input clock accuracy must
match that of the system requirement; for example, OMAP device.
11.2.2 HFCLKIN
HFCLKIN can be a square- or a sine-wave input clock. If a square-wave input clock is provided, it is
recommended to switch the block to bypass mode to avoid loading the clock.
Figure 11-2 shows the HFCLKIN clock distribution.
HFCLKIN
Slicer
HFCLKOUT
Clock
generator
Slicer bypass
SLICER_OK
CLKEN2
Timer
CLKEN
Main state-machine
CLKREQ
SLEEP1
SLEEP2
Optional request
configurable by software
only for legacy support
037-044
Figure 11-2. HFCLKIN Clock Distribution
When a device needs a clock signal other than 32.768 kHz, it makes a clock request and activates the
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CLKREQ pin. As a result, the TPS65920/TPS65930 device immediately sets CLKEN to 1 to warn the
clock provider in the system about the clock request and starts a timer (maximum of 5.2 ms using the
32.768-kHz clock). When the timer expires, the TPS65920/TPS65930 device opens a gated clock, the
timer automatically reloads the defined value, and a high-frequency output clock signal is available
through the HFCLKOUT pin. The output drive of HFCLKOUT is programmable (minimum load 10 pF,
maximum load 40 pF) and must be at 40 pF by default.
With a register setting, the mirroring of CLKEN can be enabled on CLKEN2. When this mirroring feature is
not enabled, CLKEN2 can be used as a general-purpose output controlled through I2C accesses.
CLKREQ, when enabled, has a weak pulldown resistor to support the wired-OR clock request.
Figure 11-3 shows an example of the wired-OR clock request.
Device
PERIPH1
VIO
CLKREQ
PERIPH2
VIO
PERIPHn
VIO
037-043
Figure 11-3. Example of Wired-OR Clock Request
The timer default value must be the worst case (10 ms) for the clock providers. For legacy or workaround
support, the NSLEEP1 and NSLEEP2 signals can also be used as a clock request even if it is not their
primary goal. By default, this feature is disabled and must be enabled individually by setting the register
bits associated with each signal.
Clock Specifications
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When the external clock signal is present on the HFCLKIN ball, it is possible to use this clock instead of
the internal RC oscillator and then synchronize the system on the same clock. The RC oscillator can then
go to idle mode.
Table 11-2 lists the input clock electrical characteristics of the HFCLKIN input clock.
Table 11-2. HFCLKIN Input Clock Electrical Characteristics
Parameter Description
Configuration Mode Slicer
Min
Frequency
Typ
Max
19.2, 26, or 38.4
LP (1)/HP (2) (sine wave)
Start-up time
4
LP/HP (sine wave)
Input dynamic range
0.3
BP (3)/PD (4) (square wave)
Current consumption
0.7
1.45
1.85 (5)
0
LP
175
HP
235
BP/PD
Harmonic content of input signal (with 0.7-VPP amplitude):
second component
LP/HP (sine wave)
VIH
Voltage input high
BP (square wave)
VIL
Voltage input low
BP (square wave)
(1)
(2)
(3)
(4)
(5)
Unit
MHz
μs
VPP
μA
39
nA
–25
dBc
1
V
0.6
V
LP = Low-power mode
HP = High-power mode
BP = Bypass mode
PD = Power-down mode
Bypass input max voltage is the same as the maximum voltage provided for the I/O interface (IO.1P8V).
Table 11-3 lists the input clock timing requirements of the HFCLKIN input clock when the source is a
square wave. Figure 11-4 shows the HFCLKIN squared input clock timings.
Table 11-3. HFCLKIN Square Input Clock Timing Requirements with Slicer in Bypass
Name
Parameter
Description
Min
Typ
Max
Unit
CH0
1/tC(HFCLKIN)
Frequency, HFCLKIN
CH1
tW(HFCLKIN)
Pulse duration, HFCLKIN low or high
0.55*tC(HFCLKIN)
ns
CH3
tR(HFCLKIN)
Rise time, HFCLKIN (1)
5
ns
CH4
tF(HFCLKIN)
Fall time, HFCLKIN (1)
5
ns
(1)
19.2, 26, or 38.4
0.45*tC(HFCLKIN)
MHz
Default drive capability is 40 pF.
CH0
CH1
CH1
HFCLKIN
019-017
Figure 11-4. HFCLKIN Squared Input Clock
11.2.3 32-kHz Input Clock
A 32.768-kHz input clock (often abbreviated to 32-kHz) generates the clocks for the RTC. It has a low-jitter
mode where the current consumption increases for lower jitter. It is possible to use the 32-kHz input clock
with an external crystal or clock source. Depending on the mode chosen, the 32K oscillator is configured
one of two ways:
• An external 32.768-kHz crystal through the 32KXIN/32KXOUT balls (see Figure 11-5). This
configuration is available only for master mode (for more information, see Section 12).
• An external square/sine wave of 32.768 kHz through 32KXIN with amplitude equal to 1.8 or 1.85 V
(see Figure 11-7, Figure 11-8, and Figure 11-9). This configuration is available for the master and
slave modes (for more information, see Section 12).
86
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11.2.3.1 External Crystal Description
Figure 11-5 shows the 32-kHz oscillator block diagram with crystal in master mode.
Current control
circuit and
mode selection
Bias generator
and startup
circuit
Signal swing
limiting circuit
Y
Signal
shaping
(1)
VBATOK
Internal
GND
XI
(1)
VBATOK
XO
C1
XTAL
C2
Internal
GND
External to device
037-042
NOTE: Switches close by default and open only if register access enables very-low-power mode when VBAT < 2.7 V.
Figure 11-5. 32-kHz Oscillator Block Diagram In Master Mode With Crystal
CXIN and CXOUT represent the total capacitance of the printed circuit board (PCB) and components,
excluding the crystal. Their values depend on the datasheet of the crystal, the internal capacitors, and the
parallel capacitor. The frequency of the oscillations depends on the value of the capacitors. The crystal
must be in the fundamental mode of operation and parallel resonant.
NOTE
For the values of CXIN and CXOUT, see Table 14-1.
Table 11-4 lists the required electrical constraints.
Table 11-4. Crystal Electrical Characteristics
Parameter
Min
Parallel resonance crystal frequency
Typ
Input voltage, Vin (normal mode)
1.0
Internal capacitor on each input (Cint)
1.3
Unit
kHz
1.55
10
Parallel input capacitance (Cpin)
Pin-to-pin capacitance
V
pF
1
Nominal load cap on each oscillator input CXIN and CXOUT (1)
(1)
Max
32.768
pF
CXIN = CXOUT = Cosc*2 – (Cint +
Cpin)
pF
1.6
pF
1.8
Nominal load capacitor on each oscillator input defined as CXIN = CXOUT = Cosc*2 – (Cint + Cpin). Cosc is the load capacitor defined
in the crystal oscillator specification, Cint is the internal capacitor, and Cpin is the parallel input capacitor.
Clock Specifications
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Table 11-4. Crystal Electrical Characteristics (continued)
Parameter
Min
Typ
Max
Unit
75
kΩ
Crystal ESR (2)
Crystal shunt capacitance, CO
1
pF
Crystal tolerance at room temperature, 25°C
–30
30
ppm
Crystal tolerance versus temperature range (–40°C to 85°C)
–200
200
ppm
1
μW
0.5
μW
Maximum drive power
Operating drive level
(2)
The crystal motional resistance Rm relates to the equivalent series resistance (ESR) by the following formula:
2
ESR = Rm
C
1+ O
CL
Measured with the load capacitance specified by the crystal manufacturer. If CXIN = CXOUT = 10 pF, CL = 5 pF. Parasitic capacitance
from the package and board must also be considered.
When selecting a crystal, the system design must consider the temperature and aging characteristics of a
crystal versus the user environment and expected lifetime of the system.
Table 11-5 and Table 11-6 list the switching characteristics of the oscillator and the timing requirements of
the 32.768-kHz input clock. Figure 11-6 shows the crystal oscillator output in normal mode.
Table 11-5. Base Oscillator Switching Characteristics
Name
Parameter Description
fP
Oscillation frequency
tSX
Start-up time
Min
Typ
Max
32.768
kHz
0.5
IDDA
Active current consumption
IDDQ
Current consumption
Unit
LOJIT <1:0> = 00
1.8
LOJIT <1:0> = 11
8
Low battery mode (1.2 V)
1
Startup
8
s
μA
μA
Table 11-6. 32-kHz Crystal Input Clock Timing Requirements
Name
Parameter Description
OC0
1/tC(32KHZ)
Frequency, 32 kHz
OC1
tW(32KHZ)
Pulse duration, 32 kHz low or high
Min
Typ
Max
32.768
0.40*tC(32KHZ)
OC0
OC1
Unit
kHz
0.60*tC(32KHZ)
μs
OC1
32KX
019-019
Figure 11-6. 32-kHz Crystal Input
11.2.3.2 External Clock Description
When an external 32K clock is used instead of a crystal, three configuration can be used:
• A square- or sine-wave input can be applied to the 32KXIN pin with amplitude of 1.85 or 1.8 V. The
32KXOUT pin can be driven to a dc value of the square- or sine-wave amplitude divided by 2. This
configuration, shown in Figure 11-7, is recommended if a large load is applied on the 32KXOUT pin.
• A square- or sine-wave input can be applied to the 32KXIN pin with amplitude of 1.85 or 1.8 V. The
32KXOUT pin can be left floating. This configuration, showed in Figure 11-8, is used if no charge is
applied on the 32KXOUT pin.
• The oscillator is in bypass mode and a square-wave input can be applied to the 32KXIN pin with
amplitude of 1.8 V. The 32KXOUT pin can be left floating. This configuration, shown in Figure 11-9, is
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used if the oscillator is in bypass mode.
Current control
circuit and mode
selection
Bias generator
and startup
circuit
Signal swing
limiting circuit
Y
Signal
shaping
(1)
VBATOK
Square/sine wave:
Vpp = VRRTC or
VIO_1P8V
XI
XO
DC level:
DC
Vpp/2
Internal
GND
(1)
VBATOK
Internal
GND
037-041
(1)
Switches close by default and open only if register access enables very-low-power mode when VBAT < 2.7 V.
Figure 11-7. 32-kHz Oscillator Block Diagram Without Crystal Option 1
Current control
circuit and mode
selection
Bias generator
and startup
circuit
Signal swing
limiting circuit
Y
Signal
shaping
(1)
VBATOK
Internal
GND
XI
XO
(1)
VBATOK
Floating
Square/sine wave:
Vpp = VRRTC or
VIO_1P8V
Internal
GND
037-039
(1)
Switches close by default and open only if register access enables very-low-power mode when VBAT < 2.7 V.
Figure 11-8. 32-kHz Oscillator Block Diagram Without Crystal Option 2
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Current control
circuit and mode
selection
Bias generator
and startup
circuit
Signal swing
limiting circuit
Y
Signal
shaping
(1)
VBATOK
XI
(1)
VBATOK
XO
Floating
Square wave:
Vpp = VIO_1P8V
Internal
GND
Internal
GND
037-040
(1)
Switches close by default and open only if register access enables very-low-power mode when VBAT < 2.7 V.
Figure 11-9. 32-kHz Oscillator in Bypass Mode Block Diagram Without Crystal Option 3
Table 11-7 lists the electrical constraints required by the 32-kHz input square- or sine-wave clock.
Table 11-7. 32-kHz Input Square- or Sine-Wave Clock Source Electrical Characteristics
Name
Parameter Description
f
Frequency
CI
CFI
Min
Typ
Max
Unit
32.768
kHz
Input capacitance
35
pF
On-chip foot capacitance to GND on each input (see Figure 11-7, Figure 11-8, and
Figure 11-9)
10
VPP
Square-/sine-wave amplitude in bypass mode or not
(1)
VIH
Voltage input high, square wave in bypass mode
VIL
Voltage input low, square wave in bypass mode
(1)
1.8
pF
V
0.8
V
0.6
V
Bypass input maximum voltage is the same as the maximum voltage provided for the I/O interface.
Table 11-8 lists the timing requirements of the 32-kHz square-wave input clock.
Table 11-8. 32-kHz Square-Wave Input Clock Source Timing Requirements
Name
Parameter
Description
CK0
1/tC(32KHZ)
Frequency, 32 kHz
CK1
tW(32KHZ)
Pulse duration, 32 kHz low or high
tR(32KHZ)
Rise time, 32 kHz
CK4
tF(32KHZ)
Fall time, 32 kHz (1)
90
Typ
Max
32.768
0.45*tC(32KHZ)
(1)
CK3
(1)
Min
Unit
MHz
0.55*tC(32KHZ)
μs
0.1*tC(32KHZ)
μs
0.1*tC(32KHZ)
μs
The capacitive load is 30 pF.
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Figure 11-10 shows the 32-kHz square- or sine-wave input clock.
CK0
CK1
CK1
32KX
037-038
Figure 11-10. 32-kHz Square- or Sine-Wave Input Clock
11.3 Output Clock Specifications
The TPS65920/TPS65930 device provides two output clocks:
• 32KCLKOUT
• HFCLKOUT
11.3.1 32KCLKOUT Output Clock
Figure 11-11 is the block diagram for the 32.768-kHz clock output.
IO_1P8
(1.8 V)
OR
32KXIN
32-kHz
OSC
OR
32KCLKOUT
32 kHz
32KXOUT
RTC
037-037
Figure 11-11. 32.768-kHz Clock Output Block Diagram
The TPS65920/TPS65930 device has an internal 32.768-kHz oscillator connected to an external
32.768-kHz crystal through the 32KXIN/32KXOUT balls or an external digital 32.768-kHz clock through the
32KXIN input (see Figure 11-11). The TPS65920/TPS65930 device also generates a 32.768-kHz digital
clock through the 32KCLKOUT pin and can broadcast it externally to the application processor or any
other devices. The 32KCLKOUT clock is broadcast by default in TPS65920/TPS65930 active mode, but
can be disabled if it is not used.
The 32.768-kHz clock (or signal) is also used to clock the RTC embedded in the TPS65920/TPS65930
device. The RTC is not enabled by default. The host processor must set the correct date and time and
enable the RTC functionality.
The 32KCLKOUT output buffer can drive several devices (up to 40-pF load). At startup, 32KCLKOUT
must be stabilized (frequency/duty cycle) before the signal output. Depending on the startup conditions,
this can delay the startup sequence.
Table 11-9 lists the electrical characteristics of the 32KCLKOUT output clock.
Clock Specifications
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Table 11-9. 32KCLKOUT Output Clock Electrical Characteristics
Name
Parameter Description
Min
f
Frequency
CL
Load capacitance
VOUT
Output clock voltage, depending on output reference level IO_1P8 (see Section 2)
VOH
Voltage output high
VOL
(1)
Typ
Max
Unit
32.768
kHz
40
pF
1.8 (1)
V
VOUT – 0.45
VOUT
V
0
0.45
V
Voltage output low
The output voltage depends on the output reference level, which is IO_1P8 (see Section 2, Terminal Description).
Table 11-10 lists the output clock switching characteristics. Figure 11-12 shows the 32KCLKOUT output
clock waveform.
Table 11-10. 32KCLKOUT Output Clock Switching Characteristics
Name
Parameter
Description
CK0
1/tC(32KCLKOUT)
Frequency
CK1
tW(32KCLKOUT)
Pulse duration, 32KCLKOUT low or high
Typ
Max
Unit
32.768
MHz
0.40*tC(32KCLKOUT)
0.60*tC(32KCLKOUT)
ns
16
ns
16
ns
(1)
CK2
tR(32KCLKOUT)
Rise time, 32KCLKOUT
CK3
tF(32KCLKOUT)
Fall time, 32KCLKOUT (1)
(1)
Min
The output capacitive load is 30 pF.
CK0
CK1
CK1
32KCLKOUT
037-035
Figure 11-12. 32KCLKOUT Output Clock
11.3.2 HFCLKOUT Output Clock
Table 11-11 lists the electrical characteristics of the HFCLKOUT output clock.
Table 11-11. HFCLKOUT Output Clock Electrical Characteristics
Name
Parameter Description
Min
f
Frequency
CL
Load capacitance
VOUT
Output clock voltage, depending on output reference level IO_1P8 (see Section 2)
VOH
Voltage output high
VOL
Voltage output low
(1)
Typ
Max
19.2, 26, or 38.4
Unit
MHz
30
1.8 (1)
pF
V
VOUT – 0.45
VOUT
V
0
0.45
V
The output voltage depends on the output reference level, which is IO_1P8 (see Section 2).
Table 11-12 lists the switching characteristics of the HFCLKOUT output clock.
Table 11-12. HFCLKOUT Output Clock Switching Characteristics
Name
Parameter
Description
Min
Typ
Max
Unit
CHO1
1/tC(HFCLKOUT)
Frequency
CHO2
tW(HFCLKOUT)
Pulse duration, HFCLKOUT low or high
0.60*tC(HFCLKOUT)
ns
CHO3
tR(HFCLKOUT)
Rise time, HFCLKOUT (1)
2.6
ns
CHO4
tF(HFCLKOUT)
Fall time, HFCLKOUT (1)
2.6
ns
(1)
92
19.2, 26, or 38.4
0.40*tC(HFCLKOUT)
MHz
The output capacitive load is 30 pF.
Clock Specifications
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Figure 11-13 shows the HFCLKOUT output clock waveform.
CHO1
CHO2
CHO2
HFCLKOUT
037-036
Figure 11-13. HFCLKOUT Output Clock
11.3.3 Output Clock Stabilization Time
Figure 11-14 shows the 32KCLKOUT and HFCLKOUT clock stabilization time.
XIN
Starting_Event
Tstartup
CLK32KOUTEN
CLK32KOUT
CLKEN
Delay1
HFCLKOUTEN
HFCLKOUT
Delay2
NRESPWRON
037-034
NOTE: Tstartup, Delay1, and Delay2 depend on the boot mode (see Section 4.5, Power Management).
NOTE: Ensure that the high frequency oscillator start-up time is in spec for the boot mode used. During power-up the internal
delay, Delay1 above is fixed (5.2 ms and 5.3 ms depending on boot mode). The start-up time for the oscillator must
be less than the fixed delay.
Figure 11-14. 32KCLKOUT and HFCLKOUT Clock Stabilization Time
Figure 11-15 shows the HFCLKOUT behavior.
HFCLKIN
HFCLKOUT
019-028
Figure 11-15. HFCLKOUT Behavior
Clock Specifications
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Timing Requirements and Switching Characteristics
12.1 Timing Parameters
The timing parameter symbols used in the timing requirement and switching characteristic tables are
created in accordance with JEDEC Standard 100. To shorten the symbols, some pin names and other
related terminologies are abbreviated, as shown in Table 12-1.
Table 12-1. Timing Parameters
Subscripts
Symbol
Cycle time (period)
d
Delay time
dis
Disable time
en
Enable time
h
Hold time
su
Setup time
START
Start bit
t
Transition time
v
Valid time
w
Pulse duration (width)
X
Unknown, changing, or don't care level
H
High
L
Low
V
Valid
IV
Invalid
AE
Active edge
FE
First edge
LE
Last edge
Z
94
Parameter
c
High impedance
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12.2 Target Frequencies
Table 12-2 assumes testing over the recommended operating conditions.
Table 12-2. TPS65920/TPS65930 Interface Target Frequencies
I/O Interface
SmartReflex inter-integrated
circuit (I2C™)
Interface Designation
2
I C
General-purpose I2C
USB
USB
JTAG
Voice/Bluetooth® pulse code
modulation (PCM) interface
(1)
(2)
1.5 V
Slave HS mode
3.6 Mbps
Slave fast-speed mode
400 Kbps
Slave standard mode
100 Kbps
HS
480 Mbps
FS
12 Mbps
LS
1.5 Mbps
Real/View® ICE tool
30 MHz
XDS560 and XDS510 tools
30 MHz
Lauterbach™ tool
TDM/inter-IC sound (I2S™)
Target Frequency
30 MHz
I2S
1/(64 * Fs) (1)
Right-justified
1/(64 * Fs) (1)
Left-justified
1/(64 * Fs) (1)
TDM
1/(128 * Fs) (1)
PCM (master mode)
1/(65 * Fs) (2)
PCM (slave mode)
1/(33 to 65 * Fs) (2)
Fs = 8 to 48 kHz; 96 kHz for RX path only (TDM/I2S interface)
Fs = 8 or 16 kHz (voice/Bluetooth PCM interface)
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12.3 I2C Timing
The TPS65920/TPS65930 device provides two I2C HS slave interfaces (one for general-purpose and one
for SmartReflex). These interfaces support standard mode (100 Kbps), fast mode (400 Kbps), and HS
mode (3.4 Mbps). The general-purpose I2C module embeds four slave hard-coded addresses (ID1 = 48h,
ID2 = 49h, ID3 = 4Ah, and ID4 = 4Bh). The SmartReflex I2C module uses one slave hard-coded address
(ID5). The master mode is not supported.
Table 12-3 and Table 12-4 assume testing over the recommended operating conditions (see Figure 12-1).
START
I1
I2C.SCL
RESTART
I2
1
8
9
1
I8
8
9
I8
I3
I2C.SDA
STOP
I4
MSB
I7
LSB
ACK
I9
MSB
LSB
ACK
037-033
Figure 12-1. I2C Interface—Transmit and Receive in Slave Mode
Table 12-3. I2C Interface—Timing Requirements (1)
Notation
Parameter
(2)
Min
Max
Unit
Slave HS Mode
I3
tsu(SDA-SCLH)
Setup time, SDA valid to SCL high
10
I4
th(SCLL-SDA)
Hold time, SDA valid from SCL low
0
ns
I7
tsu(SCLH-SDAL)
Setup time, SCL high to SDA low
160
ns
I8
th(SDAL-SCLL)
Hold time, SCL low from SDA low
160
ns
I9
tsu(SDAH-SCLH)
Setup time, SDA high to SCL high
160
ns
I3
tsu(SDA-SCLH)
Setup time, SDA valid to SCL high
100
I4
th(SCLL-SDA)
Hold time, SDA valid from SCL low
0
I7
tsu(SCLH-SDAL)
Setup time, SCL high to SDA low
0.6
ns
I8
th(SDAL-SCLL)
Hold time, SCL low from SDA low
0.6
ns
I9
tsu(SDAH-SCLH)
Setup time, SDA high to SCL high
0.6
ns
70
ns
Slave Fast-Speed Mode
ns
0.9
ns
Slave Standard Mode
(1)
(2)
I3
tsu(SDA-SCLH)
Setup time, SDA valid to SCL high
250
ns
I4
th(SCLL-SDA)
Hold time, SDA valid from SCL low
0
ns
I7
tsu(SCLH-SDAL)
Setup time, SCL high to SDA low
4.7
ns
I8
th(SDAL-SCLL)
Hold time, SCL low from SDA low
4
ns
I9
tsu(SDAH-SCLH)
Setup time, SDA high to SCL high
4
ns
The input timing requirements are given by considering a rising or falling time of:
80 ns in HS mode (3.4 Mbps)
300 ns in fast-speed mode (400 Kbps)
1000 ns in standard mode (100 Kbps)
SDA is equal to I2C.SR.SDA or I2C.CNTL.SDA.
SCL is equal to I2C.SR.SCL or I2C.CNTL.SCL.
Table 12-4 lists the switching requirements of the I2C interface.
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Table 12-4. I2C Interface—Switching Requirements (1)
Notation
Parameter
(2)
Min
Max
Unit
Slave HS Mode
I1
tw(SCLL)
Pulse duration, SCL low
160
ns
I2
tw(SCLH)
Pulse duration, SCL high
60
ns
1.3 (3)
µs
0.6
µs
4.7
µs
4
µs
Slave Fast-Speed Mode
I1
tw(SCLL)
Pulse duration, SCL low
I2
tw(SCLH)
Pulse duration, SCL high
Slave Standard Mode
(1)
(2)
(3)
I1
tw(SCLL)
Pulse duration, SCL low
I2
tw(SCLH)
Pulse duration, SCL high
The capacitive load is:
100 pF in HS mode (3.4 Mbps)
400 pF in fast-speed mode (400 Kbps)
400 pF in standard mode (100 Kbps)
SDA is equal to I2C.SR.SDA or I2C.CNTL.SDA
SCL is equal to I2C.SR.SCL or I2C.CNTL.SCL
SCL low timing for slave fast-speed mode is compatibile with 0.79 µs.
12.4 Audio Interface: TDM/I2S Protocol
The TPS65920/TPS65930 device acts as a master for the TDM and I2S interfaces or as a slave for only
the I2S interface. If the TPS65920/TPS65930 device is the master, it must provide the frame
synchronization (TDM/I2S_SYNC) and bit clock (TDM/I2S_CLK) to the host processor. If it is the slave,
the TPS65920/TPS65930 device receives frame synchronization and the bit clock.
The TPS65920/TPS65930 device supports the I2S, TDM, left-justified, and right-justified data formats, but
does not support TDM slave mode.
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12.4.1 I2S Right- and Left-Justified Data Format
Table 12-5 and Table 12-6 assume testing over the recommended operating conditions (see Figure 12-2
and Figure 12-3).
Right channel
Left channel
I2S.SYNC
I1
I2
I0
I1
I2
I2
I2S.CLK
I4
I4
I3
I2S.DIN
23
22
1
22
1
I5
I2S.DOUT
I4
I3
0
8 dummy bits
0
8 dummy bits
23
I3
22
1
22
1
I5
I5
23
I4
I3
0
8 dummy bits
23
0
8 dummy bits
23
22
I5
23
22
037-031
Figure 12-2. I2S Interface—I2S Master ModeI
Left channel
Right channel
I2S.SYNC
I1
I6
I0
I1
I7
I6
I2S.CLK
I4
I4
I3
I2S.DIN
23
22
1
22
1
I5
I2S.DOUT
23
I4
I3
I4
I3
0
8 dummy bits
0
8 dummy bits
I5
23
I3
22
1
22
1
I5
23
0
8 dummy bits
23
0
8 dummy bits
23
22
I5
22
037-032
Figure 12-3. I2S Interface—I2S Slave Mode
The timing requirements listed in Table 12-5 are valid on the following conditions of input slew and output
load:
• Rise and fall time range of inputs (SYNC, DIN) is tR/tF = 1.0 ns/6.5 ns
• Capacitance load range of outputs (CLK, SYNC, DOUT) is CLoad = 1 pF/30 pF
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The input timing requirements in Table 12-5 are given by considering a rising or falling time of 6.5 ns.
Table 12-5. I2S Interface—Timing Requirements
Notation
Parameter
Min
Max
Unit
Master Mode
I3
tsu(DIN-CLKH)
Setup time, I2S.DIN valid to I2S.CLK high2
25
ns
I4
th(DIN-CLKH)
Hold time, I2S.DIN valid from I2S.CLK high.
0
ns
Slave Mode
(1)
(2)
I0
tc(CLK)
Cycle time, I2S.CLK (1)
I1
tw(CLK)
Pulse duration, I2S.CLK high or low (2)
I3
tsu(DIN-CLKH)
Setup time, I2S.DIN valid to I2S.CLK high
5
ns
I4
th(DIN-CLKH)
Hold time, I2S.DIN valid from I2S.CLK high.
5
ns
I6
tsu(SYNC-CLKH)
Setup time, I2S.SYNC valid to I2S.CLK high
5
ns
I7
th(SYNC-CLKH)
Hold time, I2S.SYNC valid from I2S.CLK high
5
ns
1/64 * Fs
0.45 * P
ns
0.55 * P
ns
Fs = 8 to 48 kHz; 96 kHz for RX path only
P = I2S.CLK period
The capacitive load for Table 12-6 is 7 pF. Table 12-6 lists the switching characteristics for the I2S
interface.
Table 12-6. I2S Interface—Switching Characteristics
Notation
Parameter
Min
Max
Unit
Master Mode
I0
tc(CLK)
Cycle time, I2S.CLK (1)
I1
tw(CLK)
Pulse duration, I2S.CLK high or low (2)
I2
td(CLKL-SYNC)
I5
I5
1/64 * Fs
ns
0.45 * P
0.55 * P
ns
Delay time, I2S.CLK falling edge to I2S.SYNC
transition
–10
10
ns
td(CLKL-DOUT)
Delay time, I2S.CLK falling edge to I2S.DOUT
transition
–10
10
ns
td(CLKL-DOUT)
Delay time, I2S.CLK falling edge to I2S.DOUT
transition
0
20
ns
Slave Mode
(1)
(2)
Fs = 8 to 48 kHz; 96 kHz for RX path only
P = I2S.CLK period
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12.4.2 TDM Data Format
Table 12-7 and Table 12-8 assume testing over the recommended operating conditions (see Figure 12-4).
Channel 1
Channel 2
Channel 3
Channel 4
I2S.SYNC
T0
T1
T2 T2
T1
T2 T2
I2S.CLK
I2S.DIN
T4
T4
T4
T4
T4
T4
T4
T4
T3
T3
T3
T3
T3
T3
T3
T3
23 22
1
T5
I2S.DOUT
23 22
0
T5
1
0
8 dummy
bits
8 dummy
bits
23 22
1
T5
23 22
0
T5
1
0
8 dummy
bits
8 dummy
bits
23 22
1
T5
23 22
0
T5
1
0
8 dummy
bits
8 dummy
bits
23 22
1
T5
23 22
0
T5
1
0
037-030
Figure 12-4. TDM Interface—TDM Master Mode
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The timing requirements listed in Table 12-7 are valid on the following conditions of input slew and output
load:
• Rise and fall time range of inputs (SYNC, DIN) is tR/tF = 1.0 ns/6.5 ns
• Capacitance load range of outputs (CLK, SYNC, DOUT) is CLoad = 1 pF/30 pF
Table 12-7. TDM Interface Master Mode—Timing Requirements
Notation
Parameter
T3
tsu(DIN-CLKH)
Setup time, TDM.DIN valid to TDM.CLK
high
T4
th(DIN-CLKH)
Hold time, TDM.DIN valid from TDM.CLK
high
Min
Max
Unit
25
ns
0
ns
Table 12-8 lists the switching characteristics of the TDM interface master mode.
Table 12-8. TDM Interface Master Mode—Switching Characteristics
Notation
(1)
(2)
Parameter
(1)
T0
tc(CLK)
Cycle time, TDM.CLK
T1
tw(CLK)
Pulse duration, TDM.CLK high or low (2)
T2
td(CLKL-SYNC)
T5
td(CLKL-DOUT)
Min
Max
Unit
1/64 * Fs
ns
0.45*P
0.55*P
ns
Delay time, TDM.CLK rising edge to TDM.SYNC
transition
–10
10
ns
Delay time, TDM.CLK rising edge to TDM.DOUT
transition
–10
12
ns
Fs = 8 to 48 kHz; 96 kHz for RX path only
P = TDM.CLK period
12.5 JTAG Interfaces
The TPS65920/TPS65930 device JTAG TAP controller handles standard IEEE JTAG interfaces. This
section describes the timing requirements for the tools used to test TPS65920/TPS65930 device power
management.
The JTAG/TAP module provides a JTAG interface according to IEEE Std1149.1a. This interface uses the
four I/O pins TMS, TCK, TDI, and TDO. The TMS, TCK, and TDI inputs contain a pullup device, which
makes their state high when they are not driven. The output TDO is a 3-state output, which is high
impedance except when data are shifted between TDI and TDO.
• TCK is the test clock signal.
• TMS is the test mode select signal.
• TDI is the scan path input.
• TDO is the scan path output.
TMS and TDO are multiplexed at the top level with the GPIO0 and GPIO1 pins. The dedicated external
TEST pin switches from functional mode (GPIO0/GPIO1) to JTAG mode (TMS/TDO). The JTAG
operations are controlled by a state-machine that follows the IEEE Std1149.1a state diagram. This
state-machine is reset by the TPS65920/TPS65930 internal power-on reset (POR). A test mode is
selected by writing a 6-bit word (instruction) into the instruction register and then accessing the related
data register.
Table 12-9 and Table 12-10 assume testing over the recommended operating conditions (see
Figure 12-5).
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JL1
JL2
JL2
JTAG.TCK
JL3
JL4
JL5
JL6
JTAG.TDI
JTAG.TMS
JL7
JTAG.TDO
jtag_inter_time_wcs019
Figure 12-5. JTAG Interface Timing
The input timing requirements are given by considering a rising or falling edge of 7 ns.
Table 12-9. JTAG Interface—Timing Requirements
Notation
Parameter
Min
Max
Unit
Clock
JL1
tc(TCK)
Cycle time, JTAG.TCK period
JL2
tw(TCK)
Pulse duration, JTAG.TCK high or low (1)
30
JL3
tsu(TDIV-TCKH)
Setup time, JTAG.TDI valid before JTAG.TCK
high
8
ns
JL4
th(TDIV-TCKH)
Hold time, JTAG.TDI valid after JTAG.TCK high
5
ns
JL5
tsu(TMSV-TCKH)
Setup time, JTAG.TMS valid before JTAG.TCK
high
8
ns
JL6
th(TMSV-TCKH)
Hold time, JTAG.TMS valid after JTAG.TCK high
5
ns
0.48*P
ns
0.52*P
ns
Read Timing
(1)
P = JTAG.TCK clock period
The capacitive load is 35 pF.
Table 12-10. JTAG Interface—Switching Characteristics
Notation
Parameter
Min
Max
0
14
Unit
Write Timing
JL7
102
td(TCK-TDOV))
Delay time, JTAG, TCK active edge to JTAG.TDO valid
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13
Debouncing Time
Table 13-1 lists the characteristics of debouncing.
Table 13-1. Debouncing
Block
Programmable
Debouncing Time
Default
USB plug detection
Debouncing Functions
USB
No
9x50 ms
9x50 ms
Plug/unplug detection VBUS (1)
USB
Yes
0 to 250 ms
(32/32468-second
steps)
28 ms
Plug/unplug detection ID (2)
USB
Yes
0 to 250 ms
(32/32468-second
steps)
50 ms
Power
Yes
0 to 250 ms
30 ms
Thermistor
No
60 μs
60 μs
Debouncing function interrupt generation
debounce for VBUS and ID (3)
Hot-die detection
Thermal shutdown detection
PWRON (4)
Start/stop button
No
60 μs
60 μs
No
31.25 ms
31.25 ms
Button reset
No
60 μs
60 μs
SIM card plug/unplug
GPIO
Yes
0 or 30 ms ± 1 ms
0 ms
MMC1 (plug/unplug)
GPIO
Yes
0 or 30 ms ± 1 ms
0 ms
NRESWARM
(1)
(2)
(3)
(4)
Programmable in the VBUS_DEBOUNCE register
Programmable in the ID_DEBOUNCE register
Programmable in the RESERVED_E[2:0] CFG_VBUSDEB register
The PWRON signal is debounced 1024*CLK32K (maximum 1026*CLK32K) falling edge in master mode.
Figure 13-1 is a sample debouncing sequence chronogram.
Event1
Event2
31 ms
32K clock
50 ms
50-ms clock
Event1 detected on 32K
clock synchronized with
50-ms clock
Event1
Debounced after 50 ms
50 ms
dT
Event2
Debounced after 50 ms + dT
50 ms + dT
037-029
Figure 13-1. Debouncing Sequence Chronogram Example
Event1 is correctly debounced after 5 ms. Event2 is debounced after 50ms + dT because the capture of
the event is considered after the next rising edge of the 50-ms clock.
Debouncing Time
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External Components
Table 14-1 lists the TPS65920/TPS65930 device external components.
Table 14-1. TPS65920/TPS65930 External Components
Function
Component
Reference
Value
Note
Link
Power Supplies
Capacitor
CVDD1.IN
10 μF
Range ± 50%
ESR min = 1 mΩ
ESR max = 20 mΩ
Taiyo Yuden: JMK212BJ106KD
Capacitor
CVDD1.OUT
10 μF
Range ± 50%
ESR min = 1 mΩ
ESR max = 20 mΩ
Taiyo Yuden: JMK212BJ106KD
Inductor
LVDD1
1 μH
Range ± 30%
DCR max = 100 mΩ
Capacitor
CVDD2.IN
10 μF
Range ± 50%
ESR min = 1 mΩ
ESR max = 20 mΩ
Taiyo Yuden: JMK212BJ106KD
Capacitor
CVDD2.OUT
10 μF
Range ± 50%
ESR min = 1 mΩ
ESR max = 20 mΩ
Taiyo Yuden: JMK212BJ106KD
Inductor
LVDD2
1 μH
Range ± 30%
DCR max = 100 mΩ
10 μF
Range ± 50%
ESR min = 1 mΩ
ESR max = 20 mΩ
Taiyo Yuden: JMK212BJ106KD
VDD1
VDD2
Capacitor
CVIO.IN
Figure 4-1
Figure 4-1
Capacitor
CVIO.OUT
10 μF
Range ± 50%
ESR min = 1 mΩ
ESR max = 20 mΩ
Taiyo Yuden: JMK212BJ106KD
Inductor
LVVIO
1 μH
Range ± 30%
DCR max = 100 mΩ
VRUSB_3V
Capacitor
CVUSB.3P1
1 μF
Range: 0.3 to 2.7 μF
ESR min = 20 mΩ
ESR max = 300 mΩ
Figure 4-1
Figure 7-2
VRUSB_1V5
Capacitor
CVINTUSB1P5.OUT
1 μF
Range: 0.3 to 2.7 μF
ESR min = 20 mΩ
ESR max = 600 mΩ
Figure 4-1
Figure 7-2
VRUSB_1V8
Capacitor
CVINTUSB1P8.OUT
1 μF
Range: 0.3 to 2.7 μF
ESR min = 20 mΩ
ESR max = 600 mΩ
Figure 4-1
Figure 7-2
Capacitor
CVDAC.IN
1 μF
Range: 0.3 to 2.7 μF
ESR min = 20 mΩ
ESR max = 600 mΩ
VIO
VDAC
Figure 4-1
Figure 4-1
Capacitor
CVDAC.OUT
1 μF
Range: 0.3 to 2.7 μF
ESR min = 20 mΩ
ESR max = 600 mΩ
VPLLA3R
Capacitor
CVPLLA3R.IN
1 μF
Range: 0.3 to 2.7 μF
ESR min = 20 mΩ
ESR max = 600 mΩ
Figure 4-1
VPLL1
Capacitor
CVPLL1.OUT
1 μF
Range: 0.3 to 2.7 μF
ESR min = 20 mΩ
ESR max = 600 mΩ
Figure 4-1
104
External Components
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Table 14-1. TPS65920/TPS65930 External Components (continued)
Function
Component
Capacitor
Reference
CVMMC1.IN
Value
Note
1 μF
Range: 0.3 to 2.7 μF
ESR min = 20 mΩ
ESR max = 600 mΩ
VMMC1
Link
Figure 4-1
Capacitor
CVMMC1.OUT
1 μF
Range: 0.3 to 2.7 μF
ESR min = 20 mΩ
ESR max = 600 mΩ
VAUX12S
Capacitor
CVAUX12S.IN
1 μF
Range: 0.3 to 2.7 μF
ESR min = 20 mΩ
ESR max = 600 mΩ
Figure 4-1
VAUX2
Capacitor
CVAUX2.OUT
1 μF
Range: 0.3 to 2.7 μF
ESR min = 20 mΩ
ESR max = 600 mΩ
Figure 4-1
VINT
Capacitor
CVINT.IN
1 μF
Range: 0.3 to 2.7 μF
ESR min = 20 mΩ
ESR max = 600 mΩ
Figure 4-1
VINTANA1
Capacitor
CVINTANA1.OUT
1 μF
Range: 0.3 to 2.7 μF
ESR min = 20 mΩ
ESR max = 600 mΩ
Figure 4-1
VINTANA2
Capacitor
CVINTANA2.OUT
1 μF
Range: 0.3 to 2.7 μF
ESR min = 20 mΩ
ESR max = 600 mΩ
Figure 4-1
VINTDIG
Capacitor
CVINTDIG.OUT
1 μF
Range: 0.3 to 2.7 μF
ESR min = 20 mΩ
ESR max = 600 mΩ
Figure 4-1
VBAT.USB
Capacitor
CVBAT.USB
1 μF
Range: 0.3 to 2.7 μF
ESR min = 20 mΩ
ESR max = 600 mΩ
Figure 7-2
Capacitor
CVBUS.FC
2.2 μF ± 40%
Capacitor
CVBUS.IN
10 μF
Capacitor
CVBUS
Capacitor
CXIN
10 pF
Capacitor
CXOUT
10 pF
USB CP
4.7 μF ± 40%
ESR max = 20 mΩ
Figure 7-2
ESR max = 20 mΩ
32.768 kHz
32K OSC
32.768 kHz
Range: 9 pF to 12.5 pF
Figure 11-5
±30 ppm (at 25°C)
±200 ppm (–40°C to 85°C)
Quartz
X32.768kHz
Capacitor
CPL.O
Capacitor
CPL
1 μF
Resistor
RPL
>15 kΩ
Resistor
RPL.M
>15 kΩ
Resistor
RPL.O
10 kΩ
Capacitor
CPL.M
1 μF
Capacitor
CPR.O
50 pF
Capacitor
CPR
1 μF
Resistor
RPR
>15 kΩ
Resistor
RPR.M
>15 kΩ
Resistor
RPR.O
10 kΩ
Capacitor
CPR.M
1 μF
Ferrite bead
LV.M
BLM18BD221S1N
Ferrite bead
LV.P
BLM18BD221S1N
Capacitor
CV.V
1 μF
Capacitor
CV.M
1 nF
Capacitor
CV.P
1 nF
Audio
External class-D
predriver left
External class-D
predriver right
Vibrator H-bridge
50 pF
Figure 6-2
Figure 6-2
Figure 6-3
External Components
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Table 14-1. TPS65920/TPS65930 External Components (continued)
Function
MIC main
(pseudo
differential mode)
Component
Silicon MIC
Auxiliary right
Value
CMM.M
100 nF
Capacitor
CMM.P
100 nF
Capacitor
CMM.O
47 pF
Resistor
RMM.O
~500 Ω
Resistor
RMM.MP
~1.7 kΩ
Capacitor
CMM.B
0 to 200 pF
Capacitor
CMM.M
100 nF
Capacitor
CMM.P
100 nF
Capacitor
CMM.PM
47 pF
Capacitor
CMM.O
47 pF
CMM.GM
47 pF
CMM.GP
47 pF
Resistor
RMM.BP
1 kΩ
Resistor
RMM.GM
1 kΩ
Capacitor
CMM.B
Capacitor
CVMIC1.OUT
1 μF
Capacitor
CSM
1 μF
Capacitor
CSM.P
100 nF
Capacitor
CSM.M
100 nF
Capacitor
CSM.PG
47 nF
Resistor
RSM
>500 Ω
Capacitor
CAUXR
100 nF
Capacitor
CAUXR.M
47 pF
MIC main
Capacitor
(differential mode)
Capacitor
VMIC1
Reference
Capacitor
0 to 200 pF
Note
Link
Figure 6-6
If greater than 200 pF, a serial resistor is
required for bias stability
Figure 6-7
If greater than 200 pF, a serial resistor is
required for bias stability
Range: 0.3 μF to 3.3 μF
ESR min = 20 mΩ
ESR max = 600 mΩ
Figure 6-8
Figure 6-9
LED Driver
LED
Resistor
RLED.A
120 Ω
Needed for each LED
Resistor
RLED.B
160 kΩ
Needed for each LED
Figure 9-1
I2C Bus—External Pullup
I2C SmartReflex
I2C control
Resistor
RPSR.SDA
Resistor
RPSR.SCL
Resistor
RCNTL.SD;
Resistor
106
RCNTL.SCL
Pullups for various bus capacitances (CL) and I2C speeds
(Std, Fast, and HS)
If CL = 10 pF: Std = 118 kΩ, Fast = 35.4 kΩ, HS = 4.7 kΩ
If CL = 12 pF: Std = 98.3 kΩ, Fast = 29.5 kΩ, HS = 3.9 kΩ
If CL = 50 pF: Std = 23.6 kΩ, Fast = 7.1 kΩ, HS = 940 Ω
If CL = 100 pF: Std = 11.8 kΩ, Fast = 3.54 kΩ, HS = 470 Ω
If CL ≤ 12 pF, there is no need for an external pullup, the
internal 3-kΩ pullup can be used.
If an external pullup is used, disable the internal 3-kΩ pullup
(reference the GPPUPDCTR1 register; see the TRM).
External Components
Section 12.3
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15
TPS65920/TPS65930 Package
15.1
TPS65920/TPS65930 Standard Package Symbols
Figure 15-1 shows the printed device reference.
Pin 1 indicator
o
YMLLLLS
$
037-028
Figure 15-1. Printed Device Reference
Table 15-1 lists the fields and their meanings.
Table 15-1. TPS65920/TPS65930 Nomenclature Description
Field
Marking used to note prototype (X), preproduction (P), or qualified/production device (blank) (1)
A
Mask set version descriptor (initial silicon = BLANK, first silicon revision = A, second silicon revision = B,...) (2)
YM
LLLLS
$
(1)
(2)
Meaning
P
Year month
Lot code
Fab planning code
A blank in the symbol or part number is collapsed so there are no gaps between characters.
Initial silicon version is ES1.0; first revision can be named ES2.0, ES1.1, or ES1.01, depending on the level of change.
Note: The device name is a maximum of 10 characters.
15.2 Package Thermal Resistance Characteristics
Table 15-2 and Table 15-3 list the thermal resistance characteristics for the TPS65920 and TPS65930
devices, respectively.
Table 15-2. TPS65920 Thermal Resistance Characteristics
RθJA(°C/W)
RθJB(°C/W)
RθJC(°C/W)
Board Type
33.40
13.80
6.74 (1)
2S2P (2)
14.50
(1)
1S0P (2)
57.04
(1)
(2)
6.74
This measurement is not affected by the board on which the device is mounted.
The board types are defined by JEDEC (reference JEDEC standard JESD51-9, Test Board for Area
Array Surface Mount Package Thermal Measurements).
Table 15-3. TPS65930 Thermal Resistance Characteristics
RθJA(°C/W)
RθJB(°C/W)
RθJC(°C/W)
Board Type
33.42
13.81
6.74 (1)
2S2P (2)
14.51
(1)
1S0P (2)
57.05
(1)
(2)
6.74
This measurement is not affected by the board on which the device is mounted.
The board types are defined by JEDEC (reference JEDEC standard JESD51-9, Test Board for Area
Array Surface Mount Package Thermal Measurements).
TPS65920/TPS65930 Package
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15.3 Mechanical Data
Figure 15-2 is the bottom view of the TPS65920/TPS65930 mechanical package.
037-016
Figure 15-2. TPS65920/TPS65930 Mechanical Package Bottom View
Figure 15-3 shows the ball size.
0.35 mm
0.41 (±0.05) mm
037-027
Figure 15-3. Ball Size
108
TPS65920/TPS65930 Package
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15.4 ESD Specifications
The device has built-in ESD protection to the limits specified below. It is recommended that the leads are
shorted together, or the device placed in conductive foam, during storage or handling to prevent
electrostatic damage.
(1)
ESD Method
Standard Reference
Performance
Human Body Model (HBM)
EIA / JESD22-A114D
2000V (1)
Charge Device Model (CDM)
EIA / JESD22-C101C
500V
The pin CLK32KOUT is 1500V HBM compliant.
TPS65920/TPS65930 Package
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SWCS037G – MAY 2008 – REVISED APRIL 2011
16
Glossary
ADC
Analog-to-digital converter
ALC
Automatic level control
ASIC
Application-specific integrated circuit
BGA
Ball grid array
BW
Signal bandwidth
CMOS
Complementary metal oxide semiconductor
CMT
Cellular mobile telephone
CPU
Central processing unit
DAC
Digital-to-analog converter
DBB
Digital baseband
DCR
Data capture record
DM
Data manual
DSP
Digital signal processor
DVFS
Dynamic voltage and frequency scaling
ESD
Electrostatic discharge
ESR
Equivalent series resistance
FET
Field effect transistor
FS
Full speed
FSR
Full-scale range
GND
Ground
GP
General-purpose
GPIO
General-purpose input/output
hiZ
High impedance
HS
High speed or high security
HW
Hardware
2
110
www.ti.com
IC
Inter-integrated circuit
I2S
Inter IC sound
IC
Integrated circuit
ICN
Idle channel noise
ID
Identification
IDDQ
Direct drain quiescent current
IF
Interface
IO or I/O
Input/output
JTAG
Joint Test Action Group, IEEE 1149.1 standard
LDO
Low-dropout regulator
LED
Light-emitting diode
LJF
Left-justified format
LS
Low speed
MADC
Monitoring analog-to-digital converter
Glossary
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MMC
Multimedia card
NA, N/A
Not applicable
NRZI
Nonreturn to zero inverted
OCP
Open-core protocol
OTG
On-the-Go
PBGA
Plastic ball grid array
PCB
Printed circuit board
PD
Pulldown
PDM
Pulse density modulated
PFM
Pulse frequency modulation
PLL
Phase-locked loop
POL
Polarity
POR
Power-on reset
PSR
Power-supply rejection
PSRR
Power-supply rejection ratio
PU
Pullup
PWL
Pulse-width length
PWM
Pulse-width modulation
PWT
Pulse-width time
RJF
Right-justified format
RTC
Real-time clock
RX
Receive
SDI
Serial display interface
SMPS
Switch-mode power supplies
SNR
Signal-to-noise ratio
SW
Software
SYNC/SYNCHRO Synchronization
SYS
System
TBD
To be defined
THRU
Feed through
TRM
Technical reference manual
TX
Transmit
UART
Universal asynchronous receiver/transmitter
ULPI
UTMI+ low pin Interface
UPR
Uninterrupted power rail
USB
Universal serial bus
UTMI
USB transceiver macrocell Interface
Glossary
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Jul-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
TPS65920A2ZCH
ACTIVE
NFBGA
ZCH
139
184
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
TPS65920A2ZCHR
ACTIVE
NFBGA
ZCH
139
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
TPS65920BZCH
NRND
NFBGA
ZCH
139
184
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
TPS65920BZCHR
NRND
NFBGA
ZCH
139
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
TPS65930A2ZCH
ACTIVE
NFBGA
ZCH
139
184
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
TPS65930A2ZCHR
ACTIVE
NFBGA
ZCH
139
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
TPS65930BZCH
NRND
NFBGA
ZCH
139
184
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
TPS65930BZCHR
NRND
NFBGA
ZCH
139
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jul-2011
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jun-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS65920A2ZCHR
NFBGA
ZCH
139
1000
330.0
24.4
10.4
10.4
2.3
16.0
24.0
Q1
TPS65930A2ZCHR
NFBGA
ZCH
139
1000
330.0
24.4
10.4
10.4
2.3
16.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jun-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS65920A2ZCHR
NFBGA
ZCH
139
1000
333.2
345.9
41.3
TPS65930A2ZCHR
NFBGA
ZCH
139
1000
333.2
345.9
41.3
Pack Materials-Page 2
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