3D3225 MONOLITHIC 5-TAP FIXED DELAY LINE (SERIES 3D3225) FEATURES • • • • • • • • • • • • PACKAGES All-silicon, low-power CMOS technology TTL/CMOS compatible inputs and outputs Vapor phase, IR and wave solderable Auto-insertable (DIP pkg.) Low ground bounce noise Leading- and trailing-edge accuracy Delay range: 0.75ns through 3500ns Delay tolerance: 2% or 0.5ns Temperature stability: ±2% typical (-40C to 85C) Vdd stability: ±1% typical (3.0V-3.6V) Minimum input pulse width: 30% of total delay 8-pin Gull-Wing available as drop-in replacement for hybrid delay lines IN O2 O4 GND 1 2 3 4 VDD O1 O3 O5 8 7 6 5 3D3225Z-xx SOIC-8 3D3225M-xx DIP-8 3D3225H-xx Gull-Wing IN NC NC O2 NC O4 NC GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD NC NC O1 NC O3 NC O5 IN 1 14 VDD NC 2 13 NC NC 3 12 O1 O2 4 11 NC NC 5 10 O3 O4 6 9 NC GND 7 8 O5 3D3225-xx 3D3225G-xx 3D3225K-xx 3D3225S-xx SOL-16 DIP-14 Gull-Wing Unused pins removed For mechanical dimensions, click here. For package marking details, click here. FUNCTIONAL DESCRIPTION PIN DESCRIPTIONS The 3D3225 5-Tap Delay Line product family consists of fixed-delay CMOS integrated circuits. Each package contains a single delay line, tapped and buffered at 5 points spaced uniformly in time. Tap-to-tap (incremental) delay values can range from 0.75ns through 700ns. The input is reproduced at the outputs without inversion, shifted in time as per the user-specified dash number. The 3D3225 is TTL- and CMOScompatible, capable of driving ten 74LS-type loads, and features both rising- and falling-edge accuracy. IN O1 O2 O3 O4 O5 VDD GND Delay Line Input Tap 1 Output (20%) Tap 2 Output (40%) Tap 3 Output (60%) Tap 4 Output (80%) Tap 5 Output (100%) +3.3 Volts Ground The all-CMOS 3D3225 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 8-pin auto-insertable DIP and space saving surface mount 8-pin SOIC and 16-pin SOL packages. TABLE 1: PART NUMBER SPECIFICATIONS DASH NUMBER -.75 -1 -1.5 -2 -2.5 -4 -5 -10 -20 -50 -100 -200 -700 TOLERANCES TOTAL TAP-TAP DELAY (ns) DELAY (ns) 3.0 ± 0.5* 0.75 ± 0.4 4.0 ± 0.5* 1.0 ± 0.5 6.0 ± 0.5* 1.5 ± 0.7 8.0 ± 0.5* 2.0 ± 0.8 10.0 ± 0.5* 2.5 ± 1.0 16.0 ± 0.7* 4.0 ± 1.3 25.0 ± 1.0 5.0 ± 1.5 50.0 ± 1.0 10.0 ± 2.0 100.0 ± 2.0 20.0 ± 4.0 250.0 ± 5.0 50.0 ± 10 500.0 ± 10 100 ± 20 1000 ± 20 200 ± 40 3500 ± 70 700 ± 140 Rec’d Max Frequency 41.7 MHz 37.0 MHz 31.2 MHz 25.0 MHz 22.2 MHz 8.33 MHz 13.3 MHz 6.67 MHz 3.33 MHz 1.33 MHz 0.67 MHz 0.33 MHz 0.10 MHz INPUT RESTRICTIONS Absolute Max Rec’d Min Frequency Pulse Width 166.7 MHz 12.0 ns 166.7 MHz 13.5 ns 166.7 MHz 16.0 ns 166.7 MHz 20.0 ns 125.0 MHz 22.5 ns 133.3 MHz 30.0 ns 66.7 MHz 37.5 ns 33.3 MHz 75.0 ns 16.7 MHz 150 ns 6.67 MHz 375 ns 3.33 MHz 750 ns 1.67 MHz 1500 ns 0.48 MHz 5250 ns * Total delay referenced to Tap1 output; Input-to-Tap1 = 7.5ns ± 1.0ns NOTE: Any dash number between .75 and 700 not shown is also available as standard. Doc #05003 12/22/05 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 Absolute Min Pulse Width 3.00 ns 3.00 ns 3.00 ns 3.00 ns 4.00 ns 6.00 ns 7.50 ns 15.0 ns 30.0 ns 75.0 ns 150 ns 300 ns 1050 ns 2005 Data Delay Devices 1 3D3225 APPLICATION NOTES To guarantee the Table 1 delay accuracy for input frequencies higher than the Maximum Operating Frequency, the 3D3225 must be tested at the user operating frequency. Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency of operation. The programmed delay accuracy of the device is guaranteed, therefore, only at the user specified input frequency. Small input frequency variation about the selected frequency will only marginally impact the programmed delay accuracy, if at all. Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted. OPERATIONAL DESCRIPTION The 3D3225 five-tap delay line architecture is shown in Figure 1. The delay line is composed of a number of delay cells connected in series. Each delay cell produces at its output a replica of the signal present at its input, shifted in time. The delay cells are matched and share the same compensation signals, which minimizes tap-totap delay deviations over temperature and supply voltage variations. INPUT SIGNAL CHARACTERISTICS The Frequency and/or Pulse Width (high or low) of operation may adversely impact the specified delay accuracy of the particular device. The reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. Therefore a Maximum and an Absolute Maximum operating input frequency and a Minimum and an Absolute Minimum operating pulse width have been specified. OPERATING PULSE WIDTH The Absolute Minimum Operating Pulse Width (high or low) specification, tabulated in Table 1, determines the smallest Pulse Width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion. OPERATING FREQUENCY The Minimum Operating Pulse Width (high or low) specification determines the smallest Pulse Width of the delay line input signal for which the output delay accuracy tabulated in Table 1 is guaranteed. The Absolute Maximum Operating Frequency specification, tabulated in Table 1, determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion. To guarantee the Table 1 delay accuracy for input pulse width smaller than the Minimum Operating Pulse Width, the 3D3225 must be tested at the user operating pulse width. Therefore, to facilitate production and device identification, the part number will include a The Maximum Operating Frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed. IN O1 20% O2 20% O3 20% O4 20% O5 20% Temp & VDD Compensation VDD GND Figure 1: 3D3225 Functional Diagram Doc #05003 12/22/05 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 2 3D3225 APPLICATION NOTES (CONT’D) custom reference designator identifying the intended frequency and duty cycle of operation. The programmed delay accuracy of the device is guaranteed, therefore, only for the user specified input characteristics. Small input pulse width variation about the selected pulse width will only marginally impact the programmed delay accuracy, if at all. Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted. circuitry to minimize the delay variations induced by fluctuations in power supply and/or temperature. The thermal coefficient is reduced to 250 PPM/C, which is equivalent to a variation, over the -40C to 85C operating range, of ±2% from the roomtemperature delay settings and/or 1.0ns, whichever is greater. The power supply coefficient is reduced, over the 3.0V-3.6V operating range, to ±1% of the delay settings at the nominal 3.3VDC power supply and/or 1.0ns, whichever is greater. It is essential that the power supply pin be adequately bypassed and filtered. In addition, the power bus should be of as low an impedance construction as possible. Power planes are preferred. POWER SUPPLY AND TEMPERATURE CONSIDERATIONS The delay of CMOS integrated circuits is strongly dependent on power supply and temperature. The monolithic 3D3225 programmable delay line utilizes novel and innovative compensation DEVICE SPECIFICATIONS TABLE 2: ABSOLUTE MAXIMUM RATINGS PARAMETER DC Supply Voltage Input Pin Voltage Input Pin Current Storage Temperature Lead Temperature SYMBOL VDD VIN IIN TSTRG TLEAD MIN -0.3 -0.3 -1.0 -55 MAX 7.0 VDD+0.3 1.0 150 300 UNITS V V mA C C NOTES 25C 10 sec TABLE 3: DC ELECTRICAL CHARACTERISTICS (-40C to 85C, 3.0V to 3.6V) PARAMETER Static Supply Current* High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Current Low Level Output Current Output Rise & Fall Time SYMBOL IDD VIH VIL IIH IIL IOH MIN IOL 4.0 TR & TF *IDD(Dynamic) = 5 * CLD * VDD * F where: CLD = Average capacitance load/tap (pf) F = Input frequency (GHz) Doc #05003 12/22/05 TYP 3.5 MAX 5.5 -15.0 0.8 1.0 1.0 -4.0 2.0 15.0 2.0 UNITS mA V V µA µA mA mA 2.5 ns NOTES VIH = VDD VIL = 0V VDD = 3.0V VOH = 2.4V VDD = 3.0V VOL = 0.4V CLD = 5 pf Input Capacitance = 10 pf typical Output Load Capacitance (CLD) = 25 pf max DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 3 3D3225 SILICON DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: Ambient Temperature: 25oC ± 3oC Supply Voltage (Vcc): 3.3V ± 0.1V Input Pulse: High = 3.0V ± 0.1V Low = 0.0V ± 0.1V Source Impedance: 50Ω Max. Rise/Fall Time: 3.0 ns Max. (measured between 0.6V and 2.4V ) Pulse Width: PWIN = 1.25 x Total Delay Period: PERIN = 2.5 x Total Delay OUTPUT: Rload: Cload: Threshold: 10KΩ ± 10% 5pf ± 10% 1.5V (Rising & Falling) Device Under Test Digital Scope 10KΩ 5pf 470Ω NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. PRINTER COMPUTER SYSTEM PULSE GENERATOR DEVICE UNDER TEST (DUT) OUT IN TRIG OUT1 OUT2 OUT3 OUT4 OUT5 REF IN TRIG DIGITAL SCOPE/ TIME INTERVAL COUNTER Figure 2: Test Setup PERIN PW IN tRISE INPUT SIGNAL tFALL VIH 2.4V 1.5V 0.6V 2.4V 1.5V 0.6V tPLH OUTPUT SIGNAL VIL tPHL 1.5V VOH 1.5V VOL Figure 3: Timing Diagram Doc #05003 12/22/05 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 4