ATMEL TSPC603RVGB/Q12LC

Features
•
•
•
•
•
•
•
Superscalar (3 Instructions per Clock Peak)
Dual 16 KB Caches
Selectable Bus Clock
32-bit Compatibility PowerPC Implementation
On-chip Debug Support
Nap, Doze and Sleep Power Saving Modes
Device Offered in Cerquad, CBGA 255, HiTCE CBGA 255 and CI-CGA 255
Features Specific to CBGA 255, HiTCE CBGA 255 and CI-CGA 255
•
•
•
•
•
•
•
•
•
•
•
7.4 SPECint95, 6.1 SPECfp95 at 300 MHz (Estimated)
PD Typically = 3.5W (266 MHz), Full Operating Conditions
Branch Folding
64-bit Data Bus (32-bit Data Bus Option)
4-Gbytes Direct Addressing Range
Pipelined Single/Double Precision Float Unit
IEEE 754 Compatible FPU
IEEE P 1149-1 Test Mode (JTAG/C0P)
fINT Max = 300 MHz
fBUS Max = 75 MHz
Compatible CMOS Input/TTL Output
PowerPC® 603e
RISC
Microprocessor
Family
PID7t-603e
TSPC603R
Features Specific to Cerquad
• 5.6 SPECint95, 4 SPECfp95 and 200 MHz (Estimated)
• PD Typically = 2.5W (200 MHz), Full Operating Conditions
1. Description
The PID7t-603e implementation of the PowerPC 603e (renamed after the 603R) is a
low-power implementation of the Reduced Instruction Set Computer (RISC) microprocessor PowerPC family. The 603R is pin-to-pin compatible with the PowerPC 603e
and 603P in a Cerquad package. The 603R implements 32-bit effective addresses,
integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits.
The 603R is a low-power 2.5/3.3V design and provides four software controllable
power-saving modes. This device is a superscalar processor capable of issuing and
retiring as many as three instructions per clock. Instructions can be executed in any
order for increased performance, but, the 603R makes completion appear sequential.
It integrates five execution units and is able to execute five instructions in parallel.
The 603R provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed caches for instructions and data, as well as on-chip instructions, and
data Memory Management Units (MMUs). The MMUs contain 64-entry, two-way
set-associative, data and instruction translation look aside buffers that provide support
for demand-paged virtual memory address translation and variable-sized block translation. The 603R has a selectable 32- or 64-bit data bus and a 32-bit address bus. The
interface protocol allows multiple masters to compete for system resources through a
central external arbiter. The device supports single-beat and burst data transfers for
memory accesses, and supports memory-mapped I/Os.
Rev. 5410B–HIREL–09/05
The 603R uses an advanced, 2.5/3.3V CMOS process technology and maintains full interface
compatibility with TTL devices. It also integrates in-system testability and debugging features
through JTAG boundary-scan capabilities.
2. Screening/Quality/Packaging
This product is manufactured in full compliance with:
• HiTCE CBGA according to Atmel Standards
• CI-CGA 255 and Cerquad: MIL-PRF-38535 class Q or according to Atmel standards
• CBGA 255: Upscreenings based upon Atmel standards
• CBGA, CI-CGA, HiTCE packages:
– Full military temperature range (TC = -55°C, Tj = +125°C)
– Industrial temperature range
(TC = -40°C, Tj = +110°C)
• Cerquad:
– Full military temperature range (TC = -55°C, Tc = +125°C)
– Industrial temperature range
(TC = -40°C, Tc = +110°C)
– Commercial temperature ranges (TC = 0°C, TC = +70°C)
• Internal I/O Power Supply = 2.5 ±5% // 3.3V ±5%
G suffix
CBGA 255
Ceramic Ball Grid Array
A suffix
CERQUAD 240
Ceramic Leaded Chip Carrier
Cavity up
GS suffix
CI-CGA 255
Ceramic Ball Grid Array
with Solder Column Interposer (SCI)
CERQUAD 240
GH suffix
HiTCE 255
Ceramic Ball Grid Array
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3. Block Diagram
Figure 3-1.
Block Diagram
Fetch
Unit
Completion
Unit
Branch
Unit
Dispatch
Unit
Integer
Unit
Gen
Reg
Unit
Load/
Store
Unit
Gen
Rename
FP
Rename
D MMU
I MMU
16K Data Cache
16K Inst. Cache
FP
Reg
File
Float
Unit
Bus Interface Unit
32b Address
64b Data
System Bus
4. Overview
The 603R is a low-power implementation of the PowerPC microprocessor family of Reduced
Instruction Set Computing (RISC) microprocessors. The 603R implements the 32-bit portion of
the PowerPC architecture, which provides 32-bit effective addresses, integer data types of 8, 16
and 32 bits, and floating-point data types of 32 and 64 bits. For 64-bit PowerPC microprocessors, the PowerPC architecture provides 64-bit integer data types, 64-bit addressing, and other
features required to complete the 64-bit architecture.
The 603R provides four software controllable power-saving modes. Three of the modes (nap,
doze, and sleep) are static in nature, and progressively reduce the amount of power dissipated
by the processor. The fourth is a dynamic power management mode that causes the functional
units in the 603R to automatically enter a low-power mode when the functional units are idle
without affecting operational performance, software execution, or any external hardware.
The 603R is a superscalar processor capable of issuing and retiring as many as three instructions per clock. Instructions can be executed in any order for increased performance, but, the
603R makes completion appear sequential.
The 603e integrates five execution units:
• an Integer Unit (IU)
• a Floating-point Unit (FPU)
• a Branch Processing Unit (BPU)
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• a Load/Store Unit (LSU)
• a System Register Unit (SRU)
The ability to execute five instructions in parallel and the use of simple instructions with rapid
execution times yield high efficiency and throughput for 603R-based systems. Most integer
instructions execute in one clock cycle. The FPU is pipelined so a single-precision multiply-add
instruction can be issued every clock cycle.
The 603R provides independent on-chip, 16 Kbyte, four-way set-associative, physically
addressed caches for instructions and data, as well as on-chip instruction and data Memory
Management Units (MMUs). The MMUs contain 64-entry, two-way set-associative, Data and
Instruction Translation Lookaside Buffers (DTLB and ITLB) that provide support for
demand-paged virtual memory address translation and variable-sized block translation. The
TLBs and caches use a Least Recently Used (LRU) replacement algorithm. The 603R also supports block address translation through the use of two independent Instruction and Data Block
Address Translation (IBAT and DBAT) arrays of four entries each. Effective addresses are compared simultaneously with all four entries in the BAT array during block translation. In
accordance with the PowerPC architecture, if an effective address hits in both the TLB and BAT
array, the BAT translation has priority.
The 603R has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603R interface
protocol allows multiple masters to compete for system resources through a central external
arbiter. The 603R provides a three-state coherency protocol that supports the exclusive, modified, and invalid cache states. This protocol is a compatible subset of the MESI
(Modified/Exclusive/Shared/Invalid) four-state protocol and operates coherently in systems that
contain four-state caches. The 603R supports single-beat and burst data transfers for memory
accesses, and supports memory-mapped I/Os.
The 603R uses an advanced, 0.29 µm 5-metal-layer CMOS process technology and maintains
full interface compatibility with TTL devices.
5. Signal Description
Figure 5-1 on page 5, Table 10-5 and Table 10-6 on page 20 describe the signals on the
TSPC603R and indicate signal functions. The test signals, TRST, TMS, TCK, TDI and TDO,
comply with the subset P-1149.1 of the IEEE testability bus standard.
The three signals LSSD_MODE, LI_TSTCLK and L2_TSTCLK are test signals for factory use
only and must be pulled up to VDD for normal machine operations.
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TSPC603R
Figure 5-1.
Functional Signal Groups
BR
ADDRESS
ARBITRATION
BG
ABB
TS
ADDRESS
START
1
1
1
1
1
1
1
64
8
A[0-31]
ADDRESS
BUS
AP[0-3]
APE
TT[0-4]
TBST
TSIZ[0-2]
GBL
TRANSFER
ATTRIBUTE
CI
WT
CSE[0-1]
TC[0-1]
1
32
1
1
1
1
ARTRY
5
1
3
2
1
1
SYSCLK
CLOCKS
PLL_CFG[0-3]
1
VOLTDETGND
DP[0-7]
DPE
DATA
TRANSFER
DBDIS
TA
DR TR Y
TEA
DATA
TERMINATION
1
603r
INT, SMI
MCP
2
2
HRESET, SRESET
INTERRUPTS
CHECKSTOPS
RESET
2
2
1
1
RSRV
QREQ, QACK
TBEN
PROCESSOR
STATUS
TLBISYNC
1
1
1
1
3
4
20
POWER SUPPLY
INDICATOR
DATA
ATTRIBUTION
DH[0-31], DL[0-31]
CKSTP_IN, CKSTP_OUT
5
CLK_OUT
DBB
1
1
ADDRESS
TERMINATION
DBWO
4
2
AACK
DBG
1
19
40
1
TRST, TCK, TMS, TDI, TD0
LSSD_MODE
L1_TSTCLK, L2_TSTCLK
JTAG/COP
INTERFACE
LSSD TEST
CONTROL
VDD
OVDD
GND
POWER SUPPLY
AVDD
6. Detailed Specifications
This specification describes the specific requirements for the microprocessor TSPC603R, in
compliance with MIL-STD-883 class B or Atmel standard screening.
7. Applicable Documents
1. MIL-STD-883: Test methods and procedures for electronics
2. MIL-PRF-38535: General specifications for microcircuits
The microcircuits are in accordance with the applicable documents and as specified herein.
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7.1
Design and Construction
7.1.1
Terminal Connections
Depending on the package, the terminal connections are as shown in Table 10-2 on page 15,
Table 10-4 on page 18, ”Recommended Operating Conditions” on page 6, Figure 15-2 on page
49, Figure 15-4 on page 52 and Figure 5-1 on page 5.
7.1.2
Lead Material and Finish
Lead material and finish shall be as specified in MIL-STD-1835. (See “Package Mechanical
Data” on page 47.)
7.2
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only and functional operation at the maximum is
not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent
damage to the device.
7.2.1
Absolute Maximum Ratings for the 603R(1)(2)(3)
Parameter
Symbol
Min
Max
Unit
Core supply voltage
VDD
-0.3
2.75
V
PLL supply voltage
AVDD
-0.3
2.75
V
I/O supply voltage
OVDD
-0.3
3.6
V
VIN
-0.3
5.5
V
TSTG
-55
+150
°C
Input voltage
Storage temperature range
Notes:
1. Caution: The input voltage must not be greater than OVDD by more than 2.5V at any time,
including during power-on reset.
2. Caution: The OVDD voltage must not be greater than VDD/AVDD by more than 1.2V at any time,
including during power-on reset.
3. Caution: The VDD/AVDD voltage must not be greater than OVDD by more than 0.4V at any time,
including during power-on reset.
Functional operating conditions are given in AC and DC electrical specifications. Stresses
beyond the absolute maximums listed may affect device reliability or cause permanent damage
to the device.
7.2.2
Recommended Operating Conditions
The following are the recommended and tested operating conditions. Proper device operation
outside of these ranges is not guaranteed.
7.2.3
Recommended Operating Conditions
Parameter
6
Symbol
Min
Max
Unit
Core supply voltage
VDD
2.375
2.625
V
PLL supply voltage
AVDD
2.375
2.625
V
I/O supply voltage
OVDD
3.135
3.465
V
Input voltage
VIN
GND
5.5
V
Operating temperature
Tc
-55
+125
°C
Junction operating temperature specific to Cerquad
Tj
–
+135
°C
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8. Thermal Characteristics
8.1
CBGA 255 and CI-CGA 255 Packages
The data found in this section concerns 603R devices packaged in the 255-lead 21 mm
multi-layer ceramic (MLC) and ceramic BGA package. Data is included for use with a Thermalloy #2328B heat sink.
The internal thermal resistance for this package is negligible due to the exposed die design. A
thermal interface material is recommended at the package lid to heat sink interface to minimize
the thermal contact resistance.
Additionally, the CBGA package offers an excellent thermal connection to the card and power
planes. Heat generated at the chip is dissipated through the package, the heat sink (when used)
and the card. The parallel heat flow paths result in the lowest overall thermal resistance as well
as offer significantly better power dissipation capability if a heat sink is not used.
The thermal characteristics for the flip-chip CBGA and CI-CGA packages are as follows:
Thermal resistance (junction-to-case) = Rjc or
θjc = 0.095°C/Watt for the 2 packages.
Thermal resistance (junction-to-ball) = Rjb or
θjb = 3.5°C/Watt for the CBGA package.
Thermal resistance (junction-to-bottom SCI) = Rjs or
θjs = 3.7°C/Watt for the CI-CGA package.
The junction temperature can be calculated from the junction to ambient thermal resistance, as
follow:
Junction temperature:
Tj = Ta + (Rjc + Rcs + Rsa) × P
where:
Ta is the ambient temperature in the vicinity of the device
Rjc is the die junction to case thermal resistance of the device
Rcs is the case to heat sink thermal resistance of the interface material
Rsa is the heat sink to ambient thermal resistance
P is the power dissipated by the device
During operation, the die-junction temperatures (Tj) should be maintained at a lower value than
the value specified in ”Recommended Operating Conditions” on page 6.
The thermal resistance of the thermal interface material (Rcs) is typically about 1°C/Watt.
Assuming a Ta of 85°C and a consumption (P) of 3.6 Watts, the junction temperature of the
device would be as follow:
Tj = 85°C + (0.095°C/Watt + 1°C/Watt + Rsa) × 3.5 Watts.
For the Thermalloy heat sink #2328B, the heat sink-to-ambient thermal resistance (Rsa) versus
airflow velocity is shown in Figure 8-1.
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5410B–HIREL–09/05
Figure 8-1.
CBGA Thermal Management Example
Heat Sink Thermal Resistance
Rsa (°C/W)
7
6
5
4
3
2
1
0
0
1
2
3
Approach Air Velocity (m/sec)
Assuming an air velocity of 1 m/sec, the associated overall thermal resistance and junction temperature, found in Table 8-1 will result.
Table 8-1.
Thermal Resistance and Junction Temperature
Configuration
With 2328B heat sink
Rja (°C/W)
Tj (°C)
5
106
Vendors such as Aavid, Thermalloy®, and Wakefield Engineering can supply heat sinks with a
wide range of thermal performance.
8.2
HiTCE CBGA Package
Table 8-2.
HiTCE CBGA Package
Characteristic
Symbol
Value
Unit
RθJ
7.5
°C/W
Junction-to-ambient thermal resistance natural convection,
four-layer (2s2p) board
RθJMA
22.4(2)
°C/W
Junction to board thermal resistance
Notes: 1. Simulation, no convection air flow.
2. Per JEDEC JESD51-2 with the board horizontal.
3. Per JEDEC JESD51-8 with the board horizontal.
RθJB
11.7(3)
°C/W
Junction-to-bottom of balls
8.3
(1)
CERQUAD 240 Package
This section provides thermal management data for the 603R. This information is based on a
typical desktop configuration using a 240 lead, 32 mm x 32 mm, wire-bond CERQUAD package
with the cavity up (the silicon die is attached to the bottom of the package). This configuration
enables dissipation through the PCB.
The thermal characteristics for a wire-bond CERQUAD package are as follows:
• Thermal resistance (junction to bottom of the case) (typical) = Rθjc or θjc = 2.5°C/Watt
• Thermal resistance (junction to top of the case) is typically 16°C/W
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8.3.1
Thermal Management Example
The junction temperature can be calculated from the junction to ambient thermal resistance, as
follows:
Junction temperature:
Tj = TC + Rθjc × P
Tj = Ta + (Rcs + Rsa) × P + Rθjc × P
so
Tj = Ta + (Rθjc + Rcs + Rsa) × P
Where:
Ta is the ambient temperature in the vicinity of the device
Rθja is the junction to ambient resistance
Rθjc is the junction to case thermal resistance of the device
Rcs is the case to heat sink thermal resistance of the interface material
Rsa is the heat sink to ambient thermal resistance
P is the power dissipated by the device
Because dissipation is made through the PCB, Rcs and Rsa are user values, and can vary considerably depending on the customer’s application.
In a typical customer application, if Rcs is 0.5°C/W, Rsa is 3°C/W and Ta is 110°C, Tj can be
estimated.
Tj = 110°C + (2.5 + 0.5 + 3) × 2.5 = 125°C
Note that verification of external thermal resistance and case temperature should be performed
for each application. Thermal resistance depends on many factors including the amount of air
turbulence and can therefore vary considerably.
9. Power Consideration
The PowerPC 603R is a microprocessor specifically designed for low-power operation. Like the
603e microprocessor version, the 603R provides both automatic and program-controllable
power reduction modes for progressive reduction of power consumption. This section describes
the hardware support provided by the 603R for power management.
9.1
Dynamic Power Management
Dynamic power management automatically powers up and down the individual execution units
of the 603R, based upon the contents of the instruction stream. For example, if no floating-point
instructions are being executed, the floating-point unit is automatically powered down. Power is
not actually removed from the execution unit; instead, each execution unit has an independent
clock input, which is automatically controlled on a clock-by-clock basis. Since CMOS circuits
consume negligible power when they are not switching, stopping the clock to an execution unit
effectively eliminates its power consumption. The operation of DPM is completely transparent to
software or any external hardware. Dynamic power management is enabled by setting bit 11 in
HID0 on power-up, following HRESET.
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9.2
Programmable Power Modes
The 603R provides four programmable power states, full power, doze, nap and sleep. The software selects these modes by setting one (and only one) of the three power saving mode bits.
The hardware can enable a power management state through external asynchronous interrupts.
The hardware interrupt causes the transfer of program flow to interrupt the handler code. The
appropriate mode is then set by the software. The 603R provides a separate interrupt and interrupt vector for power management, the System Management Interrupt (SMI). The 603R also
contains a decrement timer which allows it to enter the nap or doze mode for a predetermined
amount of time and then return to full power operation through the Decrementer Interrupt (DI).
Note that the 603R cannot switch from power-on management mode to another without first
returning to full on mode. The nap and sleep modes disable bus snooping; therefore, a hardware
handshake is provided to ensure coherency before the 603R enters these power management
modes.
Table 9-1 summarizes the four power states.
Table 9-1.
Power PC 603R Microprocessor Programmable Power Modes
PM Mode
Functioning Units
Activation Method
Full-power Wake-up Method
Full Power
All units active
–
–
Full Power (with DPM)
Requested logic by demand
By instruction dispatch
–
Doze
- Bus snooping
- Data cache as needed
- Decrementer timer
Controlled by SW
External asynchronous exceptions(1)
Decrementer interrupt
Reset
Nap
Decrementer timer
Controlled by hardware and
software
External asynchronous exceptions
Decrementer interrupt
Reset
Sleep
None
Controlled by hardware and
software
External asynchronous exceptions
Reset
Note:
1. Exceptions are referred to as interrupts in the architecture specification.
9.3
Power Management Modes
The following describes the characteristics of the 603R’s power management modes, the
requirements for entering and exiting the various modes, and the system capabilities provided
by the 603R while the power management modes are active.
Full Power Mode with DPM Disabled
Full power mode with DPM disabled; power mode is selected when the DPM enable bit (bit 11)
in HID0 is cleared
• Default state following power-up and HRESET
• All functional units are operating at full processor speed at all times
Full Power Mode with DPM Enabled
Full power mode with DPM enabled (HID0[11] = 1); provides on-chip power management without affecting the functionality or performance of the 603R
• Required functional units are operating at full processor speed
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• Functional units are clocked only when needed
• No software or hardware intervention required after mode is set
• Software/hardware and performance are transparent
Doze Mode
The doze mode disables most functional units but maintains cache coherency by enabling the
bus interface unit and snooping. A snoop hit will cause the 603R to enable the data cache, copy
the data back to the memory, disable the cache, and fully return to the doze state. In this mode:
• Most functional units are disabled
• Bus snooping and time base/decrementer are still enabled
• Dose mode sequence:
– Set doze bit (HID0[8) = 1)
– 603R enters doze mode after several processor clocks
• There are several methods for returning to full-power mode
– Assert INT, SMI, MCP or decrementer interrupts
– Assert hard reset or soft reset
• The Transition to full-power state takes no more than a few processor cycles
• Phase Locked Loop (PLL) running and locked to SYSCLK
Nap Mode
The nap mode disables the 603R but still maintains the phase locked loop (PLL) and the time
base/decrementer. The time base can be used to restore the 603R to full-on state after a programmed amount of time. Because bus snooping is disabled for nap and sleep modes, a
hardware handshake using the quiesce request (QREQ) and quiesce acknowledge (QACK) signals is required to maintain data coherency. The 603R will assert the QREQ signal to indicate
that it is ready to disable bus snooping. When the system has ensured that snooping is no
longer necessary, it will assert QACK and the 603R will enter the sleep or nap mode. In this
mode:
• The time base/decrementer is still enabled
• Most functional units are disabled (including bus snooping)
• All non-essential input receivers are disabled
• Nap mode sequence:
– Set nap bit (HID0[9] = 1)
– 603R asserts quiesce request (QREQ) signal
– System asserts quiesce acknowledge (QACK) signal
– 603R enters sleep mode after several processor clocks
• There are several methods for returning to full-power mode:
– Assert INT, SPI, MCP or decrementer interrupts
– Assert hard reset or soft reset
• Transition to full-power takes no more than a few processor cycles
• The PLL is running and locked to SYSCLK
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Sleep Mode
Sleep mode consumes the least amount of power of the four modes since all functional units are
disabled. To conserve the maximum amount of power, the PLL may be disabled and the
SYSCLK may be removed. Due to the fully static design of the 603R, the internal processor
state is preserved when no internal clock is present. Because the time base and decrementer
are disabled while the 603R is in sleep mode, the 603R’s time base contents will have to be
updated from an external time base following sleep mode if accurate time-of-day maintenance is
required. Before the 603R enters the sleep mode, the 603R will assert the QREQ signal to indicate that it is ready to disable bus snooping. When the system has ensured that snooping is no
longer necessary, it will assert QACK and the 603R will enter the sleep mode.
In this mode:
• All functional units are disabled (including bus snooping and time base)
• All non-essential input receivers are disabled
– Internal clock regenerators are disabled
– The PLL is still running (see below)
• Sleep mode sequence
– Set sleep bit (HID0[10] = 1)
– 603R asserts quiesce request (QREQ)
– System asserts quiesce acknowledge (QACK)
– 603R enters sleep mode after several processor clocks
• There are several methods for returning to full-power mode
– Assert INT, SMI, or MCP interrupts
– Assert hard reset or soft reset
• The PLL may be disabled and SYSCLK may be removed while in sleep mode
• Return to full-power mode after PLL and SYSCLK disabled in sleep mode
– Enable SYSCLK
– Reconfigure PLL into the desired processor clock mode
– System logic waits for PLL startup and relock time (100 µs)
– System logic asserts one of the sleep recovery signals (for example, INT or SMI)
9.4
Power Management Software Considerations
Since the 603R is a dual issue processor with out-of-order execution capabilities, care must be
taken with the way the power management mode is entered. Furthermore, nap and sleep modes
require all outstanding bus operations to be completed before the power management mode is
entered. Normally, during the system configuration time, one of the power management modes
would be selected by setting the appropriate HID0 mode bit. Later on, the power management
mode is invoked by setting the MSR[POW] bit. To provide a clean transition into and out of the
power management mode, the stmsr[POW] should be preceded by a sync instruction and followed by an isync instruction.
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9.5
Power Dissipation
Table 9-2.
Power Dissipation(1)(2)(3)(4) with VDD/AVDD = 2.5 ±5%V, OVDD = 3.3 ±5%V, GND = 0V, 0°C ≤ TC ≤ 125°C
Cerquad 240 Package
CPU Clock Frequency
CBGA 255, HiTCE CBGA 255 and CI-CGA 255
166 MHz
200 MHz
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
Units
Typical
2.1
2.5
2.1
2.5
3
3.5
4
W
Max
3.2
4
3.2
4
4.6
5.3
6
W
1.5
1.7
1.5
1.7
1.8
2
2.1
W
100
120
100
120
140
160
180
mW
96
110
96
110
123
135
150
mW
60
60
60
60
60
60
60
mW
Full-on Mode (DPM Enabled)
Doze Mode
Typical
Nap Mode
Typical
Sleep Mode
Typical
Sleep Mode-PLL Disabled
Typical
Sleep Mode-PLL and SYSCLK Disabled
Typical
25
25
25
25
25
25
25
mW
Maximum
60
60
60
60
60
80
100
mW
Notes:
1. These values apply for all valid PLL_CFG[0-3] settings and do not include output driver power (OVDD) or analog supply
power (AVDD). OVDD power is system dependent but is typically ≤ 10% of VDD. Worst case AVDD = 15 mW.
2. Typical power is an average value measured at VDD = AVDD = 2.5V, OVDD = 3.3V, in a system executing typical applications
and benchmark sequences.
3. Maximum power is measured at VDD = 2.625V using a worst-case instruction mix.
4. To calculate the power consumption at low temperature (-55°C), use a factor of 1.25.
9.6
Marking
Each microcircuit is legible and permanently marked with at least the following information:
• Atmel logo
• Manufacturer’s part number
• Class B identification if applicable
• Date code of inspection lot
• ESD identifier if available
• Country of manufacture
10. Pin Assignments
10.1
CBGA 255 and CI-CGA 255 Packages
Figure 10-1 (pin matrix) shows the pinout as viewed from the top of the CBGA and CI-CGA
packages. The direction of the top surface view is shown by the side profile of the packages.
13
5410B–HIREL–09/05
Figure 10-1. CBGA 255, HiTCE CBGA 255 and CI–CGA 255 Top View
Pin matrix top view
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
View
Substrate Assembly
Die
CBGA 255, CBGA HiTCE 255
Encapsulant
CI-CGA 255
Not to scale
14
TSPC603R
5410B–HIREL–09/05
TSPC603R
10.1.1
Pinout Listing
Table 10-1.
Power and Ground Pins
CBGA, HiTCE CBGA and CI-CGA Pin Number
VDD
PLL (AVDD)
A10
Internal Logic(1) (VDD)
F06, F08, F09, F11, G07, G10, H06, H08, H09, H11,
J06, J08, J09, J11, K07, K10, L06, L08, L09, L11
I/O Drivers(1) (OVDD)
C07, E05, E07, E10, E12, G03, G05, G12, G14, K03,
K05, K12, K14, M05, M07, M10, M12, P07, P10
Notes:
GND
C05, C12, E03, E06, E08, E09, E11, E14, F05, F07,
F10, F12, G06, G08, G09, G11, H05, H07, H10,
H12, J05, J07, J10, J12, K06, K08, K09, K11, L05,
L07, L10, L12, M03, M06, M08, M09, M11, M14,
P05, P12
1. OVDD inputs apply power to the I/O drivers and VDD inputs supply power to the processor core.
Table 10-2.
Signal Pinout Listing
Signal Name
CBGA, HiTCE CBGA and CI-CGA Pin Number
Active
I/O
A[0-31]
C16, E04, D13, F02, D14, G01, D15, E02, D16, D04, E13, G02, E15, H01, E16, H02,
F13, J01, F14, J02, F15, H03, F16, F04, G13, K01, G15, K02, H16, M01, J15, P01
High
I/O
AACK
L02
Low
Input
ABB
K04
Low
I/O
AP[0-3]
C01, B04, B03, B02
High
I/O
APE
A04
Low
Output
ARTRY
J04
Low
I/O
BG
L01
Low
Input
BR
B06
Low
Output
CI
E01
Low
Output
CKSTP_IN
D08
Low
Input
CKSTP_OUT
A06
Low
Output
CLK_OUT
D07
-
Output
CSE[0-1]
B01, B05
High
Output
DBB
J14
Low
I/O
DBG
N01
Low
Input
DBDIS
H15
Low
Input
DBWO
G04
Low
Input
DH[0-31]
P14, T16, R15, T15, R13, R12, P11, N11, R11, T12, T11, R10, P09, N09, T10, R09,
T09, P08, N08, R08, T08, N07, R07, T07, P06, N06, R06, T06, R05, N05, T05, T04
High
I/O
DL[0-31]
K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15, N13, N14, P16, P15,
R16, R14, T14, N10, P13, N12, T13, P03, N03, N04, R03, T01, T02, P04, T03, R04
High
I/O
DP[0-7]
M02, L03, N02, L04, R01, P02, M04, R02
High
I/O
DPE
A05
Low
Output
DRTRY
G16
Low
Input
15
5410B–HIREL–09/05
Table 10-2.
Signal Pinout Listing (Continued)
Signal Name
CBGA, HiTCE CBGA and CI-CGA Pin Number
Active
I/O
GBL
F01
Low
I/O
HRESET
A07
Low
Input
INT
B15
Low
Input
L1_TSTCLK(1)
D11
-
Input
L2_TSTCLK(1)
D12
-
Input
B10
Low
Input
MCP
C13
Low
Input
PLL_CFG[0-3]
A08, B09, A09, D09
High
Input
QACK
D03
Low
Input
QREQ
J03
Low
Output
RSRV
D01
Low
Output
SMI
A16
Low
Input
SRESET
B14
Low
Input
SYSCLK
C09
-
Input
TA
H14
Low
Input
TBEN
C02
High
Input
TBST
A14
Low
I/O
TC[0-1]
A02, A03
High
Output
TCK
C11
-
Input
TDI
A11
High
Input
TDO
A12
High
Output
TEA
H13
Low
Input
TLBISYNC
C04
Low
Input
TMS
B11
High
Input
TRST
C10
Low
Input
TS
J13
Low
I/O
TSIZ[0-2]
A13, D10, B12
High
I/O
TT[0-4]
B13, A15, B16, C14, C15
High
I/O
WT
D02
Low
Output
B07, B08, C03, C06, C08, D05, D06, F03, H04, J16
Low
Input
F03
Low
Output
LSSD_MODE
(1)
NC
(2)
VOLTDETGND
Notes:
16
1. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.
2. NC (not connected) in the 603e BGA package; internally tied to GND in the 603R BGA package to indicate to the power supply that a low-voltage processor is present.
TSPC603R
5410B–HIREL–09/05
OVDD
DL29
DL30
DL31
GND
DH31
DH30
DH29
OGND
OVDD
DH28
DH27
DH26
DH25
DH24
DH23
OGND
DH22
OVDD
DH21
DH20
DH19
DH18
DH17
DH16
OGND
DH15
OVDD
DH14
DH13
DH12
DH11
DH10
DH9
OGND
OVDD
DH8
DH7
DH6
DL22
DL21
DL20
OGND
OVDD
DL19
DL18
DL17
DH5
DH4
DH3
OGND
OVDD
DH2
DH1
DH0
GND
DL16
DL15
DL14
OGND
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
240
239
238
237
236
235
234
233
232
231
230
229
228
227
226
225
224
223
222
221
220
219
218
217
216
215
214
213
212
211
210
209
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
OVDD
GND
OGND
CI
WT
QACK
TBEN
TLBISYNC
RSRV
AP0
AP1
OVDD
OGND
AP2
AP3
CSE0
TC0
TC1
OVDD
CLK_OUT
OGND
BR
APE
DPE
CKSTP_OUT
CKSTP_IN
HRESET
PLL_CFG0
SYSCLK
PLL_CFG1
PLL_CFG2
AVDD
PLL_CFG3
VDD
GND
LSSD_MODE
L1_TSTCLK
L2_TSTCLK
TRST
TCK
TMS
TDI
TDO
TSIZ0
TSIZ1
TSIZ2
OVDD
OGND
TBST
TT0
TT1
SRESET
INT
SMI
MCP
TT2
TT3
OVDD
GND
OGND
TSPC603R
10.2
GBL
A1
A3
VDD
A5
A7
A9
OGND
GND
OVDD
A11
A13
A15
VDD
A17
A19
A21
OGND
GND
OVDD
A23
A25
A27
VDD
DBWO
DBG
BG
AACK
GND
A29
QREQ
ARTRY
OGND
VDD
OVDD
ABB
A31
DP0
GND
DP1
DP2
DP3
OGND
VDD
OVDD
DP4
DP5
DP6
GND
DP7
DL23
DL24
OGND
OVDD
DL25
DL26
DL27
DL28
VDD
OGND
CERQUAD 240 Package
Figure 10-2. CERQUAD 240: Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
1
TOP VIEW
5410B–HIREL–09/05
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
TT4
A0
A2
VDD
A4
A6
A8
OVDD
GND
OGND
A10
A12
A14
VDD
A16
A18
A20
OVDD
GND
OGND
A22
A24
A26
VDD
DRTR
TA
TEA
DBDIS
GND
A28
CSE1
TS
OVDD
VDD
OGND
DBB
A30
DL0
GND
DL1
DL2
DL3
OVDD
VDD
OGND
DL4
DL5
DL6
GND
DL7
DL8
DL9
OVDD
OGND
DL10
DL11
DL12
DL13
VDD
OVDD
17
10.2.1
Pinout Listing
Table 10-3.
Power and Ground Pins
CERQUAD Pin Number
VCC
GND
PLL (AVDD)
209
Internal Logic
4, 14, 24, 34, 44, 59, 122, 137, 147, 157, 167, 177,
207
9, 19,29, 39, 49, 65, 116, 132, 142, 152, 162, 172,
182, 206, 239
Output Drivers
10, 20, 35, 45, 54, 61, 70, 79, 88, 96, 104, 112, 121,
128, 138, 148, 163, 173, 183, 194, 222, 229, 240
8, 18, 33, 43, 53, 60, 69, 77, 86, 95, 103, 111, 120,
127, 136, 146, 161, 171, 181, 193, 220, 228, 238
Table 10-4.
Signal Pinout Listing
Signal Name
CERQUAD Pin Number
A[0-31]
179, 2, 178, 3, 176, 5, 175, 6, 174, 7, 170, 11, 169, 12, 168, 13, 166, 15, 165, 16, 164, 17, 160, 21, 159, 22,
158, 23, 151, 30, 144, 37
AACK
28
ABB
36
AP[0-3]
231,230,227,226
APE
218
ARTRY
32
BG
27
BR
219
CI
237
CKSTP_IN
215
CKSTP_OUT
216
CLK_OUT
221
CSE[0-1]
225,150
DBB
145
DBG
26
DBDIS
153
DBWO
25
DH[0-31]
115, 114, 113, 110, 109, 108, 99, 98, 97, 94, 93, 92, 91, 90, 89, 87, 85, 84, 83, 82, 81, 80, 78, 76, 75, 74, 73,
72, 71, 68, 67, 66
DL[0-31]
143, 141, 140, 139, 135, 134, 133, 131, 130, 129, 126, 125, 124, 123, 119, 118, 117, 107, 106, 105, 102, 101,
100, 51, 52, 55, 56, 57, 58, 62, 63, 64
DP[0-7]
38, 40, 41, 42, 46, 47, 48, 50
DPE
217
DRTRY
156
GBL
1
HRESET
214
18
TSPC603R
5410B–HIREL–09/05
TSPC603R
Table 10-4.
Signal Pinout Listing (Continued)
Signal Name
CERQUAD Pin Number
INT
188
L1_TSTCLK
(1)
204
L2_TSTCLK
(1)
203
LSSD_MODE(1)
205
MCP
186
PLL_CFG[0-3]
213, 211, 210, 208
QACK
235
QREQ
31
RSRV
232
SMI
187
SRESET
189
SYSCLK
212
TA
155
TBEN
234
TBST
192
TC[0-1]
224, 223
TCK
201
TDI
199
TDO
198
TEA
154
TLBISYNC
233
TMS
200
TRST
202
TS
149
TSIZ[0-2]
197, 196, 195
TT[0-4]
191, 190, 185, 184, 180
WT
236
NC
Notes:
1. These are test signals for factory use only and must be pulled up to VDD for normal machine operation.
2. OVDD inputs supply power to the I/O drivers and VDD inputs supply power to the processor core. Future members of the 603
family may use different OVDD and VDD input levels.
19
5410B–HIREL–09/05
Table 10-5.
Address and Data Bus Signal Index for Cerquad, CBGA 255 and CI-CGA 255 Packages
Signal
Type
Signal Name
Abbreviation
Signal Function
Address Bus
A[0-31]
If output, physical address of data to be transferred
If input, represents the physical address of a snoop operation
I/O
Data Bus
DH[0-31]
Represents the state of data, during a data write operation if output, or during a
data read operation if input
I/O
Data Bus
DL[0-31]
Represents the state of data, during a data write operation if output, or during a
data read operation if input
I/O
Table 10-6.
Signal Index for Cerquad, CBGA 255, HiTCE CBGA 255 and CI-CGA 255 Packages
Signal Name
Abbreviation
Signal Function
Signal
Type
Address Acknowledge
AACK
The address phase of a transaction is complete
Input
Address Bus Busy
ABB
If output, the 603R is the address bus master
If input, the address bus is in use
I/O
Address Bus Parity
AP[0-3]
If output, represents odd parity for each of 4 bytes of the physical address for a
transaction
If input, represents odd parity for each of 4 bytes of the physical address for
snooping operations
I/O
Address Parity Error
APE
Incorrect address bus parity detected on a snoop
Output
Address Retry
ARTRY
If output, detects a condition in which a snooped address tenure must be
retried
If input, must retry the preceding address tenure
I/O
Bus Grant
BG
May, with the proper qualification, assume mastership of the address bus
Input
Bus Request
BR
Request mastership of the address bus
Output
Cache Inhibit
Cl
A single-beat transfer will not be cached
Output
Checkstop Input
CKSTP_IN
Must terminate operation by internally gating off all clocks, and release all
outputs
Input
Checkstop Output
CKSTP_OUT
Has detected a checkstop condition and has ceased operation
Output
Cache Set Entry
CSE[0-1]
Cache replacement set element for the current transaction reloading into or
writing out of the cache
Output
Data Bus Busy
DBB
If output, the 603R is the data bus master
If input, another device is bus master
I/O
Data Bus Disable
DBDIS
(For a write transaction) must release data bus and the data bus parity to high
impedance during the following cycle
Input
Data Bus Grant
DBG
May, with the proper qualification, assume mastership of the data bus
Input
Data Bus Write Only
DBW0
May run the data bus tenure
Input
Data Bus Parity
DP[0-7]
If output, odd parity for each of 8 bytes of data write transactions
If input, odd parity for each byte of read data
I/O
Data Parity Error
DPE
Incorrect data bus parity
Output
Data Retry
DRTRY
Must invalidate the data from the previous read operation
Input
20
TSPC603R
5410B–HIREL–09/05
TSPC603R
Table 10-6.
Signal Index for Cerquad, CBGA 255, HiTCE CBGA 255 and CI-CGA 255 Packages (Continued)
Signal
Type
Signal Name
Abbreviation
Signal Function
Global
GBL
If output, a transaction is global
If input, a transaction must be snooped by the 603R
I/O
Hard Reset
HRESET
Initiates a complete hard reset operation
Input
Interrupt
INT
Initiates an interrupt if bit EE of MSR register is set
Input
LSSD_MODE
LSSD test control signal for factory use only
Input
L1_TSTCLK
LSSD test control signal for factory use only
Input
L2_TSTCLK
LSSD test control signal for factory use only
Input
Machine Check
Interrupt
MCP
Initiates a machine check interrupt operation if the bit ME of MSR register and
bit EMCP of HID0 register are set
Input
PLL Configuration
PLL_CFG[0-3]
Configures the operation of the PLL and the internal processor clock frequency
Input
Power supply indicator
VOLTDETGND
Available only on BGA package
Indicates to the power supply that a low-voltage processor is present.
Output
Quiescent
Acknowledge
QACK
All bus activity has terminated and the 603R may enter a quiescent (or low
power) state
Input
Quiescent Request
QREQ
Is requesting all bus activity normally to enter a quiescent (low power) state
Output
Reservation
RSRV
Represents the state of the reservation coherency bit in the reservation
address register
Output
System Management
Interrupt
SMI
Initiates a system management interrupt operation if the bit EE of MSR register
is set
Input
Soft Reset
SRESET
Initiates processing for a reset exception
Input
System Clock
SYSCLK
Represents the primary clock input for the 603R, and the bus clock frequency
for 603R bus operation
Input
Test Clock
CLK_OUT
Provides PLL clock output for PLL testing and monitoring
Output
Transfer Acknowledge
TA
A single-beat data transfer completed successfully or a data beat in a burst
transfer completed successfully
Input
Timebase Enable
TBEN
The timebase should continue clocking
Input
Transfer Burst
TBST
If output, a burst transfer is in progress
If input, when snooping for single-beat reads
I/O
Transfer Code
TC[0-1]
Special encoding for the transfer in progress
Output
Test Clock
TCK
Clock signal for the IEEE P1149.1 test access port (TAP)
Input
Test Data Input
TDI
Serial data input for the TAP
Input
Test Data Output
TDO
Serial data output for the TAP
Output
Transfer Error
Acknowledge
TEA
A bus error occurred
Input
TLBI Sync
TLBISYNC
Instruction execution should stop after execution of a tlbsync instruction
Input
Test Mode Select
TMS
Selects the principal operations of the test-support circuitry
Input
Test Reset
TRST
Provides an asynchronous reset of the TAP controller
Input
Transfer Size
TSIZ[0-2]
For memory accesses, these signals along with TBST indicate the data
transfer size for the current bus operation
I/O
Factory Test
21
5410B–HIREL–09/05
Table 10-6.
Signal Index for Cerquad, CBGA 255, HiTCE CBGA 255 and CI-CGA 255 Packages (Continued)
Signal Name
Signal
Type
Abbreviation
Signal Function
Transfer Start
TS
If output, begun a memory bus transaction and the address bus and transfer
attribute signals are valid
If input, another master has begun a bus transaction and the address bus and
transfer attribute signals are valid for snooping (see GBL)
I/O
Transfer Type
TT[0-4]
Type of transfer in progress
I/O
Write-through
WT
A single-beat transaction is write-through
Output
11. Electrical Characteristics
11.1
General Requirements
All static and dynamic electrical characteristics specified for inspection purposes and the relevant measurement conditions are given below:
• Table 11-1: Static electrical characteristics for the electrical variants
• Table 11-2: Dynamic electrical characteristics for the 603R
The processor core frequency is determined by the bus (SYSCLK) frequency and the settings of
the PLL_CFG0 to PLL_CFG3 signals. All timings are respectively specified to the rising edge of
SYSCLK.
These specifications are for 166 MHz to 300 MHz processor core frequencies for CBGA 255,
HiTCE CBGA 255 and CI-CGA 255 packages and 166 MHz to 200 MHz processor core frequencies for the Cerquad 240 package.
11.2
Static Characteristics
Table 11-1.
Electrical Characteristics with VDD = AVDD = 2.5V ±5%; OVDD = 3.3 ±5%V, GND = 0V, -55°C ≤ TC ≤ 125°C
Characteristics
Symbol
Min
Max
Unit
Input High Voltage (all inputs except SYSCLK)
VIH
2
5.5
V
Input Low Voltage (all inputs except SYSCLK)
VIL
GND
0.8
V
CVIH
2.4
5.5
V
CVIL
GND
0.4
V
IIN
-
30
µA
IIN
-
300
µA
ITSI
-
30
µA
SYSCLK Input High Voltage
SYSCLK Input Low Voltage
(1)(3)
VIN = 3.465V
Input Leakage Current
(1)(3)
VIN = 5.5V
(1)(3)
Hi-Z (off-state)
Leakage Current
VIN = 3.465V
VIN = 5.5V(1)(3)
ITSI
-
300
µA
Output High Voltage
IOH = -7 mA
VOH
2.4
-
V
IOL = +7 mA
VOL
-
0.4
V
CIN
-
10
pF
CIN
-
15
pF
Output Low Voltage
(2)
Capacitance, VIN = 0V, f = 1 MHz
(excludes TS, ABB, DBB, and ARTRY)
Capacitance, VIN = 0V, f = 1 MHz(2) (for TS, ABB, DBB, and ARTRY)
Notes:
22
1. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK, and JTAG signals).
2. Capacitance is periodically sampled rather than 100% tested.
TSPC603R
5410B–HIREL–09/05
TSPC603R
3. Leakage currents are measured for nominal OVDD and VDD or both OVDD and VDD. Same variation (for example, both VDD
and OVDD vary by either +5% or -5%)
11.3
Dynamic Characteristics
11.3.1
Clock AC Specifications
Table 11-2 provides the clock AC timing specifications as defined in Figure 11-1.
Table 11-2.
Clock AC Timing Specifications(1)(2)(3)(4) with VDD = AVDD = 2.5V ±5%; OVDD = 3.3 ±5%V, GND = 0V,
-55°C ≤ TC ≤ 125°C
CBGA 255, HiTCE CBGA
255, CI-CGA 255 and
CERQUAD
166 MHz
Figure
Number
200 MHz
CBGA 255, HiTCE CBGA 255 and CI-CGA 255
233 MHz
266 MHz
300 MHz
Characteristics
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Note
Processor Frequency
150
166
150
200
180
233
180
266
180
300
MHz
(5)
VCO Frequency
300
332
300
400
360
466
360
532
360
600
MHz
(5)
SYSCLK (bus)
Frequency
25
66.7
33.3
66.7
33.3
75
33.3
75
33.3
75
MHz
(5)
1
SYSCLK Cycle Time
15
30
13.3
30
13.3
30
13.3
30
13.3
30
ns
2,3
SYSCLK Rise and
Fall Time
–
2
–
2
–
2
–
2
–
2
ns
(1)
4
SYSCLK Duty Cycle
(1.4V measured)
40
60
40
60
40
60
40
60
40
60
%
(3)
SYSCLK Jitter
–
±150
–
±150
–
±150
–
±150
–
±150
ps
(2)
603R Internal PLL
Relock Time
–
100
–
100
–
100
–
100
–
100
µs
(3)(4)
Notes:
1.
2.
3.
4.
Rise and fall times for the SYSCLK input are measured from 0.4V to 2.4V.
Cycle-to-cycle jitter is guaranteed by design.
Timing is guaranteed by design and characterization and is not tested.
The PLL relock time is the maximum amount of time required for PLL lock after a stable VDD, OVDD, AVDD and SYSCLK are
reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after
the PLL relock time (100 µs) during the power-on reset sequence.
5. Caution: The SYSCLK frequency and PLL_CFG[0-3] settings must be chosen so that the resulting SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0-3] signal description for valid PLL_CFG[0-3] settings.
Figure 11-1. SYSCLK Input Timing Diagram
1
2
3
CVih
SYSCLK
VM
VM
VM
CVil
VM = Midpoint Voltage (1.4V)
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5410B–HIREL–09/05
11.3.2
Input AC Specifications
Table 11-3 provides the input AC timing specifications for the 603R as defined in Figure 11-2
and Figure 11-3.
Table 11-3.
Input AC Timing Specifications(1) with VDD = AVDD = 2.5V ±5%; OVDD = 3.3 ±5%V, GND = 0V,
-55°C ≤ TC ≤ 125°C
CBGA 255, HiTCE
CBGA 255, CI-CGA
255 and Cerquad
240 Packages
Figure
Number
166, 200 MHz
CBGA 255, HiTCE CBGA 255
and CI-CGA 255
233, 266 MHz
300 MHz
Characteristics
Min
Max
Min
Max
Min
Max
Unit
Note
10a
Address/data/transfer attribute inputs valid to
SYSCLK (input setup)
2.5
–
2.5
–
2.5
–
ns
(2)
10b
All other inputs valid to SYSCLK (input setup)
4
–
3.5
–
3.5
–
ns
(3)
Mode select inputs valid to HRESET (input
setup) (for DRTRY, QACK and TLBISYNC)
8
–
8
–
8
–
tsyscl
(4)(5)(6
10c
11a
SYSCLK to address/data/transfer attribute
inputs invalid (input hold)
1
–
1
–
1
–
ns
(2)
11b
SYSCLK to all other inputs invalid (input hold)
1
–
1
–
1
–
ns
(3)
11c
HRESET to mode select inputs invalid (input
hold) (for DRTRY, QACK, and TLBISYNC)
0
–
0
–
0
–
ns
Notes:
)(7)
k
(4)(6)
(7)
1. All input specifications are measured from the TTL level (0.8 or 2V) of the signal in question to the 1.4V of the rising edge of
the input SYSCLK. Both input and output timings are measured at the pin. See Figure 11-3.
2. Address/data/transfer attribute input signals are composed of the following: A[0-31], AP[0-3], TT[0-4], TC[0-1], TBST,
TSIZ[0-2], GBL, DH[0-31], DL[0-31], DP[9-7].
3. All other input signals are composed of the following: TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO, TA, DRTRY, TEA,
DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC.
4. The setup and hold time is with respect to the rising edge of HRESET. See Figure 11-3.
5. tsysclk is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied
by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question.
6. These values are guaranteed by design, and are not tested.
7. This specification is for configuration mode only. Also note that HRESET must be held asserted for a minimum of 255 bus
clocks after the PLL relock time (100 µs) during the power-on reset sequence.
Figure 11-2. Input Timing Diagram
VM
SYSCLK
10a
10b
11a
11b
All inputs
VM = Midpoint Voltage (1.4V)
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Figure 11-3. Mode Select Input Timing Diagram
VM
HRESET
10c
11c
MODE PINS
VM = Midpoint Voltage (1.4V)
11.3.3
Output AC Specifications
Table 11-4 provides the output AC timing specifications for the 603R (shown in Figure 11-4).
Table 11-4.
Output AC Timing Specifications(1)(2) with VDD = AVDD = 2.5V ±5%; OVDD = 3.3 ±5%V, GND = 0V, CL = 50 pF,
55°C ≤ TC ≤ 125°C
CBGA 255, HiTCE
CBGA 255, CI-CGA
255 and Cerquad
240 Packages
166, 200 MHz
Number
Characteristics
CBGA 255, HiTCE CBGA 255 and
CI-CGA 255
233, 266 MHz
300 MHz
Min
Max
Min
Max
Min
Max
Unit
Note
12
SYSCLK to output driven (output
enable time)
1
–
1
–
1
–
ns
13a
SYSCLK to output valid (5.5V to 0.8V –
TS, ABB, ARTRY, DBB)
–
9
–
9
–
9
ns
(4)
13b
SYSCLK to output valid (TS, ABB,
ARTRY, DBB)
–
8
–
8
–
8
ns
(6)
14a
SYSCLK to output valid (5.5V to 0.8V –
all except TS, ABB, ARTRY, DBB)
–
11
–
11
–
11
ns
(4)
14b
SYSCLK to output valid (all except TS,
ABB, ARTRY, DBB)
–
9
–
9
–
9
ns
(6)
15
SYSCLK to output invalid (output hold)
1
–
1
–
1
–
ns
(3)
16
SYSCLK to output high impedance
(all except ARTRY, ABB, DBB)
–
8.5
–
8
–
8
ns
17
SYSCLK to ABB, DBB, high impedance
after precharge
–
1
–
1
–
1
tSYSCLK
18
SYSCLK to ARTRY high impedance
before precharge
–
8
–
7.5
–
7.5
ns
19
SYSCLK to ARTRY precharge enable
0.2 ×
tSYSCLK
+1
–
0.2 ×
tSYSCLK
+1
–
–
ns
20
Maximum delay to ARTRY precharge
–
1
–
1
–
1
tSYSCLK
(5)(8)
21
SYSCLK to ARTRY high impedance
after precharge
–
2
–
2
–
2
tSYSCLK
(6)(8)
0.2 ×
tSYSCLK
(5)(7)
(3)(5)
(8)
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5410B–HIREL–09/05
Notes:
1. All output specifications are measured from the 1.4V of the rising edge of SYSCLK to the TTL level (0.8V or 2V) of the signal
in question. Both input and output timings are measured at the pin. See Figure 11-4.
2. All maximum timing specifications assume CL = 50 pF.
3. This minimum parameter assumes CL = 0 pF.
4. SYSCLK to output valid (5.5V to 0.8V) includes the extra delay associated with discharging the external voltage from 5.5V to
0.8V instead of from VDD to 0.8V (5V CMOS levels instead of 3.3V CMOS levels).
5. tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (ns) of the parameter in question.
6. The output signal transitions from GND to 2V or VDD to 0.8V.
7. The nominal precharge width for ABB and DBB is 0.5 × tsysclk.
8. The nominal precharge width for ARTRY is 1 × tsysclk.
Figure 11-4. Output Timing Diagram
VM
VM
VM
SYSCLK
14
15
16
12
ALL OUTPUTS
(Except TS, ABB,
DBB, ARTRY)
15
13
13
16
TS
17
ABB, DBB
21
20
19
18
ARTRY
VM = Midpoint Voltage (1.4V)
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TSPC603R
11.4
JTAG AC Timing Specifications
Table 11-5.
Number
JTAG AC Timing Specifications (independent of SYSCLK); VDD = AVDD = 2.5V ±5%; OVDD = 3.3 ±5%V,
GND = 0V, CL = 50 pF, -55°C ≤ TC ≤ 125°C
Characteristics
TCK frequency of operation
Min
Max
Unit
0
16
MHz
62.5
–
ns
Notes
1
TCK cycle time
2
TCK clock pulse width measured at 1.4V
25
–
ns
3
TCK rise and fall times
0
3
ns
4
TRST setup time to TCK rising edge
13
–
ns
5
TRST assert time
40
–
ns
6
Boundary scan input data setup time
6
–
ns
(2)
7
Boundary scan input data hold time
27
–
ns
(2)
8
TCK to output data valid
4
25
ns
(3)
9
TCK to output high impedance
3
24
ns
(3)
10
TMS, TDI data setup time
0
–
ns
11
TMS, TDI data hold time
25
–
ns
12
TCK to TDO data valid
4
24
ns
13
TCK to TDO high impedance
3
15
ns
Notes:
(1)
1. TRST is an asynchronous signal. The setup time is for test purposes only.
2. Non-test signal input timing with respect to TCK.
3. Non-test signal output timing with respect to TCK.
Figure 11-5. Clock Input Timing Diagram
1
2
2
VM
VM
TCK
VM
3
3
VM = Midpoint Voltage (1.4V)
Figure 11-6. TRST Timing Diagram
VM
TCK
4
TRST
5
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5410B–HIREL–09/05
Figure 11-7. Boundary-scan Timing Diagram
TCK
VM
VM
6
Data Inputs
7
Input data valid
8
Output data valid
Data Outputs
9
Data Outputs
8
Data Outputs
Output data valid
Figure 11-8. Test Access Port Timing Diagram
TCK
VM
VM
10
TDI, TMS
11
Input Data Valid
12
TDO
Output Data Valid
13
TDO
12
TDO
Output Data Valid
12. Functional Description
12.1
PowerPC Registers and Programming Model
The PowerPC architecture defines register-to-register operations for most computational instructions. Source operands for these instructions are accessed from the registers or are provided as
immediate values embedded in the instruction opcode. The three-register instruction format
allows specification of a target register distinct from the two source operands. Load and store
instructions transfer data between registers and memory.
PowerPC processors have two levels of privilege—supervisor mode of operation (typically used
by the operating system) and user mode of operation (used by the application software). The
programming models incorporate 32 GPRs, 32 FPRs, Special-purpose Registers (SPRs) and
several miscellaneous registers. Each PowerPC microprocessor also has its own unique set of
Hardware Implementation (HID) registers.
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TSPC603R
Having access to privilege instructions, registers, and other resources allows the operating system to control the application environment (providing virtual memory and protecting operating
system and critical machine resources). Instructions that control the state of the processor, the
address translation mechanism, and supervisor registers can be executed only when the processor is operating in supervisor mode.
The following sections summarize the PowerPC registers that are implemented in the 603R.
12.1.1
General-purpose Registers (GPRs)
The PowerPC architecture defines 32 user-level, General-purpose Registers (GPRs). These
registers are either 32 bits wide in 32-bit PowerPC microprocessors or 64 bits wide in 64-bit
PowerPC microprocessors. The GPRs serve as the data source or destination for all integer
instructions.
12.1.2
Floating-point Registers (FPRs)
The PowerPC architecture also defines 32 user-level, 64-bit Floating-point Registers (FPRs).
The FPRs serve as the data source or destination for floating-point instructions. These registers
can contain data objects of either single- or double-precision floating-point formats.
12.1.3
Condition Register (CR)
The CR is a 32-bit user-level register that consists of eight four-bit fields that reflect the results of
certain operations, such as move, integer and floating-point compare, arithmetic, and logical
instructions, and provide a mechanism for testing and branching.
12.1.4
Floating-Point Status and Control Register (FPSCR)
The Floating-point Status and Control Register (FPSCR) is a user-level register that contains all
exception signal bits, exception summary bits, exception enable bits, and rounding control bits
needed for compliance with the IEEE 754 standard.
12.1.5
Machine State Register (MSR)
The Machine State Register (MSR) is a supervisor-level register that defines the state of the processor. The contents of this register are saved when an exception is taken and restored when
the exception handling is completed. The 603R implements the MSR as a 32-bit register, 64-bit
PowerPC processors implement a 64-bit MSR.
12.1.6
Segment Registers (SRs)
For memory management, 32-bit PowerPC microprocessors implement sixteen 32-bit Segment
Registers (SRs). To speed access, the 603R implements the segment registers as two arrays; a
main array (for data memory accesses) and a shadow array (for instruction memory accesses).
Loading a segment entry with the Move to Segment Register (STSR) instruction loads both
arrays.
29
5410B–HIREL–09/05
12.1.7
Special-purpose Registers (SPRs)
The powerPC operating environment architecture defines numerous special-purpose registers
that serve a variety of functions, such as providing controls, indicating status, configuring the
processor, and performing special operations. During normal execution, a program can access
the registers, shown in Figure 12-1 on page 32, depending on the program’s access privilege
(supervisor or user, determined by the privilege-level (PR) bit in the MSR. Note that registers
such as the GPRs and FPRs are accessed through operands that are part of the instructions.
Access to registers can be explicit (that is, through the use of specific instructions for that purpose such as Move to special-purpose register (mtspr) and move from special-purpose register
(mfspr) instructions or implicit, as the part of the execution of an instruction. Some registers are
accessed both explicitly and implicitly.
In the 603R, all SPRs are 32 bits wide.
• User-level SPRs:
The following 603R SPRs are accessible by user-level software:
– Link Register (LR) - The link register can be used to provide the branch target
address and to hold the return address after branch and link instructions. The LR is
32 bits wide in 32-bit implementations.
– Count Register (CTR) - The CRT is decremented and tested automatically as a
result of branch-and-count instructions. The CTR is 32 bits wide in 32-bit
implementations.
– Integer Exception Register (XER) - The 32-bit XER contains the summary overflow
bit, integer carry bit, overflow bit, and a field specifying the number of bytes to be
transferred by a Load String Word Indexed (LSWX) or Store String Word Indexed
(STSWX) instruction.
• Supervisor-level SPRs:
The 603R also contains SPRs that can be accessed only by supervisor-level software. These
registers consist of the following:
– The 32-bit DSISR defines the cause of data access and alignment exceptions.
– The Data Address Register (DAR) is a 32-bit register that holds the address of an
access after an alignment or DSI exception.
– Decrementer register (DEC) is a 32-bit decrementing counter that provides a
mechanism for causing a decrementer exception after a programmable delay.
– The 32-bit SDR1 specifies the page table format used in virtual-to-physical address
translation for pages. (Note that physical address is referred to as real address in the
architecture specification).
– The machine status Save/Restore Register 0 (SRR0) is a 32-bit register that is used
by the 603R for saving the address of the instruction that caused the exception, and
the address to return to when a Return from Interrupt (RFI) instruction is executed.
– The machine status Save/Restore Register 1 (SRR1) is a 32-bit register used to
save machine status on exceptions and to restore machine status when an RFI
instruction is executed.
– The 32-bit SPRG0-SPRG3 registers are provided for operating system use.
– The External Access Register (EAR) is a 32-bit register that controls access to the
external control facility through the External Control In Word Indexed (ECIWX) and
External Control Out Word Indexed (ECOWX) instructions.
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5410B–HIREL–09/05
TSPC603R
– The Time Base register (TB) is a 64-bit register that maintains the time of day and
operates interval timers. The TB consists of two 32-bit fields - Time Base Upper
(TBU) and Time Base Lower (TBL).
– The Processor Version Register (PVR) is a 32-bit, read-only register that identifies
the version (model) and revision level of the PowerPC processor.
– Block Address Translation (BAT) arrays - The PowerPC architecture defines 16 BAT
registers, divided into four pairs of Data BATs (DBATs) and four pairs of instruction
BATs (IBATs). See Figure 12-1 for a list of the SPR numbers for the BAT arrays.
The following supervisor-level SPRs are implementation-specific to the 603R:
– The DMISS and IMISS registers are read-only registers that are loaded
automatically upon an instruction or data TLB miss.
– The HASH1 and HASH2 registers contain the physical addresses of the primary and
secondary Page Table Entry Groups (PTEGs).
– The ICMP and DCMP registers contain a duplicate of the first word in the Page Table
Entry (PTE) for which the table search is looking.
– The Required Physical Address (RPA) register is loaded by the processor with the
second word of the correct PTE during a page table search.
– The hardware implementation (HID0 and HID1) registers provide the means for
enabling the 603R’s checkstops and features, and allows software to read the
configuration of the PLL configuration signals.
– The Instruction Address Breakpoint Register (IABR) is loaded with an instruction
address that is compared to instruction addresses in the dispatch queue. When an
address match occurs, an instruction address breakpoint exception is generated.
Figure 12-1 shows all the 603R registers available at the user and supervisor level. The number
to the right of the SPRs indicate the number that is used in the syntax of the instruction operands
to access the register.
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5410B–HIREL–09/05
Figure 12-1. PowerPC Microprocessor Programming Model – Register
SUPERVISOR MODEL
Configuration Registers
USER MODEL
General-purpose
Registers
GPR0
Hardware
Implementation
Registers(1)
HID0
SPR1 008
HID1
SPR1 009
GPR1
Machine State
Register
Processor Version
Register
MSR
PVR
SPR 287
Memory Management Registers
Instruction BAT
Registers
IBAT0U
GPR31
Floating-point
Registers
FPR0
FPR1
Software Table
Search Registers(1)
Data BAT Registers
SPR 528
DBAT0U
SPR 536
DMISS
SPR 976
SPR 977
IBAT0L
SPR 529
DBAT0L
SPR 537
DCMP
IBAT1U
SPR 530
DBAT1U
SPR 538
HASH1
SPR 978
SPR 539
HASH2
SPR 979
SPR 540
IMISS
SPR 980
IBAT1L
SPR 531
IBAT2U
SPR 532
DBAT1L
DBAT2U
IBAT2L
SPR 533
DBAT2L
SPR 541
ICMP
SPR 981
IBAT3U
SPR 534
DBAT3U
SPR 542
RPA
SPR 982
IBAT3L
SPR 535
DBAT3L
SPR 543
Segment Registers
SR0
SDR1
GPR31
SDR1
SR1
SPR 25
Condition Register
SR 15
CR
Exception Handling Registers
Floating-point Status
and Control Register
FPSCR
Data Address Register
DAR
DSISR
SPR 18
Save and Restore
SPRGs
XER
SPRG0
SPR 272
SRR0
SPR 26
SPRG1
SPR 273
SRR1
SPR 27
Link Register
SPRG2
SPR 274
LR
SPR8
SPRG3
SPR 275
SPR9
Time Base Facility
(for writing)
XER
SPR1
Miscellaneous Registers
Count Register
CTR
Time Base Facility
(for reading)
32
SPR 19
DSISR
TBL
SPR 284
TBU
SPR 285
TBL
TBR 268
Instruction Address
Breakpoint Register(1)
TBU
TBR 269
IABR
SPR 1010
Decrementer
DEC
SPR 22
External Address
Register (Optional)
EAR
SPR 282
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5410B–HIREL–09/05
TSPC603R
12.2
Instruction Set and Addressing Modes
The following subsections describe the PowerPC instruction set and addressing modes in
general.
12.2.1
PowerPC Instruction Set and Addressing Modes
All PowerPC instructions are encoded as single-word (32-bit) opcodes. Instruction formats are
consistent among all instruction types, permitting efficient decoding to occur in parallel with operand accesses. This fixed instruction length and consistent format greatly simplifies instruction
pipelining.
PowerPC Instruction Set
The PowerPC instructions are divided into the following categories:
• Integer Instructions – these include computational and logical instructions
– Integer arithmetic instructions
– Integer compare instructions
– Integer logical instructions
– Integer rotate and shift instructions
• Floating-point Instructions – these include floating-point computational instructions, as well
as instructions that affect the FPSCR
– Floating-point arithmetic instructions
– Floating-point multiply/add instructions
– Floating-point rounding and conversion instructions
– Floating-point compare instructions
– Floating-point status and control instructions
• Load/Store Instructions – these include integer and floating-point load and store
instructions
– Integer load and store instruction
– Integer load and store multiple instructions
– Floating-point load and store
– Primitives used to construct atomic memory operations (lwarx and stwcx
instructions)
• Flow Control Instructions – these include branching instructions, condition register logical
instructions, trap instructions, and other instructions that affect the instruction flow
– Branch and trap instructions
– Condition register logical instructions
• Processor Control Instructions – these instructions are used for synchronizing memory
accesses and management of caches, TLBs, and the segment registers
– Move to/from SPR instructions
– Move to/from MSR
– Synchronize
– Instruction synchronize
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5410B–HIREL–09/05
• Memory Control Instructions – these instructions provide control of caches, TLBs, and
segment registers
– Supervisor-level cache management instructions
– User-level cache instructions
– Segment register manipulation instructions
– Translation lookaside buffer management instructions
Note that this grouping of the instructions does not indicate which execution unit executes a particular instruction or group of instructions.
Integer instructions operate on byte, half-word, and word operands. Floating-point instructions
operate on single-precision (one word) and double-precision (one double word) floating-point
operands. The PowerPC architecture uses instructions that are four bytes long and
word-aligned. It provides for byte, half-word, and word operand loads and stores between the
memory and a set of 32 GPRs. It also provides for word and double-word operand loads and
stores between the memory and a set of 32 Floating-point Registers (FPRs).
Computational instructions do not modify the memory. To use a memory operand in a computation and then modify the same or another memory location, the memory contents must be
loaded into a register, modified, and then written back to the target location with distinct
instructions.
PowerPC processors follow the program flow when they are in the normal execution state. However, the flow of instructions can be interrupted directly by the execution of an instruction or by
an asynchronous event. Either kind of exception may cause one of several components of the
system software to be invoked.
• Calculating Effective Address
The Effective Address (EA) is the 32-bit address computed by the processor when executing
a memory access or branch instruction or when fetching the next sequential instruction.
The PowerPC architecture supports two simple memory addressing modes:
– EA = (RA|0) + offset (including offset = 0) (register indirect with immediate index)
– EA = (RA|0) + rB (register indirect with index)
These simple addressing modes allow efficient address generation for memory accesses. Calculation of the effective address for aligned transfers occurs in a single clock cycle.
For a memory access instruction, if the sum of the effective address and the operand length
exceeds the maximum effective address, the memory operand is considered to wrap around
from the maximum effective address to effective address 0.
Effective address computations for both data and instruction accesses use 32-bit unsigned
binary arithmetic. A carry over from bit 0 is ignored in 32-bit implementations.
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12.2.2
PowerPC 603R Microprocessor Instruction Set
The 603R instruction set is defined as follows:
• The 603R provides hardware support for all 32-bit PowerPC instructions.
• The 603R provides two implementation-specific instructions used for software table search
operations following TLB misses:
– Load Data TLB Entry (tlbld)
– Load Instruction TLB Entry (tlbli)
• The 603R implements the following instructions which are defined as optional by the
PowerPC architecture :
– External Control in Word Indexed (eciwx)
– External Control Out Word Indexed (ecowx)
– Floating Select (fsed)
– Floating Reciprocal Estimate Single-Precision (fres)
– Floating Reciprocal Square Root Estimate (frsqrte)
– Store Floating-Point as Integer Word (stfiwx)
12.3
Cache Implementation
The following subsections describe the way the PowerPC architecture deals with cache in general, and the 603R’s specific implementation.
12.3.1
PowerPC Cache Characteristics
The PowerPC architecture does not define hardware aspects of cache implementations. For
example, some PowerPC processors, including the 603R, have separate instruction and data
caches (harvard architecture).
The PowerPC microprocessor controls the following memory access modes on a page or block
basis:
• Write-back/write-through mode
• Cache-inhibited mode
• Memory coherency
Note that in the 603R, a cache line is defined as eight words. The VEA defines cache management instructions that provide a means by which the application programmer can affect the
cache contents.
12.3.2
PowerPC 603R Microprocessor Cache Implementation
The 603R has two 16-Kbyte, four-way set-associative (instruction and data) caches. The caches
are physically addressed, and the data cache can operate in either write-back or write-through
modes as specified by the PowerPC architecture.
The data cache is configured as 128 sets of four lines each. Each line consists of 32 bytes, two
state bits, and an address tag. The two state bits implement the three-state MEI (Modified/Exclusive/Invalid) protocol. Each line contains eight 32-bit words. Note that the PowerPC architecture
defines the term block as the cacheable unit. For the 603R, the block size is equivalent to a
cache line. A block diagram of the data cache organization is shown in Figure 12-2 on page 36.
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5410B–HIREL–09/05
The instruction cache also consists of 128 sets of 4 lines, and each line consists of 32 bytes, an
address tag, and a valid bit. The instruction cache may not be written to except through a line fill
operation. The instruction cache is not snooped, and cache coherency must be maintained by
software. A fast hardware invalidation capability is provided to support cache maintenance. The
organization of the instruction cache is very similar to the data cache shown in Figure 12-2 on
page 36.
Each cache line contains eight contiguous words from memory that are loaded from an 8-word
boundary (that is, bits A27-A32 of the effective addresses are zero); thus, a cache line never
crosses a page boundary. Misaligned accesses across a page boundary can incur a performance penalty.
The 603’s cache lines are loaded in four beats of 64 bits each. The burst load is performed as
“critical double word first”. The cache that is being loaded is blocked to internal accesses until
the load is completed. The critical double word is simultaneously written to the cache and forwarded to the requesting unit, thus minimizing stalls due to load delays.
To ensure coherency among caches in a multiprocessor (or multiple caching device) implementation, the 603R implemements the MEI protocol. These three states, modified, exclusive, and
invalid, indicate the state of the cache block as follows:
• Modified - the cache line is modified with respect to system memory; that is, data for this
address is valid only in the cache and not in the system memory
• Exclusive - this cache line holds valid data that is identical to the data at this address insystem memory. No other cache has this data
• Invalid - this cache line does not hold valid data
Cache coherency is enforced by on-chip bus snooping logic. Since the 603R’s data cache tags
are single ported, a simultaneous load or store and snoop access represent a resource contention. The snoop access is granted first access to the tags. The load or store then occurs on the
clock following snoop.
Figure 12-2. Data Cache Organization
128 sets
Block 0
Address Tag 0
State
Words 0-07
Block 1
Address Tag 1
State
Words 0-07
Block 2
Address Tag 2
State
Words 0-07
Block 3
Address Tag 3
State
Words 0-07
8 words/block
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12.3.3
Exception Model
The following subsections describe the PowerPC exception model and the 603R
implementation.
12.3.4
PowerPC Exception Model
The PowerPC exception mechanism allows the processor to change to supervisor state as a
result of external singles, errors, or unusual conditions arising in the execution of instructions,
and differ from the arithmetic exceptions defined by the IEEE for floating-point operations. When
exceptions occur, information about the state of the processor is saved to certain registers and
the processor begins execution at an address (exception vector) predetermined for each exception. Processing of exceptions occurs in supervisor mode.
Although multiple exception conditions can map to a single exception vector, a more specific
condition may be determined by examining a register associated with the exception - for example, the DSISR and the FPSCR. Additionally, some exception conditions can be explicitly
enabled or disabled by software.
The PowerPC architecture requires that exceptions be handled in program order; therefore,
although a particular implementation may recognize exception conditions out of order, they are
presented strictly in order. When an instruction-caused exception is recognized, any unexecuted
instructions that appear earlier in the instruction stream, including any that have not yet entered
the execute state, must be completed before the exception is taken. Any exceptions caused by
such instructions are handled first. Likewise, exceptions that are asynchronous and precise are
recognized when they occur, but are not handled until the instruction currently in the completion
state successfully completes execution or generates an exception, and the completed store
queue is emptied.
Unless a catastrophe event causes a system reset or machine check exception, only one exception is handled at a time. If, for example, a single instruction encounters multiple exception
conditions, those conditions are encountered sequentially.
After the exception handler handles an exception, the instruction execution continues until the
next exception condition is encountered. However, in many cases there is no attempt to re-execute the instruction. This method of recognizing and handling exception conditions sequentially
guarantees that exceptions are recoverable.
Exception handlers should save the information stored in SRR0 and SRR1 early to prevent the
program state from being lost due to a system reset and machine check exception or to an
instruction-caused exception in the exception handler, and before enabling external interrupts.
The PowerPC architecture supports four types of exceptions:
• Synchronous, Precise – these are caused by instructions. All instruction-caused exceptions
are handled precisely; that is, the machine state at the time the exception occurs is known
and can be completely restored. This means that (excluding the trap and system call
exceptions) the address of the faulting instruction is provided to the exception handler and
that neither the faulting instruction nor subsequent instructions in the code stream will
complete execution before the exception is taken. Once the exception is processed,
execution resumes at the address of the faulting instruction (or at an alternate address
provided by the exception handler). When an exception is taken due to a trap or system call
instruction, execution resumes at an address provided by the handler.
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• Synchronous, Imprecise – the PowerPC architecture defines two imprecise floating-point
exception modes, recoverable and nonrecoverable. Even though the 603R provides a means
to enable the imprecise modes, it implements these modes identically to the precise mode
(That is, all enabled floating-point exceptions are always precise on the 603R).
• Asynchronous, Maskable – the external, SMI, and decrementer interrupts are maskable
asynchronous exceptions. When these exceptions occur, their handling is postponed until the
next instruction, and any exceptions associated with that instruction completes execution. If
there are no instructions in the execution units, the exception is taken immediately upon
determination of the correct restart address (for loading SRR0).
• Asynchronous, Non-maskable – there are two non-maskable asynchronous exceptions:
the system reset and machine check exception. These exceptions may not be recoverable, or
may provide a limited degree of recoverability. All exceptions report recoverability through the
SMR[RI] bit.
12.3.5
PowerPC 603R Microprocessor Exception Model
As specified by the PowerPC architecture, all 603R exceptions can be described as either precise or imprecise and either synchronous or asynchronous. Asynchronous exceptions (some of
which are maskable) are caused by events external to the processor’s execution; synchronous
exceptions, which are all handled precisely by the 603R, are caused by instructions. The 603R
exception classes are shown in Table 12-1.
Table 12-1.
PowerPC 603R Microprocessor Exception Classifications
Synchronous/Asynchronous
Precise/Imprecise
Exception Type
Asynchronous, Non Maskable
Imprecise
Machine check
System reset
Asynchronous, Maskable
Precise
External interrupt
Decrementer
System management interrupt
Synchronous
Precise
Instruction-caused exceptions
Although exceptions have other characteristics as well, such as whether they are maskable or
non-maskable, the distinctions shown in Table 12-1 define categories of exceptions that the
603R handles uniquely. Note that Table 12-1 includes no synchronous imprecise instructions.
While the PowerPC architecture supports imprecise handling of floating-point exceptions, the
603R implements these exception modes as precise exceptions.
The 603R’s exceptions, and conditions that cause them, are listed in Table 12-2. Exceptions that
are specific to the 603R are indicated.
Table 12-2.
Exceptions and Conditions
Exception Type
Vector Offset
(hex)
Causing Conditions
Reserved
00000
–
System reset
00100
A system reset is caused by the assertion of either SRESET or HRESET
Machine check
00200
A machine check is caused by the assertion of the TEA signal during a data bus
transaction, assertion of MCP, or an address or data parity error
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Table 12-2.
Exceptions and Conditions (Continued)
Exception Type
DSI
Vector Offset
(hex)
00300
Causing Conditions
The cause of a DSI exception can be determined by the bit settings in the DSISR, listed as
follows:
1 Set if the translation of an attempted access is not found in the primary hash table entry
group (HTEG), or in the rehashed secondary HTEG, or in the range of the DBAT register;
otherwise cleared
4 Set if a memory access is not permitted by the page or DBAT protection mechanism;
otherwise cleared
5 Set by an eciwx or ecowx instruction if the access is to an address that is marked as
write-through, or execution of a load/store instruction that accesses a direct-store segment
6 Set for a store operation and cleared for a load operation
11 Set if eciwx or ecowx is used and EAR[E] is cleared
An ISI exception is caused when an instruction fetch cannot be performed for any of the
following reasons:
ISI
00400
• The effective (logical) address cannot be translated. That is, there is a page
fault for this portion of the translation, so an ISI exception must be taken to load
the PTE (and possibly the page) into memory
• The fetch access violates memory protection. If the key bits (Ks and Kp) in the
segment register and the PP bits in the PTE are set to prohibit read access,
instructions cannot be fetched from this location
External interrupt
00500
An external interrupt is caused when MSR[EE] = 1 and the INT signal is asserted
An alignment exception is caused when the 603e cannot perform a memory access for any
of the reasons described below:
• The operand of a floating-point load or store instruction is not word-aligned
• The operand of lmw, stmw, lwarx, and stwcx, instructions are not aligned
Alignment
00600
• The operand of a single-register load or store operation is not aligned, and the
603e is in little-endian mode
• The instruction is lmw, stmw, lswi, lwsx, stswi, stswx and the 603e is in littleendian mode
• The operand of dcbz is in storage that is write-through-required, or caching
inhibited
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Table 12-2.
Exceptions and Conditions (Continued)
Exception Type
Vector Offset
(hex)
Causing Conditions
A program exception is caused by one of the following exception conditions, which
correspond to bit settings in SRR1 and arise during execution of an instruction:
• Floating-point enabled exception – A floating-point enabled exception condition
is generated when the following condition is met: (MSR[FE0] | MSR[FE1]) &
FPSCR[FEX] is 1 FPSER[FEX] is set by the execution of a floating-point
instruction that causes an enabled exception or by the execution of one of the
“move to FPSCR” instructions that results in both an exception condition bit
and its corresponding enable bit being set in the FPSCR
Program
• Illegal instruction – an illegal instruction program exception is generated when
execution of an instruction is attempted with an illegal opcode or illegal
combination of opcode and extended opcode fields (including PowerPC
instructions not implemented in the 603e), or when execution of an optional
instruction not provided in the 603e is attempted (these do not include those
optional instructions that are treated as no-ops)
00700
• Privileged instruction – a privileged instruction type program exception is
generated when the execution of a privileged instruction is attempted and the
MSR register user privilege bit, MSR[PR], is set. In the 603e, this exception is
generated for mtspr or mfspr with an invalid SPR field if SPR[0] = 1 and
MSR[PR] = 1. This may not be true for all PowerPC processors
• Trap – a trap type program exception is generated when any of the conditions
specified in a trap instruction is met
Floating-point
unavailable
00800
A floating-point unavailable exception is caused by an attempt to execute a floating-point
instruction (including floating-point load, store, and more instructions) when the floatingpoint available bit is disabled, (MSR[FP] = 0)
Decrementer
00900
The decrementer exception occurs when the most significant bit of the decrementer (DEC)
register transitions from 0 to 1. Must also be enabled with the MSR[EE] bit
Reserved
00A00–00BFF
–
System call
00C00
A system call exception occurs when a System Call (sc) instruction is executed
Trace
00D00
A trace execution is taken when MSR[SE] = 1 or when the currently completing instruction
is a branch and MSR[BE] = 1
Reserved
00E00
The 603e does not generate an exception to this vector. Other PowerPC processors may
use this vector for floating-point assist exceptions
Reserved
00E10–00FFF
–
Instruction
translation miss
01000
An instruction translation miss exception is caused when an effective address for an
instruction fetch cannot be translated by the ITLB
Data load
translation miss
01100
A data load translation miss exception is caused when an effective address for a data load
operation cannot be translated by the DTLB
Data store
translation miss
01200
A data store translation miss exception is caused when an effective address for a data store
operation cannot be translated by the DTLB; or where a DTLB hit occurs, and the change
bit in the PTE must be set due to a data store operation
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Table 12-2.
Exceptions and Conditions (Continued)
Exception Type
Vector Offset
(hex)
Causing Conditions
Instruction
address
breakpoint
01300
An instruction address breakpoint exception occurs when the address (bits 0-29) in the
IABR matches the next instruction to complete in the completion unit, and the IABR enable
bit (bit 30) is set to 1
System
management
interrupt
01400
A system management interrupt is caused when MSR[EE] = 1 and the SMI input signal is
asserted
Reserved
12.4
01500–02FFF
–
Memory Management
The following subsections describe the memory management features of the PowerPC architecture, and the 603R implementation, respectively.
12.4.1
PowerPC Memory Management
The primary functions of the MMU are to translate logical (effective) addresses to physical
addresses for memory accesses, and to provide access protection on blocks and pages of
memory.
There are two types of accesses generated by the 603R that require address translation —
instruction accesses, and data accesses to memory generated by load and store instructions.
The PowerPC MMU and exception model support demand-paged virtual memory. Virtual memory management permits execution of programs larger than the size of physical memory;
demand-paged implies that individual pages are loaded into physical memory from system
memory only when they are first accessed by an executing program.
The hashed page table is a variable-sized data structure that defines the mapping between virtual page numbers and physical page numbers. The page table size is a power of 2, and its
starting address is a multiple of its size.
The page table contains a number of Page Table Entry Groups (PTEGs). A PTEG contains eight
Page Table Entries (PTEs) of eight bytes each; therefore, each PTEG is 64 bytes long. PTEG
addresses are entry points for table search operations.
Address translations are enabled by setting bits in the MSR-MSR[IR] enables instruction
address translations and MSR[DR] enables data address translations.
12.4.2
PowerPC 603R Microprocessor Memory Management
The instruction and data memory management units in the 603R provide 4 Gbytes of logical
address space accessible to the supervisor and user programs with a 4 Kbyte page size and
256M byte segment size. Block sizes range from 128 Kbytes to 256 Mbytes and are software
selectable. In addition, the 603R uses an interim 52-bit virtual address and hashed page tables
for generating 32-bit physical addresses. The MMUs in the 603R rely on the exception processing mechanism for the implementation of the paged virtual memory environment and for
enforcing protection of designated memory areas.
Instruction and data TLBs provide address translation in parallel with the on-chip cache access,
incurring no additional time penalty in the event of a TLB hit. A TLB is a cache of the most
recently used page table entries. The software is responsible for maintaining the consistency of
the TLB with memory.
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The 603R’s TLBs are 64-entry, 2-way set-associative caches that contain instruction and data
address translations. The 603R provides hardware assistance for software table search operations through the ashed page table on the TLB misses. The supervisor software can invalidate
TLB entries selectively.
The 603R also provides independent four-entry BAT arrays for instructions and data that maintain address translations for blocks of memory. These entries define blocks that can vary from
128 Kbytes to 256 Mbytes. The BAT arrays are maintained by system software.
As specified by the PowerPC architecture, the hashed page table is a variable-sized data structure that defines the mapping between virtual page numbers and physical page numbers. The
page table size is a power of 2, and its starting address is a multiple of its size.
Also as specified by the PowerPC architecture, the page table contains a number of Page Table
Entry Groups (PTEGs). A PTEG contains eight Page Table Entries (PTEs) of eight bytes each;
therefore, each PTEG is 64 bytes long. PTEG addresses are entry points for table search
operations.
12.4.3
Instruction Timing
The 603R is a pipelined superscalar processor. A pipelined processor is one in which the processing of an instruction is reduced into discrete stages. Because the processing of an
instruction is broken into a series of stages, an instruction does not require the entire resources
of an execution unit. For example, after an instruction completes the decode stage, it can pass
on to the next stage, while the subsequent instruction can advance into the decode stage. This
improves the throughput of the instruction flow. For example, it may take three cycles for a floating-point instruction to complete, but if there are no stalls in the floating-point pipeline, a series of
floating-point instructions can have a throughput of one instruction per cycle.
The instruction pipeline in the 603R has four major pipeline stages, described as follows:
• The fetch pipeline stage primarily involves retrieving instructions from the memory system
and determining the location of the next instruction retrieval. Additionally, the BPU decodes
branches during the fetch stage and folds out branch instructions before the dispatch stage if
possible.
• The dispatch pipeline stage is responsible for decoding the instructions supplied by the
instruction retrieval stage, and determining which of the instructions are eligible to be
dispatched in the current cycle. In addition, the source operands of the instructions are read
from the appropriate register file and dispatched with the instruction to the execute pipeline
stage. At the end of the dispatch pipeline stage, the dispatched instructions and their
operands are latched by the appropriate execution unit.
• During the execute pipeline stage each execution unit that has an executable instruction
executes the selected instruction (perhaps over multiple cycles), writes the instruction’s result
into the appropriate rename register, and notifies the completion stage when the instruction
has finished execution. In the case of an internal exception, the execution unit reports the
exception to the completion/writeback pipeline stage and discontinues instruction execution
until the exception is handled. The exception is not signaled until that instruction is the next to
be completed. Execution of most floating-point instructions is pipelined within the FPU
allowing up to three instructions to be executing in the FPU concurrently. The pipeline stages
for the floating-point unit are multiply, add, and round-convert. Execution of most load/store
instructions is also pipelined. The load/store unit has two pipeline stages. The first stage is for
effective address calculation and MMU translation and the second stage is for accessing the
data in the cache.
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• The complete/writeback pipeline stage maintains the correct architectural machine state and
transfers the contents of the rename registers to the GPRs and FPRs as instructions are
retired. If the completion logic detects an instruction causing an exception, all following
instructions are cancelled, their execution results in rename registers are discarded, and
instructions are fetched from the correct instruction stream.
A superscalar processor is one that issues multiple independent instructions into multiple pipelines allowing instructions to execute in parallel. The 603R has five independent execution units,
one each for integer instructions, floating-point instructions, branch instructions, load/store
instructions, and system register instructions. The IU and the FPU each have dedicated register
files for maintaining operands (GPRs and FPRs, respectively), enabling integer calculations and
floating-point calculations to occur simultaneously without interference.
Because the PowerPC architecture can be applied to such a wide variety of implementations,
instruction timing among various PowerPC processors varies accordingly.
13. Preparation for Delivery
13.1
Packaging
Microcircuits are prepared for delivery in accordance with MIL-PRF-38535.
13.2
Certificate of Compliance
Atmel offers a certificate of compliance with each shipment of parts, affirming the products are in
compliance with the MIL-STD-883 standard and guaranteeing the parameters that are not tested
at temperature extremes for the entire temperature range.
13.3
Handling
MOS devices must be handled with certain precautions to avoid damage caused by an accumulation of static charge. Input protection devices have been designed in the chip to minimize the
effect of this static buildup. However, the following handling practices are recommended:
1. The devices should be handled on benches with conductive and grounded surfaces.
2. Ground test equipment and tools should be used.
3. The devices should not be handled by the leads.
4. The devices should be stored in conductive foam or carriers.
5. Use of plastic, rubber, or silk in MOS areas should be avoided.
6. Relative humidity above 50 percent should be maintained if practical.
13.4
Choice of Clock Relationships
The 603R microprocessors provide customers with numerous clocking options. An internal
phase-lock loop synchronizes the processor (CPU) clock to the bus or system clock (SYSCLK)
at various ratios.
Inside each PowerPC microprocessor is a phase-lock loop circuit. A Voltage Controlled Oscillator (VCO) is precisely controlled in frequency and phase by a frequency/phase detector which
compares the input bus frequency (SYSCLK frequency) to a submultiple of the VCO.
The ratio of CPU to SYSCLK frequencies is often referred to as the bus mode (for example, 2:1
bus mode).
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In Table 13-1, the horizontal scale represents the bus frequency (SYSCLK) and the vertical
scale represents the PLL-CFG[0-3] signals.
For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and
VCO frequency of operation.
Table 13-1.
CPU Frequencies for Common Bus Frequencies and Multipliers
CPU Frequency in MHZ (VCO Frequency in MHz) specific to CBGA 255, HiTCE CBGA 255 and CI-CGA 255
PLL_CFG[0-3]
Bus-toCore
Multiplier
Core-to
VCO
Multiplier
Bus
25 MHz
Bus
33.33 MHz
Bus
40 MHz
Bus
50 MHz
Bus
60 MHz
Bus
66.67 MHz
Bus
75 MHz
0100
2x
2x
-
-
-
-
-
-
150
(300)
0101
2x
4x
-
-
-
-
-
-
-
0110
2.5x
2x
-
-
-
-
150
(300)
166
(333)
187
(375)
1000
3x
2x
-
-
-
150
(300)
180
(360)
200
(400)
225
(450)
1110
3.5x
2x
-
-
-
175
(350)
210
(420)
233
(466)
263
(525)
1010
4x
2x
-
-
160
(320)
200
(400)
240
(480)
267
(533)
300
(600)
0111
4.5x
2x
-
150
(300)
180
(360)
225
(450)
270
(540)
300
(600)
-
1011
5x
2x
-
166
(333)
200
(400)
250
(500)
300
(600)
-
-
1001
5.5x
2x
-
183
(366)
220
(440)
275
(550)
-
-
-
1101
6x
2x
150
(300)
200
(400)
240
(480)
300
(600)
-
-
-
0011
PLL bypass
1111
Clock off
CPU Frequency in MHZ (VCO Frequency in MHz) specific to CERQUAD
PLL_CFG[0-3]
Bus-to-Core
Multiplier
Core-to VCO
Multiplier
Bus
25 MHz
Bus
33.33 MHz
Bus
40 MHz
Bus
50 MHz
Bus
60 MHz
Bus
66.67 MHz
0100
2x
2x
–
–
–
–
–
–
0101
2x
4x
–
–
–
–
–
–
0110
2.5x
2x
–
–
–
–
150
(300)
166
(333)
1000
3x
2x
–
–
–
150
(300)
180
(360)
200
(400)
1110
3.5x
2x
–
–
–
175
(350)
–
–
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CPU Frequency in MHZ (VCO Frequency in MHz) specific to CERQUAD
PLL_CFG[0-3]
Bus-to-Core
Multiplier
Core-to VCO
Multiplier
Bus
25 MHz
Bus
33.33 MHz
Bus
40 MHz
Bus
50 MHz
Bus
60 MHz
Bus
66.67 MHz
1010
4x
2x
–
–
160
(320)
200
(400)
–
–
0111
4.5x
2x
–
150
(300)
180
(360)
–
–
–
1011
5x
2x
–
166
(333)
200
(400)
–
–
–
1001
5.5x
2x
–
183
(366)
–
–
–
–
1101
6x
2x
150
(300)
200
(400)
–
–
–
–
Notes:
0011
PLL bypass
1111
Clock off
1. Some PLL configurations may select bus, CPU or VCO frequencies which are not supported.
2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode
is set for 1:1 mode operation. This mode is intended for factory use only.
The AC timing specifications given in this document do not apply in PLL-bypass mode.
3. In clock-off mode, no clocking occurs inside the 603e regardless of the SYSCLK input.
14. System Design Information
14.1
PLL Power Supply Filtering
The AVDD power signal is implemented on the 603e to provide power to the clock generation
phase-locked loop. To ensure stability of the internal clock, the power supplied to the AVDD input
signal should be filtered using a circuit similar to the one shown in Figure 14-1. The circuit should
be placed as close as possible to the AVDD pin to ensure it filters out as much noise as possible.
The 0.1 µF capacitor should be closest to the AVDD pin, followed by the 10 µF capacitor, and
finally the 10Ω resistor to VDD. These traces should be kept short and direct.
Figure 14-1. PLL Power Supply Filter Circuit
VDD
10Ω
AVDD
10 µF
0.1 µF
GND
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14.2
Decoupling Recommendations
Due to the 603e’s dynamic power management feature, large address and data buses, and high
operating frequencies, the 603e can generate transient power surges and high frequency noise
in its power supply, especially while driving large capacitive loads. This noise must be prevented
from reaching other components in the 603e system, and the 603e itself requires a clean, tightly
regulated source of power. Therefore, it is recommended that the system designer place at least
one decoupling capacitor at each VDD and OVDD pin of the 603e. It is also recommended that
these decoupling capacitors receive their power from separate VDD, OVDD, and GND power
planes in the PCB, utilizing short traces to minimize inductance.
These capacitors should vary in value from 220 pF to 10 µF to provide both high and low frequency filtering, and should be placed as close as possible to their associated VDD or OVDD pin.
The suggested values for the VDD pins are 220 pF (ceramic), 0.01 µF (ceramic) and 0.1 µf
(ceramic). The suggested values for the OVDD pins are 0.01 µF (ceramic), 0.1 µF (ceramic), and
10 µF (tantalum). Only SMT (Surface Mount Technology) capacitors should be used to minimize
lead inductance.
In addition, it is recommended that there be several bulk storage capacitors distributed around
the PCB, feeding the VDD and OVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should also have a low ESR (equivalent series resistance) rating to
ensure the quick response time necessary. They should also be connected to the power and
ground planes through two vias to minimize inductance. The suggested bulk capacitors are 100
µF (AVX TPS tantalum) or 330 µf (AVX TPS tantalum).
14.3
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to VDD. Unused active high inputs
should be connected to GND. All NC (non-connected) signals must remain unconnected.
Power and ground connections must be made to all external VDD, OVDD, and GND pins of the
603e.
14.4
Pull-up Resistor Requirements
The 603e requires high-resistive (weak: 10 kΩ) pull-up resistors on several control signals of the
bus interface to maintain the control signals in the negated state after they have been actively
negated and released by the 603e or other bus master. These signals are: TS, ABB, DBB, and
ARTRY.
In addition, the 603e has three open-drain style outputs that require pull-up resistors (weak or
stronger: 4.7 kΩ - 10 kΩ) if they are used by the system. These signals are: APE, DPE, and
CKSTP_OUT.
During inactive periods on the bus, the address and transfer attributes on the bus are not driven
by any master and may float in the high-impedance state for relatively long periods of time.
Since the 603e must continually monitor these signals for snooping, this floating condition may
cause excessive power to be drawn by the input revivers on the 603e. It is recommended that
these signals be pulled up through weak (10 kΩ) pull-up resistors or restored in some manner by
the system. The snooped address and transfer attribute inputs are: A[0-3], AP[0-3], TT[0-4],
TBST, and GBL.
The data bus input receivers are normally turned off when no read operation is in progress and
do not require pull-up resistors on the data bus.
46
TSPC603R
5410B–HIREL–09/05
TSPC603R
15. Package Mechanical Data
The following sections provide the package parameters and mechanical dimensions for the
CBGA, HiTCE CBGA and the Cerquad packages.
15.1
HiTCE CBGA Package Parameters
The package parameters are as provided in the following list. The package type is 21 mm, 255lead HiTCE Ceramic Ball Array (HiTCE CBGA).
Package outline
21 mm × 21 mm
Interconnects
255
Pitch
1.27 mm
Maximum module height
3.08 mm
47
5410B–HIREL–09/05
15.1.1
Mechanical Dimensions of the HiTCE CBGA Package
Figure 15-1 provides the mechanical dimensions and bottom surface nomenclature of the
HiTCE CBGA package.
Figure 15-1. Mechanical Dimensions of the HiTCE CBGA Package
0.2
D
Ball A1
Index
A
D2
A4
B
D4
E3
E4
E2
603r
E
1
0.35 A
0.2
D3
C
A2
A1
D1
A
T
R
MILLIMETERS
P
MIN
MAX
MIN
MAX
A1
2.42
0.80
3.08
1.00
0.095
0.031
0.12
0.039
A2
0.90
1.14
0.035
0.045
A4
0.80
0.90
0.031
0.035
D
B
0.82
0.93
0.032
0.037
C
D
21.00 BASIC
0.827 BASIC
D1
19.05 BASIC
0.75 BASIC
M
L
A
K
J
H
G
F
E1
K
E
B
A
1
2
3
4
5
6
7
G
8
9 10 11 12 13 14 15 16
K
B
255X
D2
10.8 Typ
0.425 Typ
D3
8.75 BASIC
0.344 BASIC
5.65
E
21.00 BASIC
0.222
0.827 BASIC
E1
19.05 BASIC
0.75 BASIC
E2
12.0 Typ
0.472 Typ
E3
6.15 BASIC
E4
7.7
0.303
1.27 BASIC
0.05 BASIC
D4
G, K
48
INCHES
DIM
N
0.242 BASIC
TSPC603R
5410B–HIREL–09/05
TSPC603R
15.2
CBGA Package Parameters
The package parameters are as provided in the following list. The package type is 21 mm,
255-lead Ceramic Ball Grid Array (CBGA).
15.2.1
Package outline
21 mm × 21 mm
Interconnects
255
Pitch
1.27 mm
Maximum module height
3 mm
Mechanical Dimensions of the CBGA Package
Figure 15-2 provides the mechanical dimensions and bottom surface nomenclature of the CBGA
package.
Figure 15-2. Mechanical Dimensions and Bottom Surface Nomenclature of the CBGA Package
2X
0.200
A
A1 CORNER
-E-T0.150 T
B
P
2X
Notes: 1. Dimensioning and tolerancing per
ASME Y14.5M - 1994
2. controlling dimension: millimeter
0.200
N
-F-
DIM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
K
G
C
MIN
MAX
INCHES
MIN
MAX
A
21.000 BSC
0.827 BSC
B
21.000 BSC
0.827 BSC
C
2.450
3.000
0.097
0.118
D
0.820
0.930
0.032
0.036
G
H
MILLIMETERS
H
K
1.270 BSC
0.790
0.990
0.635 BSC
0.050 BSC
0.031
0.039
0.025 BSC
N
5.000
16.000
0.197
0.630
P
5.000
16.000
0.197
0.630
K
255X
D
0.300
S
T E
0.150
S
T
S
F
S
49
5410B–HIREL–09/05
15.3
CI-CGA Package Parameters
The package parameters are as provided in the following list. The package type is 21 mm,
255-lead ceramic ball grid array (CI-CGA).
15.3.1
50
Package outline
21 mm × 21 mm
Interconnects
255
Pitch
1.27 mm
Typical module height
3.84 mm
Mechanical Dimensions of the CI-CGA Package
Figure 15-3 provides the mechanical dimensions and bottom surface nomenclature of the CICGA package.
TSPC603R
5410B–HIREL–09/05
TSPC603R
Figure 15-3. Mechanical Dimensions and Bottom Surface Nomenclature of the CI-CGA Package
2X
A1
CORNER
0.200
A
Notes: 1. Dimensioning and tolerancing per
ASME Y14.5M—1994
2. Controlling dimension: millimeter
-E-
Millimeters
-T-
B
P
0.150 T
Dim
Min
Max
A
21.000 BSC
B
21.000 BSC
3.84 BSC
C
D
0.790
H
2X
K
0.200
N
-F-
1.545
1.695
0.635 BSC
N
5.000
P
7.000
3.02 BSC
R
0.10 BSC
U
V
0.990
1.270 BSC
G
0.25
0.35
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
K
K
G
255X
D
0.300 S T E S
0.150 S T
F S
H
U
V
R
C
51
5410B–HIREL–09/05
15.4
CERQUAD 240 Package
Figure 15-4. Mechanical Dimensions of the Wire-bond CERQUAD Package
TOP
Die
Wire Bonds
Ceramic Body
AD
AD
Alloy 42 Leads
G
P
X
View AC
S
X = L, M or N
U
180
VIEW AC
4 Places
121
181
D
F
120
Z
Y
J
0.08 M T L-N S M S
Section AD
240 Places
B
V
N
L
81
240
1
Notes:
1. Dimensioning and tolerancing per ASMEY14.5M-1994
2. Controlling dimension: millimeter
3. Datum plane H is located at bottom of lead and
is coincident with the lead where the lead exists the
ceramic body at the bottom of the parting line
4. Datum L. M and N to be determined at datum plane H
5. Dimension S and V to be determined at seating plane T.
6. Dimension A and B define maximum ceramic body
dimensions including glass protrusion and top and
bottom mismatch
80
M
A
4 x 60 tips
0.16 T
L-N
0.20 M H L-N S M S
M
H
C E
W
0.10
T Seating
Plane
View AE
AB
H Datum
Θ2
Plane
HE
52
K
AA
View AE
Datum
Plane
DIM
A
B
C
D
E
F
G
HE
J
K
P
S
U
V
W
Y
Z
AA
AB
Θ2
MILLIMETERS
MIN
TYP
30.86
31.00
30.86
31.00
3.67
3.95
0.185
0.220
3.10
3.50
0.175
0.200
0.50 BSC
2.025
2.100
0.130
0.147
0.45
0.50
0.25 BSC
34.41
34.58
17.20
17.30
34.41
34.58
0.45
0.70
17.20
17.30
0.122
0.127
1.80 REF
0.95 REF
1°
4°
MAX
31.75
31.75
4.15
0.270
3.90
0.225
2.175
0.175
0.55
34.75
17.40
34.75
0.95
17.40
0.132
7°
TSPC603R
5410B–HIREL–09/05
TSPC603R
16. Ordering Information
16.1
Ordering Information of the CBGA, CI-CGA and HiTCE Packages
TS (X)
PC603R
M
G
B /Q
12
L
(C)
Revision level
Prefix
Bus divider (to be confirmed)
L: any bus at 75 MHz
Prototype
Type
Temperature range : TC
M: Tc = -55, Tj = +125˚C
V: Tc = -40, Tj = +110˚C
Package :
G: CBGA
GS: CI-CGA
GH: HiTCE CBGA
Maximum internal processor speed
6 : 166 MHz
8 : 200 MHz
10: 233 MHz
12: 266 MHz
14: 300 MHz
Screening level:
__ : Standard
B/Q: MIL-PRF-38535, class Q
U: Upscreening
16.2
Ordering Information of the CERQUAD 240 Package
TS (X)
PC603R
M
A
B /Q
8
L
(C )
Revision level
Prefix
Prototype
Bus divider (to be confirmed)
L: any bus ≤ 66 MHz
Type
Maximum internal processor speed
8: 200 MHz
Temperature range: TC
M: -55, +125˚C
V: -40, +110˚C
C: 0, +70˚C
Package:
A : CERQUAD
Screening level:
__ : Standard
B/Q : MIL-PRF-38535, class Q
Note:
For availability of the different versions, contact your Atmel sales office.
53
5410B–HIREL–09/05
17. Definitions
Datasheet Status
Validity
Objective specification
This datasheet contains target and goal specifications for
discussion with the customer and application validation
Before design phase
Target specification
This datasheet contains target or goal specifications for
product development
Valid during the design phase
Preliminary specification α site
This datasheet contains preliminary data. Additional data
may be published at a later date and could include
simulation results
Valid before characterization
phase
Preliminary specification β site
This datasheet also contains characterization results
Valid before the
industrialization phase
Product specification
This datasheet contains final product specifications
Valid for production purpose
Limiting Values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stresses above one or more of the
limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at
any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values
for extended periods may affect device reliability.
Application Information
Where application information is given, it is advisory and does not form part of the specification
17.1
Life Support Applications
These products are not designed for use in life support appliances, devices, or systems where
malfunction of these products can reasonably be expected to result in personal injury. Atmel
customers using or selling these products for use in such applications do so at their own risk and
agree to fully indemnify Atmel for any damages resulting from such improper use or sale.
18. Document Revision History
Table 18-1 provides a revision history for this hardware specification.
Table 18-1.
54
Document Revision History
Revision
Number
Date
B
07/2005
Added HiTCE package for PowerPC 603R
A
10/2004
This document is a merge of TSPC603R in CBGA255/CI-CGA 255 package (ref 2125B) and
TSPC603R in Cerquad package (ref 2127A)
Substantive Change(s)
TSPC603R
5410B–HIREL–09/05
TSPC603R
Table of Contents
Features .................................................................................................... 1
Features Specific to CBGA 255, CBGA HiTCE 255 and CI-CGA 255 ... 1
Features Specific to Cerquad ................................................................. 1
1
Description ............................................................................................... 1
2
Screening/Quality/Packaging ................................................................. 2
3
Block Diagram .......................................................................................... 3
4
Overview ................................................................................................... 3
5
Signal Description ................................................................................... 4
6
Detailed Specifications ............................................................................ 5
7
Applicable Documents ............................................................................ 5
7.1 Design and Construction ..........................................................................................6
7.2 Absolute Maximum Ratings ......................................................................................6
8
Thermal Characteristics .......................................................................... 7
8.1 CBGA 255 and CI-CGA 255 Packages ....................................................................7
8.2 HiTCE CBGA Package .............................................................................................8
8.3 CERQUAD 240 Package .........................................................................................8
9
Power Consideration ............................................................................... 9
9.1 Dynamic Power Management ..................................................................................9
9.2 Programmable Power Modes .................................................................................10
9.3 Power Management Modes ...................................................................................10
9.4 Power Management Software Considerations .......................................................12
9.5 Power Dissipation ...................................................................................................13
9.6 Marking ...................................................................................................................13
10 Pin Assignments .................................................................................... 13
10.1 CBGA 255 and CI-CGA 255 Packages ................................................................13
10.2 CERQUAD 240 Package .....................................................................................17
11 Electrical Characteristics ...................................................................... 22
11.1 General Requirements .........................................................................................22
11.2 Static Characteristics ............................................................................................22
11.3 Dynamic Characteristics .......................................................................................23
i
5410B–HIREL–09/05
11.4 JTAG AC Timing Specifications ...........................................................................27
12 Functional Description .......................................................................... 28
12.1 PowerPC Registers and Programming Model ......................................................28
12.2 Instruction Set and Addressing Modes .................................................................33
12.3 Cache Implementation .........................................................................................35
12.4 Memory Management ..........................................................................................41
13 Preparation for Delivery ........................................................................ 43
13.1 Packaging .............................................................................................................43
13.2 Certificate of Compliance .....................................................................................43
13.3 Handling ...............................................................................................................43
13.4 Choice of Clock Relationships ..............................................................................43
14 System Design Information .................................................................. 45
14.1 PLL Power Supply Filtering ..................................................................................45
14.2 Decoupling Recommendations ............................................................................46
14.3 Connection Recommendations ............................................................................46
14.4 Pull-up Resistor Requirements .............................................................................46
15 Package Mechanical Data ..................................................................... 47
15.1 CBGA HiTCE Package Parameters .....................................................................47
15.2 CBGA Package Parameters .................................................................................49
15.3 CI-CGA Package Parameters ..............................................................................50
15.4 CERQUAD 240 Package .....................................................................................52
16 Ordering Information ............................................................................. 53
16.1 Ordering Information of the CBGA, CI-CGA and HiTCE Packages .....................53
16.2 Ordering Information of the CERQUAD 240 Package ..........................................53
17 Definitions .............................................................................................. 54
17.1 Life Support Applications ......................................................................................54
18 Document Revision History .................................................................. 54
ii
TSPC603R
5410B–HIREL–09/05
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5410B–HIREL–09/05
iv
TSPC603R
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