Features • • • • • • • • • Supply Voltage: 5V Low Power Consumption: 15 mA/5V Output Level and Spurious Products Adjustable (Optional) Excellent Sideband Suppression by Means of Duty Cycle Regeneration of the LO Input Signal Phase-control Loop for Precise 90° Phase Shifting Power-down Mode Low LO Input Level: -15 dBm 50-Ω Single-ended LO and RF Port LO Frequency Range of 30 MHz to 300 MHz 300-MHz Quadrature Modulator Benefits • Low Current Consumption • Few External Components Result in Cost and Board Space Saving • Adjustment Free Hence Saves Time U2793B Electrostatic sensitive device. Observe precautions for handling. 1. Description The IC U2793B is a 300-MHz quadrature modulator that uses Atmel®’s advanced UHF process. It features low current consumption, single-ended RF ports and adjustment-free application, which makes the device suitable for all digital radio systems, e.g., GSM, PCN, JDC and WLAN. As an option, output level and spurious products are adjustable at pins 19 and 20. In conjunction with Atmel’s U2795B mixer, an up-converter up to 2 GHz can be realized. Figure 1-1. Block Diagram SPD BBAi BBAi LOi LOi BBBi BBBi 8 10 9 14 Duty cycle 15 regenerator Frequency doubler 0° 90° 90° control loop Σ PU 1 Power 6,7 VS up VRef 13 19 LP2 LP1 20 RFo 4 11 12 3,16,17,18 2 ACGND 5 ACGND GND 4651E–CELL–07/06 2. Pin Configuration Figure 2-1. Pinning SSO20 PU 1 20 LP1 ACGND 2 19 LP2 GND 3 18 GND RFO 4 17 GND ACGND 5 16 GND VS 6 15 LOI VS 7 14 LOI SPU 8 13 VREF BBAI 9 12 BBBI BBAI 10 11 BBBI U2793B 2 U2793B 4651E–CELL–07/06 U2793B Table 2-1. Pin Description Pin Symbol Function 1 PU 2 ACGND 3 GND Ground 4 RFO RF output 5 ACGND AC ground 6 VS Supply voltage 7 VS Supply voltage 8 SPU Settling time power-up 9 BBAI Baseband input A 10 BBAI Baseband input A inverse 11 BBBI Baseband input B 12 BBBI Baseband input B inverse 13 VREF Reference voltage (2.5V) 14 LOI Input LO 15 LOI Input LO inverse, typically grounded 16 GND Ground 17 GND Ground 18 GND Ground 19 LP2 Output low pass and power control 20 LP1 Output low pass and power control Power-up input AC ground 3 4651E–CELL–07/06 3. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Value Unit Supply voltage VS 6 V Input voltage Vi 0 to VS V Junction temperature Tj 125 °C TStg –55 to +125 °C Symbol Value Unit RthJA 140 K/W Symbol Value Unit Storage temperature range 4. Thermal Resistance Parameters Junction ambient SSO20 5. Operating Range Parameters Supply voltage Ambient temperature range VS 4.5 to 5.5 V Tamb –40 to +85 °C 6. Electrical Characteristics Test conditions (unless otherwise specified); VS = 5V, Tamb = 25°C, referred to test circuit. System impedance Zo = 50Ω, fLO =150 MHz, PLO = -15 dBm, VBBi = 1.0 Vpp, differential No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 4.5 5 5.5 V A mA A mVpp D kΩ D MHz D 1.1 Supply voltage range 6, 7 VS 1.2 Supply current 6, 7 IS 15 2 Baseband Inputs, Pin 9-10, 11-12 2.1 Input-voltage range (differential) VBBi 1000 2.2 Input impedance ZBBi 30 2.3 Input-frequency range fBBi 2.4 Input voltage, common mode 3 3.1 0 1500 50 2.5 V LO Input, Pins 14 and 15 Frequency range (1) fLOi 30 3.2 Input level PLOi –15 3.3 Input impedance ZiLO (2) 3.4 Voltage standing wave ratio VSWRLO 3.5 3.5 Duty-cycle range Notes: 1. Required LO level is a function of the LO frequency. DCRLO 0.4 300 MHz D –5 dBm D Ω D D 0.6 D 2. The LO input impedance is consisting of a 50 Ω resistor in series with a 15 pF capacitor. 3. With the pins 19 and 20 spurious performance especially for low frequency application can be improved by adding a chip capacitor between LP1 and LP2. In conjunction with a parallel resistor the output level can be adjusted to the following mixer stage without degration of LO suppression and noise performance which would decrease if the I/Q input level is reduced. 4. For Tamb = –40°C to +85°C and VS = 4.5V to 5.5V 4 U2793B 4651E–CELL–07/06 U2793B 6. Electrical Characteristics (Continued) Test conditions (unless otherwise specified); VS = 5V, Tamb = 25°C, referred to test circuit. System impedance Zo = 50Ω, fLO =150 MHz, PLO = -15 dBm, VBBi = 1.0 Vpp, differential (Continued) No. 4 Parameters Test Conditions Symbol Min. Typ. Max. –3 –1 +2 Unit Type* dBm A/B dB A RF Output, Pin 4 4.1 Output level fLO = 150 MHz VBBi = 1 Vpp, differential fLO = 50 MHz VBBi = 0.3 Vpp, differential 4.2 LO suppression PLO = –20 dBM 4.3 Voltage standing wave ratio 4.4 Pin Sideband suppression PRFo LORFO 0 32 45 1.4 VSWRRF (3) SBSRFo (4) 35 2 D 45 dB A 4.5 Phase error Pe <1 deg D 4.6 Amplitude error Ae < ±0.25 dB D 4.7 Noise floor VBBi = 2V, VBBi = 3V VBBi = VBBi = 2.5V NFL –137 –143 dBm/Hz D µA D µs D V D 5 Power-up Mode 5.1 Supply current VPU ≤0.5V, pins 6, 7 VPU = 1V IPU 10 5.2 Settling time Pins 1 to 4, CSPU = 100 pF CLO = 100 pF, CRFo = 1 nF tSPU 10 6 6.1 7 7.1 1 Switching Voltage, Pin 1 Power on VPUON 4 VRef 2.375 Reference Voltage, Pin 13 Voltage range 7.2 Output impedance Notes: 1. Required LO level is a function of the LO frequency. ZoRef 2.5 30 2.625 V A Ω D 2. The LO input impedance is consisting of a 50 Ω resistor in series with a 15 pF capacitor. 3. With the pins 19 and 20 spurious performance especially for low frequency application can be improved by adding a chip capacitor between LP1 and LP2. In conjunction with a parallel resistor the output level can be adjusted to the following mixer stage without degration of LO suppression and noise performance which would decrease if the I/Q input level is reduced. 4. For Tamb = –40°C to +85°C and VS = 4.5V to 5.5V 5 4651E–CELL–07/06 7. Diagrams Figure 7-1. Reference Voltage versus Tamb 2.57 2.56 VRef (V) 2.55 2.54 2.53 2.52 2.51 2.5 -40 0 40 80 120 Temperature (°C) Figure 7-2. OIP3 versus Tamb, LO = 150 MHz, Level -10 dBm 8 IP3 (dBm) 6 4 2 0 -40 0 40 80 120 80 120 Temperature (°C) Figure 7-3. Supply Current versus Tamb 20 Supply Current (mA) 16 12 8 4 0 -40 0 40 Temperature (°C) 6 U2793B 4651E–CELL–07/06 U2793B Figure 7-4. Recommended LO Power Range versus LO Frequency at Tamb = 25° C 0 PLO (dBm) -10 -20 -30 -40 0 50 100 150 200 250 300 fLO (MHz) Figure 7-5. Output Power versus Tamb 0 Output Power (dBm) -0.4 -0.8 -1.2 -1.6 -2 -40 0 40 120 80 Temperature (°C) Figure 7-6. Typical Output Power versus LO Frequency at Tamb = 25° C, VBBi = 250 mV (Differential) 5 1.2 Vpp 0 1.0 Vpp 800 mVpp -5 Pout (dBm) -10 -15 -20 100 mVpp 200 mVpp -25 400 mVpp -30 600 mVpp -35 0 50 100 150 200 250 300 FLO (MHz) 7 4651E–CELL–07/06 Figure 7-7. Typical Required VBBi Input Signal (Differential) versus LO Frequency for PO = 1 dBm and PO = -3 dBm 2000 1800 -3 dBm -1 dBm 1600 -5 dBm Pout (dBm) 1400 1200 1000 800 600 400 200 0 0 50 100 150 200 250 300 FLO (MHz) 8 U2793B 4651E–CELL–07/06 U2793B 8. Evaluation Board Drawings Figure 8-1. Evaluation Board Circuitry C1 L1 PU 20 1 C2 C9 R1 2 19 3 18 4 17 C3 OUT C4 16 5 U2793B L2 VS C5 C7 6 15 7 14 LO C8 8 13 9 12 10 11 C6 Ainv A GND B VRef Binv Part List C1, C2, C3, C4, C6 = 1 nF C7, C8 = 100 pF C5 = 100 nF C9, R1 = 1 pF to 10 pF = 50-Ω Microstrip = optional The above listed components result in a PD settling time of <20 µs. The use of other component values will require consideration for time requirements in burst-mode applications. 9 4651E–CELL–07/06 Figure 8-2. 10 PCB Layout Evaluation Board U2793B 4651E–CELL–07/06 U2793B 9. Application Circuits Bias network for AC-coupled baseband inputs (VBA, VBB). R1 = 2.5 kΩ, R2 ≤10 kΩ for ≥ 35 dB LO suppression which is in reference to < 2 mV input offset. Figure 9-1. Application Circuit with AC-coupled Baseband Inputs R1 1n VRef R2 13 10 BBAi PU 1 Power up 9 BBAi 6,7 VS 15 Duty cycle regenerator Frequency doubler 0° 90° 90° control loop 20 Σ 100n 8 SPU 19 LOi 14 LOi Power down 4 LP2 LP1 RFo ACGND BBBi 11 BBBi 12 2 5 ACGND 3,16,17,18 GND Figure 9-2. Application Circuit with DC-coupled Baseband Inputs VRef 100n 13 1n PU 1 10 10k BBAi Power up 9 BBAi Baseband processing 10k 100p LOi 14 LO LOi 15 Power down 6,7 VS 8 SPU 19 Duty cycle regenerator Frequency doubler 0° 90° 90° control loop 20 Σ 100n LP2 LP1 1n OUT 4 RFo 1n ACGND 1n 10k 10k 100n 2 BBBI 11 1n BBBI 12 5 3,16,17,18 ACGND GND 10. Ordering Information Extended Type Number Package Remarks U2793B-NFSH SSO20 Tube, lead free U2793B-NFSG3H SSO20 Taped and reeled, lead free 11 4651E–CELL–07/06 11. Package Information 12. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. 12 Revision No. History 4651E-CELL-07/06 • • • • • Page 1, PB-free logo deleted Page 3, Pin Desription table: Symbols of Pins 10,12, 15 changed Page 4, Abs. Max. Ratings table: Storage temperature values changed Page 5, row 4.7 changed Put datasheet in a new template U2793B 4651E–CELL–07/06 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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