ATMEL U3742BM

Features
• IC Distinguishes the Signal Strength of Several Transmitters via RSSI (Received Signal
Strength Indicator) Output
• Minimal External Circuitry Requirements, No RF Components on the PC Board Except
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Matching to the Receiver Antenna
High Sensitivity, Especially at Low Data Rates
Sensitivity Reduction Possible Even While Receiving
Fully Integrated VCO
Low Power Consumption Due to Configurable Self-polling with a Programmable Time
Frame Check
Supply Voltage 4.5 V to 5.5 V
Operating Temperature Range -40°C to 105°C
Single-ended RF Input for Easy Adaptation to λ/4 Antenna or Printed Antenna on PCB
Low-cost Solution Due to High Integration Level
ESD Protection According to MIL-STD. 883 (4 KV HBM)
High Image Frequency Suppression Due to 1 MHz IF in Conjunction with a SAW
Front-end Filter (Up to 40 dB Achievable with Newer SAWs)
Communication to Microcontroller Possible via a Single, Bi-directional Data Line
Power Management (Polling) is also Possible by Means of a Separate Pin via the
Microcontroller
UHF ASK/FSK
Receiver
U3742BM
Description
The U3742BM is a multi-chip PLL receiver device supplied in an SO20 package. It has
been especially developed for the demands of RF low-cost data transmission systems
with data rates from 1 kBaud to 10 kBaud (1 kBaud to 3.2 kBaud for FSK) in Manchester or Bi-phase code. The receiver is well suited to operate with Atmel's PLL RF
transmitter IC U2741B. Its main applications in the area of wireless control are telemetering, security technology, tire-pressure monitoring and keyless-entry systems. It can
be used in the frequency receiving range of f0 = 300 MHz to 450 MHz for ASK or FSK
data transmission. All the statements made in this data sheet refer both to
433.92 MHz and 315 MHz applications.
Rev. 4735A–RKE–11/03
Figure 1. System Block Diagram
1 Li cell
UHF ASK/FSK
Remote control receiver
U3742BM
U2741B
Demod.
Keys
Encoder
ATARx9x
Control
PLL
1...3
Microcontroller
UHF ASK/FSK
Remote control transmitter
IF Amp
Antenna Antenna
XTO
VCO
PLL
Power
amp.
LNA
XTO
VCO
Figure 2. Block Diagram
FSK/ASKDemodulator
and data filter
FSK/ASK
CDEM
RSSI
VS
Dem_out
50 kΩ
DATA
Limiter out
RSSI
ENABLE
SENS
IF Amp
AVCC
Sensitivity
reduction
Polling circuit
and
control logic
TEST
AGND
MODE
4. Order
DGND
FE
CLK
DVCC
Standby logic
LPF
3 MHz
MIXVCC
LFGND
LNAGND
LFVCC
IF Amp
LPF
3 MHz
VCO
XTO
XTO
f
LNA_IN
LF
LNA
64
2
U3742BM
4735A–RKE–11/03
U3742BM
Pin Configuration
Figure 3. Pinning SO20
SENS
1
20
DATA
FSK/ASK
2
19
ENABLE
CDEM
3
18
TEST
AVCC
4
17
RSSI
AGND
5
16
MODE
DGND
6
15
DVCC
MIXVCC
7
14
XTO
LNAGND
8
13
LFGND
LNA_IN
9
12
LF
NC
10
11
LFVCC
Pin Description
Pin
Symbol
1
SENS
2
FSK/ASK
3
CDEM
Lower cut-off frequency of the data filter
4
AVCC
Analog power supply
5
AGND
Analog ground
6
DGND
Digital ground
7
MIXVCC
Power supply mixer
8
LNAGND
High-frequency ground LNA and mixer
9
LNA_IN
10
NC
11
LFVCC
12
LF
13
LFGND
14
XTO
15
DVCC
Function
Sensitivity-control resistor
Selecting FSK/ASK
Low: FSK, High: ASK
RF input
Not connected
Power supply VCO
Loop filter
Ground VCO
Crystal oscillator
Digital power supply
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Pin Description (Continued)
Pin
Symbol
Function
16
MODE
17
RSSI
Output of the RSSI amplifier
18
TEST
Test pin, during operation at GND
19
ENABLE
20
DATA
Selecting 433.92 MHz/315 MHz
Low: 4.90625 MHz (USA)
High: 6.76438 (Europe)
Enables the polling mode
Low: polling mode off (sleep mode)
High: polling mode on (active mode)
Data output/configuration input
RF Front End
The RF front end of the receiver is a heterodyne configuration that converts the input
signal into a 1 MHz IF signal. According to Figure 2 on page 2, the front end consists of
an LNA (low noise amplifier), LO (local oscillator), a mixer and an RF amplifier.
The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO
(crystal oscillator) generates the reference frequency fXTO. The VCO (voltage-controlled
oscillator) generates the drive voltage frequency fLO for the mixer. fLO is dependent on
the voltage at pin LF. fLO is divided by a factor of 64. The divided frequency is compared
to fXTO by the phase frequency detector. The current output of the phase frequency
detector is connected to a passive loop filter and thereby generates the control voltage
VLF for the VCO. By means of that configuration, VLF is controlled in a way that fLO/64 is
equal to fXTO. If fLO is determined, fXTO can be calculated using the following formula:
fXTO = fLO/64
The XTO is a one-pin oscillator that operates at the series resonance of the quartz crystal. According to Figure 4, the crystal should be connected to GND via the capacitor CL.
The value of that capacitor is recommended by the crystal supplier. The value of CL
should be optimized for the individual board layout to achieve the exact value of fXTO and
hereby of fLO. When designing the system in terms of receiving bandwidth, the accuracy
of the crystal and the XTO must be considered.
Figure 4. PLL Peripherals
VS
DVCC
CL
XTO
LFGND
R1 = 820 Ω
C9 = 4.7 nF
C10 = 1 nF
LF
LFVCC
4
VS
R1
C10
C9
U3742BM
4735A–RKE–11/03
U3742BM
The passive loop filter connected to pin LF is designed for a loop bandwidth of
BLoop = 100 kHz. This value for BLoop exhibits the best possible noise performance of the
LO. Figure 4 on page 4 shows the appropriate loop filter components to achieve the
desired loop bandwidth. If the filter components are changed for any reason, please
note that the maximum capacitive load at pin LF is limited. If the capacitive load is
exceeded, a bit check may no longer be possible since fLO cannot settle in time before
the bit check starts to evaluate the incoming data stream. Self-polling does therefore
also not work in that case.
fLO is determined by the RF input frequency fRF and the IF frequency fIF using the following formula:
fLO = fRF - fIF
To determine fLO, the construction of the IF filter must be considered at this point. The
nominal IF frequency is fIF = 1 MHz. To achieve a good accuracy of the filter's corner frequencies, the filter is tuned by the crystal frequency fXTO. This means that there is a
fixed relation between fIF and fLO, that depends on the logic level at pin MODE. This is
described by the following formulas:
fLO
MODE = 0 (USA) f IF = --------314
f LO
MODE = 1 (Europe) f IF = ----------------432.92
The relation is designed to achieve the nominal IF frequency of fIF = 1 MHz for most
applications. For applications where fRF = 315 MHz, MODE must be set to '0'. In the
case of fRF = 433.92 MHz, MODE must be set to '1'. For other RF frequencies, fIF is not
equal to 1 MHz. fIF is then dependent on the logical level at pin MODE and on fRF. Table
1 on page 6 summarizes the different conditions.
The RF input either from an antenna or from a generator must be transformed to the RF
input pin LNA_IN. The input impedance of that pin is provided in the electrical parameters. The parasitic board inductances and capacitances also influence the input
matching. The RF receiver U3742BM exhibits its highest sensitivity at the best signal-tonoise ratio in the LNA. Hence, noise matching is the best choice for designing the transformation network.
A good practice when designing the network is to start with power matching. From that
starting point, the values of the components can be varied to some extent to achieve the
best sensitivity.
If a SAW is implemented into the input network, a mirror frequency suppression of
D P Ref = 40 dB can be achieved. There are SAWs available that exhibit a notch at
Df = 2 MHz. These SAWs work best for an intermediate frequency of IF = 1 MHz. The
selectivity of the receiver is also improved by using a SAW. In typical automotive applications, a SAW is used.
Figure 5 on page 6 shows a typical input matching network for fRF = 315 MHz and
fRF = 433.92 MHz using a SAW. Figure 6 on page 6 illustrates input matching to 50 W
without a SAW. The input matching networks shown in Figure 6 on page 6 are the reference networks for the parameters given in the electrical characteristics.
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4735A–RKE–11/03
Table 1. Calculation of LO and IF Frequency
Conditions
Local Oscillator
Frequency
Intermediate Frequency
fRF = 315 MHz, MODE = 0
fLO = 314 MHz
fIF = 1 MHz
fRF = 433.92 MHz, MODE = 1
fLO = 432.92 MHz
fIF = 1 MHz
300 MHz < fRF < 365 MHz, MODE = 0
fRF
fLO = ------------------1
1 + ---------314
f LO
fIF = --------314
365 MHz < fRF < 450 MHz, MODE = 1
f RF
fLO = --------------------------1
1 + -----------------432.92
f LO
fIF = ----------------432.92
Figure 5. Input Matching Network with SAW Filter
8
8
LNAGND
U3742BM
9
C3
L
22p
25n
100p
C17
L3
27n
C17
C16
8.2p
100p
fRF = 315 MHz
TOKO LL2012
F27NJ
L2
L3
47n
22p
TOKO LL2012
F47NJ
L2
TOKO LL2012
F33NJ
RFIN
LNA_IN
25n
47p
fRF = 433.92 MHz
9
L
C3
LNA_IN
C16
LNAGND
U3742BM
33n
1
2
C2
8.2p
B3555
IN
OUT
OUT_GND
IN_GND
CASE_GND
3, 4 7, 8
5
TOKO LL2012
F82NJ
RFIN
6
82n
C2
1
2
10p
B3551
IN
OUT
OUT_GND
IN_GND
CASE_GND
3, 4 7, 8
5
6
Figure 6. Input Matching Network without SAW Filter
fRF = 433.92 MHz
8
LNAGND
fRF = 315 MHz
8
U3742BM
9
25n
15p
RFIN
U3742BM
9
LNA_IN
25n
33p
LNA_IN
RFIN
3.3p
100p
22n
6
LNAGND
TOKO LL2012
F22NJ
3.3p
100p
39n
TOKO LL2012
F39NJ
U3742BM
4735A–RKE–11/03
U3742BM
Please note that for all coupling conditions (see Figure 5 on page 6 and Figure 6 on
page 6), the bond wire inductivity of the LNA ground is compensated. C3 forms a series
resonance circuit together with the bond wire. L = 25 nH is a feed inductor to establish a
DC path. Its value is not critical but must be large enough not to detune the series resonance circuit. For cost reduction, this inductor can be easily printed on the PCB. This
configuration improves the sensitivity of the receiver by about 1 dB to 2 dB.
Analog Signal
Processing
IF Amplifier
The signals coming from the RF front end are filtered by the fully integrated 4th-order IF
filter. The IF center frequency is fIF = 1 MHz for applications where fRF = 315 MHz or
fRF = 433.92 MHz is used. For other RF input frequencies, refer to Table 1 on page 6 to
determine the center frequency.
The receiver U3742BM - M3 employs an IF bandwidth of BIF = 600 kHz and can be used
together with the U2741B in FSK and ASK mode.
RSSI Amplifier
The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is
fed into the demodulator. The dynamic range of this amplifier is DRRSSI = 60 dB. If the
RSSI amplifier is operated within its linear range, the best S/N ratio is maintained in ASK
mode. If the dynamic range is exceeded by the transmitter signal, the S/N ratio is
defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage
due to a disturber. The dynamic range of the RSSI amplifier is exceeded if the RF input
signal is about 60 dB higher compared to the RF input signal at full sensitivity.
In FSK mode, the S/N ratio is not affected by the dynamic range of the RSSI amplifier.
The output voltage of the RSSI amplifier is internally compared to a threshold voltage
VTh_red. VTh_red is determined by the value of the external resistor RSense. RSense is connected between pin SENS and GND or VS. The output of the comparator is fed into the
digital control logic. By this means it is possible to operate the receiver at a lower
sensitivity.
Pin RSSI
The output voltage of the RSSI amplifier (VRSSI) is available at pin RSSI. Using the RSSI
output signal, the signal strength of different transmitters can be distinguished. The
usable input-power range PRef is -100 dBm to -55 dBm. The temperature coefficient TC
of VRSSI is typically -2.2 mV/K. Due to TC and gain tolerance, it is not possible to find out
the absolute level of each transmitter, but the level differences can be used to distinguish several transmitters. As illustrated in Figure 8 on page 8, the RSSI output voltage
is not constant over the temperature range. Figure 7 on page 8 illustrates an application
that realizes a temperature compensation of VRSSI.
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4735A–RKE–11/03
Figure 7. Temperature Compensation of VRSSI
V RSSI_temp_comp.
I ~ Ig(VLNA_IN)
180k
RSSI
B min = 60
50k
I
V RSSI
47k
U3742BM
Figure 8. RSSI Characteristic
1.6
1.5
1.4
max
VRSSI (V)
1.3
1.2
1.1
1.0
-40°C
0.9
25°C
0.8
0.7
min
105°C
0.6
0.5
-110
-100
-90
-80
-70
-60
-50
PRef (dBm)
If RSense is connected to VS, the receiver operates at a lower sensitivity. The reduced
sensitivity is defined by the value of RSense, the maximum sensitivity by the signal-tonoise ratio of the LNA input. The reduced sensitivity is dependent on the signal strength
at the output of the RSSI amplifier.
Since different RF input networks may exhibit slightly different values for the LNA gain,
the sensitivity values given in the electrical characteristics refer to a specific input
matching. This matching is illustrated in Figure 6 on page 6 and exhibits the best possible sensitivity.
R Sense can be connected to V S or GND via a microcontroller. The receiver can be
switched from full sensitivity to reduced sensitivity or vice versa at any time. In polling
mode, the receiver will not wake up if the RF input signal does not exceed the selected
sensitivity. If the receiver is already active, the data stream at pin DATA will disappear
when the input signal is lower than defined by the reduced sensitivity. Instead of the
data stream, the pattern according to Figure 9 on page 9 is issued at pin DATA to indicate that the receiver is still active.
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U3742BM
4735A–RKE–11/03
U3742BM
Figure 9. Steady L State Limited DATA Output Pattern
DATA
tmin2
FSK/ASK Demodulator
and Data Filter
tDATA_L_max
The signal coming from the RSSI amplifier is converted into the raw data signal by the
ASK/FSK demodulator. The operating mode of the demodulator is set via pin ASK/FSK.
Logic 'L' sets the demodulator to FSK, Logic 'H' sets it into ASK mode.
In ASK mode, an automatic threshold control circuit (ATC) is employed to set the detection reference voltage to a value where a good signal-to-noise ratio is achieved. This
circuit also implies the effective suppression of any kind of inband noise signals or competing transmitters. If the S/N ratio exceeds 10 dB, the data signal can be detected
properly.
The FSK demodulator is intended to be used for an FSK deviation of Df ³ 20 kHz. Lower
values may be used but the sensitivity of the receiver is reduced in that condition. The
minimum usable deviation is dependent on the selected baud rate. In FSK mode, only
BR_Range0 and BR_Range1 are available. In FSK mode, the data signal can be
detected if the S/N Ratio exceeds 2 dB.
The output signal of the demodulator is filtered by the data filter before it is fed into the
digital signal processing circuit. The data filter improves the S/N ratio as its pass band
can be adopted to the characteristics of the data signal. The data filter consists of a
1st-order high-pass and a 1st-order low-pass filter.
The high-pass filter cut-off frequency is defined by an external capacitor connected to
pin CDEM. The cut-off frequency of the high-pass filter is defined by the following
formula:
1
fcu_DF = ----------------------------------------------------------2 ´ p ´ 30 k W ´ CDEM
In self-polling mode, the data filter must settle very rapidly to achieve a low current consumption. Therefore, CDEM cannot be increased to very high values if self-polling is
used. On the other hand, CDEM must be large enough to meet the data filter requirements according to the data signal. Recommended values for CDEM are given in
“Electrical Characteristics” on page 25. The values are slightly different for ASK and
FSK mode.
The cut-off frequency of the low-pass filter is defined by the selected baud rate range
(BR_Range). BR_Range is defined in the OPMODE register (refer to section “Configuration of the Receiver” on page 19). BR_Range must be set in accordance to the used
baud rate.
The U3742BM is designed to operate with data coding where the DC level of the data
signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation
schemes are used, the DC level should always remain within the range of VDC_min = 33%
and VDC_max = 66%. The sensitivity may be reduced by up to 1.5 dB in that condition.
Each BR_Range is also defined by a minimum and a maximum edge-to-edge time
(tee_sig). These limits are defined in the electrical characteristics. They should not be
exceeded to maintain full sensitivity of the receiver.
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Receiving
Characteristics
The RF receiver U3742BM can be operated with and without a SAW front-end filter. In a
typical automotive application, a SAW filter is used to achieve better selectivity. The
selectivity with and without a SAW front-end filter is illustrated in Figure 10. This example relates to ASK mode. FSK mode exhibits similar behavior. Note that the mirror
frequency is reduced by 40 dB. The plots are printed relatively to the maximum sensitivity. If a SAW filter is used, an insertion loss of about 4 dB must be considered.
When designing the system in terms of receiving bandwidth, the LO deviation must be
considered as it also determines the IF center frequency. The total LO deviation is calculated to be the sum of the deviation of the crystal and the XTO deviation of the
U3742BM. Low-cost crystals are specified to be within ±100 ppm. The XTO deviation of
the U3742BM is an additional deviation due to the XTO circuit. This deviation is specified to be ±30 ppm. If a crystal of ±100 ppm is used, the total deviation is ±130 ppm in
that case. Note that the receiving bandwidth and the IF-filter bandwidth are equivalent in
ASK mode but not in FSK mode.
Figure 10. Receiving Frequency Response
0
-10
-20
without SAW
dP (dB)
-30
-40
-50
-60
-70
-80
with SAW
-90
-100
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
df (MHz)
Polling Circuit and
Control Logic
The receiver is designed to consume less than 1 mA while being sensitive to signals
from a corresponding transmitter. This is achieved via the polling circuit. This circuit
enables the signal path periodically for a short time. During this time the bit check logic
verifies the presence of a valid transmitter signal. Only if a valid signal is detected the
receiver remains active and transfers the data to the connected microcontroller. If there
is no valid signal present, the receiver is in sleep mode most of the time resulting in low
current consumption. This condition is called polling mode. A connected microcontroller
is disabled during that time.
All relevant parameters of the polling logic can be configured by the connected microcontroller. This flexibility enables the user meets the specifications in terms of current
consumption, system response time, data rate etc.
Regarding the number of connection wires to the microcontroller, the receiver is very
flexible. It can be either operated by a single bi-directional line to save ports to the connected microcontroller, or it can be operated by up to three uni-directional ports.
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U3742BM
4735A–RKE–11/03
U3742BM
Basic Clock Cycle of the
Digital Circuitry
The complete timing of the digital circuitry and the analog filtering is derived from one
clock. According to Figure 11, this clock cycle TClk is derived from the crystal oscillator
(XTO) in combination with a divider. The division factor is controlled by the logical state
at pin MODE. According to section “RF Front End” on page 4, the frequency of the crystal oscillator (f XTO) is defined by the RF input signal (f RFin ) which also defines the
operating frequency of the local oscillator (fLO).
Figure 11. Generation of the Basic Clock Cycle
TCLK
MODE
Divider
:14/:10
fXTO
16
L : USA(:10)
H: Europe(:14)
DVCC
15
XTO
XTO
14
Pin MODE can now be set in accordance with the desired clock cycle TClk. TClk controls
the following application-relevant parameters:
•
Timing of the polling circuit including bit check
•
Timing of the analog and digital signal processing
•
Timing of the register programming
•
Frequency of the reset marker
•
IF filter center frequency (fIF0)
Most applications are dominated by two transmission frequencies: fSend = 315 MHz is
mainly used in the USA, fSend = 433.92 MHz in Europe. In order to ease the usage of all
TClk-dependent parameters, the electrical characteristics display three conditions for
each parameter.
•
Application USA (fXTO = 4.90625 MHz, MODE = L, TClk = 2.0383 µs)
•
Application Europe (fXTO = 6.76438 MHz, MODE = H, TClk = 2.0697 µs)
•
Other applications (TClk is dependent on fXTO and on the logical state of pin MODE.
The electrical characteristic is given as a function of TClk).
The clock cycle of some function blocks depends on the selected baud rate range
(BR_Range) which is defined in the OPMODE register. This clock cycle TXClk is defined
by the following formulas for further reference:
BR_Range =
BR_Range0:
TXClk = 8 ´ TClk
BR_Range1:
TXClk = 4 ´ TClk
BR_Range2:
TXClk = 2 ´ TClk
BR_Range3:
TXClk = 1 ´ TClk
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4735A–RKE–11/03
Polling Mode
According to Figure 13 on page 14, the receiver stays in polling mode in a continuous
cycle of three different modes. In sleep mode, the signal processing circuitry is disabled
for the time period TSleep while consuming low current of IS = ISoff. During the start-up
period, TStartup, all signal processing circuits are enabled and settled. In the following bit
check mode, the incoming data stream is analyzed bit by bit contra a valid transmitter
signal. If no valid signal is present, the receiver is set back to sleep mode after the
period TBitcheck. This period varies check by check as it is a statistical process. An average value for TBitcheck is given in the electrical characteristics. During TStartup and TBitcheck
the current consumption is IS = ISon. The average current consumption in polling mode is
dependent on the duty cycle of the active mode and can be calculated as:
I Soff ´ T Sleep + I Son ´ ( T Startup + T Bitcheck )
I Spoll = ---------------------------------------------------------------------------------------------------------T Sleep + T Startup + TBitcheck
During TSleep and TStartup, the receiver is not sensitive to a transmitter signal. To guarantee the reception of a transmitted command, the transmitter must start the telegram with
an adequate preburst. The required length of the preburst is dependent on the polling
parameters TSleep, TStartup, TBitcheck and the startup time of a connected microcontroller
(TStart,microcontroller). TBitcheck thus depends on the actual bit rate and the number of bits
(NBitcheck) to be tested.
The following formula indicates how to calculate the preburst length.
TPreburst ³ TSleep + TStartup + TBitcheck + TStart_microcontroller
Sleep Mode
The length of period TSleep is defined by the 5-bit word Sleep of the OPMODE register,
the extension factor XSleep, according to Table 8 on page 21, and the basic clock cycle
TClk. It is calculated to be:
TSleep = Sleep ´ XSleep ´ 1024 ´ TClk
In US- and European applications, the maximum value of TSleep is about 60 ms if XSleep
is set to 1. The time resolution is about 2 ms in that case. The sleep time can be
extended to almost half a second by setting XSleep to 8. X Sleep can be set to 8 by bit
XSleep Std or by bit XSleep Temp resulting in a different mode of action as described
below:
XSleepStd = 1 implies the standard extension factor. The sleep time is always extended.
XSleepTemp = 1 implies the temporary extension factor. The extended sleep time is used
as long as every bit check is OK. If the bit check fails once, this bit is set back to 0 automatically resulting in a regular sleep time. This functionality can be used to save current
in the presence of a modulated disturber similar to an expected transmitter signal. The
connected microcontroller is rarely activated in that condition. If the disturber disappears, the receiver switches back to regular polling and is again sensitive to appropriate
transmitter signals.
According to Table 7 on page 21, the highest register value of Sleep sets the receiver
into a permanent sleep condition. The receiver remains in that condition until another
value for Sleep is programmed into the OPMODE register. This function is desirable
where several devices share a single data line.
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U3742BM
Bit Check Mode
In bit check mode, the incoming data stream is examined to distinguish between a valid
signal from a corresponding transmitter and signals due to noise. This is done by subsequent time frame checks where the distances between 2 signal edges are continuously
compared to a programmable time window. The maximum count of these edge-to-edge
tests, before the receiver switches to receiving mode, is also programmable.
Configuring the Bit Check
Assuming a modulation scheme that contains 2 edges per bit, two time frame checks
are verifying one bit. This is valid for Manchester, bi-phase and most other modulation
schemes. The maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the
variable NBitcheck in the OPMODE register. This implies 0, 6, 12 and 18 edge-to-edge
checks respectively. If NBitcheck is set to a higher value, the receiver is less likely to
switch to receiving mode due to noise. In the presence of a valid transmitter signal, the
bit check takes less time if NBitcheck is set to a lower value. In polling mode, the bit check
time is not dependent on NBitcheck. Figure 11 on page 11 shows an example where 3 bits
are tested successfully and the data signal is transferred to pin DATA.
According to Figure 12, the time window for the bit check is defined by two separate
time limits. If the edge-to-edge time tee is in between the lower bit check limit TLim_min and
the upper bit check limit TLim_max , the check will be continued. If t ee is smaller than
T Lim_min or t ee exceeds T Lim_max , the bit check will be terminated and the receiver
switches to sleep mode.
Figure 12. Valid Time Window for Bit Check
1/fSig
Dem_out
tee
TLim_min
TLim_max
For best noise immunity it is recommended to use a low span between TLim_min and
TLim_max. This is achieved using a fixed frequency at a 50% duty cycle for the transmitter
preburst. A '11111...' or a '10101...' sequence in Manchester or bi-phase is a good
choice concerning that advice. A good compromise between receiver sensitivity and
susceptibility to noise is a time window of ±25% regarding the expected edge-to-edge
time tee. Using preburst patterns that contain various edge-to-edge time periods, the bit
check limits must be programmed according to the required span.
The bit check limits are determined by means of the formula below:
TLim_min = Lim_min ´ TXClk
TLim_max = (Lim_max - 1) ´ TXClk
Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.
Using above formulas, Lim_min and Lim_max can be determined according to the
required TLim_min, TLim_max and TXClk. The time resolution when defining TLim_min and
TLim_max is TXClk. The minimum edge-to-edge time tee (tDATA_L_min, tDATA_H_min) is defined
according to the section “Receiving Mode” on page 16. Due to this, the lower limit
should be set to Lim_min ³ 10. The maximum value of the upper limit is Lim_max = 63.
13
4735A–RKE–11/03
Figure 13. Polling Mode Flow Chart
Sleep mode:
All circuits for signal processing
are disabled. Only XTO and
polling logic are enabled.
IS = ISoff
Sleep:
5-bit word defined by Sleep0 to
Sleep4 in OPMODE register
XSleep:
Extension factor defined by
XSleepStd and XSleepTemp
according to Table 8
TSleep = Sleep × XSleep × 1024 × TClk
TCLK:
Start-up mode:
The signal processing circuits are
enabled. After the start-up time
(TStartup) all circuits are in stable
condition and ready to receive.
IS = ISon
TStartup
Bit check mode:
The incoming data stream is
analyzed. If the timing indicates a
valid transmitter signal, the receiver
is set to receiving mode. Otherwise
it is set to Sleep mode.
IS = ISon
TBitcheck
NO
Bit check
OK ?
TStartup:
TBitcheck :
Basic clock cycle defined by fXTO and pin MODE
Is defined by the selected baud rate range and TClk.
The baud rate range is defined by Baud0 and Baud1
in the OPMODE register.
Depends on the result of the bit check
If the bit check is ok, Tbitcheck depends on
the number of bits to be checked (NBitcheck)
and on the utilized data rate.
If the bit check fails, the average time period for
that check depends on the selected baud rate
range and on TClk. The baud rate is defined by
Baud0 and Baud1 in the OPMODE register.
YES
Receiving mode:
The receiver is turned on permanently
and passes the data stream to the
connected microcontroller. It can be set
to Sleep mode through an OFF
command via pin DATA or ENABLE.
IS = ISon
14
OFF command
U3742BM
4735A–RKE–11/03
U3742BM
Figure 14. Timing Diagram for Complete Successful Bit Check
(Number of checked bits: 3)
Bit check ok
Enable IC
Bit check
1/2 Bit
1/2 Bit
1/2 Bit
1/2 Bit
1/2 Bit
1/2 Bit
Dem_out
DATA
Bit check mode
Startup mode
Receiving mode
Figure 15. Timing Diagram During Bit Check
(Lim_min = 14, Lim_max = 24)
Bit check ok
Bit check ok
Enable IC
TStartup
Bit check
1/2 Bit
1/2 Bit
1/2 Bit
Dem_out
Bit check counter
0
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 1011121314151617 18 1 2 3 4 5 6 7 8 9 1011121314 15 1 2 3 4
TXCLK
Figure 16. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)
(Lim_min = 14, Lim_max = 24)
Bit check failed (CV_Lim < Lim_min)
Enable IC
Bit check
1/2 Bit
Dem_out
Bit check counter
0
Startup mode
1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 10 1112
Bit check mode
0
Sleep mode
15
4735A–RKE–11/03
Figure 17. Timing Diagram for Failed Bit Check (Condition: CV_Lim ³ Lim_max)
(Lim_min = 14, Lim_max = 24)
Bit check failed (CV_Lim ≥ Lim_max)
Enable IC
Bit check
1/2 Bit
Dem_out
0
Bit check counter
Startup mode
1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 1011121314151617181920 21222324
Bit check mode
0
Sleep mode
Figure 15 to Figure 17 illustrate the bit check for the default bit check limits
Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits
are enabled during TStartup. The output of the ASK/FSK demodulator (Dem_out) is undefined during that period. When the bit check becomes active, the bit check counter is
clocked with the cycle TXClk.
Figure 15 on page 15 shows how the bit check proceeds if the bit check counter value
CV_Lim is within the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In Figure 16 on page 15, the bit check fails as the value CV_lim is lower than
the limit Lim_min. The bit check also fails if CV_Lim reaches Lim_max. This is illustrated
in Figure 17.
Duration of the Bit Check
If no transmitter signal is present during the bit check, the output of the ASK/FSK
demodulator delivers random signals. The bit check is a statistical process and TBitcheck
varies for each check. Therefore, an average value for TBitcheck is given in the electrical
characteristics. TBitcheck depends on the selected baud rate range and on TClk. A higher
baud rate range causes a lower value for TBitcheck resulting in a lower current consumption in polling mode.
In the presence of a valid transmitter signal, TBitcheck is dependant on the frequency of
that signal, fSig and the count of the checked bits, NBitcheck. A higher value for NBitcheck
thereby results in a longer period for TBitcheck requiring a higher value for the transmitter
preburst TPreburst.
Receiving Mode
If the bit check has been successful for all bits specified by N Bitcheck , the receiver
switches to receiving mode. According to Figure 14, the internal data signal is switched
to pin DATA in that case. A connected microcontroller can be woken up by the negative
edge at pin DATA. The receiver stays in that condition until it is switched back to polling
mode explicitly.
Digital Signal Processing
The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different
ways and as a result converted into the output signal data. This processing depends on
the selected baud rate range (BR_Range). Figure 18 on page 17 illustrates how
Dem_out is synchronized by the extended clock cycle TXClk. This clock is also used for
the bit check counter. Data can change its state only after T XClk elapsed. The
edge-to-edge time period tee of the Data signal as a result is always an integral multiple
of TXClk.
16
U3742BM
4735A–RKE–11/03
U3742BM
The minimum time period between two edges of the data signal is limited to
tee ³ TDATA_min. This implies an efficient suppression of spikes at the DATA output. At the
same time, it limits the maximum frequency of edges at DATA. This eases the interrupt
handling of a connected microcontroller. TDATA_min is to some extent affected by the preceding edge-to-edge time interval tee as illustrated in Figure 19. If tee is in between the
specified bit check limits, the following level is frozen for the time period
TDATA_min = tmin1, in case of tee being outside that bit check limits TDATA_min = tmin2 is
the relevant stable time period.
The maximum time period for DATA to be Low is limited to TDATA_L_max. This function
ensures a finite response time during programming or switching off the receiver via pin
DATA. TDATA_L_max is thereby longer than the maximum time period indicated by the
transmitter data stream. Figure 20 gives an example where Dem_out remains Low after
the receiver is in receiving mode.
Figure 18. Synchronization of the Demodulator Output
TXClk
Clock bit check
Counter
Dem_out
DATA
tee
Figure 19. Debouncing of the Demodulator Output
Dem_out
DATA
Lim_min ≤ CV_Lim < Lim_max
tmin1
tee
CV_Lim < Lim_min or CV_Lim ≥ Lim_max
tee
tmin2
Figure 20. Steady L State Limited DATA Output Pattern after Transmission
Enable IC
Bit check
Dem_out
DATA
Startup mode
Bit check mode
Receiving mode
tmin2
tDATA_L_max
17
4735A–RKE–11/03
After the end of data transmission, the receiver remains active and random noise pulses
appear at pin DATA. The edge-to-edge time period tee of the majority of these noise
pulses is equal to or slightly higher than TDATA_min.
Switching the Receiver Back
to Sleep Mode
The receiver can be set back to polling mode via pin DATA or via pin ENABLE.
When using pin DATA, this pin must be pulled to Low for the period t1 by the connected
microcontroller. Figure 21 illustrates the timing of the OFF command (see also Figure 25
on page 23). The minimum value of t1 depends on BR_Range. The maximum value for
t1 is not limited but it is recommended not to exceed the specified value to prevent erasing the reset marker. This item is explained in more detail in the section “Configuration
of the Receiver” on page 19. Setting the receiver to sleep mode via DATA is achieved
by programming bit 1 of the OPMODE register to be '1'. Only one sync pulse (t 3) is
issued.
The duration of the OFF command is determined by the sum of t1, t2 and t10. After the
OFF command, the sleep time TSleep elapses. Note that the capacitive load at pin DATA
is limited. The resulting time constant t together with an optional external pull-up resistor
may not be exceeded to ensure proper operation.
If the receiver is set to polling mode via pin ENABLE, an 'L' pulse (TDoze) must be issued
at that pin. Figure 22 on page 19 illustrates the timing of that command. After the positive edge of this pulse, the sleep time TSleep elapses. The receiver remains in sleep
mode as long as ENABLE is held to 'L'. If the receiver is polled exclusively by a microcontroller, TSleep can be programmed to 0 to enable a instantaneous response time. This
command is the faster option than via pin DATA at the cost of an additional connection
to the microcontroller.
Figure 21. Timing Diagram of the OFF-command via Pin DATA
t1
t2
t3
t5
t4 t10
t7
Out1 (microcontroller)
DATA (U3742BM)
X
Serial bi-directional
data line
X
Bit 1
("1")
(Startbit)
Receiving
mode
TSleep
Startup mode
OFF command
18
U3742BM
4735A–RKE–11/03
U3742BM
Figure 22. Timing Diagram of the OFF-command via Pin ENABLE
TSleep
TDoze
toff
ENABLE
DATA (U3742BM)
X
Serial bi-directional
data line
X
Receiving mode
Configuration of the
Receiver
Startup mode
The U3742BM receiver is configured via two 12-bit RAM registers called OPMODE and
LIMIT. The registers can be programmed by means of the bi-directional DATA port. If
the register contents have changed due to a voltage drop, this condition is indicated by a
certain output pattern called reset marker (RM). The receiver must be reprogrammed in
that case. After a power-on reset (POR), the registers are set to default mode. If the
receiver is operated in default mode, there is no need to program the registers.
Table 3 on page 20 shows the structure of the registers. According to Table 2, bit 1
defines if the receiver is set back to polling mode via the OFF command, (see section
“Receiving Mode” on page 16) or if it is programmed. Bit 2 represents the register
address. It selects the appropriate register to be programmed.
Table 2. Effect of Bit 1 and Bit 2 in Programming the Registers
Bit 1
Bit 2
1
x
Action
The receiver is set back to polling mode (OFF command)
0
1
The OPMODE register is programmed
0
0
The LIMIT register is programmed
Table 4 on page 20 and the following illustrate the effect of the individual configuration
words. The default configuration is highlighted for each word.
BR_Range sets the appropriate baud rate range. At the same time it defines XLim. XLim
is used to define the bit check limits TLim_min and TLim_max as shown in Table 4 on page
20.
19
4735A–RKE–11/03
Table 3. Effect of the Configuration Words within the Registers
Bit 1 Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
OFF Command
1
OPMODE Register
0
1
0
1
BR_Range
NBitcheck
VPOUT
Sleep
XSleep
Baud1
Baud0
BitChk1
BitChk0
POUT
Sleep4
Sleep3
Sleep2
Sleep1
Sleep0
XSleep Std
XSleep Temp
0
0
1
0
0
0
1
0
1
1
0
0
(Default)
LIMIT Register
0
0
0
0
Lim_min
Lim_max
Lim_min5 Lim_min4 Lim_min3 Lim_min2 Lim_min1 Lim_min0 Lim_max5 Lim_max4 Lim_max3 Lim_max2 Lim_max1 Lim_max0
(Default)
0
0
1
1
1
0
0
1
1
0
0
0
Table 4. Effect of the Configuration Word BR_Range
BR_Range
Baud1
Baud0
Baud Rate Range/Extension Factor for Bit Check Limits (XLim)
0
0
BR_Range0 (application USA/Europe: BR_Range0 = 1.0 kBaud to 1.8 kBaud) (Default)
XLim = 8 (Default)
0
1
BR_Range1 (application USA/Europe: BR_Range1 = 1.8 kBaud to 3.2 kBaud)
XLim = 4
1
0
BR_Range2 (application USA/Europe: BR_Range2 = 3.2 kBaud to 5.6 kBaud)
XLim = 2
1
1
BR_Range3 (Application USA/Europe: BR_Range3 = 5.6 kBaud to 10 kBaud)
XLim = 1
Table 5. Effect of the Configuration Word NBitcheck
NBitcheck
BitChk1
BitChk0
Number of Bits to be Checked
0
0
0
0
1
3
1
0
6 (Default)
1
1
9
Table 6. Effect of the Configuration Bit Reserved
Reserved Bit
No Function (Reserved for Future Use)
0
(Default)
1
20
U3742BM
4735A–RKE–11/03
U3742BM
Table 7. Effect of the Configuration Word Sleep
Sleep
Sleep4
Sleep3
Sleep2
Sleep1
Sleep0
Start Value for Sleep Counter
(TSleep = Sleep × Xsleep × 1024 × TClk)
0
0
0
0
0
0 (Receiver is continuously polling until a valid signal occurs)
0
0
0
0
1
1 (TSleep » 2ms for XSleep = 1 in US/European applications)
0
0
0
1
0
2
0
0
0
1
1
3
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
0
1
0
1
1
11 (USA: TSleep = 22.96 ms, Europe: TSleep = 23.31 ms) (Default)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
0
1
29
1
1
1
1
0
30
1
1
1
1
1
31 (Permanent sleep mode)
Table 8. Effect of the Configuration Word XSleep
XSleep
XSleepStd
XSleepTemp
Extension Factor for Sleep Time (TSleep = Sleep × Xsleep × 1024 × TClk)
0
0
1 (Default)
0
1
8 (XSleep is reset to 1 if bit check fails once)
1
0
8 (XSleep is set permanently)
1
1
8 (XSleep is set permanently)
Table 9. Effect of the Configuration Word Lim_min
Lim_min
Lower Limit Value for Bit Check
Lim_min < 10 is not applicable
(TLim_min = Lim_min × XLim × TClk)
0
0
1
0
1
0
10
0
0
1
0
1
1
11
0
0
1
1
0
0
12
0
0
1
1
0
1
13
0
0
1
1
1
0
14 (Default)
(USA: TLim_min = 228 µs, Europe: TLim_min = 232 µs)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
0
1
61
1
1
1
1
1
0
62
1
1
1
1
1
1
63
21
4735A–RKE–11/03
Table 10. Effect of the Configuration Word Lim_max
Lim_max
Upper Limit Value for Bit Check
Lim_max < 12 is not applicable
(TLim_max = (Lim_max - 1) × XLim × TClk)
0
0
1
1
0
0
12
0
0
1
1
0
1
13
0
0
1
1
1
0
14
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
0
1
1
0
0
0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
0
1
61
1
1
1
1
1
0
62
1
1
1
1
1
1
63
Conservation of the Register
Information
24 (Default)
(USA: TLim_max = 375 µs, Europe: TLim_max = 381 µs)
The U3742BM has an integrated power-on reset (POR) and brown-out detection circuitry to provide a mechanism to preserve the RAM register information.
According to Figure 23, a power-on reset is generated if the supply voltage VS drops
below the threshold voltage VThReset. The default parameters are programmed into the
configuration registers in that condition. Once VS exceeds VThReset, the POR is canceled
after the minimum reset period tRst. A POR is also generated when the supply voltage of
the receiver is turned on.
To indicate that condition, the receiver displays a reset marker (RM) at pin DATA after a
reset. The RM is represented by the fixed frequency fRM at a 50% duty cycle. RM can be
canceled via an 'L' pulse t1 at pin DATA. The RM implies the following characteristics:
•
fRM is lower than the lowest feasible frequency of a data signal. This means, RM
cannot be misinterpreted by the connected microcontroller.
•
If the receiver is set back to polling mode via pin DATA, RM cannot be cancelled by
accident if t1 is applied according to the proposal in the section “Programming the
Configuration Register” on page 23.
By means of that mechanism, the receiver cannot lose its register information without
communicating that condition via the reset marker RM.
Figure 23. Generation of the Power-on Reset
VS
VThReset
POR
tRst
DATA (U3742BM)
X
1/fRM
22
U3742BM
4735A–RKE–11/03
U3742BM
Figure 24. Timing of the Register Programming
t1
t2
t3
t5
t4
t9
TSleep
t8
t6
t7
Out1
(microcontroller)
DATA (U3742BM)
X
Serial bi-directional
data line
X
Receiving
mode
Programming the
Configuration Register
Bit 1
("0")
(Startbit)
Bit 2
("1")
(Registerselect)
Programming frame
Bit 13
("0")
(Poll8)
Bit 14
("1")
(Poll8R)
Startup
mode
The configuration registers are programmed serially via the bi-directional data line
according to Figure 24 and Figure 25.
Figure 25. One-wire Connection to a Microcontroller
U3742BM
Microcontroller
Internal pull-up
resistor
Bi-directional
data line
DATA
Data
(U3742BM)
I/O
Out 1 (microcontroller)
To start programming, the serial data line DATA is pulled to 'L' for the time period t1 by
the microcontroller. When DATA has been released, the receiver becomes the master
device. When the programming delay period t2 has elapsed, it emits 14 subsequent synchronization pulses with the pulse length t3. After each of these pulses, a programming
window occurs. The delay until the program window starts is determined by t4, the duration is defined by t5. Within the programming window, the individual bits are set. If the
microcontroller pulls down pin DATA for the time period t7 during t5, the bit is set to '0'. If
no programming pulse t7 is issued, this bit is set to '1'. All 14 bits are subsequently programmed in this way. The time frame to program a bit is defined by t6.
Bit 14 is followed by the equivalent time window t9. During this window, the equivalent
acknowledge pulse t8 (E_Ack) occurs if the just programmed mode word is equivalent to
the mode word that was already stored in that register. E_Ack should be used to verify
that the mode word was correctly transferred to the register. The register must be programmed twice in that case.
Programming of a register is possible both during sleep and active mode of the receiver.
23
4735A–RKE–11/03
During programming, the LNA, LO, low-pass filter, IF-amplifier and the FSK/ASK
Manchester demodulator are disabled.
The programming start pulse t1 initiates the programming of the configuration registers.
If bit 1 is set to '1', it represents the OFF-command to set the receiver back to polling
mode at the same time. For the length of the programming start pulse t1, the following
convention should be considered:
•
t1(min) < t1 < 1535 ´ TClk: [t1(min) is the minimum specified value for the relevant
BR_Range]
Programming (respectively OFF-command) is initiated if the receiver is not in reset
mode. If the receiver is in reset mode, programming (respectively Off-command) is not
initiated, and the reset marker RM is still present at pin DATA.
This period is generally used to switch the receiver to polling mode. In a reset condition,
RM is not canceled by accident.
•
t1 > 5632 ´ TClk
Programming (respectively OFF-command) is initiated in any case. RM is canceled if
present.
This period is used if the connected microcontroller detected RM. If a configuration register is programmed, this time period for t 1 can generally be used. Note that the
capacitive load at pin DATA is limited. The resulting time constant t together with an
optional external pull-up resistor may not be exceeded to ensure proper operation.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Power dissipation
Symbol
Min.
Max.
Unit
Ptot
450
mW
Junction temperature
Tj
150
°C
Storage temperature
Tstg
-55
+125
°C
Ambient temperature
Tamb
-40
+105
°C
10
dBm
Maximum input level, input matched to 50 W
Pin_max
Thermal Resistance
Parameters
Junction ambient
24
Symbol
Value
Unit
RthJA
100
K/W
U3742BM
4735A–RKE–11/03
U3742BM
Electrical Characteristics
All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5 V, Tamb = 25°C)
Parameter
Test Condition
Symbol
6.76438 Mhz Oscillator
(Mode 1)
4.90625 Mhz Oscillator
(Mode 0)
Min.
Min.
Typ.
Max.
Typ.
Max.
Variable Oscillator
Min.
Typ.
Max.
Unit
Basic Clock Cycle of the Digital Circuitry
Basic clock
cycle
MODE = 0 (USA)
MODE = 1 (Europe)
Extended
basic clock
cycle
BR_Range0
BR_Range1
BR_Range2
BR_Range3
2.0383
1/(fXTO/10)
1/(fXTO/14)
µs
µs
TXClk
16.6
8.3
4.1
2.1
16.3
8.2
4.1
2.0
8 ´ TClk
4 ´ TClk
2 ´TClk
1 ´ TClk
µs
µs
µs
µs
TSleep
Sleep ´
XSleep ´
1024 ´
2.0697
Sleep ´
XSleep ´
1024 ´
2.0383
Sleep ´
XSleep ´
1024 ´
TClk
ms
1855
1061
1061
663
1827
1045
1045
653
896.5
512.5
512.5
320.5
´ TClk
0.45
0.24
0.14
0.14
0.47
0.26
0.16
0.15
TClk
2.0697
Polling Mode
Sleep time
Start-up time
Time for Bit
Check
Sleep and XSleep
are defined in the
OPMODE register
BR_Range0
BR_Range1
BR_Range2
BR_Range3
TStartup
Average bit check
time while polling
BR_Range0
BR_Range1
BR_Range2
BR_Range3
TBitcheck
Bit check time for a
valid input signal fSig
NBitcheck = 0
NBitcheck = 3
NBitcheck = 6
NBitcheck = 9
TBitcheck
3/fSig
6/fSig
9/fSig
3.5/fSig
6.5/fSig
9.5/fSig
3/fSig
6/fSig
9/fSig
µs
µs
µs
µs
ms
ms
ms
ms
3.5/fSig
6.5/fSig
9.5/fSig
TXClk
3/fSig
6/fSig
9/fSig
TXClk
3.5/fSig
6.5/fSig
9.5/fSig
ms
ms
ms
ms
Receiving Mode
Intermediate
frequency
Baud rate
range
Minimum time
period
between
edges at
pin DATA
(Figure 19 on
page 17)
MODE=0 (USA)
MODE=1 (Europe)
BR_Range0
BR_Range1
BR_Range2
BR_Range3
BR_Range0
BR_Range1
BR_Range2
BR_Range3
fIF
1.0
1.0
BR_Range
TDATA_min
tmin1
tmin2
tmin1
tmin2
tmin1
tmin2
tmin1
tmin2
1.8
3.2
5.6
10.0
1.0
1.8
3.2
5.6
149
182
75
91
37.3
45.5
18.6
22.8
1.0
1.8
3.2
5.6
1.8
3.2
5.6
10.0
147
179
73
90
36.7
44.8
18.3
22.4
fXTO ´ 64/314
fXTO ´ 64/432.92
MHz
MHz
BR_Range0 ´ 2 µs/TClk
BR_Range1 ´ 2 µs/TClk
BR_Range2 ´ 2 µs/TClk
BR_Range3 ´ 2 µs/TClk
kBaud
kBaud
kBaud
kBaud
9 ´ TXClk
11 ´ TXCl
9 ´ TXClk
11 ´ TXClk
9 ´ TXClk
11 ´ TXClk
9 ´ TXClk
11 ´ TXClk
µs
µs
µs
µs
µs
µs
µs
25
4735A–RKE–11/03
Electrical Characteristics (Continued)
All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5 V, Tamb = 25°C)
Parameter
Test Condition
BR_Range0
Maximum low
BR_Range1
period at DATA
BR_Range2
(Figure 20)
BR_Range3
OFF
command at
pin ENABLE
(Figure 22)
Symbol
6.76438 Mhz Oscillator
(Mode 1)
4.90625 Mhz Oscillator
(Mode 0)
Min.
Min.
Max.
2169
1085
542
271
TDATA_L_max
tDoze
Typ.
Typ.
Max.
Variable Oscillator
Min.
3.1
Typ.
Max.
131 ´ TXClk
131 ´ TXClk
131 ´ TXClk
131 ´ TXClk
2136
1068
534
267
µs
µs
µs
µs
1.5 ´
TClk
3.05
Unit
µs
Configuration of the Receiver
Frequency of
the reset
marker
(Figure 23)
Programming
start pulse
(Figure 21,
Figure 24)
117.9
fRM
1
--------------------------------4096 ´ T CLK
119.8
BR_Range0
2188
3176
2155
3128
BR_Range1
1104
3176
1087
3128
561
3176
553
3128
290
3176
286
3128
BR_Range2
t1
BR_Range3
after POR
11656
11479
1057 ´
TClk
533 ´
TClk
271 ´
TClk
140 ´
TClk
5632 ´
TClk
Hz
1535 ´
TClk
1535 ´
TClk
1535 ´
TClk
1535 ´
TClk
µs
Programming
delay period
(Figure 21,
Figure 24)
t2
Synchronization pulse
(Figure 21,
Figure 24)
t3
265
261
128 ´ TClk
µs
Delay until the
program
window starts
(Figure 21,
Figure 24)
t4
131
129
63.5 ´ TClk
µs
Programming
window
(Figure 21,
Figure 24)
t5
530
522
256 ´ TClk
µs
Time frame
of a bit
(Figure 24)
t6
1060
1044
512 ´ TClk
µs
Programming
pulse (Figure
21, Figure 24)
t7
26
795
133
798
529
783
131
786
521
384.5 ´
TClk
64 ´
TClk
385.5 ´
TClk
256 ´
TClk
µs
µs
U3742BM
4735A–RKE–11/03
U3742BM
Electrical Characteristics (Continued)
All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5 V, Tamb = 25°C)
Parameter
Test Condition
Symbol
6.76438 Mhz Oscillator
(Mode 1)
4.90625 Mhz Oscillator
(Mode 0)
Min.
Min.
Typ.
Max.
Typ.
Max.
Variable Oscillator
Min.
Typ.
Max.
Unit
Equivalent
acknowledge
pulse: E_Ack
(Figure 24)
t8
265
261
128 ´ TClk
µs
Equivalent
time window
(Figure 24)
t9
534
526
258 ´ TClk
µs
OFF-bit
programming
window
(Figure 21)
t10
930
916
449.5 ´ TClk
µs
Electrical Characteristics
All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5 V, Tamb = 25°C)
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Sleep mode
(XTO and polling logic active)
ISoff
190
350
µA
IC active
(startup-, bit check-, receiving mode)
pin DATA = H
ISon
7.0
8.6
mA
Third-order intercept point
LNA/mixer/IF amplifier
input matched according to Figure 6
IIP3
-28
LO spurious emission at RFIn
Input matched according to Figure 6,
required according to I-ETS 300220
ISLORF
-73
Noise figure LNA and mixer (DSB)
Input matching according to Figure 6
NF
7
dB
LNA_IN input impedance
at 433.92 MHz
at 315 MHz
ZiLNA_IN
1.0 || 1.56
1.3 || 1.0
kW || pF
kW || pF
1 dB compression point
(LNA, mixer, IF amplifier)
Input matched according to Figure 6,
referred to RFin
IP1db
-40
dBm
Maximum input level
Input matched according to Figure 6,
BER £ 10-3,
ASK mode
Pin_max
Current consumption
LNA Mixer
dBm
-57
dBm
-28
-20
dBm
dBm
449
MHz
-93
-113
-90
-110
dBC/Hz
dBC/Hz
-55
-47
dBC
Local Oscillator
Operating frequency range VCO
fVCO
Phase noise VCO/LO
fosc = 432.92 MHz
at 1 MHz
at 10 MHz
Spurious of the VCO
at ±fXTO
VCO gain
L (fm)
KVCO
299
190
MHz/V
27
4735A–RKE–11/03
Electrical Characteristics (Continued)
All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5 V, Tamb = 25°C)
Parameters
Test Conditions
Loop bandwidth of the PLL
For best LO noise
(design parameter)
R1 = 820 W
C9 = 4.7 nF
C10 = 1 nF
BLoop
Capacitive load at pin LF
The capacitive load at pin LF is limited
if bit check is used. The limitation
therefore also applies to self-polling.
CLF_tot
XTO operating frequency
XTO crystal frequency,
appropriate load capacitance must be
connected to XTAL
6.764375 MHz
Symbol
fXTO
4.90625 MHz
Series resonance resistor of the
crystal
fXTO = 6.764 MHz
4.906 MHz
Static capacitance of the crystal
Min.
Typ.
Max.
100
Unit
kHz
10
6.764375 6.764375 6.764375
-30 ppm
+30 ppm
4.90625 4.90625 4.90625
-30 ppm
+30 ppm
nF
MHz
MHz
RS
150
220
W
W
Cxto
6.5
pF
Analog Signal Processing
Input sensitivity ASK
Input sensitivity ASK
Input matched according to Figure 6
ASK (level of carrier)
BER £ 10-3, fIF = 1 MHz
fin = 433.92 MHz/315 MHz
T = 25°C, VS = 5 V
PRef_ASK
BR_Range0
-108
-110
-112
dBm
BR_Range1
-106.5
-108.5
-110.5
dBm
BR_Range2
-106
-108
-110
dBm
BR_Range3
-104
-106
-108
dBm
+2.5
-1.5
dB
+5.5
+7.5
-1.5
-1.5
dB
dB
Sensitivity variation ASK for the full
operating range compared to
Tamb = 25°C, VS = 5 V
fin = 433.92 MHz/315 MHz
fIF = 1 MHz
PASK = PRef_ASK + DPRef
DPRef
Sensitivity variation ASK for full
operating range including IF filter
compared to Tamb = 25°C, VS = 5 V
fin = 433.92 MHz/315 MHz
fIF = 0.79 MHz to 1.21 MHz
fIF = 0.73 MHz to 1.27 MHz
PASK = PRef_ASK + DPRef
DPRef
Input sensitivity FSK
Input matched according to Figure 6,
BER £ 10-3, fIF = 1 MHz
fin = 433.92 MHz/315 MHz
T = 25°C, VS = 5 V
Input sensitivity FSK
28
PRef_FSK
BR_Range0
df ³ ±20 kHz
df ³ ±30 kHz
-95.5
-96.5
-97.5
-98.5
-99.5
-100.5
dBm
dBm
BR_Range1
df ³ ±20 kHz
df ³ ±30 kHz
-94.5
-95.5
-96.5
-97.5
-98.5
-99.5
dBm
dBm
U3742BM
4735A–RKE–11/03
U3742BM
Electrical Characteristics (Continued)
All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5 V, Tamb = 25°C)
Parameters
Test Conditions
Symbol
Min.
Sensitivity variation FSK for the full
operating range compared to
Tamb = 25°C, VS = 5 V
fin = 433.92 MHz/315 MHz
fIF = 1 MHz
PFSK = PRef_FSK + DPRef
DPRef
Sensitivity variation FSK for full
operating range including IF filter
compared to Tamb = 25°C, VS = 5 V
fin = 433.92 MHz/315 MHz
fIF = 0.86 MHz to 1.14 MHz
fIF = 0.82 MHz to 1.18 MHz
PFSK = PRef_FSK + DPRef
FSK frequency deviation
The sensitivity of the receiver is higher
for higher values of DfFSK
BR_Range0
BR_Range1
BR_Range2 and BR_Range3 are not
suitable for FSK operation
S/N ratio to suppress inband noise
signals
ASK mode
FSK mode
Max.
Unit
+2.5
-1.5
dB
DPRef
+5.5
+7.5
-1.5
-1.5
dB
dB
DfFSK
20
20
50
50
kHz
kHz
SNRASK
SNRFSK
10
2
12
3
dB
dB
DRRSSI
Dynamic range RSSI amplifier
Lower cut-off frequency of the data
filter
1
f cu_DF = ----------------------------------------------------------2 ´ p ´ 30 k W ´ CDEM
Recommended CDEM for best
performance
ASK mode
BR_Range0 (Default)
BR_Range1
BR_Range2
BR_Range3
CDEM
Recommended CDEM for best
performance
FSK mode
BR_Range0 (Default)
BR_Range1
BR_Range2 and BR_Range3 are not
suitable for FSK operation
CDEM
BR_Range0 (Default)
Maximum edge-to-edge time period of BR_Range1
the input data signal for full sensitivity BR_Range2
BR_Range3
Upper cut-off frequency data filter
Upper cut-off frequency programmable
in 4 ranges via a serial mode word
BR_Range0 (Default)
BR_Range1
BR_Range2
BR_Range3
BR_Range0 (Default)
Minimum edge-to-edge time period of BR_Range1
the input data signal for full sensitivity BR_Range2
BR_Range3
Reduced sensitivity
RSense connected from pin Sens to VS,
input matched according to Figure 6
fcu_DF
Typ.
30
30
60
0.11
0.16
tee_sig
PRef_Red
2.5
4.3
7.6
13.6
0.20
kHz
39
22
12
8.2
nF
nF
nF
nF
27
15
nF
nF
tee_sig
fu
dB
3.1
5.4
9.5
17.0
1000
560
320
180
µs
µs
µs
µs
3.7
6.5
11.4
20.4
kHz
kHz
kHz
kHz
270
156
89
50
µs
µs
µs
µs
dBm
(peak
level)
29
4735A–RKE–11/03
Electrical Characteristics (Continued)
All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5 V, Tamb = 25°C)
Parameters
Reduced sensitivity
Reduced sensitivity variation over full
operating range
Test Conditions
Min.
Typ.
Max.
Unit
(VS = 5 V, Tamb = 25°C)
RSense = 56 kW, fin = 433.92 MHz,
-67
-72
-77
dBm
RSense = 100 kW, fin = 433.92 MHz
-76
-81
-86
dBm
RSense = 56 kW, fin = 315 MHz
-68
-73
-78
dBm
RSense = 100 kW, fin = 315 MHz
-77
-82
-87
dBm
5
6
0
0
0
0
dB
dB
RSense = 56 kW
RSense = 100 kW
PRed = PRef_Red + DPRed
Symbol
DPRed
Values relative to
RSense = 56 kW
Reduced sensitivity variation for
different values of RSense
RSense = 56 kW
RSense = 68 kW
RSense = 82 kW
RSense = 100 kW
RSense = 120 kW
RSense = 150 kW
PRed = PRef_Red + DPRed
Threshold voltage for reset
DPRed
VThRESET
dB
dB
dB
dB
dB
dB
0
-3.5
-6.0
-9.0
-11.0
-13.5
1.95
2.8
3.75
V
39
0.08
50
0.3
61
2.5
41
540
V
kW
µs
pF
pF
0.2 ´ VS
V
V
0.2 ´ VS
V
V
0.2 ´ VS
V
V
0.2 ´ VS
V
Digital Ports
Data output
- Saturation voltage LOW
- Internal pull-up resistor
- Maximum time constant
- Maximum capacitive load
Iol = 1 mA
t = CL (Rpup//RExt)
without external pull-up resistor
Rext = 5 kW
VOI
RPup
t
CL
CL
FSK/ASK input
- Low-level input voltage
- High-level input voltage
FSK selected
ASK selected
VIl
VIh
0.8 ´ VS
ENABLE input
- Low-level input voltage
- High-level input voltage
Idle mode
Active mode
VIl
VIh
0.8 ´ VS
MODE input
- Low-level input voltage
- High-level input voltage
Division factor = 10
Division factor = 14
VIl
VIh
0.8 ´ VS
TEST input
- Low-level input voltage
30
Test input must always be set to LOW
VIl
U3742BM
4735A–RKE–11/03
U3742BM
Ordering Information
Extended Type Number
Package
Remarks
U3742BM-M3FL
SO20
Tube
U3742BM-M3FLG3
SO20
Taped and reeled
Package Information
9.15
8.65
Package SO20
Dimensions in mm
12.95
12.70
7.5
7.3
2.35
0.25
0.25
0.10
0.4
10.50
10.20
1.27
11.43
20
11
technical drawings
according to DIN
specifications
1
10
31
4735A–RKE–11/03
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4735A–RKE–11/03