TI UCD9080RHBR

UCD9080
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SLVS692A – SEPTEMBER 2006 – REVISED DECEMBER 2006
8-CHANNEL POWER SUPPLY SEQUENCER AND MONITOR
FEATURES
APPLICATIONS
•
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•
•
•
•
•
•
•
•
•
•
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Telecommunications Switches
Servers
Networking Equipment
Test Equipment
Any System Requiring Sequencing of Multiple
Voltage Rails
DESCRIPTION
The UCD9080 Power Supply Sequencer controls the
enable sequence of up to 8 independent voltage rails
and provides four general purpose digital outputs.
The device operates from a 3.3-V supply, provides
3.2-mV resolution of voltage rails, and requires no
external memory or clock. The UCD9080 monitors
the voltage rails independently at more than a 20
kHz rate and has a high degree of rail sequence and
rail error response configurability. The sequencing of
rails can be based on timed events, or timed events
in conjunction with other rails achieving regulation or
a voltage threshold. In addition, each rail is
monitored for undervoltage and overvoltage glitches
and thresholds. Each rail the UCD9080 monitors can
be configured to shutdown a user-defined set of
other rails, and alarm conditions are monitored on a
per-rail basis.
Figure 1 shows the UCD9080 Power Supply
Sequencer in a typical application
MON [1:8]
VOUT1
10 kW
3.3 V
EN [1:7]
RST
0.01 mF
3.3 V
Power
Supply
EN
1
XIN
VOUT2
TEST
UCD 9080
100 kW
3.3 V
EN
VCC
ROSC
10 kW
3.3 V
3.3 V
Power
Supply
2
1 mF
SCL
10 kW
3.3 V
SDA
EN8/
ADDR1/
GPO1
2
To I C
Master Device
VSS
ADDR2/ ADDR3/
GPO3
GPO2
VOUTX
ADDR4/
GPO4
3.3 V
2
Slave I C
Address
A1
A2
A3
A4
Power
Supply
EN
X
Digital
Outputs
Figure 1. Typical Application Diagram
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320 is a trademark of Texas Instruments.
Microsoft Windows is a trademark of Microsoft Corporation.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2006, Texas Instruments Incorporated
PRODUCT PREVIEW
•
Single Supply Voltage: 3.3 V
Low Power Consumption
Sequences and Monitors up to 8 Voltage Rails
Rail Voltages Sampled Every 50 µs With
3.2-mV Resolution
Four Configurable Digital Outputs for
Power-On-Reset and Other Functions
Configurable Rail Enable Output Polarity
Flexible Rail Sequencing: Timeline (ms),
Parent Rail Regulation Window, Parent Rail
Achieving Defined Threshold
Under and Overvoltage Thresholds: Settable
Per-Rail
Regulation Expiration Time: Settable Per-Rail
Flexible Rail Shutdown: Parent Rail Shutdown
can Shutdown Child Rails, Independent Rail
Configuration
Per-Rail Alarm Conditions, with Timestamp:
Under and Overvoltage Glitch, Sustained
Under and/or Overvoltage, Rail Did Not Start
I2C Interface for Configuration and Monitoring
Microsoft Windows™ GUI for Configuration
and Monitoring
UCD9080
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SLVS692A – SEPTEMBER 2006 – REVISED DECEMBER 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
PACKAGED DEVICES
(2)
MSOP SYMBOL
UCD9080RHBR
–40°C to 85°C
(1)
(1) (2)
RHB
UCD9080RHBT
The package is available taped and reeled. Add the R suffix for reeled quantities. Add the T suffix for
taped quantities.
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Voltage applied at VCC to VSS
Voltage applied to any
pin (2)
VALUE
UNIT
–0.3 to 4.1
V
–0.3 to VCC + 0.3
V
±2
mA
–40 to 85
°C
Diode current at any device terminal
PRODUCT PREVIEW
Tstg
(1)
(2)
Storage temperature
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS.
RECOMMENDED OPERATING CONDITIONS
VCC
TA
MIN
NOM
MAX
Supply voltage during operation
3
3.3
3.6
Supply during configuration changes
3
3.3
3.6
Operating free-air temperature range
–40
UNIT
V
°C
85
ELECTRICAL CHARACTERISTICS
These specifications are over recommended ranges of supply voltage and operating free-air temperature, unless otherwise
noted
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
300
350
µA
3
7
mA
SUPPLY CURRENT
IS
Supply current into VCC excluding external
current
VCC = 3 V
IC
Supply current during configuration
2.5 V / 3.6 V
STANDARD INPUTS (RST, TEST)
VIL
Low-level input voltage
VCC = 3 V
VSS
VSS +0.6
V
VIH
High-level input voltage
VCC = 3 V
0.8×VCC
VCC
V
SCHMITT TRIGGER INPUTS (SDA, SCL, ADDR1, ADDR2, ADDR3, ADDR4)
VIT+
Positive-going input threshold voltage
VCC = 3 V
1.5
1.9
V
VIT–
Negative-going input threshold voltage
VCC = 3 V
0.9
1.3
V
Vhys
Input voltage hysteresis, (VIT+– VIT–)
VCC = 3 V
0.5
1
V
High impedance leakage current
RST, TEST, SDA, SCL, ADDR1, ADDR2,
ADDR3, ADDR4
±50
nA
Ilkg
2
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ELECTRICAL CHARACTERISTICS (continued)
These specifications are over recommended ranges of supply voltage and operating free-air temperature, unless otherwise
noted
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
ANALOG INPUTS (MON1, MON2, MON3, MON4, MON5, MON6, MON7, MON8, ROSC)
Analog supply voltage
VCC(min)
VCC minimum voltage when sampling
VSS = 0 V
1.8
0
2.5
External voltage reference
(VCC = 3.3 V used as reference)
0
VCC
Analog input voltage
CI (1)
Input capacitance
Only one terminal can be selected at a time
(MON1–MON8)
RI(1)
Input MUX ON resistance
0 V ≤ VAx ≤ VCC, VCC = 3 V
Ilkg
High-impedance leakage current
MON1–MON8
Positive internal reference voltage output
VCC minimum voltage, Positive built-in
reference active
V(acc)
Accuracy of voltage sampling from rails
TREF+(1)
Temperature coefficient of built-in
reference
27
V
pF
2000
Ω
±50
nA
REF2_5V = 1 for 2.5 V
I(VREF+) ≤ I(VREF+)max
VCC = 3 V
2.35
2.5
2.65
V
REF2_5V = 0 for 1.5 V
I(VREF+) ≤ I(VREF+)max
VCC = 3 V
1.41
1.5
1.59
V
REF2_5V = 0, I(VREF+) ≤ 1 mA
VCC(min)
V
V
Internal voltage reference
V(R<1..8>)
VREF+
3.6
2.35
2.2
V
REF2_5V = 1, I(VREF+) ≤ 0.5 mA
VREF+ + 0.15
V
REF2_5V = 1, I(VREF+) ≤ 1 mA
VREF+ + 0.15
V
Internal reference (2.5 V)
±6.8
±12
±17.4
External reference (3.3 V/VCC)
±0.2
±1.6
±6.8
I(VREF+) is a constant in the range of
0 mA ≤ I(VREF+)≤ 1 mA, VCC = 3 V
PRODUCT PREVIEW
VCC
mV
±100
ppm/°C
185
nS
DCO OPERATING PERIOD
t(PERIOD)
VCC = 3 V, TA = 25°C, ROSC = 100 kΩ
227
TJ = 25°C
100
204
MISCELLANEOUS
Tretention
Retention of configuration parameters
POR, Brownout, Reset (see
Years
(2) (3))
td(BOR)
2000
VCC(start)
V(B_IT–)
0.7×V(B_IT-)
Brownout
dVCC/dt ≤ 3 V/s
Vhys(B_IT–)
70
Pulse length needed at RST pin to accept
reset internally, VCC = 3 V
t(reset)
130
µs
V
1.71
V
180
mV
µs
2
DIGITAL OUTPUTS (EN8/GPO1, GPO2, GPO3, GPO4, EN1, EN2, EN3, EN4, EN5, EN6, EN7, SDA)
VOH
High-level output voltage
VOL
VOL Low-level output voltage
Ilkg
High-impedance leakage current
(1)
(2)
(3)
(4)
(5)
IOH(max) = –1.5 mA, (4) VCC = 3 V
IOH(max) = –6 mA, (5) VCC = 3 V
IOH(max)= –1.5 mA, (4) VCC = 3 V
IOH(max) = –6
mA, (5)
VCC = 3 V
VCC = 3 V
VCC – 0.25
VCC
VCC – 0.6
VCC
VSS
VSS + 0.25
VSS
VSS + 0.6
±50
V
V
nA
Not production tested. Limits verified by design.
The current consumption of the brown-out module is already included in the ICC current consumption data.
During power up, device initialization starts following a period of td(BOR) after VCC = V(B_IT–) + Vhys(B_IT–).
The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop
specified.
The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
The UCD9080 is compatible with 3.3-V IO ports of microcontrollers, TMS320™ DSP Family as well as ASICs.
The UCD9080 is available in a plastic 32-pin QFN package (RHB).
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SLVS692A – SEPTEMBER 2006 – REVISED DECEMBER 2006
DIGITAL OUTPUTS (only one output is loaded at a time)
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
50
0
VCC = 3 V
P1.0
PRODUCT PREVIEW
IOH − Typical High-Level Output Current − mA
IOL − Typical Low-Level Output Current − mA
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
o
TA = 25 C
40
TA = 85oC
30
20
10
0
VCC = 3 V
P1.0
-10
-20
-30
-40
-50
-60
0
0.5
1
1.5
2
2.5
3
3.5
o
TA = 85 C
TA = 25oC
0
0.5
1
1.5
2.5
3
VOL − Low-Level Output Voltage − V
VOH − High-Level Output Voltage − V
Figure 2.
Figure 3.
VCC
Vhys(B_IT-)
V(B_IT-)
VCC(start)
1
Set signal for
POR circuitry
0
td(BOR)
Figure 4. POR/Brownout Reset (BOR) vs Supply Voltage
4
2
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UCD9080
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SLVS692A – SEPTEMBER 2006 – REVISED DECEMBER 2006
VCC
2
VCC = 3 V
Typical Conditions
tpw
3V
VCC(min) - V
1.5
1
VCC(min)
0.5
0
0.001
1000
1
1 ns
1 ns
tpw - Pulse Width - mS
tpw - Pulse Width - mS
Figure 5. VCC(min) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
2
tpw
3V
1.5
PRODUCT PREVIEW
VCC(min) - V
VCC = 3 V
Typical Conditions
1
VCC(min)
0.5
tfall = trise
0
0.001
1
tfall
1000
tpw - Pulse Width - mS
trise
tpw - Pulse Width - ms
Figure 6. VCC(min) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
I2C TIMING
The UCD9080 supports the same timing parameters as “Standard-Mode” I2C. See the timing diagram and timing
parameters below for more information.
SDA
tf
tLOW
tSU;DAT
tHD;STA
tr
tSP
tr
tBUF
SCL
tHIGH
tHD;STA
tHD;DAT
S
tSU;STA
tSU;STO
Sr
P
S
Figure 7. Timing Diagram for I2C Interface
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TIMING PARAMETERS FOR I2C INTERFACE
PARAMETER
(1)
MIN
ns
10
pF
100
kHz
Output fall time from VOH to VOL
CI
Capacitance for each pin.
fSCL
SCL Clock Frequency
tHD;STA
Hold time (repeated) START condition. After this period, the first clock pulse is generated.
4
µs
tLOW
LOW period of the SCL clock
4.7
µs
tHIGH
HIGH period of the SCL clock
4
µs
tSU;STA
Set-up time for repeated start condition
4.7
µs
tSU;DAT
Data set-up time
250
tr
Rise time of both SDA and SCL signals
1000
ns
tf
Fall time of both SDA and SCL signals
300
ns
tSU;STO
Set-up time for STOP condition
tBUF
Bus free time between a STOP and START condition
C(b)
Capacitive load for each bus line
VnL
Noise margin at the LOW level for each connected device (including hysteresis)
0.1 VDD
V
VnH
Noise margin at the HIGH level for each connected device (including hysteresis)
0.2 VDD
V
10
ns
µs
4
µs
4.7
400
pF
ROSC
NC
VCC
TEST
ADDR4/GPO4
ADDR3/GPO3
ADDR2/GPO2
EN8/ADDR1/GPO1
VSS
1 32
31
30
29
28
27
26
25 24
EN2
SCL
NC
4
21
SDA
RST
5
20
NC
MON1
6
19
MON5
MON2
7
18
MON4
MON3
8 9
10
11
12
13
14
15
17
16
MON8
22
MON7
3
EN7
XIN
EN6
EN1
EN5
23
EN3
2
EN4
NC
MON6
PRODUCT PREVIEW
See the Electrical Characteristics section of this data sheet.
The maximum tf for the SDA and SCL bus lines (300 ns) is longer than the specified maximum tof for the output stages (250 ns). This
allows series protection resistors (Rs) to be connected between the SDA/SCL pins and the SDA/SCL bus lines without exceeding the
maximum specified tf.
RHB PACKAGE
(TOP VIEW)
6
UNIT
250 (2)
tof
(1)
(2)
with a bus capacitance from 10 pF to 400 pF.
MAX
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UCD9080
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SLVS692A – SEPTEMBER 2006 – REVISED DECEMBER 2006
TERMINAL FUNCTIONS
NAME
NO.
I/O
DESCRIPTION
VSS
1
NC
2, 4,17,
20, 31
Ground reference
XIN
3
RST
5
I
Reset input.
MON1
6
I
Analog input for voltage rail 1.
MON2
7
I
Analog input for voltage rail 2.
MON3
8
I
Analog input for voltage rail 3.
MON6
9
I
Analog input for voltage rail 6.
EN4
10
O
Voltage rail 4 enable (digital output).
EN3
11
O
Voltage rail 3 enable (digital output).
EN5
12
O
Voltage rail 5 enable (digital output).
EN6
13
O
Voltage rail 6 enable (digital output).
EN7
14
O
Voltage rail 7 enable (digital output).
MON7
15
I
Analog input for voltage rail 7.
MON8
16
I
Analog input for voltage rail 8.
MON4
18
I
Analog input for voltage rail 4.
MON5
19
I
Analog input for voltage rail 5.
SDA
21
I/O
SCL
22
I
I2C clock. Must pull-up to 3.3 V.
EN1
23
O
Voltage rail 1 enable (digital output).
EN2
24
O
Voltage rail 2 enable (digital output).
EN8 /ADDR1/
GPO1
25
I/O
Voltage rail 8 enable (digital output), I2C address select 1, general-purpose digital output 1
ADDR2/GPO2
26
I/O
I2C address select 2, general-purpose digital output 2.
ADDR3/GPO3
27
I/O
I2C address select 3, general-purpose digital output 3.
ADDR4/GPO4
28
I/O
I2C address select 4, general-purpose digital output 4.
TEST
29
I
VCC
30
Supply voltage.
ROSC
32
Internal oscillator frequency adjust. Must use 100 K pull-up to VCC for minimum drift and maximum
frequency when sampling voltage rails.
Not connected internally. Connect to VSS.
Connect to VCC
PRODUCT PREVIEW
TERMINAL
I2C data (bi-directional). Must pull-up to 3.3 V.
Connect to VSS
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FUNCTIONAL BLOCK DIAGRAM
MON1
MON2
MON3
MON4
MON5
MON6
MON7
MON8
Oscillator
Analog
Inputs
Power
Enables
Sequencing
Engine
10-bit
SAR ADC
General
Purpose
Outputs
Config
Memory
Status
Registers
PRODUCT PREVIEW
I2C
Engine
SCL SDA
8
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EN1
EN2
EN3
EN4
EN5
EN6
EN7
EN8/GPO1
GPO2
GPO3
GPO4
UCD9080
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SLVS692A – SEPTEMBER 2006 – REVISED DECEMBER 2006
FUNCTIONAL DESCRIPTION
POWER SUPPLY SEQUENCING
The UCD9080 can be configured to sequence the power rails using the enable signals or the general-purpose
outputs in one of three ways:
The first way is to specify a delay time after a sequence event. A sequence event includes a device reset
(including power-on-reset), a RESET command, or a resequence action. The enable/GPO is asserted after the
sequence event plus specified delay.
The second way is to specify a delay time after another (parent) rail has achieved regulation (Vrail is within
specified under and overvoltage settings). The enable/GPO is asserted after the (parent) rail is in regulation plus
specified delay.
The third way is to specify a (parent) rail voltage. The enable/GPO is asserted after the (parent) rail voltage is
greater than or equal to the specified voltage.
Of course, a rail does not have to be sequenced. This could be used in the case of a backplane voltage which is
not under the control of the UCD9080, but is being monitored.
The UCD9080 can sequence and enable/disable up to 8 power supplies through the ENx (EN1 to EN8) signals
on the device. These signals can be configured for either active high or active low, to support power supplies
that use either polarity.
The enable signals for up to 8 power supplies can be sequenced by the UCD9080 as described below. Note that
the EN8 is used for I2C address selection, General-purpose output as well as the enable signal for the voltage
rail 8. This means that this signal is unavailable until the UCD9080 has selected its I2C address. If the system
requires the GPO1 signal, then this signal is not available for power supply enable sequencing.
The enable signals on the UCD9080 are not intended to drive the gate of N-channel MOSFET. These pins are
LVCMOS level only, providing the capability of driving either logic high or low (3.3 V or 0 V).
Note that while the UCD9080 is not operating, the state of the enable signals is not defined. If these signals
need to be defaulted to the disabled state, according to the power supply definition, then they should be pulled
up or down accordingly on the board.
VOLTAGE REFERENCE
The UCD9080 has a voltage reference that is selectable via the I2C interface and parameter configuration
section. The voltage reference can either be an internally generated 2.5-V reference or an external 3.3-V
reference. If the external voltage reference is selected, then the 3.3-V reference is from the VCC supply to the
UCD9080.
Depending on the voltage reference that is being used, the accuracy of reading voltages is affected. The internal
reference is not as accurate as the external reference and affects the accuracy of the sampled voltages of the
monitored rails. See the Electrical Characteristics for information on voltage reading accuracy for use with each
of the references.
The section on Configuring the UCD9080 details how to select the internal or external voltage reference.
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PRODUCT PREVIEW
POWER SUPPLY ENABLES
UCD9080
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SLVS692A – SEPTEMBER 2006 – REVISED DECEMBER 2006
FUNCTIONAL DESCRIPTION (continued)
VOLTAGE MONITORING
The UCD9080 can monitor 8 voltage rails through the MONx terminals of the device (MON1–MON8). The
UCD9080 samples these 8 input channels using either an internal 2.5-V reference or VCC (3.3 V) as a voltage
reference for conversion of the voltage to digital values, which are accessible via the I2C interface for each rail.
When monitoring a voltage rail that has a nominal voltage larger than 2.5 V (internal reference) or 3.3 V
(external reference), a resistor divider network is typically used. The design must ensure that the source
impedance of that resistor network is not too high, as it causes the UCD9080 A/D converter to take longer to
perform the sample and hold conversion. This causes the frequency of the sampling of voltage rails to slow
below 20 KHz
Using a higher-valued resistor network lowers the overall power dissipation of the solution, which is desirable. In
order to keep the source impedance low, a buffer circuit is typically used. The UCD9080 analog inputs require
that a source impedance of less than 20 kΩ be used in order to maintain the high sampling rate of the voltages.
The UCD9080 allows each monitored rail to specify over voltage threshold, under voltage threshold as well as
out of regulation width, to account for glitches on the voltage rails. Each rail can be specified as a critical rail,
which marks it to have its alarm error log copied to persistent memory on the UCD9080 for later failure analysis.
Any voltage rail can also be marked to not be monitored, in which case all checks and alarm conditions are
disabled.
PRODUCT PREVIEW
RAIL SHUTDOWN
Each rail that the UCD9080 supports can be shutdown for different reasons (sustained overvoltage or
undervoltage, rail did not start). The UCD9080 provides a configurable response to this type of scenario for each
rail that it is sequencing or monitoring,
The options for rail shutdown are as follows:
• Ignore
• Retry forever
• Re-sequence (immediate)
• Retry n times, then shutdown after user-specified delay
• Shutdown after user-specified delay
If the system does not care if a monitored rail enters a sustained error condition, the UCD9080 can be
configured to ignore this type of error on a voltage rail. The UCD9080 ignores the errors and keep monitoring
the voltage of this rail. In this event, the UCD9080 logs this error event, but takes no action.
The UCD9080 also allows a rail to be configured to retry enabling the rail continuously. When the UCD9080
detects that the rail should be shutdown, the rail is disabled, then there is a fixed 5-ms delay and then the rail is
re-enabled. This process repeats continuously for this voltage rail.
The UCD9080 can also be configured to re-sequence the entire system immediately in response to the
sustained error condition. In this event, the UCD9080 disables all rails, then it performs a re-sequencing of all
configured rails and GPOs, as defined by the current sequencer configuration after a fixed 5-ms delay.
The UCD9080 can also be configured to retry up to n times in response to the sustained error condition. If the
error condition still exists after sampling this many times, then this voltage rail (and any other rails specified in
the dependency mask) are shutdown in the specified number of milliseconds.
The last option that the UCD9080 allows is a shutdown of the configured rail (and its dependent rails) when
entering the sustained error condition. A rail is shutdown after a user-specified delay.
Each rail that the UCD9080 is monitoring also has a flag that marks the selected rail to re-sequence the system
if it happens to be a dependency of another rail in the system that was shut down. For example, if rail 1 is
configured to re-sequence after shutdown (re-sequence flag set), and rail 2 has rail 1 in its dependency mask,
then if rail 2 is shutdown, the system will be re-sequenced.
10
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FUNCTIONAL DESCRIPTION (continued)
GENERAL-PURPOSE OUTPUTS
The UCD9080 can control up to 4 general-purpose digital outputs through the same sequencing mechanisms as
described below. These general-purpose outputs (referred to as GPO1–GPO4) can be used for digital signals
such as RESET signals or LEDs on a board. Note that these signals are multiplexed with other functions
(primarily I2C address selection) so be sure to consult the pin functions section to make sure that these are used
properly by the application. Also note that the GPO1 signal is multiplexed with EN8, so both of these cannot be
used at the same time.
BROWNOUT
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off.
I2C INTERFACE
I2C Address Selection
The UCD9080 supports 7-bit I2C addressing. The UCD9080 supports selection of an I2C address by sampling of
4 digital inputs to the device (ADDR1–ADDR4) and selecting an I2C address, based on the digital state of each
of these signals. When the UCD9080 is released from reset, these four signals are sampled. Based on the state
of these four signals, the I2C slave address is assigned to the UCD9080 as shown in Figure 8.
A7 = 1
A6 = 1
A5 = 0
A4 = ADDR4/GPO4
A3 =ADDR3/GPO3
A2 = ADDR2/GPO2
A1 = EN8/ADDR1/GPO1
Figure 8. I2C ADDRESS = 0x60–0x6F
External pull-up/pull-down resistors are required to configure the I2C address; the UCD9080 does not have
internal bias resistors. Note that the 7-bit I2C address refers to the address bits only, not the read/write (8th) bit in
the first byte of the I2C protocol. The base I2C address is 0x60 and the I2C general call address (0x00) is not
supported.
After the initialization process of the UCD9080 is complete, these four digital signals can be used for
general-purpose outputs of the sequencer. They can be programmed and sequenced as described later in this
document.
I2C Transactions
The UCD9080 can be configured and monitored via I2C memory-mapped registers. Registers that are
configurable (can be written) via an I2C write operation are implemented using an I2C unidirectional data
transfer, from the master to slave, with a stop bit between transactions
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PRODUCT PREVIEW
The UCD9080 Power Supply Sequencer has an I2C slave interface for communication with an I2C master for
configuration and monitoring of the power supply sequencer and rails. The UCD9080 supports slave-mode
operation for a 100 kHz I2C bus. This interface is used for configuring the UCD9080 as well as monitoring each
of the voltage rails and reporting the voltage of each independently
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I2C Unidirectional Transfer
1
7
1
1
8
1
8
1
1
S
SLAVE
ADDRESS
R/W
A
REGISTER
ADDRESS
A
DATA
A/A
P
Data transferred
(n bytes +
acknowledge)
‘0’ (write)
From master to slave
A = acknowledge (SDA low)
A
= Not acknowledge (SDA high)
S = START condition
From slave to master
P = STOP condition
2
Figure 9. I C Register Access With START/STOP
PRODUCT PREVIEW
Registers that can be read are implemented using an I2C read operation, which uses the I2C combined format
that changes data direction during the transaction. This transaction uses an I2C restart during the direction
change.
I2C Combined Format
1
S
7
1
SLAVE
ADDRESS R/W
1
A
8
REGISTER
A ADDRESS
1
1
A
Sr
A
7
1
SLAVE
ADDRESS R/W
1
A
A
8
1
1
DATA
A/A
P
DATA
(n bytes + ack)
‘0’ (write)
‘1’ (read)
A = acknowledge (SDA low)
From master to slave
A
= Not acknowledge (SDA high)
S = START condition
From slave to master
P = STOP condition
Sr = Repeated START
Figure 10. I2C Register Access with RESTART
The UCD9080 also supports a feature that auto-increments the register address pointer for increased efficiency
when accessing sequential blocks of data. It is not necessary to issue separate I2C transactions..
12
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CONFIGURING AND MONITORING THE UCD9080
The UCD9080 supports both configuration and monitoring using its I2C slave interface.
For monitoring of the sequencer, there is an I2C memory map that is used that allows an I2C host to perform
memory mapped reads (and in some cases writes) that reports status information from the UCD9080. For
instance, all rails can report their voltage through the I2C memory map. For information on which parameters are
available via the I2C memory map, see the Monitoring the UCD9080 section.
To change configuration parameters of the sequencer, a different mechanism is used. The entire set of
configuration parameters must be written at one time to the device as one large transaction over the I2C
interface. This ensures that the configuration of the device is consistent at any given time. The process for
configuring the UCD9080 is described below in the section titled Configuring the UCD9080 section.
MONITORING THE UCD9080
Register Map
Note that the UCD9080 supports functionality to automatically increment the I2C register address value when a
register is being accessed, to more efficiently access blocks of like registers. The table below also shows the
amount that the register address is incremented for each register access.
REGISTER NAME
ADDRESS
ACCESS
ADJUSTMENT AFTER ACCESS
RAIL1H
0x00
r
+1 (0x01)
RAIL1L
0x01
r
+1 (0x02)
RAIL2H
0x02
r
+1 (0x03)
RAIL2L
0x03
r
+1 (0x04)
RAIL3H
0x04
r
+1 (0x05)
RAIL3L
0x05
r
+1 (0x06)
RAIL4H
0x06
r
+1 (0x07)
RAIL4L
0x07
r
+1 (0x08)
RAIL5H
0x08
r
+1 (0x09)
RAIL5L
0x09
r
+1 (0x0A)
RAIL6H
0x0A
r
+1 (0x0B)
RAIL6L
0x0B
r
+1 (0x0C)
RAIL7H
0x0C
r
+1 (0x0D)
+1 (0x0E)
RAIL7L
0x0D
r
RAIL8H
0x0E
r
+1 (0x0F)
RAIL8L
0x0F
r
–15 (0x00)
ERROR1
0x20
r
+1 (0x21)
ERROR2
0x21
r
+1 (0x22)
ERROR3
0x22
r
+1 (0x23)
ERROR4
0x23
r
+1 (0x24)
ERROR5
0x24
r
+1 (0x25)
ERROR6
0x25
r
–5 (0x20)
STATUS
0x26
r
+0 (0x26)
RAILSTATUS1
0x28
r
+1 (0x29)
RAILSTATUS2
0x29
r
–1 (0x28)
FLASHLOCK
0x2E
rw
0 (0x2E)
RESTART
0x2F
w
+0 (0x2F)
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PRODUCT PREVIEW
The UCD9080 allows all monitoring of the system through the I2C interface on the device. The following is the
memory map of the supported registers in the system. The detail of each of these registers is given in the next
section as well.
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REGISTER NAME
ADDRESS
ACCESS
WADDR1
0x30
rw
ADJUSTMENT AFTER ACCESS
+1 (0x31)
WADDR2
0x31
rw
– 1 (0x30)
WDATA1
0x32
w
+1 (0x33)
WDATA2
0x33
w
–1 (0x32)
Register Descriptions
The following are the detailed descriptions of each of the UCD9080 I2C registers.
The register bit conventions below are used. Each register is shown with a key indicating the accessibility of
each bit, and the initial condition after device initialization.
KEY
ACCESS
PRODUCT PREVIEW
rw
Read/Write
r
Read only
r0
Read as 0
r1
Read as 1
w
Write only
w0
Write as 0
w1
Write as 1
rc
Read clears bit after read
rs
Read sets bit after read
–0, –1
Condition after initialization
RAIL
Each of the 8 voltage rails that the UCD9080 supports has two registers that contains the rolling average voltage
for the associated rail as measured by the device. This average voltage is maintained in real-time by the
UCD9080 and is calculated as the output of a 4-TAP FIR filter. There are two registers for each voltage rail. One
holds the least-significant 8 bits of the voltage and the other the most-significant 2 bits of the voltage. This is
shown below.
14
Register Name
Address
RAIL1H
0x00
Register Contents
RAIL1 Voltage, bits 9:8
RAIL1L
0x01
RAIL1 Voltage, bits 7:0
RAIL2H
0x02
RAIL2 Voltage, bits 9:8
RAIL2L
0x03
RAIL2 Voltage, bits 7:0
RAIL3H
0x04
RAIL3 Voltage, bits 9:8
RAIL3L
0x05
RAIL3 Voltage, bits 7:0
RAIL4H
0x06
RAIL4 Voltage, bits 9:8
RAIL4L
0x07
RAIL4 Voltage, bits 7:0
RAIL5H
0x08
RAIL5 Voltage, bits 9:8
RAIL5L
0x09
RAIL5 Voltage, bits 7:0
RAIL6H
0x0A
RAIL6 Voltage, bits 9:8
RAIL6L
0x0B
RAIL6 Voltage, bits 7:0
RAIL7H
0x0C
RAIL7 Voltage, bits 9:8
RAIL7L
0x0D
RAIL7 Voltage, bits 7:0
RAIL8H
0x0E
RAIL8 Voltage, bits 9:8
RAIL8L
0x0F
RAIL8 Voltage, bits 7:0
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A rail voltage is read with a 16b access. The auto-increment feature of the UCD9080 allows multiple rail voltages
to be read with a single access.
A rail voltage is provided as a 10-bit binary value in an un-signed format, as shown below.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
RAILVn
r0
r0
r0
r0
r0
r0
r
r
r
r
r
The following formulas can be used to calculate the actual measured rail voltage:
Without external voltage divider:
V RAILn + RAILVn V REF
1024
(1)
With external voltage divider:
V RAILn + RAILVn
1024
R PULLDOWN ) R PULLUP
R PULLDOWN
V REF
(2)
Error conditions are logged by the UCD9080 and are accessible to the user via reading the ERROR registers.
This is a 6-byte register and it has the following format:
0x20
15
14
13
12
Error Code
0x21
11
10
9
8
7
6
5
4
3
2
1
0
Data (dependent on error code)
RAIL
RAIL: Rail #(n) - 1, RAIL = 0 through 7
Error Code
Meaning
Data
0
0
0
0
1
1
1
1
Null Alarm
Supply did not start
Sustained overvoltage detected
Sustained undervoltage detected
Overvoltage glitch detected
Undervoltage glitch detected
Reserved
Reserved
0x0000
Average voltage on Rail
Average voltage on Rail
Average voltage on Rail
Glitch voltage level on Rail
Glitch voltage level on Rail
Reserved
Reserved
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0x22
7
7
6
6
5
5
4
3
0x23
2
1
0
7
6
5
4
3
Hour
Minutes
0x24
0x25
4
3
2
1
0
7
6
5
Seconds
4
3
2
1
0
2
1
0
Milliseconds
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PRODUCT PREVIEW
ERROR
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Error conditions encountered during processing will post error logs to this register. There are some exceptions.
This register is internally managed as a FIFO where errors are posted to the FIFO as they occur and read out of
the FIFO via I2C accesses. The FIFO is only posted to by the UCD9080 if it has room to write, due to the
unknown latency of the system reading out of this FIFO. Note that there is no real-time impact to the processing
of the UCD9080 if this FIFO is full and cannot be posted to.
The device time is reset by the following conditions:
1. Device Reset
2. A restart command issued to the device by the host via I2C.
3. A Resequence action is taken.
STATUS
The STATUS is an 8-bit read-only register. This register provides real-time status information about the state of
the UCD9080. The following bits are defined.
7
6
5
IIC Error RAIL error
rc-0
4
3
2
r-0
r-0
r-0
1
Register Status
NVERRLOG
rc-0
r
0
rc-0
PRODUCT PREVIEW
Register
Status
00
01
10
11
IIC Error Meaning
No I2C PHY layer error
0
I2C PHY layer error
1
RAIL Error Meaning
No RAIL error pending
0
RAIL error pending
1
Meaning
No Error
Invalid Address
Read Access Error
Write Access Error
NVERRLOG Meaning
ERROR points to run-time logs
0
ERROR points to non-volatile logs
1
Reading of the STATUS register clears the register except for the NVERRLOG bit, which is maintained until the
device is reset. Descriptions of the different errors are below.
The IICERROR bit is set when an I2C access fails. This is most often a case where the user has accessed an
invalid address, or performed an illegal number of operations for a given register (for example, reading 3 bytes
of a 2-byte register). In the event of an I2C error when the I2CERROR is set, bits 1:0 of the STATUS register
further define the nature of the error as shown above.
The RAIL error bit is set to alert the user to an issue with one of the voltage rails. When this bit is set, the user is
advised to then query the RAILSTATUS register to further ascertain which RAIL input(s) have an issue. The
user may then query the ERROR<n> registers to get further information about the nature of the error condition.
The NVERRLOG bit is set to 1 upon device initialization if the UCD9080 was restarted from a shutdown
sequence of a RAIL declared as critical. The purpose of this bit is to allow the user to differentiate between
stored error logs and real time error logs, and is useful for a post-mortem debug. Note that this bit is the only bit
that is not automatically cleared by a read of the STATUS register; this bit is only cleared at device reset if the
non-volatile error logs are empty.
When the IICERROR bit is set, the Register Status bits provide further information about the type of I2C error
that has been detected, as indicated above.
RAILSTATUS
The RAILSTATUS1 and RAILSTATUS2 registers are two 8-bit read-only registers that provide a bit-mask that
represent the error status of the rails as indicated in the diagram below.
15
14
13
12
11
rc-0
rc-0
rc-0
rc-0
rc-0
10
9
8
7
6
5
4
3
2
1
0
RAIL8 RAIL7 RAIL6 RAIL5 RAIL4 RAIL3 RAIL2 RAIL1
16
rc-0
rc-0
rc-0
rc-0
rc-0
rc-0
RAILn Meaning
0 => No Alarm Pending for RAILn
1 => Alarm Pending for RAILn
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rc-0
rc-0
rc-0
rc-0
rc-0
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Bits 15:8 are RAILSTATUS1 and bits 7:0 are RAILSTATUS2. These are read as two 8-bit registers or as a
single 16-bit register.
If a bit is set in these registers, then the ERROR register is read to further ascertain the specific error. Bits in the
RAILSTATUS1 and RAILSTATUS2 registers are cleared when read.
FLASHLOCK
The FLASHLOCK I2C command is used to lock and unlock the configuration memory on the UCD9080 when
updating the configuration. The section below (Configuring the UCD9080) details this process.
The format for the FLASHLOCK command is as follows:
7
6
5
4
3
2
1
0
rw-0
rw-0
rw-0
FLASHLOCK
rw-0
rw-0
rw-0
rw-0
rw-0
RESTART
The RESTART register provides the capability for the I2C host to force a re-initialization and restart of the
UCD9080. This is an 8-bit register and when written to with a 0, the UCD9080 is restarted and the rails are
resequenced. This is useful for restarting the sequencer after the configuration for the system is changed. In
order to properly restart the system, this register must be written to a 0.
Note that in order to respond to this I2C request properly, there is a 50-µs delay before the system is restarted,
so that the I2C ACK can take place.
WADDR and WDATA
In order to update the configuration on the UCD9080, two primitive commands are provided in the I2C memory
map, WADDR and WDATA (see NOTE). Each of these registers are 8-bits and there are two of each (e.g.,
WADDR1, WADDR2 and WDATA1, WDATA2) to be able to write addresses and data of up to 16b.
NOTE:
In addition to updating the WADDR and WDATA commands, users can use the
FLASHLOCK command to perform configuration updates to the UCD9080.
The format for the WADDR command is as follows:
15
8 7
0
Address
rw-0x00
rw-0x00
WADDR2
(0x31)
WADDR1
(0x30)
To set the address in the UCD9080 to write, write the LSB of the address to the WADDR1 register and the MSB
of the address to the WADDR2 register. For example, to write the address 0x1234 to the device, set WADDR1 =
0x34 and WADDR2 = 0x12. Note that since these addresses support the auto-increment feature, the user can
perform a single 16b write to WADDR1 to write the entire address.
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PRODUCT PREVIEW
FLASHLOCK
0x00
FLASH is locked (default)
0x01
FLASH is being updated
0x02
Unlock flash (before configuration)
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The format for the WDATA command is as follows:
15
8 7
0
Data
w
w
WDATA2
(0x33)
WDATA1
(0x32)
To set the data in the UCD9080 to write, write the LSB of the data to the WDATA1 register and the MSB of the
data to the WDATA2 register. For example, to write the data 0xBEEF to the device, set WDATA1 = 0xEF and
WDATA2 = 0xBE. Note that since these addresses support the auto-increment feature, the user can perform a
single 16b write to WDATA1 to write the entire data.
These two commands are used for updating the UCD9080 configuration, explained in the next section
(Configuring the UCD9080).
RESETTING THE FLASH ERROR LOGS
PRODUCT PREVIEW
The UCD9080 can be configured to log critical errors on a voltage rail to flash. This can be configured via the
SaveRailLog register, described later in this document. If the SaveRailLog bit is set for a voltage rail and an
error is detected on that voltage rail, then the error logs for that rail are written to flash memory instead of
operating memory. This mechanism permits the error logs to be read after the device has been reset and
operating memory cleared.
Once the system is in the state where the error logs are pointing to flash, the NVERRLOG bit in the STATUS
register is set to a 1 when it is read from the I2C interface. To clear this condition, take the following steps:
• Write FLASHLOCK register to a value of 0x02
• Write WADDR register to a value of 0x1000
• Write WDATA register to a value of 0xBADC
• Write WADDR register to a value of 0x107E
• Write WDATA register to a value of 0xBADC
• Write FLASHLOCK register to a value of 0x00
• Write RESTART register to a value of 0x00
This points the error logs back to operating memory, and restarts the sequencer.
CONFIGURING THE UCD9080
The UCD9080 has many different configurable parameters such as sequencing policies, shutdown policies and
dependency masks. The UCD9080 can configure all of its parameters via the I2C interface while the device is
operational; however sequencing, shutdown and rail monitoring is not performed during this time.
The configuration information can not be read from the device.
NOTE:
During runtime, if the UCD9080 is configured, there is a delay in voltage monitoring
while the new configuration parameters are applied to the device.
To configure the UCD9080, a large block of configuration information is sent to the device via the I2C interface.
This block is 512 bytes and contains all the configuration information that the device requires for any function of
the UCD9080.
This 512 byte block of configuration information is sent to the device in multiple segments. The segment size
can range from 2 to 32 bytes at one time, and must be a multiple of 2 bytes. That is, a master can send 256
2-byte segments or 32 16-byte segments, and so on. All the segments must be sent back-to-back in the proper
sequence and this operation must be completed by sending the last segment so that the last byte of the 512
byte block is written. If this is not done, the UCD9080 is in an unknown state and does not function as designed.
18
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CONFIGURING THE UCD9080 (continued)
The process for sending the configuration information to the UCD9080 is as shown in Figure 11:
I2CWrite:
FLASHSTATE=
UNLOCK(0x02)
I2CWrite:
WADDR=
0xE000
I2CWrite:
WDATA=
0xBADC
I2CWrite:
WDATA=
Data(16b)
I2CWrite:
WADDR=
0xE000
I2CWrite:
WDATA=
Data(16b)
...
I2CWrite:
FLASHSTATE=
LOCK(0x00)
Up to 16 times (32bytes)
- OR Repeat as necessary with WADDR updated
to write 512 bytes
As shown in Figure 11, the process for updating the configuration of the UCD9080 is as follows:
1. Unlock flash memory by sending the UNLOCK command (FLASHSTATE = 0x02)
2. Write the address of the configuration section of memory (WADDR = 0xE000)
3. Write the constant 0xBADC to update memory (WDATA = 0xBADC)
4. Write the address of the configuration section of memory again (WADDR = 0xE000)
5. Write the data (WDATA = <varies>). Repeat steps 4 and 5 as necessary, depending on the data segment
size used to write 512 bytes. Increment the address as necessary.
6. Lock flash memory after the last byte of the last segment is written (FLASHSTATE = 0x00)
At the conclusion of this process, the configuration of the UCD9080 is updated with the configuration changes,
as represented by the values from the data segments. The sequencer can then be reset using the RESTART
I2C command, and then the application restarts.
The memory map for the 512 byte configuration segment is defined in the section below.
Configuration Parameters Memory Map
Table 1 shows the 512 byte configuration parameters memory map. Each of the fields at each of the addresses
in this memory map either represents a configuration parameter for the UCD9080 that is changed by changing
its value, or it must be hard-coded to the given literal value.
Table 1. Configuration Parameters Memory Map
ADDRESS
+0
+1
+2
+3
+4
+5
+6
+7
0xE000
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE008
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE010
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE018
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE020
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE028
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE030
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE038
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE040
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE048
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE050
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE058
0xFF
0x00
0x00
0x00
0x00
0x00
0xC0
0x02
0xE060
0x00
0x00
0x00
0xF0
0x01
0x02
0x00
0x02
0xE068
0x7F
0x0E
0x00
0x50
0x00
0x00
0x00
0x00
0xE070
0x00
0x00
0xC0
0x20
0x00
0x00
0x00
0x00
0xE078
0x00
0x00
0x00
0x00
0x00
0xA8
0xDC
0xBA
0xE080
0xE088
SequenceEventParameters
SequenceEventParameters (continued)
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SequenceEventLink
19
PRODUCT PREVIEW
Figure 11. Configuration Information
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CONFIGURING THE UCD9080 (continued)
Table 1. Configuration Parameters Memory Map (continued)
ADDRESS
+0
+1
+2
0xE090
+3
+4
+5
+6
+7
SequenceEventLink (continued)
0xE098
0xE0A0
SequenceEventData
0xE0A8
0xE0B0
0xFF
0x7F
0xFF
0x7F
0xFF
0x7F
0xFF
0x7F
0xE0B8
0xFF
0x7F
0xFF
0x7F
0xFF
0x7F
0xFF
0x7F
0xE0C0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE0C8
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE0D0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE0D8
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE0E0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE0E8
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE0F0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE0F8
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
PRODUCT PREVIEW
0xE100
DependencyMasks
0xE108
0xE110
UnderVoltageThreholds
0xE118
0xE120
OverVoltageThresholds
0xE128
0xE130
RampTime
0xE138
0xE140
OutOfRegulationWidth
0xE148
0xE150
0xE158
UnsequenceTime
0xE160
0xE168
0xE170
EnablePolarity
0xE178
0xE180
20
0xF9
0x00
0x94
0x02
ReferenceSelect
0xE188
0x10
SaveRailLog
0x07
0x05
0xC0
0x32
0x00
LastUnusedSeq
0xE190
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE198
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE1A0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE1A8
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE1B0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE1B8
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE1C0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE1C8
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE1D0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE1D8
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE1E0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE1E8
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE1F0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE1F8
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
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SLVS692A – SEPTEMBER 2006 – REVISED DECEMBER 2006
CONFIGURATION PARAMETERS DETAIL
The following section details the format and meaning of the configuration parameters from the configuration
parameters memory map (Table 1).
SequenceEventParameters
The SequenceEventParameters field in the configuration parameters specifies the rail identification, monitoring
status and sequencing options for each rail. The address map for all these registers is as follows:
SIZE
DEFAULT VALUE
0xE080
1
0x50
Rail 1 identification, monitoring status and sequencing options.
DESCRIPTION
0xE081
1
0x51
Rail 2 identification, monitoring status and sequencing options.
0xE082
1
0x52
Rail 3 identification, monitoring status and sequencing options.
0xE083
1
0x53
Rail 4 identification, monitoring status and sequencing options.
0xE084
1
0x54
Rail 5 identification, monitoring status and sequencing options.
0xEx85
1
0x55
Rail 6 identification, monitoring status and sequencing options.
0xE086
1
0x56
Rail 7 identification, monitoring status and sequencing options.
0xE087
1
0x07
Rail 8 identification, monitoring status and sequencing options.
0xE088
1
0x08
GPO1 identification, sequencing options.
0xE089
1
0x49
GPO2 identification, sequencing options.
0xE08A
1
0x4A
GPO3 identification, sequencing options.
0xE08B
1
0x4B
GPO4 identification, sequencing options.
PRODUCT PREVIEW
ADDRESS
The format of each register is as follows:
7
6
5
4
ENABLE
0
MON
3
2
1
0
RAIL/GPO
RAIL
Rail #(n) - 1, RAIL = 0 through 7
GPO
GPO # (n) + 7, GPO = 8, 9, 0xA, 0xB
MON
0
1
ENABLE
00
01
10
11
Meaning
Do not monitor rail status (for event sequencing of GPOs)
Monitor rail status
Meaning
Sequence is disabled
Sequence is triggered after delay after sequence event
Sequence is triggered after parent rails achieves voltage level
Sequence is triggered after delay after parent rail achieves voltage regulation
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SequenceEventLink
The SequenceEventLink field in the configuration parameters specifies each rail’s parent rail as well as whether
or not to sequence it after shutdown. The address map for all these registers is as follows:
ADDRESS
SIZE
DEFAULT VALUE
DESCRIPTION
0xE08C
1
0x01
Rail 1 parent identifier and resequence indicator.
0xE08D
1
0x00
Rail 2 parent identifier and resequence indicator.
0xE08E
1
0x01
Rail 3 parent identifier and resequence indicator.
0xE08F
1
0x04
Rail 4 parent identifier and resequence indicator.
0xE090
1
0x01
Rail 5 parent identifier and resequence indicator.
0xE091
1
0x04
Rail 6 parent identifier and resequence indicator.
0xE092
1
0x05
Rail 7 parent identifier and resequence indicator.
0xE093
1
0x06
Rail 8 parent identifier and resequence indicator.
0xE094
1
0x00
GPO1 parent rail identifier and resequence indicator.
0xE095
1
0x00
GPO2 parent rail identifier and resequence indicator.
0xE096
1
0x00
GPO3 parent rail identifier and resequence indicator.
0xE097
1
0x00
GPO4 parent rail identifier and resequence indicator.
The format of each register is as follows:
PRODUCT PREVIEW
7
6
5
4
0
RESEQ
0
0
RESEQ
0
1
PARENTRAIL
0x0000
0x0001
0x0010
0x0011
0x0100
0x0101
0x0110
0x0111
22
3
2
1
0
PARENTRAIL
Meaning
Do not resequence after shutdown
Resequence after shutdown
Meaning
Sequence is dependent on RAIL1 achieving the specified event
Sequence is dependent on RAIL2 achieving the specified event
Sequence is dependent on RAIL3 achieving the specified event
Sequence is dependent on RAIL4 achieving the specified event
Sequence is dependent on RAIL5 achieving the specified event
Sequence is dependent on RAIL6 achieving the specified event
Sequence is dependent on RAIL7 achieving the specified event
Sequence is dependent on RAIL8 achieving the specified event
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SequenceEventData
The SequenceEventData field in the configuration parameters specifies each rail’s sequencing parameters. The
address map for all these registers is as follows:
ADDRESS
SIZE
DEFAULT VALUE
DESCRIPTION
0xE098
2
0xE005
Rail 1 sequencing and shutdown parameters.
0xE09A
2
0xA005
Rail 2 sequencing and shutdown parameters.
0xE09C
2
0xE032
Rail 3 sequencing and shutdown parameters.
0xE09E
2
0xE033
Rail 4 sequencing and shutdown parameters.
0xE0A0
2
0xE033
Rail 5 sequencing and shutdown parameters.
0xE0A2
2
0xE035
Rail 6 sequencing and shutdown parameters.
0xE0A4
2
0xE035
Rail 7 sequencing and shutdown parameters.
0xE0A6
2
0x0000
Rail 8 sequencing and shutdown parameters.
0xE0A8
2
0x0000
GPO1 sequencing and shutdown parameters.
0xE0AA
2
0x0000
GPO2 sequencing and shutdown parameters.
0xE0AC
2
0x0000
GPO3 sequencing and shutdown parameters.
0xE0AE
2
0x0000
GPO4 sequencing and shutdown parameters.
15
14
13
12
11
10
9
SEQPARAM
SEQPARAM
000
001
010
011
100
101
110
111
8
7
6
5
4
3
2
1
PRODUCT PREVIEW
The format for each register is as follows:
0
RAILDATA
Meaning
Ignore
Resequence after shutdown
Retry 4 times
Retry 3 times
Retry 2 times
Retry 1 time
Shutdown
Retry forever
RAILDATA Meaning
ENABLE in SequenceEventParameters register
01
Delay (ms)
10
Volatge (V)
11
Delay (mS)
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SLVS692A – SEPTEMBER 2006 – REVISED DECEMBER 2006
DependencyMasks
The DependencyMasks field in the configuration parameters specifies each rail’s dependency masks which are
used for rail shutdown. This mask represents the set of other rails and GPOs that should be shutdown when this
rail shuts down. Note that since only rails are monitored, this table only has entries for rails that are shutdown. In
the dependency mask itself, there are bits that allow for the shutting down of a GPO.
The address map for all these registers is as follows:
ADDRESS
SIZE
DEFAULT VALUE
0xE100
2
0x007F
Dependency mask for rail 1.
DESCRIPTION
0xE102
2
0x0001
Dependency mask for rail 2.
0xE104
2
0x0002
Dependency mask for rail 3.
0xE106
2
0x0004
Dependency mask for rail 4.
0xE108
2
0x0008
Dependency mask for rail 5.
0xE10A
2
0x0010
Dependency mask for rail 6.
0xE10C
2
0x0020
Dependency mask for rail 7.
0xE10E
2
0x0040
Dependency mask for rail 8.
The format for each register is as follows:
PRODUCT PREVIEW
15
14
13
12
0
0
0
0
RAILn or GPOn
0
1
11
10
9
8
7
6
5
4
3
2
1
0
GPO4 GPO3 GPO2 GPO1 RAIL8 RAIL7 RAIL6 RAIL5 RAIL4 RAIL3 RAIL2 RAIL1
Meaning
Shutdown of this rail will not shutdown RAILn or GPOn
Shutdown of this rail will shutdown RAILn or GPOn
UnderVoltageThresholds
The UnderVoltageThresholds field in the configuration parameters specifies each rail’s undervoltage thresholds
that are used when monitoring this rail. The address map for all these registers is as follows:
ADDRESS
SIZE
DEFAULT VALUE
DESCRIPTION
0xE110
2
0x0000
Undervoltage threshold for rail 8.
0xE112
2
0x0000
Undervoltage threshold for rail 7.
0xE114
2
0x0000
Undervoltage threshold for rail 6.
0xE116
2
0x0000
Undervoltage threshold for rail 5.
0xE118
2
0x0000
Undervoltage threshold for rail 4.
0xE11A
2
0x0000
Undervoltage threshold for rail 3.
0xE11C
2
0x0000
Undervoltage threshold for rail 2.
0xE11E
2
0x0000
Undervoltage threshold for rail 1.
The format for each register is as follows:
15
14
13
12
11
0
0
0
0
0
10
9
8
7
6
5
4
3
2
1
0
Vraw
The voltage conversion is dependent upon the configured voltage reference and the pull-up and pull-down
resistors used on the board for each rail. The voltage reference is selected as either 2.5 V (internal) or 3.3 V
(external via VCC). The formula to convert the desired Rail's UnderVoltageThreshold to Vraw follows:
Without external rail voltage divider:
1024 x VRAILUV
Vraw =
VREF
24
(3)
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With external rail voltage divider:
RPULLDOWN
1024 x VRAILUV
Vraw =
x
RPULLDOWN + RPULLUP
VREF
(4)
OverVoltageThresholds
The OverVoltageThreholds field in the configuration parameters specifies each rail’s over voltage thresholds that
are used when monitoring this rail. The address map for all these registers is as follows:
ADDRESS
SIZE
DEFAULT VALUE
0xE120
2
0x0400
Overvoltage threshold for rail 8.
DESCRIPTION
0xE122
2
0x0400
Overvoltage threshold for rail 7.
0xE124
2
0x0400
Overvoltage threshold for rail 6.
0xE126
2
0x0400
Overvoltage threshold for rail 5.
0xE128
2
0x0400
Overvoltage threshold for rail 4.
0xE12A
2
0x0400
Overvoltage threshold for rail 3.
0xE12C
2
0x0400
Overvoltage threshold for rail 2.
0xE12E
2
0x0400
Overvoltage threshold for rail 1.
15
14
13
12
11
0
0
0
0
0
10
9
8
7
6
5
4
3
2
1
0
Vraw
The voltage conversion is dependent upon the configured voltage reference and the pull-up and pull-down
resistors used on the board for each rail. The voltage reference is selected as either 2.5 V (internal) or 3.3 V
(external via VCC). The formula to convert the desired Rail's OverVoltageThreshold to Vraw follows:
Without external rail voltage divider:
1024 x VRAILOV
Vraw =
VREF
(5)
With external voltage divider:
1024 x VRAILOV
Vraw =
VREF
(6)
x
RPULLDOWN
RPULLDOWN + RPULLUP
RampTime
The RampTime field in the configuration parameters specifies the maximum amount of time for each rail to
achieve regulation. The address map for all these registers is as follows:
ADDRESS
SIZE
DEFAULT VALUE
0xE130
2
0x0FA0
Maximum voltage ramp time for rail 1.
DESCRIPTION
0xE132
2
0x0FA0
Maximum voltage ramp time for rail 2.
0xE134
2
0x0FA0
Maximum voltage ramp time for rail 3.
0xE136
2
0x0FA0
Maximum voltage ramp time for rail 4.
0xE138
2
0x0FA0
Maximum voltage ramp time for rail 5.
0xE13A
2
0x0FA0
Maximum voltage ramp time for rail 6.
0xE13C
2
0x0FA0
Maximum voltage ramp time for rail 7.
0xE13E
2
0x0FA0
Maximum voltage ramp time for rail 8.
The 16b value of this register is the number of milliseconds that this rail has to achieve regulation without an
error.
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PRODUCT PREVIEW
The format for each register is as follows:
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SLVS692A – SEPTEMBER 2006 – REVISED DECEMBER 2006
OutOfRegulation Width
The OutOfRegulationWidth field in the configuration parameters specifies the maximum amount of time that the
rail is allowed to be out of regulation before an error is declared (glitch width). The address map for all these
registers is as follows:
ADDRESS
SIZE
DEFAULT VALUE
0xE140
2
0x0010
The out of regulation width permissible without flagging error for Rail 1.
DESCRIPTION
0xE142
2
0x0010
The out of regulation width permissible without flagging error for Rail 2.
0xE144
2
0x0010
The out of regulation width permissible without flagging error for Rail 3.
0xE146
2
0x0010
The out of regulation width permissible without flagging error for Rail 4.
0xE148
2
0x0010
The out of regulation width permissible without flagging error for Rail 5.
0xE14A
2
0x0010
The out of regulation width permissible without flagging error for Rail 6.
0xE14C
2
0x0010
The out of regulation width permissible without flagging error for Rail 7.
0xE14E
2
0x0010
The out of regulation width permissible without flagging error for Rail 8.
The contents of this register are as follows:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OORW
PRODUCT PREVIEW
OORW= RAILn Out of regulation glitch width (in units of 1/10 mS)
UnsequenceTime
The UnsequenceTime field in the configuration parameters specifies the amount of time that each rail should
delay before unsequencing. The address map for all these registers is as follows:
ADDRESS
SIZE
DEFAULT VALUE
0xE150
2
0xC0FF
Unsequence delay for Rail 1.
DESCRIPTION
0xE152
2
0xC1FF
Unsequence delay for Rail 2.
0xE154
2
0xC2FF
Unsequence delay for Rail 3.
0xE156
2
0xC3FF
Unsequence delay for Rail 4.
0xE158
2
0xC4FF
Unsequence delay for Rail 5.
0xE15A
2
0xC5FF
Unsequence delay for Rail 6.
0xE15C
2
0xC6FF
Unsequence delay for Rail 7.
0xE15E
2
0xC7FF
Unsequence delay for Rail 8.
0xE160
2
0xC000
Unsequence delay for GPO1.
0xE162
2
0xC000
Unsequence delay for GPO2.
0xE164
2
0xC000
Unsequence delay for GPO3.
0xE166
2
0xC000
Unsequence delay for GPO4.
The contents of this register are as follows:
15
14
13
1
1
0
12
11
10
9
8
7
6
5
4
3
USTIME
USTIME = RAILn UnsequenceTime (in units of mS).
26
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1
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EnablePolarity
The EnablePolarity field in the configuration parameters specifies whether each power supply enable or GPO is
to be configured active high or active low.. The address map for all these registers is as follows:
ADDRESS
SIZE
DEFAULT VALUE
DESCRIPTION
0xE168
2
0x2004
Polarity for Rail 1 enable.
0xE16A
2
0x2008
Polarity for Rail 2 enable.
0xE16C
2
0x1804
Polarity for Rail 3 enable.
0xE16E
2
0x1802
Polarity for Rail 4 enable.
0xE170
2
0x1808
Polarity for Rail 5 enable.
0xE172
2
0x1810
Polarity for Rail 6 enable.
0xE174
2
0x1820
Polarity for Rail 7 enable.
0xE176
2
0x2010
Polarity for Rail 8 enable.
0xE178
2
0x1800
Polarity for GPO1.
0xE17A
2
0x2020
Polarity for GPO2.
0xE17C
2
0x2040
Polarity for GPO3.
0xE17E
2
0x2080
Polarity for GPO4.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DEFAULT VALUES as specified above
POL
Meaning
Railn enable or GPOn is active low
POL
0
1
Railn enable or GPOn is active high
SaveRailLog
The SaveRailLog field in the configuration parameters specifies whether each rail is marked to write the error log
to flash upon rail failure. If the rail is marked this way, then a shutdown of this rail is logged info non-volatile
memory.
The contents of this register are as follows:
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
RAILn
0
1
7
6
5
4
3
2
1
0
RAIL8 RAIL7 RAIL6 RAIL5 RAIL4 RAIL3 RAIL2 RAIL1
Meaning
Shutdown of this rail will not log this event.
Shutdown of this rail will log this event.
The default value for this register is 0x0000.
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PRODUCT PREVIEW
The contents of this register are as follows:
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ReferenceSelect
The ReferenceSelect field in the configuration parameters specifies which voltage reference is used on the
UCD9080. The selected reference can be internal (2.5-V), or external via VCC (3.3 V). The contents of this
register are as follows:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x8F2
SELREF
Meaning
External Reference Selected (VCC).
SELREF
000
001
Internal Reference Selected (2.5 V).
The default value for this register is 0x8F2, which selects the external reference.
LastUnusedSeq
The LastUnusedSeq field in the configuration parameters specifies the amount of time for the last rail to be
shutdown without creating an error.
15
14
13
12
11
10
9
8
7
6
5
4
PRODUCT PREVIEW
LUTIME
LUTIME = Maximum value USTIME + 255 (in units of mS)
The default value for this register is 0x08FF.
28
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3
2
1
0
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SLVS692A – SEPTEMBER 2006 – REVISED DECEMBER 2006
APPLICATION INFORMATION
Typical Application Diagram
PRODUCT PREVIEW
330W
Status
LEDs
ADDR3/
G PO3
27
ADDR4/
G PO4
28
26
25
1
VSS
SDA
21
SCL
EN8/
ADDR2/ ADDR1/
G PO1
G PO2
VCC
22
NIC
4
ROSC
TEST
29
32
XIN
2
EX: Slave I C Address = 0x65
(Internal ADDR[7:5] = 0b110)
DNP
DNP
1kW
1kW
10kW
10kW
10kW
10kW
3.3V
3.3V
VBUS
RTN
VBUS
3.3V
2
I C
Master
3.3V
3.3V
3.3V
10kW
10kW
100kW
3.3V
3.3V
Regulator
3.3V
3.3V
10kW
0.01mF
3.3V
3
POR4
POR1
POR2
POR3
VOUTX
1 mF
30
31
NIC
17
20
NIC
NIC
RST
MON8
16
5
MON7
15
MON5
19
MON6
MON4
18
9
MON3
8
MON1
MON2
6
7
UCD9080
NIC
2
14
EN7
13
12
EN5
EN6
10
11
EN3
EN4
24
23
EN1
EN2
3.3V
3.3V
3.3V
*
Power
Supply
X
EN
*
Power
Supply
3
EN
*
VOUT3
VOUT2
EN
EN
Power
Supply
2
Power
Supply
1
VOUT1
System
Device
Resets
Figure 12 illustrates a typical power supply sequencing configuration. Power Supply 1 and Power Supply X
require active low enables while Power Supply 2 and Power Supply 3 require active high enables. VOUT1 and
VOUT3 exceed the selected A/D reference voltage so their outputs are divided before being sampled by the
MON1 and MON3 inputs. VOUT2 and VOUTX are within the selected A/D reference voltage so their outputs can be
sampled directly by the MON2 and MON7 inputs. Figure 12 illustrates the use of the GPO digital output pins to
provide status and power on reset to other system devices.
Figure 12. Typical Power Supply Sequencing Application
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PACKAGE OPTION ADDENDUM
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13-Nov-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
UCD9080RHBR
PREVIEW
QFN
RHB
32
3000
TBD
Call TI
Call TI
UCD9080RHBT
PREVIEW
QFN
RHB
32
250
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
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Addendum-Page 1
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