TI UCD9220RGZT

UCD9220
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Digital PWM System Controller
FEATURES
1
• Fully Configurable Multi-Output and
Multi-Phase Non-Isolated DC/DC PWM
Controller
• Controls Up To Two Voltage Rails and Up To
Four Phases
• Supports Switching Frequencies Up to 2MHz
With 250 ps Duty-Cycle Resolution
• Up To 1mV Closed Loop Resolution
• Hardware-Accelerated, 3-Pole/3-Zero
Compensator With Non-Linear Gain for
Improved Transient Performance
• Supports Multiple Soft-Start and Soft-Stop
Configurations Including Prebias Start-up
• Supports Voltage Tracking, Margining and
Sequencing
• Supports Current and Temperature Balancing
for Multi-Phase Power Stages
• Supports Phase Adding/Shedding for
Multi-Phase Power Stages
• Sync In /Out Pins Align DPWM Clocks
Between Multiple UCD9220 Devices
• 12-Bit Digital Monitoring of Power Supply
Parameters Including:
– Input Current and Voltage
– Output Current and Voltage
– Temperature at Each Power Stage
• Multiple Levels of Overcurrent Fault
Protection:
– External Current Fault Inputs
– Analog Comparators Monitor Current
Sense Voltage
– Current Digitally Monitored
• Over and Undervoltage Fault Protection
• Overtemperature Fault Protection
• Enhanced Nonvolatile Memory With Error
Correction Code (ECC)
• Device Operates From a Single Supply With an
Internal Regulator Controller That Allows
Operation Over a Wide Supply Voltage Range
•
2
Supported by Fusion Digital Power™
Designer, a Full Featured PC Based Design
Tool to Simulate, Configure, and Monitor
Power Supply Performance.
APPLICATIONS
•
•
•
•
•
•
Industrial/ATE
Networking Equipment
Telecommunications Equipment
Servers
Storage Systems
FPGA, DSP and Memory Power
DESCRIPTION
The UCD9220 is a multi-rail, multi-phase
synchronous buck digital PWM controller designed for
non-isolated DC/DC power applications. This device
integrates dedicated circuitry for DC/DC loop
management with flash memory and a serial interface
to
support
configuration,
monitoring
and
management.
The UCD9220 was designed to provide a wide
variety of desirable features for non-isolated DC/DC
converter applications while minimizing the total
system component count by reducing external
circuits.
The
solution
integrates
multi-loop
management with sequencing, margining, tracking
and intelligent phase management to optimize for
total
system
efficiency.
Additionally,
loop
compensation and calibration are supported without
the need to add external components.
To facilitate configuring the device, the Texas
Instruments Fusion Digital Power™ Designer is
provided. This PC based Graphical User Interface
offers an intuitive interface to the device. This tool
allows the design engineer to configure the system
operating parameters for the application, store the
configuration to on-chip non-volatile memory and
observe both frequency domain and time domain
simulations for each of the power stage outputs.
TI has also developed multiple complementary power
stage solutions – from discrete drives in the UCD7k
family to fully tested power train modules in the PTD
family. These solutions have been developed to
complement the UCD9k family of system power
controllers.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Fusion Digital Power, Auto-ID are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
UCD9220
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
OPERATING TEMPERATURE
RANGE, TA
ORDERABLE PART
NUMBER
PIN COUNT
SUPPLY
PACKAGE
TOP SIDE
MARKING
UCD9220RGZR
48-pin
Reel of 2500
QFN
UCD9220
UCD9220RGZT
48-pin
Reel of 250
QFN
UCD9220
–40°C to 110°C
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
UNIT
Voltage applied at V33D to DGND1
–0.3 to 3.8
V
Voltage applied at V33A to AGND
–0.3 to 3.8
V
Voltage applied to any pin
(2)
Storage temperature (TSTG)
(1)
(2)
–0.3 to 3.8
V
–40 to 150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to GND.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted).
V
Supply voltage during operation, V33D, V33A
TA (1)
Operating free-air temperature range
TJ (1)
Junction temperature
(1)
2
MIN
NOM
3
3.3
–40
MAX
UNIT
3.6
V
110
°C
125
°C
When operating, the UCD9220's typical power consumption causes a 15 °C temperature rise from ambient.
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ELECTRICAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
SUPPLY CURRENT
IV33A
V33A = 3.3 V
8
15
IV33D
V33D = 3.3 V
42
55
V33D = 3.3 V while storing configuration
parameters in flash memory
52
65
3.3
3.6
4
4.6
Supply current
IV33D
mA
INTERNAL REGULATOR CONTROLLER INPUTS/OUTPUTS
V33
3.3-V linear regulator
V33FB
3.3-V linear regulator feedback
IV33FB
Series pass base drive
Beta
Series NPN pass device
Emitter of NPN transistor
3.25
VIN = 12 V; current into the pin
10
V
mA
40
EXTERNALLY SUPPLIED 3.3 V POWER
V33D
Digital 3.3-V power
TA = 25°C
3.13
3.6
V
V33A
Analog 3.3-V power
TA = 25°C
3.13
3.6
V
Common mode voltage each pin
–0.15
1.848
V
VDIFF
Differential Voltage Range
–0.25
6
1.998
V
VERROR
Internal error Voltage range
AFE_GAIN field of CLA_GAINS = 0 (1)
EAP-EAN
Error voltage digital resolution
AFE_GAIN field of CLA_Gains = 3
REA
Input Impedance
Ground reference
0.5
IOFFSET
Input offset current
1 kΩ source impedance
ERROR AMPLIFIER INPUTS EAPn, EANn
VCM
-256
248
mV
3
MΩ
–5
5
µA
0
1.6
V
1
1.5
mV
VREF DAC
VREF
Reference voltage setpoint
VREFRES
Reference voltage resolution
1.56
mV
ANALOG INPUTS CS-1A, CS-1B, CS-2A, CS-3A, Vin/IIN, Temperature, ADDR-0, ADDR-1, Vtrack, ADCref
IBIAS
Bias current for PMBus Addr pins
VADDR_OPEN
Voltage indicating open pin
ADDR-0, ADDR-1 open
VADDR_SHORT
Voltage indicating shorted pin
ADDR-0, ADDR-1 short to ground
VADC_RANGE
Measurment range for voltage
monitoring
Inputs: VIn/IIN, Vtrack, Vtemperature
CS-1A, CS-1B, CS-2A, CS-3A
VOC_THRS
Overcurrent comparator threshold
voltage range
Inputs: CS-1A, CS-1B, CS-2A, CS-3A
VOC_RES
Overcurrent comparator threshold
voltage resolution
Inputs: CS-1A, CS-1B, CS-2A, CS-3A
ADCref
External Reference input
Tempinternal
Int. temperature sense accuracy
INL
ADC integral nonlinearity
Ilkg
Input leakage current
3V applied to pin
RIN
Input impedance
Ground reference
CIN
Current Sense Input capacitance
(1)
9
Over range from 0°C to 125°C
11
2.226
µA
V
0.097
V
0
2.5
V
0.032
2
V
31.25
mV
1.8
V33A
V
–5
5
°C
2.5
mV
–2.5
100
8
nA
MΩ
10
pF
See the UCD92xx PMBus Command Reference for the description of the AFE_GAIN field of CLA_GAINS command.
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ELECTRICAL CHARACTERISTICS (continued)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
DIGITAL INPUTS/OUTPUTS
VOL
Low-level output voltage
IOL = 6 mA (2), VV33D = 3 V
VOH
High-level output voltage
IOH = –6 mA (3),V33D= 3 V
VIH
High-level input voltage
V33D = 3V
VIL
Low-level input voltage
V33D = 3.5V
DGND1
+0.25
V33D
–0.6V
V
V
2.1
3.6
V
1.1
V
SYSTEM PERFORMANCE
Setpoint Reference Accuracy
Vref commanded to be 1V, at 25°C
AFEgain = 4, 1V input to EAP/N measured
at output of the EADC (4)
–10
10
mV
Setpoint Reference Accuracy over
temperature
–40°C to 125°C
–20
20
mV
VDiffOffset
Differential offset between gain
settings
AFEgain = 4 compared to
AFEgain = 1, 2, or 8
–4
4
mV
tDelay
Digital Compensator Delay (5)
240
240 + 1
switching
period
ns
FSW
Switching Frequency
15.26
0
2000
Duty
Max and Min Duty Cycle
Configured via PMBus
0%
100%
V33Slew
V33 slew rate
V33 slew rate between 2.3 V and 2.9 V.
V33A = V33D
tretention
Retention of configuration parameters TJ = 25°C
Write_Cycles
Number of nonvolatile erase/write
cycles
VRef
(2)
(3)
(4)
(5)
TJ = 25°C
kHz
0.25
V/ms
100
Years
20
K
cycles
The maximum IOL, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified.
The maximum IOH, for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified.
With default device calibration. PMBus calibration can be used to improve the regulation tolerance.
Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay must be
accounted for when calculating the system dynamic response. Includes EADC conversion time.
ADC MONITORING INTERVALS AND RESPONSE TIMES
The ADC operates in a continuous conversion sequence that measures each rail's output voltage, each power
stage's ouput current, plus four other variables (one external temperature, Internal temperature, input voltage or
current and tracking input voltage). The length of the sequence is determined by the number of output rails
(NumRails) and total output power stages (NumPhases) configured for use. The time to complete the monitoring
sampling sequence is give by the formula:
tADC_SEQ = tADC × (NumRAILS + NumPHASE + 4)
PARAMETER
tADC
tADC_SEQ
4
(1)
TEST CONDITIONS
MIN
ADC single-sample time
ADC sequencer interval
TYP
MAX
Min = 1 Rail + 1 Phase + 4 = 6 samples
Max = 2 Rails + 4 Phases + 4 = 10 samples
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23.04
UNIT
µs
3.84
38.4+1
switching
period
µs
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The most recent ADC conversion results are periodically converted into the proper measurement units (volts,
amperes, degrees), and each measurement is compared to its corresponding fault and warning limits. The
monitoring operates asynchronously to the ADC, at intervals shown in the table below.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
µs
tVout
Output voltage monitoring interval
200
tIout
Output current monitoring interval
200 × NRails
µs
tVin
Input voltage monitoring interval
2
ms
tIin
Input current monitoring interval
2
ms
tTEMP
Temeprature monitoring interval
25 × number
of phases
tIbal
Output current balancing interval
25
100
ms
2
ms
Because the ADC sequencer and the monitoring comparisons are asynchronous to each other, the response
time to a fault condition depends on where the event occurs within the monitoring interval and within the ADC
sequence interval. Once a fault condition is detected, some additional time is required to determine the correct
action based on the FAULT_RESPONSE code, and then to perform the appropriate response. The following
table lists the worse-case fault response times.
TEST CONDITIONS
MAX TIME
UNIT
tOVF, tUVF
Over-voltage/under-voltage fault response
time during normal operation
PARAMETER
Normal regulation, no PMBus activity, 4 stages
enabled
300
µs
tOVF, tUVF
Over-voltage/under-voltage fault response
time, during data logging
During data logging to nonvolatile memory (1)
800
µs
tOVF, tUVF
Over-voltage/under-voltage fault response
time, when tracking or sequencing enable
During tracking and soft-start ramp.
400
µs
tOCF, tUCF
Over-current/under-current fault response
time during normal operation
Normal regulation, no PMBus activity, 4 stages
enabled
75% to 125% current step
100 + (600 x NRails) (2)
µs
tOCF, tUCF
Over-current/under-current fault response
time, during data logging
During data logging to nonvolatile memory
75% to 125% current step
600 + (600 x NRails)
µs
tOCF, tUCF
Over-current/under-current fault response
time, when tracking or sequencing enable
During tracking and soft start ramp
75% to 125% current step
300 + (600 x NRails)
µs
tOTF
Over-temperature fault response time
Temperature rise of 10°C/sec,
OT threshold = 100°C
5
s
(1)
(2)
During a STORE_DEFAULT_ALL command, which stores the entire configuration to nonvolatile memory, the fault detection latency can
be up to 10 ms.
Because the current measurement is averaged with a smoothing filter, the response time to an Overcurrent condition depends on a
combination of the time constant (τ) from Table 4, the recent measurement history, and how much the measured value exceeds the
overcurrent limit.
HARDWARE FAULT DETECTION LATENCY
The controller contains hardware fault detection circuits that are independent of the ADC monitoring sequencer.
PARAMETER
TEST CONDITIONS
MAX TIME
UNIT
15 + 3 ×
NumPhases
µs
tFLT
Time to disable DPWM output based on corresponding
active FLT pin
High level on FLT pin
tCLF
Time to disable the first DPWM output based on internal
analog comparator fault
Step change in CS voltage from 0V to
2.5V
4
Switch
Cycles
Time to disable all remaining DPWM and SRE outputs
configured for the voltage rail after an internal analog
comparator fault.
Step change in CS voltage from 0V to
2.5V
10 + 3 ×
NumPhases
µs
PMBUS/SMBUS/I2C
The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus and
PMBus are shown below.
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I2C/SMBus/PMBus Timing Characteristics
TA = –40°C to 85°C, 3V < V33D < 3.6V, typical values at TA = 25°C
MIN
TYP MAX
UNIT
fSMB
SMBus/PMBus operating frequency
PARAMETER
Slave mode; SMBC 50% duty cycle
TEST CONDITIONS
10
1000
kHz
fI2C
IC operating frequency
Slave mode; SCL 50% duty cycle
10
1000
kHz
t(BUF)
Bus free time between start and stop
4.7
µs
t(HD:STA)
Hold time after (repeated) start
0.26
µs
t(SU:STA)
Repeated start setup timed
0.26
µs
t(SU:STO)
Stop setup time
0.26
µs
t(HD:DAT)
Data hold time
0
ns
t(SU:DAT)
Data setup time
50
ns
Receive mode
See
(1)
t(TIMEOUT)
Error signal/detect
t(LOW)
Clock low period
t(HIGH)
Clock high period
See
(2)
t(LOW:SEXT)
Cumulative clock low slave extend time
See
µs
µs
(3)
25
µs
120
ns
120
ns
tFALL
Clock/data fall time
See
tRISE
Clock/data rise time
See
(5)
(3)
(4)
(5)
µs
50
(4)
(1)
(2)
35
0.5
0.26
The UCD9220 times out when any clock low exceeds t(TIMEOUT).
t(HIGH), max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving UCD9220 that is
in progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0).
t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
Rise time tRISE = VILMAX – 0.15) to (VIHMIN + 0.15)
Fall time tFALL = 0.9 V33D to (VILMAX – 0.15)
tr
t(LOW)
tf
VIH
SMBCLK
VIL
t(SU:STA)
t(HIGH)
t(HD:STA)
t(SU:STO)
t(SU:DAT)
t(HD:DAT)
VIH
SMBDATA
VIL
t(BUF)
P
S
S
P
Start
Stop
t(LOW:SEXT)
CLKACK
t(LOW:MEXT)
CLKACK
t(LOW:MEXT)
t(LOW:MEXT)
SMB_CLK
SMB_DATA
Figure 1. I2C/SMBus/PMBus Timing in Extended Mode Diagram
6
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FUNCTIONAL BLOCK DIAGRAM
Digital
High Res
PWM
UCD9220
DPWM-3A
FLT-3A
Fusion Power Peripheral 2
EAP2
EAN2
Analog front end
(AFE)
Digital
High Res
PWM
Compensator
3P/3Z IIR
Digital
High Res
PWM
DPWM-2A
FLT-2A
DPWM-1B
FLT-1B
Fusion Power Peripheral 1
Analog Front End
EAP1
EAN1
Diff
Amp
Ref
Compensator
Err
Amp
Digital
High Res
PWM
IIR
3P/3Z
ADC
6 bit
Coeff.
Regs
DPWM-1A
FLT-1A
SYNC-IN
SYNC -OUT
3
PWR
3
GND
BPCAP
internal
3.3V &
1.8V
regulator
TMUX-0
TMUX-1
Analog Comparators
TRIP1
ARM-7 core
SRE-3A
Ref 1
ADDR-0
ADDR-1
CS-1A
CS-1B
CS-2A
CS-3A
VIN_IIN
Vtrack
Temperature
Flash
memory with
ECC
12-bit
ADC
260 ksps
SRE
control
SRE-2A
SRE-1B
SRE-1A
TRIP2
Ref 2
Osc
TRIP4
Ref 4
POR/BOR
PMBus
PMBus-Clk
PMBus-Data
PMBus-Alert
PMBus-Cntl
internal
Temp sense
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ADCref
AGND2
Temperature
Vtrack
ADDR-0
ADDR-1
CS-1A
V33FB
EAN2
EAP2
EAN1
EAP1
48
47
46
45
44
43
42
41
40
39
38
37
PIN ASSIGNMENT
FLT-1B
7
30
TMS
FLT-2A
8
29
TDI/Sync_In
SRE-1A
9
28
TDO/Sync_Out
PMBus_CLK
10
27
TCK
PMBus_Data
11
26
PowerGood
DPWM-1A
12
25
FLT-3A
24
nTRST
TMUX-1
31
23
6
TMUX-0
FLT-1A
22
DGND1
GPIO-2
32
21
5
GPIO-1
nRESET
20
V33D
PMBus_CNTL
33
19
4
PMBus_Alert
Vin/Iin
18
V33A
SRE-1B
34
17
3
SRE-3A
CS-2A
16
BPCap
DWPM-3A
35
15
2
SRE-2A
CS-1B
14
AGND1
DPWM-2A
36
13
1
DPWM-1B
CS-3A
Figure 2. UCD9220 Pin Assignment
The UCD9220 is available in a plastic 48-pin QFN package (RGZ).
8
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TYPICAL APPLICATION SCHEMATIC
Figure 3 shows the UCD9220 power supply controller as part of a system that provides the regulation of two
independent power supplies. The loop for each power supply is created by the respective voltage outputs feeding
into the differential voltage error ADC (EADC) inputs, and completed by DPWM outputs feeding into the gate
drivers for each power stage (PTD modules in this example).
The ±Vsenserail signals must be routed to the EAp/EAn input that matches the number of the lowest DPWM
configured as part of the rail. (See more detail on page 19, "Flexible Rail/Power Stage Configuration".)
Vin
VBIAS
VIN
UCD7230
Vinput
temp
sensor
FAULT
+3.3V
PTD08A020W
Temp-1
VOUT
PWM
+3.3V
TEMP
SRE
Commutation
logic
Vin/Iin
Temperature
Vin/Iin
FLT-1A
Vtrack
DPWM-1A
Temperature
+Vs1
IOUT
BPCAP
V33D
V33FB
V33A
INH
GND
-Vs1
Vin
SRE-1A
CS-1A
ADCref
Temp-2
+Vs1
-Vs1
+Vs2
-Vs2
FLT-1B
EAP1
DPWM-1B
EAN1
SRE-1B
FAULT
PWM
CS-1B
VBIAS
VIN
TEMP
SRE
PTD08A020W
INH
IOUT
VOUT
GND
EAP2
EAN2
Temp-3
FLT-2A
nTRST
UCD9220
TMS
FAULT
DPWM-2A
PWM
SRE-2A
TDI/Sync_In
CS-2A
VBIAS
VIN
+Vs2
TEMP
SRE
PTD08A010W
INH
IOUT
VOUT
GND
TDO/Sync_Out
TCK
Temp-4
FLT-3A
ADDR-0
DPWM-3A
ADDR-1
SRE-3A
FAULT
PWM
CS-3A
PowerGood
PMBus_Clock
GPIO-1
PMBus_Data
GPIO-2
VBIAS
VIN
TEMP
SRE
PTD08A010W
INH
IOUT
VOUT
GND
-Vs2
PMBus_Alert
PowerPad
DGND1
TMUX-0
AGND2
nRESET
AGND1
PMBus_Cntl
TMUX-1
+3.3V
Vcc
Temp-1
1Y0
1Z
Temperature
Temp-2
1Y1
2Z
Vin/Iin
Temp-3
1Y2
Temp-4
1Y3
S1
S0
CD74HC4052
Vinput
2Y0
Iin
2Y1
E
2Y2
* Iin Optional
2Y3
Gnd
Figure 3. Typical Application Schematic
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PIN DESCRIPTIONS
PIN
DESCRIPTION
NAME
1
CS-3A
Input
Power stage 3A current sense input and input to analog comparator 4
2
CS-1B
Input
Power stage 1B current sense input and input to analog comparator 2
3
CS-2A
Input
Power stage 2A current sense input and input to analog comparator 3
4
Vin/Iin
Input
Input supply sense, alternates between Vin and Iin
5
nRESET
Input
Active low device reset input pullup to 3.3V with a 10 kΩ resistor
6
FLT-1A
Input
External fault input 1A, active high
7
FLT-1B
Input
External fault input 1B, active high
8
FLT-2A
Input
External fault input 2A, active high
9
SRE-1A
Output
10
PMBus_Clk
Input/Out
PMBus Clock pullup to 3.3V with a 10 KΩ resistor
put
11
PMBus_Data
Input/Out
PMBus Data pullup to 3.3V with a 10 KΩ resistor
put
12
DPWM-1A
Output
Digital Pulse Width Modulator output 1A
13
DPWM-1B
Output
Digital Pulse Width Modulator output 1B
14
DPWM-2A
Output
Digital Pulse Width Modulator output 2A
15
SRE-2A
Output
Synchronous rectifier enable 2A, active high
16
DPWM-3A
Output
Digital Pulse Width Modulator output 3A
17
SRE-3A
Output
Synchronous rectifier enable 3A, active high
18
SRE-1B
Output
Synchronous rectifier enable 1B, active high
19
PMBus_Alert
Output
PMBus Alert pullup to 3.3V with a 10 KΩ resistor
20
PMBus_Cntl
Input
Synchronous rectifier enable 1A, active high
PMBus Control pullup to 3.3V with a 10 KΩ resistor
21
GPIO-1
Input/Out
General Purpose Input/Output
put
22
GPIO-2
Input/Out
General Purpose Input/Output
put
23
TMUX-0
Input
Temperature multiplexer select S0, Vin/Iin Select
24
TMUX-1
Input
Temperature multiplexer select S1
25
FLT-3A
Input
External fault input 3A, active high
26
10
I/O
NO.
PowerGood
Input/Out
Power Good Indication
put
27
(JTAG) TCK
Input
28
(JTAG) TDO /
Sync_Out
JTAG Test Clock
Output
29
(JTAG) TDI /
Sync_In
Input
30
(JTAG) TMS
31
(JTAG) nTRST
32
DGND1
Output
33
V33D
Input
Digital core 3.3V supply
34
V33A
Input
Analog 3.3V supply
35
BPCap
Input
1.8V bypass capacitor connection
36
AGND1
Input
Analog Ground
37
EAP1
Input
Error analog, differential voltage. Positive channel #1 input
38
EAN1
Input
Error analog, differential voltage. Negative channel #1 input
39
EAP2
Input
Error analog, differential voltage. Positive channel #2 input
40
EAN2
Input
Error analog, differential voltage. Negative channel #2 input
JTAG Test data out (muxed with Sync_Out for synchronizing switching frequency across
devices)
JTAG Test data in (muxed with Sync_In for synchronizing switching frequency across
devices) pull up to 3.3V with a 10 KΩ resistor
Input/Out
JTAG Test mode select - tie to V33D with 10 kΩ resistor
put
Input/Out
JTAG Test Reset - tie to ground with a 10 KΩ resistor
put
Digital Ground
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PIN DESCRIPTIONS (continued)
PIN
I/O
DESCRIPTION
NO.
NAME
41
V33FB
Output
42
CS-1A
Input
Power stage 1A current sense input and input to analog comparator 1
43
ADDR_1
Input
Address sense. Channel 1
44
ADDR_0
Input
Address sense. Channel 0
45
Vtrack
Input
Voltage Track Input
46
Temperature
Input
Temperature Sense input
47
Agnd2
Input
Analog Ground
48
ADCref
Input
ADC Decoupling Capacitor - Tie 0.1 µF cap to ground
PowerPad
Power Pad
Input
It is recommended that this pad be connected to analog ground
Connection to the base of 3.3V linear regulator transistor (no connect if unused)
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FUNCTIONAL OVERVIEW
The UCD9220 contains two fusion power peripherals (FPP). Each FPP can be configured to regulate up to two
DC/DC converter outputs. There are four PWM outputs that can be assigned to drive the coverter outputs. Each
FPP can be configured to drive from one of the four power stages. Each FPP consists of:
• A differential input error voltage amplifier.
• A 10-bit DAC used to set the output regulation reference voltage.
• A fast ADC with programmable input gain to digitally measure the error voltage.
• A dedicated 3-pole/3-zero digital filter to compensate the error voltage.
• A digital PWM (DPWM) engine that generates the PWM pulse width based on the compensator output.
Each controller is configurable through a PMBus serial interface.
PMBus Interface
The PMBus is a serial interface specifically designed to support power management. It is based on the SMBus
interface that is built on the I2C physical specification. The UCD9220 supports revision 1.1 of the PMBus
standard. Wherever possible, standard PMBus commands are used to support the function of the device. For
unique features of the UCD9220, MFR_SPECIFIC commands are defined to configure or activate those features.
These commands are defined in the UCD92xx PMBUS Command Reference.
The UCD9220 is PMBus compliant, in accordance with the "Compliance" section of the PMBus specification. The
firmware is also compliant with the SMBus 1.1 specification, including support for the SMBus ALERT function.
The hardware can support 100 kHz, 400 kHz, or 1 MHz PMBus operation.
Resistor Programmed PMBus Address Decode
Two pins are allocated to decode the PMBus address. At power-up, the device applies a bias current to each
address detect pin, and the voltage on that pin is captured by the internal 12-bit ADC. The PMBus address is
calculated as follows:
PMBus Address = 12 × bin(VAD01) + bin(VAD00)
(2)
Where bin(VAD0x) is the address bin for one of 8 address as shown in Table 1.
ADDR-0,
ADDR-1
pins
Resistor to
set PMBus
Address
V33D
10 uA
IBIAS
UCD9220
On/Off Control
To 12 -bit ADC
Figure 4. PMBus Address Detection Method
The address bins are defined so that each bin is a constant ratio of the previous bin. This method maintains the
width of each bin relative to the tolerance of the standard 1% resistors. The ratio betweens bins is 1.30.
Table 1. PMBus Address Bins
PMBus ADDRESS
12
RPMBus
PMBus RESISTANCE (kΩ)
open
–
11
210
10
158
9
115
8
84.5
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Table 1. PMBus Address Bins (continued)
PMBus ADDRESS
RPMBus
PMBus RESISTANCE (kΩ)
7
63.4
6
47.5
5
36.5
4
27.4
short
–
A low impedance (short) on either address pin that produces a voltage below the minimum voltage causes the
PMBus address to default to address 126. A high impedance (open) on either address pin that produces a
voltage above the maximum voltage also causes the PMBus address to default to address 126.
The PMBus address can be set to any value ranging from 1 to 126, except address 12. Address 0 is not used
because it is the SMBus General Call address; address 12 is reserved for the PMBus alert response. Also, it is
recommended that address 11 not be used by this device or any other device that shares the PMBus with it,
since it is used in manufacturing to program the device. Further, address 127 cannot be used by this device or
any other device that shares the PMBus with it, since the address is reserved by this device for device
manufacturing test.
Finally, it is recommended that address 126 not be used for any devices on the PMBus, since this is the address
that the UCD9220 defaults to if the address lines are shorted to ground or left open. If any other UCD9220 has a
short or open on its address lines, then its address would conflict with the (programmed) address 126.
If a short or open is detected on the PMBus address pin, then the UCD9220 assigns the address to 126 and
enables the JTAG port. Note: if the JTAG port is enabled in this way then the JTAG pins are not avaliable for
sequencing.
Table 2. PMBus Address Assignment Rules
ADDRESS
STATUS
0
Prohibited
1-10
Avaliable
11
Avoid
12
Prohibited
13-125
Avaliable
126
Avoid
127
Prohibited
REASON
SMBus general address call
Causes confilcts with other devices during program flash updates.
PMBus alert response protocol
Default value; may cause conflicts with other devices.
Used by TI manufacturing for device tests.
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JTAG Interface
The JTAG interface can provide an alternate interface for programming the device. It is disabled by default in
order to enable the sync, and power good status pins with which it is multiplexed. There are three conditions
under which the JTAG interface is enabled:
1. When the ROM_MODE PMBus command is issued.
2. On power-up if the Data Flash is blank. This allows JTAG to be used for writing the configuration parameters
to a programmed device with no PMBus interaction.
3. When an invalid address is detected at power-up. By opening or shorting one of the address pins to ground,
an invalid address can be generated that enables JTAG.
Bias Supply Generator (Series Regulator Controller)
Internally, the circuits in the UCD92XX require 3.3V to operate. This can be provided using an existing 3.3V
power supply or it can be generated from the power supply input voltage using an internal series regulator and
an external transistor. The requirements for the external transistor are that it be an NPN device with a beta of at
least 40. Figure 3 shows the typical application using the external series pass transistor. The base of the
transistor is driven by a 10kΩ resistor to Vin and a transconduction amplifier whose output is on the V33FB pin.
The NPN emitter becomes the 3.3 V supply for the chip and requires bypass capacitors of 0.1 µF and 4.7µF.
A transconductance amplifier sinks current into the V33FB pin, in order to regulate the amount of current allowed
into the base of the transistor, which regulates the collector current, which determines the emitter voltage (3.3 V).
The resistor value should be sized low enough to give efficient base drive at minimum input voltage, yet large
enough to not exceed the maximum current sink capability of the V33FV pin at maximum input voltage. Higher
beta transistors help in increasing the minimum resistance value, as less base current is needed to sufficiently
drive the higher beta transistor. A resistor value of 10 KΩ works well for most applications that use the FCX491A
BJT.
Some circuits in the device require 1.8V that is generated internally from the 3.3V supply. This voltage requires a
0.1 to 1 µF bypass capacitor from BPCap to ground.
Vin
To Power Stage
FCX491A
+3.3V
4.7uF
10kΩ
+1.8V
V33A
V33D
BPCap
0.1uF
V33FB
0.1uF
UC9220
Figure 5. 3.3V Regulator Circuit
Power On Reset
The UCD9220 has an integrated power-on reset (POR) circuit that monitors the supply voltage. At power-up, the
POR circuit detects the V33D rise. When V33D is greater than VIH, the device initiates and internal startup
sequence. At the end of the startup sequence, the device begins normal operation, as defined by the
downloaded device PMBus configuration.
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External Reset
The device can be forced into the reset state by an external circuit connected to the nRESET pin. A logic low
voltage on this pin holds the device in reset. To avoid an erroneous trigger caused by noise, a 10 kΩ pull up
resistor to 3.3V is recommended.
Output Voltage Adjustment
The nominal output voltage is programmed by a combination of PMBus commands: VOUT_COMMAND,
VOUT_CAL_OFFSET, and VOUT_MAX. Their relationship is shown in Figure 6. Output voltage margining is
configured by the VOUT_MARGIN_HIGH and VOUT_MARGIN_LOW commands. The OPERATION command
selects between the nominal output voltage and either of the margin voltages. The OPERATION command also
includes an option to suppress certain voltage faults and warnings while operating at the margin settings.
OPERATION
Command
VOUT_MAX
VOUT_MARGIN_HIGH
3:1
Mux
VOUT_COMMAND
+
Limiter
VOUT_
SCALE_
LOOP
“Reference
Voltage
Equivalent”
VOUT_MARGIN_LOW
VOUT_CAL_OFFSET
Figure 6. PMBus Voltage Adjustment Methods
For a complete description of the commands supported by the UCD9220 see the UCD92xx PMBUS Command
Reference. Each of these commands can also be issued from the Texas Instruments Fusion Digital Power™
Designer program. This Graphical User Interface (GUI) PC program issues the appropriate commands to
configure the UCD9220 device.
Calibration
To optimize the operation of the UCD9220, PMBus commands are supplied to enable fine calibration of output
voltage, output current, and temperature measurements. The supported commands and related calibration
formulas may be found in the UCD92xx PMBUS Command Reference.
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Analog Front End (AFE)
GAFE = 1, 2, 4, or 8
EAP
Vead
EAN
6-bit result
eADC
GeADC = 8mV/LSB
Vref DAC
CPU
Vref = 1.563 mV/LSB
PMBus
Figure 7. Analog Front End Block Diagram
The UCD9220 senses the power supply output voltage differentially through the EAP and EAN pins. The error
amplifier utilizes a switched capacitor topology that provides a wide common mode range for the output voltage
sense signals. The fully differential nature of the error amplifier also ensures low offset performance.
The output voltage is sampled at a programmable time (set by the EADC_SAMPLE_TRIGGER PMBus
command). When the differential input voltage is sampled, the voltage is captured in internal capacitors and then
transferred to the error amplifier where the value is subtracted from the set-point reference which is generated by
the 10-bit Vref DAC as shown in Figure 7. The resulting error voltage is then amplified by a programmable gain
circuit before the error voltage is converted to a digital value by the flash ADC. This programmable gain is
configured through the PMBus and affects the dynamic range and resolution of the sensed error voltage as
shown in Table 3.
Table 3. Analog Front End Resolution
AFE GAIN
AFE_GAIN for
PMBus COMMAND
EFFECTIVE ADC
RESOLUTION (mV)
DIGITAL ERROR
VOLTAGE DYNAMIC
RANGE (mV)
1
0
8
-256 to 248
2
1
4
-128 to 124
4
2
2
-64 to 62
8
3
1
-32 to 31
The AFE variable gain is one of the compensation coefficients that are stored when the device is configured by
issuing the CLA_GAINS PMBus command. Compensator coefficients are arranged in several banks: one bank
for start/stop ramp or tracking, one bank for normal regulation mode and one bank for light load mode. This
allows the user to trade-off resolution and dynamic range for each operational mode.
The EADC, which samples the error voltage, has high accuracy, high resolution, and a fast conversion time.
However, its range is limited as shown in Table 3. If the output voltage is different from the reference by more
than this, the EADC reports a saturated value at -32 LSBs or 31 LSBs. The UCD9220 overcomes this limitation
by adjusting the Vref DAC up or down in order to bring the error voltage out of saturation. In this way, the
effective range of the ADC is extended. When the EADC saturates, the Vref DAC is slewed at a rate of 0.156
V/ms, referred to the EA differential inputs.
The differential feedback error voltage VEA = VEAP – VEAN. For brief instances, VEA may go as high as the
maximum value of VDIFF; however, the steady-state commanded voltage must be less than the maximum value
of Vref, which is lower. An attenuator network using resistors R1 and R2 should be used to ensure that VEA does
not exceed the maximum value of VDIFF when operating at the commanded voltage level.
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R1
EAP
+Vout
C2
R2
Rin
Ioff
-Vout
EAN
Figure 8. Input Offset Equivalent Circuit
To obtain the best possible accuracy, the input resistance and offset current on the device should be considered
when calculating the gain of a voltage divider between the output voltage and the EA sense inputs of the
UCD9220. The input resistance and input offset current are specified in the parametric tables in this datasheet.
VEA = VEAP – VEAN in the equation below.
VEA =
R2
R1R 2
VOUT +
æR R ö
æR R
R1 + R 2 + ç 1 2 ÷
R1 + R 2 + ç 1 2
R
è IN ø
è RIN
ö
÷
ø
IOFF
(3)
The effect of the offset current can be reduced by making the resistance of the divider network low. R1 should be
between 1kΩ and 5kΩ. Then R2, the lower divider resistor, can be calculated as:
R1VEA
R2 =
æ
R ö
VOUT - ç1 + 1 ÷ VEA ± R1IOFF
è RIN ø
(4)
EAP/EAN Voltage Sense Filtering
Conditioning should be provided on the EAP and EAN signals. Figure 8 shows a divider network between the
output voltage and the voltage sense input to the controller. The resistor divider is used to bring the output
voltage within the dynamic range of the controller. When no attenuation is needed, R2 can be left open and the
signal conditioned by the low-pass filter formed by R1 and C2.
As with any power supply system, maximize the accuracy of the output voltage by sensing the voltage directly
across an output capacitor, and route the positive and negative differential sense signals as a balanced pair of
traces or as a twisted pair cable back to the controller. Put the divider network close to the controller. This
ensures that there is a low impedance driving the differential voltage sense signal from the voltage rail output
back to the controller. The resistance of the divider network is a trade-off between power loss and minimizing
interference susceptibility. A parallel resistance of 1k to 4kΩ is a good compromise.
R1 =
RP
K
R2 =
RP
1-K
where K =
VEA
VOUT
and R P =
R1R 2
R1 + R 2
(5)
It is recommended that a capacitor be placed across the lower resistor of the divider network. This acts as an
additional pole in the compensation and as an anti-alias filter for the EADC. To be effective as an anti-alias filter,
the corner frequency should be 35% to 40% of the switching frequency. Then the capacitor is calculated as:
1
C2 =
2p ´ 0.35 ´ FSW ´ RP
(6)
Digital Compensator
Each voltage rail controller in the UCD9220 includes a digital compensator. The compensator consists of a
nonlinear gain stage, followed by a digital filter consisting of a second order infinite impulse response (IIR) filter
section cascaded with a first order IIR filter section.
The Texas Instruments Fusion Digital Power™ Designer development tool can be used to assist in defining the
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compensator coefficients. The design tool allows the compensator to be described in terms of the pole
frequencies, zero frequencies and gain desired for the control loop. In addition, the Fusion Digital Power™
Designer can be used to characterize the power stage so that the compensator coefficients can be chosen based
on the total loop gain for each feedback system. The coefficients of the filter sections are generated through
modeling the power stage and load.
Additionally, the UCD9220 has three banks of filter coefficients: Bank-0 is used during the soft start/stop ramp or
tracking; Bank-1 is used while in regulation mode; and Bank-2 is used when the measured output current is
below the configured light load threshold.
Limit 3
Limit 2
Limit 1
Limit 0
Threshold
logic
B01
B11
B21
X
Gain 4
Gain 3
Gain 2
Gain 1
Gain 0
+
X
X
z
-1
z
-1
X
+
Clamp
+
z-1
z-1
X
X
Nonlinear Gain Block
2nd Order Filter Section
A11
A21
Duty out
eADC
B12
z-1
X
+
Clamp
z-1
X
1st Order Filter Section A21
Figure 9. Digital Compensator
The nonlinear gain block allows a different gain to be applied to the system when the error voltage deviates from
zero. Typically Limit 0 and Limit 1 would be configured with negative values between –1 and –32 and Limit 2 and
Limit 3 would be configured with positive values between 1 and 31. However, the gain thresholds do not have to
be symmetrical. For example, the four limit registers could all be set to positive values causing the Gain 0 value
to set the gain for all negative errors and a nonlinear gain profile would be applied to only positive error voltages.
The cascaded 1st order filter section is used to generate the third zero and third pole.
DPWM Engine
The output of the compensator feeds the high resolution DPWM engine. The DPWM engine produces the pulse
width modulated gate drive output from the device. In operation, the compensator calculates the necessary duty
cycle as a digital number representing a percentage from 0 to 100%. The duty cycle value is multiplied by the
configured period to generate a comparator threshold value. This threshold is compared against the high speed
switching period counter to generate the desired DPWM pulse width. This is shown in Figure 10.
Each DPWM engine can be synchronized to another DPWM engine or to an external sync signal via the
SYNC_IN and SYNC_OUT pins. Configuration of the synchronization function is done through a MFR_SPECIFIC
PMBus command. See the DPWM Synchronization section for more details.
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DPWM Engine (1 of 4)
SysClk
SyncIn
Clk
high
res
reset
ramp
counter
Switch period
S
PWM gate drive
R
output
Current balance adj
Compensator output
EADC
(calculated duty cycle)
trigger
EADC trigger
threshold
SyncOut
Figure 10. DPWM Engine
Flexible Rail/Power Stage Configuration
The UCD9220 can control one to two voltage rails, each of which can comprise a programmable number of
power stages (up to a maximum of four). The following table shows all possible rail / power stage configurations.
Configuration is made through the PHASE_INFO command which is described in detail in the UCD92xx PMBus
Command Reference.
Power Stage Configurations (1)
NUMBER OF STAGES
RAIL #1 : RAIL #2
RAIL #1 POWER STAGES
RAIL #2 POWER STAGES
4:0
1A, 1B, 2A, 3A
(none)
3:0
1A, 1B, 2A
(none)
2:0
1A, 1B
(none)
1:0
1A
(none)
3:1
1A, 1B, 3A
2A
2:1
1A, 1B
2A
1:1
1A
2A
2:2
1A, 1B
2A, 3A
1:2
1A
1:3
(1)
2A, 3A
Invalid (use 3 : 1 instead)
0:4
Invalid (use 4: 0 instead)
0:3
Invalid (use 3 : 0 instead)
0:2
Invalid (use 2 : 0 instead)
0:1
Invalid (use 1 : 0 instead)
Phases should be selected in the order listed. For a two single phase rail configuration, power stage selections should be 1A and 2A.
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DPWM Phase Distribution
When two rails are configured, the UCD9220 offsets (in time) the phase of the 1st power stage assigned to each
rail in order to minimize input current ripple. The constant time used for this offset is:
3
t rail-rail spread = t SW
13
(7)
Where tSW is the period of the rail with the fastest switching frequency.
The ratio 3/13 is chosen because it is close to 1/4, but it is a prime ratio. This should ensure that any
configuration of rails and power stages should not have the leading edge of the DPWM signal aligned.
The PHASE_INFO PMBus command is also used to configure the number of power stages driving each voltage
rail. When multiple power stages are configured to drive a voltage rail, the UCD9220 automatically distributes the
phase of each DPWM output to minimize ripple. This is accomplished by setting the rising edge of each DPWM
pulse to be separated by:
t
t phase-phase spread = SW
NPhases
(8)
Where tSW is the switching period and NPhases is the number of power stages driving a voltage rail.
DPWM Synchronization
DPWM synchronization provides a method to link the timing between rails on two distinct devices at the switching
rate; i.e., two rails on different devices can be configured to run at the same frequency and sync forcing them not
to drift from each other. (Note that within a single device, because all rails are driven off a common clock there is
no need for an internal sync because rails will not drift.)
The PMBus SYNC_IN_OUT command sets which rails (if any) should follow the sync input, and which rail (if
any) should drive the sync output.
For rails that are following the sync input, the DPWM ramp timer for that output is reset when the sync input goes
high. This allows the slave device to sync to inputs that are either faster or slower than it is. On the fast side,
there is no limit to how much faster the input is compared to the defined frequency of the rail; when the pulse
comes in, the timer is reset and the frequencies are locked. This is the standard mode of operation - setting the
slave to run slower, and letting the sync speed it up.
If the slave rail is running fast, the sync pulse resets the counter after the DPWM output has already been turned
on. Resetting the counter at this point results in a larger duty cycle for that period. Because the system is closed
loop; however, the controller reacts by decreasing the commanded control effort, with the result being a
regulated rail synchronized to a slower master. Synchronizing to the slower master does have a limit however. If
the master is slow enough that the DPWM output has sufficient time to output the entire command pulse before
the sync input arrives, the result is a double pulse. This is likely an undesirable mode of operation.
The Sync Input and Output Configuration Word set by the PMBus command consists of two bytes. The upper
byte (sync_out) controls which rail drives the sync output signal (0=DWPM1, 1=DPWM2, 2=DPWM3, 3=DPWM4.
Any other value disables sync_out). The lower byte (sync_in) determines which rail(s) respond to the sync input
signal (each bit represents one rail - note that multiple rails can be synchronized to the input). The DPWM period
is aligned to the sync input. For more information, see the UCD92xx PMBUS Command Reference.
Note that once a rail is synchronized to an external source, the rail-to-rail spacing that attempts to minimize input
current ripple are lost. Rail-to-rail spacing can only be restored by power cycling or issuing a SOFT_RESET
command.
Phase Shedding at Light Current Load
By issuing LIGHT_LOAD_LIMIT_LOW, LIGHT_LOAD_LIMIT_HIGH, and LIGHT_LOAD_CONFIG commands, the
UCD9220 can be configured to shed (disable) power stages when at light load. When this feature is enabled, the
device disables the configured number of power stages when the average current drops below the specified
LIGHT_LOAD_LIMIT_LOW. In addition, a separate set of compensation coefficients can be loaded into the
digital compensator when entering a light load condition.
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Phase Adding at Normal Current Load
After shedding phases, if the current load is increased past the LIGHT_LOAD_LIMIT_HIGH threshold, all phases
are re-enabled. If the compensator was configured for light load, the normal load coefficients are restored as
well. See the UCD92xx PMBUS Command Reference for more information.
Current Sense Input Filtering
Each power stage current is monitored by the device at the CS pins. There are 3 "A" channel pins and 1 "B"
channel pin. The B channels monitors the current with a 12-bit ADC and samples each current sense voltage in
turn. The A channels monitor the current with the same12-bit ADC and also monitor the current with a digitally
programmable analog comparator.
Because the current sense signal is digitally sampled, it should be conditioned with an RC network acting as an
anti-alias filter. Since the sample rate for the CS inputs is 1/ tIout, a good cutoff frequency for the RC network is
from 2 kHz to 3 kHz.
Output Current Measurement
Pins CS-1A, CS-1B, CS-2A, and CS-3A are used to measure either output current or inductor current in each of
the controlled power stages. PMBus commands IOUT_CAL_GAIN and IOUT_CAL_OFFSET are used to
calibrate each measurement. See the UCD92xx PMBus Command Reference for specifics on configuring this
voltage to current conversion.
When the measured current is outside the range of either the over-current or under-current fault threshold, a
current fault is declared and the UCD9220 performs the PMBus configured fault recovery. ADC current
measurements are digitally averaged before they are compared against the current fault threshold. The output
current is measured at a rate of one output rail per tIout microseconds. The current measurements are then
passed through a digital smoothing filter to reduce noise on the signal and prevent false errors. The output of the
smoothing filter asymptotically approaches the input value with a time constant that is approximately 3.5 times
the sampling interval.
Table 4. Output Current Filter Times Constants
NUMBER OF OUTPUT RAILS
OUTPUT CURRENT SAMPLING
INTERVALS (µs)
FILTER TIME CONSTANTS (ms)
1
200
0.7
2
400
1.4
3
600
2.1
4
800
2.8
For example, with a single rail, the filter has the transfer function characteristics (Figure 11) that shows the signal
magnitude at the output of the averaging filter due to a sine wave input for a range of frequencies. This plot
includes an RC analog low pass network, with a corner frequency of 3 kHz, on the current sense inputs.
This averaged current measurement is used for output current fault detection; see Over-current Detection below.
In response to a PMBus request for a current reading, the device returns an average current value. When the
UCD9220 is configured to drive a multi-phase power converter, the device adds the average current
measurement for each of the power stages tied to a power rail.
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0
-5
-10
-15
dB
-20
-25
-30
-35
-40
-45
-50
10
100
1.0k
freq in Hz
10k
100k
Figure
1 AveragingFilter
filter for
monitoring
Figure
11. Averaging
forcurrent
Current
Monitoring
Output Current Balancing
When the UCD9220 is configured to drive multiple power stage circuits from one compensator, current balancing
is implemented by adjusting each gate drive output pulse width to correct for current imbalance between the
connected power stage sections. The UCD9220 balances the current by monitoring the current at the CS analog
input for each power stage and then adding a current balance adjustment value to the DPWM ramp threshold
value for each power stage.
When there is more than one power stage connected to the voltage rail, the device continually determines which
stage has the highest measured current and which stage has the lowest measured current. To balance the
currents while maintaining a constant total current, the adjustment value for the power stage with the lowest
current is increased by the same amount as the adjustment value for the power stage with the highest current is
decreased. A slight modification to this algorithm is made to keep the adjustment values positive in order to
ensure that a positive DPWM duty cycle is commanded under all conditions.
Over-Current Detection
Several mechanisms are provided to sense output current fault conditions. This allows for the design of power
systems with multiple layers of protection.
1. An integrated gate driver such as the UCD7230 can be used to generate the FLT signal. The UCD7230
monitors the voltage drop across the high side FET and if it exceeds a resistor/voltage programmed
threshold, the UCD7230 activates its fault output. The FLT input can be disabled by reconfiguring the FLT
pin to be a sequencing pin in the GUI. A logic high signal on the FLT input causes a hardware interrupt to the
internal CPU. The CPU then determines which DPWM outputs are configured to be associated with the
voltage rail that contained the fault and disables those DPWM and SRE outputs. This process takes about 14
microseconds.
2. Inputs CS-1A, CS-1B, CS-2A and CS-3A each drive an internal analog comparator. These comparators can
be used to detect the voltage output of a current sense circuit. Each comparator has a separate PMBus
configurable threshold. This threshold is set by issuing the FAST_OC_FAULT_LIMIT command. Though the
command is specified in amperes, the hardware threshold is programmed with a value between 31mV and
2V in 64 steps. The relationship between the amperes to sensed volts is configured using the
IOUT_CAL_GAIN command. When the current sense voltage exceeds the configured threshold the
corresponding DPWM and SRE outputs are driven low on the voltage rail with the fault.
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3. Each Current Sense input to the UCD9220 is also monitored by the 12-bit ADC. Each measured value is
scaled using the IOUT_CAL_GAIN and IOUT_CAL_OFFSET commands. The currents for each power stage
configured as part of a voltage rail are summed and compared to the OC limit set by the
IOUT_OC_FAULT_LIMIT command. The action taken when a fault is detected is defined by the
IOUT_OC_FAULT_RESPONSE command.
Because the current measurement is averaged with a smoothing filter, the response time to an Over-current
condition depends on a combination of the time constant (τ) from Table 4, the recent measurement history,
and how much the measured value exceeds the over-current limit. When the current steps from a current (I1)
that is less than the limit to a higher current (I2) that is greater than the limit, the output of the smoothing filter
is:
-t ö
æ
t ÷
ç
1
e
=
+
I
I
I
(
)
2 1
Ismoothed (t ) 1
ç
÷
è
ø
(9)
At the point when Ismoothed exceeds the limit, the smoothing filter lags time, tlag is:
æ I -I ö
tlag = t ln ç 2 1 ÷
è I2 - Ilimit ø
(10)
The worst case response time to an over-current condition is the sum of the sampling interval (see Table 4) and
the smoothing filter lag, tlag from the equation above.
Current Foldback Mode
When the measured output current exceeds the value specified by the IOUT_OC_FAULT_LIMIT command, the
UCD9220 attempts to continue to operate by reducing the output voltage in order to maintain the output current
at the value set by IOUT_OC_FAULT_LIMIT. This continues indefinitely as long as the output voltage remains
above the minimum value specified by IOUT_OC_LV_FAULT_LIMIT. If the output voltage is pulled down to less
than that value, the device responds as programmed by the IOUT_OC_LV_FAULT_RESPONSE command.
Input Voltage and Current Monitoring
The Vin/Iin pin on the UCD9220 monitors the input voltage and current. To measure both input voltage and input
current, an external multiplexer is required, see Figure 3. If measurement of only the input voltage, and not input
current, is desired, then a multiplexer is not needed. The multiplexer is switched between voltage and current
using the TMUX-0 signal. (This signal is the LSB of the temperature mux select signals, so the TMUX-0 signal is
connected both to the temperature multiplexer as well as the voltage/current multiplexer). When TMUX-0 is low,
the Vin/Iin pin will be sampled for Vin. When TMUX-0 is high, the Vin/Iin pin will be sampled for Iin. The Vin/Iin pin is
monitored using the internal 12-bit ADC which has a dynamic range of 0 to 2.5V. The fault thresholds for the
input voltage are set using the VIN_OV_FAULT_LIMIT and VIN_UV_FAULT_LIMIT commands. The scaling for
Vin is set using the VIN_SCALE_MONITOR command, and the scaling for Iin is set using the
IIN_SCALE_MONITOR command.
Temperature Monitoring
Both the internal device temperature and up to four external temperatures are monitored by the UCD9220. The
controller supports multiple PMBus commands related to temperature, including READ_TEMPERATURE_1,
which reads the internal temperature, READ_TEMPERATURE_2, which reads the external power stage
temperatures, OT_FAULT_LIMIT, which sets the over temperature fault limit, and OT_FAULT_RESPONSE,
which defines the action to take when the configured limit is exceeded.
If more than one external temperature is to be measured, the UCD9220 provides analog multiplexer select pins
(TMUX0-1) to allow up to 4 external temperatures to be measured. The output of the multiplexer is routed to the
Temperature pin. The controller cycles through each of the power stage temperature measurement signals. The
signal from the external temperature sensor is expected to be a linear voltage proportional to temperature. The
PMBus commands TEMPERATURE_CAL_GAIN and TEMPERATURE_CAL_OFFSET are used to scale the
measured temperature-dependent voltage to °C.
The inputs to the multiplexer are mapped in the order that the outputs are assigned in the PHASE_INFO PMBus
command. For example, if only one power stage is wired to each DPWM, the two temperature signals should be
wired to the first two multiplexer inputs.
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The UCD9220 monitors temperature using the 12-bit monitor ADC, sampling each temperature in turn with a 800
ms sample period. These measurements are smoothed by a digital filter, similar to that used to smooth the
output current measurements. The filter has a time constant 15.5 times the sample interval, or 12.4 s (15.5 × 800
ms = 12.4 seconds). This filtering reduces the probability of false fault detections.
Figure 3 is an example of a system with two output voltage rails where each output is driven by 2 power stages.
The first output voltage rail is driven with DPWM-1A and DPWM-1B. The second output voltage rail is driven with
DPWM-2A and DPWM-3A. The order in which the temperature multiplexer inputs are assigned is shown in
Table 5.
Table 5. Temperature Sensor Mapping
TEMPERATURE MUX INPUT
POWER STAGE
1Y0
DPWM-1A
1Y1
DPWM-1B
1Y2
DPWM-2A
1Y3
DPWM-3A
Temperature Balancing
Temperature balancing between phases is performed by adjusting the current such that cooler phases draw a
larger share of the current. Temperature balancing occurs slowly (the loop runs at a 10 Hz rate), and only when
the phase currents exceeds the PMBus settable TEMP_BALANCE_IMIN. This minimum current threshold
prevents the controller from "winding up" and forcing one phase to carry all the current under a low-load
condition, when the total current may be insufficient to significantly affect phase temperatures.
Soft Start, Soft Stop Ramp Sequence
The UCD9220 performs soft start and soft stop ramps under closed loop control. Performing a start or stop ramp
or tracking is considered a separate operational mode. The other operational modes are normal regulation and
light load regulation. Each operational mode can be configured to have an independent loop gain and
compensation. Each set of loop gain coefficients is called a "bank" and is configured using the CLA_GAINS
PMBus command.
Start ramps are performed by waiting for the configured start delay TON_DELAY and then ramping the internal
reference toward the commanded reference voltage at the rate specified by the TON_RISE time and
VOUT_COMMAND. The DPWM and SRE outputs are enabled when the internal ramp reference equals the
preexisting voltage (pre-bias) on the output and the calculated DPWM pulse width exceeds the pulse width
specified by DRIVER_MIN_PULSE. This ensures that a constant ramp rate is maintained, and that the ramp is
completed at the same time it would be if there were not a pre-bias condition.
The behavior of soft-stop ramps depends on how the voltage rail is configured. If PAGE_ISOLATED is set to 1
through the PAGE_ISOLATED PMBus command, the controller assumes that it is the only device driving the
voltage rail, and the soft-stop ramp is performed with SRE enabled until the voltage associated with the
configured minimum supported pulse width is reached. If PAGE_ISOLATED is set to 0, the controller assumes
that multiple power stages may be supplying the voltage rail and SRE is disabled at the beginning of the
soft-stop ramp. Figure 12 shows the operation of soft-start ramps and soft-stop ramps.
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Soft-Start
Soft-Stop
1.2
1.2
1.0
1.0
0.8
0.8
Start into a pre-bias
0.6
Volts
Volts
Bridged, 0.45-V bias
0.4
0.6
Unbridged,
0.45-V bias
0.4
PWM begins here with pre-bias
0.2
0.2
Unbridged,
no bias
Start from zero
0
0
PWM begins here from 0 output voltage
–0.2
–0.2
0
2
4
6
8
10
12
14
16
0
2
Time ms
4
6
8
10
12
14
16
Time ms
Figure 12. Start and Stop Ramps
When a voltage rail is in its idle state, the DPWM and SRE outputs are disabled, and the differential voltage on
the EAP/EAN pins are monitored by the controller. During idle the Vref DAC is adjusted to minimize the error
voltage. If there is a pre-bias (that is, a non-zero voltage on the regulated output), then the device can begin the
start ramp from that voltage with a minimum of disturbance. This is done by calculating the duty cycle that is
required to match the measured voltage on the rail. Nominally this is calculated as Vout / Vin; however, to allow
for losses and offsets in the system, PREBIAS_GAIN and PREBIAS_OFFSET can be used for fine tuning. If the
pre-bias voltage on the output requires a smaller pulse width than the driver can deliver, as defined by the
DRIVER_MIN_PULSE PMBus command, then the start ramp is delayed until the internal ramp reference voltage
has increased to the point where the required duty cycle exceeds the specified minimum duty.
Once a soft start/stop ramp has begun, the output is controlled by adjusting the Vref DAC at a fixed rate and
allowing the digital compensator control engine to generate a duty cycle based on the error. The Vref DAC
adjustments are made at a rate of 10 kHz and are based on the TON_RISE or TOFF_FALL PMBus configuration
parameters.
Although the presence of a pre-bias voltage or a specified minimum DPWM pulse width affects the time when
the DPWM and SRE signals become active, the time from when the controller starts processing the turn-on
command to the time when it reaches regulation is TON_DELAY plus TON_RISE, regardless of the pre-bias or
minimum duty cycle.
During a normal ramp (i.e. no tracking, no current limiting events and no EADC saturation), the Vref slews at a
pre-calculated rate based on the commanded output voltage and TON_RISE. Under closed loop control, the
compensator follows this ramp up to the regulation point.
Because the EADC in the controller has a limited range, it may saturate due to a large transient during a
start/stop ramp. If this occurs, the controller overrides the calculated Vref ramp value, and adjusts the Vref DAC
in the direction to minimize the error. It continues to step the Vref DAC in this direction until the EADC comes out
of saturation. Once it is out of saturation, the start ramp continues, but from this new Vref voltage; and therefore,
has an impact on the ramp time.
Input Under-Voltage Lockout
The UCD9220 monitors the input voltage throught the Vin/Iin pin and adjusts this value by VIN_SCALE. The input
supply voltage lock-out thresholds are configured with the VIN_ON and VIN_OFF commands. When input supply
voltage drops below the value set by VIN_OFF, the device starts a normal soft stop ramp. When the input supply
voltage drops below the voltage set by VIN_UV_FAULT_LIMIT, the device performs per the configuration using
the VIN_UV_FAULT_RESPONSE command. For example, when the bias supply for the controller is derived
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from another source, the response code can be set to "Continue" or "Continue with delay," and the controller
attempts to finish the soft stop ramp. If the bias voltages for the controller and gate driver are uncertain below
some voltage, the user can set the UV fault limit to that voltage and specify the response code to be "shut down
immediately" disabling all DPWM and SRE outputs. VIN_OFF sets the voltage at which the output voltage
soft-stop ramp is initiated, and VIN_UV_FAULT_LIMIT sets the voltage where power conversion is stopped.
Voltage Tracking
Each voltage rail can be configured to operate in a tracking mode. When a voltage rail is configured to track
another voltage rail, it adjusts the Vref to follow the master, which can be either the other internal rail or the
external Vtrack pin. As in standard non-tracking mode, a target Vout is still specified for the voltage rail. If the
tracking input exceeds this target, the tracking voltage rail stops following the master signal, switches to
regulation gains, and regulates at the target voltage. When the tracking input drops back below the target (with
20 mV of hysteresis), tracking gains are re-loaded, and the voltage rail follows the tracking reference. Note that
the target can be set above the range of the tracking input, forcing the voltage rail to always remain in tracking
mode.
During tracking, the setpoint DAC is permitted to change only as fast as is possible without inducing the EADC to
saturate. This limit may be reached if the master ramps at an extremely fast rate, or if the master is at a
significantly different voltage when the rail is turned on. As in normal regulation, a current limit (current foldback)
or the detection of the EADC saturating forces the rail to temporarily deviate from the tracking reference.
The PMBus command TRACKING_SOURCE is available to enable tracking mode and select the master to track.
The tracking mode is set individually for each rail, allowing each rail to have a different master, both rails to share
a master, or one rail to track while the other remains independent. Additionally, TRACKING_SCALE_MONITOR
permits tracking a voltage with a fixed ratio to a master voltage. For example, a ratio of 0.5 causes the rail to
regulate at one half of the master’s voltage.
Sequencing
There are three methods to squence voltage rails controlled by the UCD9220 that allow for a variety of system
sequencing configurations. Each of these options is configurable in the GUI. These methods include:
1. Use the PMBus to set the soft start/stop parameters for each rail. Multiple start/stop sequences may be
triggered simultaneously. Each voltage rail performs its sequencing in an open-loop manner. If any rail fails
to complete its sequence, all other rails are unaffected.
2. Daisy-chain the PowerGood output signal from one controller to the PMBus-CNTL input on another.
3. Use the GPIO_SEQ_CONFIG command to assign dependencies between rails, or to configure unused pins
as sequencing control inputs or sequencing status outputs.
Method 1: Each rail has programmable delay times, TON_DELAY and TOFF_DELAY, before beginning a soft
start ramp or a soft stop ramp, and programmable ramp times, TON_RISE and TOFF_FALL determine how long
the ramp takes. These PMBus commands are defined in the UCD92xx PMBUS Command Reference. The
parameters can also be configured using the Fusion Digital Power™ Designer GUI (see
http://focus.ti.com/docs/toolsw/folders/print/fusion_digital_power_designer.html). The configurable times can be
used to program a time based sequence for each voltage rail. Using this method each rail ramps independently
and completes the ramp regardless of the success of the other rails.
The start/stop sequence is initiated for a single rail by the PMBus-CNTL pin or via the PMBus using the
OPERATION or ON_OFF_CONTROL commands.
The start/stop sequence may be initiated simultaneously for multiple rails within the same controller by
configuring each rail to respond to the PMBus-CNTL pin. Alternatively, after setting the PMBus PAGE variable to
255, subsequent OPERATION or ON_OFF_CONTROL commands applies to all rails at the same time.
To simultaneously initiate start/stop sequences in multiple controllers, a common PMBus-CNTL signal can be fed
into each controller. Alternatively, the PMBus Group Command Protocol may be used to send separate
commands to multiple controllers. All the commands are sent in one continuous transmission and wait for the
final STOP signal in order to start executing their commands simultaneously.
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Method 2: The PowerGood pin can be used to coordinate multiple controllers by running the PowerGood pin
output from one controller to the PMBus-CNTL input pin of another. This imposes a master/slave relationship
between multiple devices. During startup, the slave controllers initiates their start sequences after the master
completes its start sequence and reaches its regulation voltage. During shut-down, as soon as the master starts
its shut-down sequence, the shut-down signals to its slaves.
Unlike Method 1, a shut-down on one or more rails on the master can initiate shut-downs of the slave devices.
The master shut-downs can initiate intentionally or by a fault condition.
The PMBus specification implies that the PowerGood signal is active when ALL the rails in a controller are above
their power-good “on” threshold setting. The UCD9220 allows the PowerGood pin to be reprogrammed using the
GPIO_SEQ_CONFIG command so that the pin responds to a desired subset of rails.
This method works to coordinate multiple controllers, but it does not enforce interdependency between rails
within a single controller.
Method 3: Using the GPIO_SEQ_CONFIG command, several sequencing options can be configured using
undedicated pins for input/output. As many as four pins can be configured as inputs, and as many as eight as
outputs. The outputs can be open-drain or actively driven with selectable polarity.
Each rail can be configured to respond to a combination of the power-good status of other internal rails and/or
the state of sequencing input pins. The output pins can be configured to reflect the power-good status of a
combination of rails, or to one of several status indicators including power-good, an Overcurrent warning, or the
“open-drain outputs valid” signal.
When using the output signals for sequencing, they may be routed to sequencing control inputs or to the
PMBus-CNTL inputs on other controllers.
Once each rail’s input dependencies are configured, the rail responds to those input pins or internal rails. Like
method 2, shut-downs on one rail or controller can initiate shut-downs of other rails or controllers. Unlike method
2, GPIO_SEQ_CONFIG offers much more flexibility in assigning relationships between multiple rails within a
single controller or between multiple controllers. It is possible for each controller to be both a master and a slave
to another controller.
GPIO_SEQ_CONFIG allows the configuration of fault relationships such that a fault on one rail can result in the
shut down of any selection of rails in addition to the rail at fault. These fault interactions are not constrained to a
single master/slave relationship; for example, a system can be configured such that a fault on any rail shuts
down all rails. If the fault response of the failing rail is to shut down immediately, all dependent rails follow suit
and shuts down immediately regardless of their programmed response code.
Each rail can be optionally configured to monitor a sequencing input pin for a specified period of time after it
turns on and reaches its power good threshold. If the programmable timeout is reached before the input pin state
matches its defined logic level, the rail is shut down, and a status error posted. This feature could be used, for
example, to ensure that an LDO on the board did turn on when the main system voltage came up. Each rail is
enabled independently of the other rails and has a unique timeout value; a single input pin is used as the timeout
source.
The setup of the GPIO_SEQ_CONFIG command is aided by the use of the Fusion Digital Power™ Designer,
which graphically displays relationships between rails and provides intuitive controls to allocate and configure
available resources.
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The following pins are available for use as GPIO or sequencing control, provided they are not being used for
their primary purpose:
PIN NAME
48-PIN
DPWM-1A
IN/OUT
DPWM-1B
IN/OUT
DPWM-2A
IN/OUT
DPWM-3A
IN/OUT
FAULT-1A
IN/OUT
FAULT-2A
IN/OUT
FAULT-3A
IN/OUT
FAULT-4A
IN/OUT
SRE-1A
IN/OUT
SRE-1B
IN/OUT
SRE-2A
IN/OUT
SRE-3A
IN/OUT
PowerGood
IN/OUT
GPIO_1
IN/OUT
GPIO_2
IN/OUT
Non-volatile Memory Error Correction Coding
The UCD9220 uses Error Correcting Code (ECC) to improve data integrity and provide high reliability storage of
Data Flash contents. ECC uses dedicated hardware to generate extra check bits for the user data as it is written
into the Flash memory. This adds an additional six bits to each 32-bit memory word stored into the Flash array.
These extra check bits, along with the hardware ECC algorithm, allow for any single bit error to be detected and
corrected when the Data Flash is read.
ADCref Pin
ACDref pin is the decoupling pin of the ADC12. Connect this pin to ground through a 0.1µF – 1µF capacitor.
General Purpose I/O Pin
The UCD9220 has 2 general purpose I/O pins that can be use for sequencing. For more information about
sequencing see the sequencing section above and the GPIO_SEQ_CONFIG command in the UDC92xx PMBus
Command Reference.
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APPLICATION INFORMATION
Calculation of Open Loop Gain Using the UCD9220
When designing a power supply it is necessary to determine the stability of the closed loop system. The usual
way to do this is to determine the open loop gain versus frequency and from the open loop gain determine the
gain margin and phase margin. Figure 13 shows a block diagram of a complete control loop using the UDC9220.
Each component of the loop gain that is a function of frequency is labeled "Gx". Constant gain components are
labeled "Kx".
CONSTANT GAIN COMPONENTS
DESCRIPTION
Transfer function for the power stage circuit consisting of the FET switches, LC output filter
and load.
Gplant
Gdiv
Transfer function for the VOUT sense divider and its capacitive filter network.
KAFE
Analog fron-end amplifier gain.
KEADC
Gain of the 6-bit EADC in units of LSBs/V
Gdelay
Phase shift due to the delays in the control loop.
Knonlinear
Nonlinear function gain. Gain for the limit interval that contains zero error.
GCLA2
Transfer function of the second order filter section of the compensator.
GCLA1
Transfer function of the first order filter section of the compensator.
KPWM
Accounts for the bit resolution of the input to the DPWM
Vin
Gplant(f)
Gdiv(f)
Vout
divider
Power Stage
PMBus
UCD9220
UCD9240
KPWM
GCLA1
GCLA2
Knonlinear
VrefDAC
CPU
Gdelay
KEADC
+
KAFE
Figure 13. Loop Gain Contributions
Several of the gain blocks are programmable. They are configured by issuing a CLA_GAINS command over the
PMBus. The syntax for this command is shown in the UCD92xx PMBUS Command Reference. These gains can
also be configured using the Fusion Digital Power™ Designer PC program.
Automatic System Identification (Auto-ID™)
By using digital circuits to create the control function for a switch-mode power supply, additional features can be
implemented. One of those features is the measurement of the open loop gain and stability margin of the power
supply without the use of external test equipment. This capability is called automatic system identification or
Auto-ID™. To identify the frequency response, the UCD9220 internally synthesizes a sine wave signal and
injects it into the loop at the set point DAC. This signal excites the system, and the closed-loop response to that
excitation can be measured at another point in the loop. The UCD9220 measures the response to the excitation
at the output of the digital compensator. From the closed-loop response, the open-loop transfer function is
calculated. The open-loop transfer function may be calculated from the closed-loop response.
Note that since the compensator and DPWM are digital, their transfer functions are known exactly and can be
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divided out of the measured open-loop gain. In this way the UCD9220 can accurately measure the power
stage/load plant transfer function in situ (in place), on the factory floor or in an end equipment application and
send the measurement data back to a host through the PMBus interface without the need for external test
equipment. Details of the Auto-ID™ PMBus measurement commands can be found in the UCD92xx PMBus
Command Reference.
Output Voltage Margining
The UCD9220 supports Voltage Margining using the PMBus VOUT_MARGIN_HIGH and VOUT_MARGIN_LOW
commands in conjunction with the OPERATION command. The margin voltages can be configured at device
configuration and saved into Data Flash. The output can be commanded to switch between Margin High,
Nominal, and Margin Low using bits [3:2] of the OPERATION command.
Data Logging
The UCD9220 maintains a data log in non-volatile memory. This log tracks the peak internal and external
temperature measurements, peak current measurements, and fault history. The PMBus commands and data
format for data logging can be found in the UCD92xx PMBUS Command Reference.
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
UCD9220RGZR
ACTIVE
QFN
RGZ
48
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
UCD9220RGZT
ACTIVE
QFN
RGZ
48
250
CU NIPDAU
Level-3-260C-168 HR
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Mar-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
UCD9220RGZR
QFN
RGZ
48
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
UCD9220RGZT
QFN
RGZ
48
250
180.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Mar-2009
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UCD9220RGZR
QFN
RGZ
48
2500
346.0
346.0
33.0
UCD9220RGZT
QFN
RGZ
48
250
190.5
212.7
31.8
Pack Materials-Page 2
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