PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD72870A IEEE1394 1-CHIP OHCI HOST CONTROLLER The µPD72870A is the LSI which integrated OHCI-Link and PHY function into a single chip. The µPD72870A complies with the P1394a draft 2.0 specifications and the OpenHCI IEEE1394 1.0, and works up to 400 Mbps. It makes design so compact for PC and PC card application. FEATURES • Compliant with Link Layer Services as defined in 1394 Open Host Controller Interface specification release 1.0 • Compliant with Physical Layer Services as defined in P1394a draft 2.0 (Data Rate 100/200/400 Mbps) • Numbers of supported port (1, 2, 3 ports) are selectable • Compliant with protocol enhancement as defined in P1394a draft 2.0 • Modular 32-bit host interface compliant to PCI Specification release 2.1 • Support PCI-Bus Power Management Interface Specification release 1.0 • Modular 32-bit host interface compliant to Card Bus Specification • Cycle Master and Isochronous Resource Manager capable • Built-in FIFOs for isochronous transmit (1024 bytes), asynchronous transmit (1024 bytes), and receive (2048 bytes) • 32-bit CRC generation and checking for receive/transmit packets • 4 isochronous transmit DMAs and 4 isochronous receive DMAs supported • 32-bit DMA channels for physical memory read/write • Clock generation by 24.576 MHz X’tal • Internal control and operational registers direct-mapped to PCI configuration space • 2-wire Serial EEPROMTM interface supported • Separate power supply Link and PHY • Programmable latency timer from serial EEPROM in Cardbus mode (CARD_ON = 1) ORDERING INFORMATION Part number Package µPD72870AGM-8ED 160-pin plastic LQFP (Fine pitch) (24 x 24) µPD72870AF1-FA2 192-pin plastic FBGA (14 x 14) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S14653EJ1V0DS00 (1st edition) Date Published January 2000 NS CP (K) Printed in Japan 2000 µPD72870A Firewarden™ ROADMAP Firewarden Series PC Application OHCI Link µPD72862 IEEE1394-1995 Core Development OHCI Link µPD72861 OHCI Link µPD72860 1 Chip OHCI+PHY µPD72870A 800M/1.6G P1394.b Link µPD7286x 1 Chip OHCI+PHY µPD72870 Link Core 1997 2 1998 1999 Preliminary Data Sheet S14653EJ1V0DS00 2000 2001 µPD72870A BLOCK DIAGRAMS Top Block Diagram Serial ROM Interface PCI Bus/ Cardbus Link PHY Cable Interface PHY Signal Preliminary Data Sheet S14653EJ1V0DS00 3 µPD72870A PHY Block Diagram Cable Port1 PHY Control Signal (CMC,PC0-PC2) Arbitration and Control State Machine Logic Link Interface I/O PHY/Link Interface Transmit Data Encoder Cable Power Status 4 Cable Interface Cable Port3 Receive Data Decoder and Retimer Remark Cable Port2 Cable Port: Preliminary Data Sheet S14653EJ1V0DS00 Voltage and Current Generator Crystal Oscillator PLL System and Transmit Clock Generator PHY Signal µPD72870A Link Block Diagram PCI Controller Interface (Master, Parity Check & Generator) Byte Buf Swap PCI-DMA IOREG CSR (CIS) PFCOMM OPCI Internal Bus PCIS Bus (PCI Slave Bus) PCIS_CNT PCICFG ATDMA Byte Swap ATF Byte Swap ITF ITCF PAU GRSU OPCIBUS_ARB Byte RF Swap GRQU RCF ITDMA IOREG Link Layer Core PHY/Link Interface PCI Bus / Cardbus Interface Serial ROM Interface IRDMA0IRDMA3 SFIDU ATDMA : Asynchronous Transmit DMA ATF : Asynchronous Transmit FIFO CIS : CIS Register CSR : Control and Status Registers IOREG : IO Registers IRDMA : Isochronous Receive DMA ITCF : Isochronous Transmit Control FIFO ITDMA : Isochronous Transmit DMA ITF : Isochronous Transmit FIFO OPCIBUS_ARB : OPCI Internal Bus Arbitration PAU : Physical Response and Request Unit PCICFG : PCI Configuration Registers PCIS_CNT : PHY Control Isochronous Control PFCOMM : Pre Fetch Command FIFO RCF : Receive Control FIFO RF : Receive FIFO SFIDU : Self-ID DMA Preliminary Data Sheet S14653EJ1V0DS00 5 µPD72870A PIN CONFIGURATION • 160-pin plastic LQFP (Fine pitch) (24 x 24) µPD72870AGM-8ED 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 DGND IC(L) IC(L) CARD_ON CIS_ON GROM_EN GROM_SCL GROM_SDA DGND L_VDD DGND P_DVDD P_AVDD P_AVDD P_AVDD AGND AGND AGND AGND AGND TpA0p TpA0n TpB0p TpB0n TpA1p TpA1n TpB1p TpB1n TpA2p TpA2n TpB2p TpB2n TpBias0 TpBias1 TpBias2 P_AVDD AGND CPS RI1 RI0 Top View 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DGND STOP PERR SERR PAR L_VDD CBE1 DGND AD15 AD14 PCI_VDD AD13 AD12 DGND AD11 AD10 AD9 AD8 L_VDD CBE0 AD7 AD6 AD5 AD4 DGND AD3 AD2 AD1 AD0 PCI_VDD DGND L_VDD PIN_EN IC(N) IC(H) IC(N) IC(N) IC(N) IC(N) DGND 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 L_V D D CLKRUN PME INTA PRST PCLK GNT REQ DGND PCI_V D D AD31 AD30 AD29 AD28 DGND AD27 AD26 AD25 AD24 L_V D D DGND CBE3 IDSEL AD23 AD22 AD21 AD20 DGND AD19 AD18 PCI_V D D AD17 AD16 DGND CBE2 FRAME IRDY TRDY DEVSEL L_V D D 6 Preliminary Data Sheet S14653EJ1V0DS00 P_AVDD AGND XO XI P_AVDD FIL0 FIL1 AGND AGND P_AVDD P_RESETB DGND P_DVDD P_AVDD SUS_RESM PORTDIS DGND P_DVDD IC(L) IC(L) IC(H) IC(H) DGND P_DVDD CMC PC2 PC1 PC0 IC(N) IC(L) DGND IC(L) IC(N) IC(N) IC(N) DGND IC(N) IC(N) IC(N) L_V D D µPD72870A • 192-pin plastic FBGA (14 x 14) µPD72870AF1-FA2 Bottom View Top View 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 T R P N M L K J H G F E D C B A A B C D E F G H J K L M N P R T Index mark Remark : Pin connected on the FBGA board. Preliminary Data Sheet S14653EJ1V0DS00 7 8 µPD72870AF1-FA2 Top View Preliminary Data Sheet S14653EJ1V0DS00 A B C D E 16 RI0 RI1 AGND XO FIL0 15 CPS AGND XI FIL1 14 TpBias2 TpBias1 TpBias0 P_AV 13 TpB2n TpB2p AGND P_AV 12 TpA2n TpA2p AGND P_AV 11 TpB1n TpB1p AGND P_AVDD PCI_V 10 TpA1n TpA1p AGND AGND L_V 9 TpB0n TpB0p AGND AGND L_V 8 TpA0n TpA0p AGND 7 AGND AGND AGND 6 AGND 5 4 3 1 DD DD DGND P_AV L_V DD DD DD GROM_SDA GROM_SCL GROM_EN CIS_ON L_V DD CLKRUN H J K L M N P PORTDIS IC(L) CMC PC1 IC(L) IC(N) IC(N) L_V DGND IC(H) PC2 PC0 DGND IC(N) IC(N) IC(N) IC(N) IC(H) P_DV IC(N) IC(L) DGND IC(N) IC(N) IC(N) DGND P_DV IC(N) L_V PIN_EN IC(N) IC(H) DD DGND AD1 AD0 DD DGND AD3 AD2 DD DGND AD5 AD4 DD CBE0 AD7 AD6 AGND DGND DGND AD9 AD8 AGND DGND DGND AD11 AD10 AD13 AD12 P_AV G P_RESETB P_AVDD P_AV DD SUS_RESM DD AGND DGND P_DV DD AGND DGND P_DV DD DD P_DV DD IC(L) DD DD P_DV DD PCI_V DD PCI_V DD L_V DGND IC(L) DD DGND PCI_V DGND PCI_V DGND DGND L_V DGND DGND DGND DD L_V L_V DD DGND DGND DGND DGND DD DD R PCI_V DD T DD DGND DD DGND AD15 AD14 DGND DGND PAR CBE1 DD PERR SERR PCI_V L_V CARD_ON IC(L) DGND PME PRST GNT AD31 AD29 AD27 AD25 CBE3 AD23 AD21 AD19 AD17 CBE2 IRDY STOP INTA PCLK REQ AD30 AD28 AD26 AD24 IDSEL AD22 AD20 AD18 AD16 FRAME TRDY DEVSEL DD DD DD µPD72870A 2 P_DV P_AV P_AV F µPD72870A PIN NAME AD0-AD31 : PCI Multiplexed Address and Data PME AGND : Analog GND PORTDIS : Port Disable PRST : Reset CBE0-CBE3 : Command/Byte Enables P_AVDD : PHY Analog VDD CIS_ON : CIS Register ON P_DVDD : PHY Digital VDD CLKRUN : PCICLK Running P_RESETB : PHY Power on Reset Input CMC : Configuration Manager Capable REQ : Bus_master Request CPS : Cable Power Status Input RI0 : Resistor0 for Reference Current Setting DEVSEL : Device Select RI1 : Resistor1 for Reference Current Setting DGND : Digital GND SERR : System Error FIL0 : APLL Filter GND STOP : PCI Stop FIL1 : APLL Filter Terminal SUS_RESM : Suspend/Resume Function Select FRAME : Cycle Frame TpA0n : Port-1 Twisted Pair A Negative Input/Output GNT : Bus_master Grant CARD_ON : PCI/Card Select : PME Output TpA0p : Port-1 Twisted Pair A Positive Input/Output GROM_EN : Serial EEPROM Enable TpA1n : Port-2 Twisted Pair A Negative Input/Output GROM_SCL : Serial EEPROM Clock Output TpA1p : Port-2 Twisted Pair A Positive Input/Output GROM_SDA : Serial EEPROM Data Input / Output TpA2n : Port-3 Twisted Pair A Negative Input/Output IC(H) : Internally Connected (High Clamped) TpA2p : Port-3 Twisted Pair A Positive Input/Output IC(L) : Internally Connected (Low Clamped) TpB0n : Port-1 Twisted Pair B Negative Input/Output IC(N) : Internally Connected (Open) TpB0p : Port-1 Twisted Pair B Positive Input/Output IDSEL : ID Select TpB1n : Port-2 Twisted Pair B Negative Input/Output INTA : Interrupt TpB1p : Port-2 Twisted Pair B Positive Input/Output IRDY : Initiator Ready TpB2n : Port-3 Twisted Pair B Negative Input/Output L_VDD : VDD for Link Digital Core and Link I/Os TpB2p : Port-3 Twisted Pair B Positive Input/Output PAR : Parity TpBias0 : Port-1 Twisted Pair Bias Voltage Output PC0-PC2 : Power Class Input TpBias1 : Port-2 Twisted Pair Bias Voltage Output PCI_VDD : VDD for PCI I/Os TpBias2 : Port-3 Twisted Pair Bias Voltage Output PCLK : PCI Clock TRDY : Target Ready PERR : Parity Error XI : X’tal XI PIN_EN : Pin Enable Input XO : X’tal XO Preliminary Data Sheet S14653EJ1V0DS00 9 µPD72870A CONTENTS 1. PIN FUNCTIONS ................................................................................................................................... 12 1.1 PCI/Cardbus Interface Signals: (52 pins)..................................................................................... 12 1.2 Cable Interface Signals: (15 pins) ................................................................................................ 13 1.3 PHY Signals: (9 pins)..................................................................................................................... 14 1.4 PHY Control Signals: (5 pins) ....................................................................................................... 14 1.5 PCI/Cardbus Select Signals: (2 pins) ........................................................................................... 15 1.6 Serial ROM Interface Signals: (3 pins) ......................................................................................... 15 1.7 Miscellaneous Signal: (1 pin)........................................................................................................ 15 1.8 IC: (21 pins) .................................................................................................................................... 16 1.9 VDD ................................................................................................................................................... 16 1.10 GND ............................................................................................................................................... 16 2. PHY REGISTERS .................................................................................................................................. 17 2.1 Complete Structure for PHY Registers ........................................................................................ 17 2.2 Port Status Page (Page 000) ......................................................................................................... 20 2.3 Vendor ID Page (Page 001) ........................................................................................................... 21 3. CONFIGURATION REGISTERS........................................................................................................... 22 3.1 PCI Bus Mode Configuration Register (CARD_ON = Low) ........................................................ 22 3.1.1 Offset_00 Vendor ID Register............................................................................................................ 23 3.1.2 Offset_02 Device ID Register ............................................................................................................ 23 3.1.3 Offset_04 Command Register ........................................................................................................... 23 3.1.4 Offset_06 Status Register.................................................................................................................. 24 3.1.5 Offset_08 Revision ID Register.......................................................................................................... 25 3.1.6 Offset_09 Class Code Register ......................................................................................................... 25 3.1.7 Offset_0C Cache Line Size Register ................................................................................................. 25 3.1.8 Offset_0D Latency Timer Register..................................................................................................... 25 3.1.9 Offset_0E Header Type Register....................................................................................................... 25 3.1.10 Offset_0F BIST Register................................................................................................................... 25 3.1.11 Offset_10 Base Address 0 Register................................................................................................. 26 3.1.12 Offset_20 Subsystem Vendor ID Register ....................................................................................... 26 3.1.13 Offset_22 Subsystem ID Register.................................................................................................... 26 3.1.14 Offset_30 Expansion Rom Base Address Register ......................................................................... 26 3.1.15 Offset_34 Cap_Ptr Register............................................................................................................. 26 3.1.16 Offset_3C Interrupt Line Register .................................................................................................... 27 3.1.17 Offset_3D Interrupt Pin Register...................................................................................................... 27 3.1.18 Offset_3E Min_Gnt Register ............................................................................................................ 27 3.1.19 Offset_3F Max_Lat Register ............................................................................................................ 27 3.1.20 Offset_40 PCI_OHCI_Control Register ........................................................................................... 27 3.1.21 Offset_60 Cap_ID & Next_Item_Ptr Register .................................................................................. 28 3.1.22 Offset_62 Power Management Capabilities Register ...................................................................... 28 3.1.23 Offset_64 Power Management Control/Status Register .................................................................. 29 3.2 CardBus Mode Configuration Register (CARD_ON = High) ...................................................... 30 3.2.1 Offset_14/18 10 Base_Address_1/2 Register (Cardbus Status Registers) ............................................ 31 3.2.2 Offset_28 Cardbus CIS Pointer ......................................................................................................... 32 3.2.3 Offset_80 CIS Area............................................................................................................................ 32 Preliminary Data Sheet S14653EJ1V0DS00 µPD72870A 4. PHY FUNCTION .................................................................................................................................... 33 4.1 Cable Interface ............................................................................................................................... 33 4.1.1 Connections .......................................................................................................................................... 33 4.1.2 Cable Interface Circuit .......................................................................................................................... 34 4.1.3 CPS....................................................................................................................................................... 34 4.1.4 Unused Ports ........................................................................................................................................ 34 4.2 Suspend/Resume........................................................................................................................... 35 4.2.1 Suspend/Resume On Mode (SUS_RESM = 1)..................................................................................... 35 4.2.2 Suspend/Resume Off Mode (SUS_RESM = 0)..................................................................................... 35 4.3 PLL and Crystal Oscillation Circuit.............................................................................................. 36 4.3.1 Crystal Oscillation Circuit...................................................................................................................... 36 4.3.2 PLL ....................................................................................................................................................... 36 4.4 PC0-PC2, CMC................................................................................................................................ 36 4.5 P_RESETB ...................................................................................................................................... 36 4.6 RI0, RI1 ............................................................................................................................................ 36 5. SERIAL ROM INTERFACE .................................................................................................................. 37 5.1 Serial EEPROM Register ............................................................................................................... 37 5.2 Serial EEPROM Register Description .......................................................................................... 37 5.3 Load Control................................................................................................................................... 42 5.4 Programming Sequence Example................................................................................................ 42 6. ELECTRICAL SPECIFICATIONS ......................................................................................................... 44 7. APPLICATION CIRCUIT EXAMPLE.................................................................................................... 47 8. PACKAGE DRAWINGS ........................................................................................................................ 48 Preliminary Data Sheet S14653EJ1V0DS00 11 µPD72870A 1. PIN FUNCTIONS 1.1 PCI/Cardbus Interface Signals: (52 pins) (1/2) Name I/O Pin No. LQFP PAR I/O 45 IOL Volts(V) Function PCI/Cardbus 5/3.3 Parity is even parity across AD0-AD31 and CBE0- FBGA R4 Link *1 CBE3. It is an input when AD0-AD31 is an input; it is an output when AD0-AD31 is an output. AD0-AD31 I/O 11-14, E1,E2, 16-19, F1,F2, 24-27, G1,G2, 29,30,32, H1,H2, 33,49,50, K1,K2, 52,53, L1,L2, 55-58, M1,M2, 61-64, N1,N2, 66-69 R5-R12, PCI/Cardbus 5/3.3 PCI Multiplexed Address and Data Link - 5/3.3 Command/Byte Enables are multiplexed Bus Link T5-T12 CBE0-CBE3 FRAME I I/O 22,35,47, J2,P2,P9, 60 T4 36 P1 Commands & Byte enables. PCI/Cardbus 5/3.3 Frame is asserted by the initiator to indicate the Link cycle beginning and is kept asserted during the burst cycle. If Cardbus mode (CARD_ON = 1), this pin should be pulled up to VDD. TRDY I/O 38 R1 PCI/Cardbus 5/3.3 Target Ready indicates that the current data phase Link of the transaction is ready to be completed. IRDY I/O 37 R2 PCI/Cardbus 5/3.3 Initiator Ready indicates that the current bus Link master is ready to complete the current data phase. During a write, its assertion indicates that the initiator is driving valid data onto the data bus. During a read, its assertion indicates that the initiator is ready to accept data from the currentlyaddressed target. REQ O 8 D1 PCI/Cardbus 5/3.3 Bus_master Request indicates to the bus arbiter GNT I 7 D2 - 5/3.3 Bus_master Grant indicates to this device that Link that this device wants to become a bus master. Link access to the bus has been granted. IDSEL I 23 J1 - 5/3.3 Initialization Device Select is used as chip select for configuration read/write transaction during the phase of device initialization. If Cardbus mode (CARD_ON = 1), this pin should be pulled up to VDD. 12 Preliminary Data Sheet S14653EJ1V0DS00 Link µPD72870A (2/2) Name I/O Pin No. LQFP DEVSEL I/O 39 IOL Volts(V) PCI/Cardbus 5/3.3 Function FBGA T1 Device Select when actively driven, indicates that Link the driving device has decoded its address as the target of the current access. STOP I/O 42 T2 PCI/Cardbus 5/3.3 PCI Stop when actively driven, indicates that the Link target is requesting the current bus master to stop the transaction. PME O 3 B2 PCI/Cardbus 5/3.3 PME Output for power management enable. Link CLKRUN I/O 2 A1 PCI/Cardbus 5/3.3 PCICLK Running as input, to determine the status Link of PCLK; as output, to request starting or speeding up clock. INTA O 4 B1 PCI/Cardbus 5/3.3 Interrupt the PCI interrupt request A. Link PERR I/O 43 R3 PCI/Cardbus 5/3.3 Parity Error is used for reporting data parity errors Link during all PCI transactions, except a Special Cycle. It is an output when AD0-AD31 and PAR are both inputs. It is an input when AD0-AD31 and PAR are both outputs. SERR O 44 T3 PCI/Cardbus 5/3.3 System Error is used for reporting address parity Link errors, data parity errors during the Special Cycle, or any other system error where the effect can be catastrophic. When reporting address parity errors, it is an output. PRST I 5 C2 - 5/3.3 Reset PCI reset Link PCLK I 6 C1 - 5/3.3 PCI Clock 33 MHz system bus clock. Link IOL Volts(V) 1.2 Cable Interface Signals: (15 pins) (1/2) Name I/O Pin No. LQFP Function FBGA TpA0p I/O 140 B8 - - Port-1 Twisted Pair A Positive Input/Output Note TpA0n I/O 139 A8 - - Port-1 Twisted Pair A Negative Input/Output Note Note TpB0p I/O 138 B9 - - Port-1 Twisted Pair B Positive Input/Output TpB0n I/O 137 A9 - - Port-1 Twisted Pair B Negative Input/Output Note TpA1p I/O 136 B10 - - Port-2 Twisted Pair A Positive Input/Output Note Note TpA1n I/O 135 A10 - - Port-2 Twisted Pair A Negative Input/Output TpB1p I/O 134 B11 - - Port-2 Twisted Pair B Positive Input/Output Note TpB1n TpA2p I/O I/O 133 132 A11 B12 - - Port-2 Twisted Pair B Negative Input/Output Port-3 Twisted Pair A Positive Input/Output Note Note Note TpA2n I/O 131 A12 - - Port-3 Twisted Pair A Negative Input/Output TpB2p I/O 130 B13 - - Port-3 Twisted Pair B Positive Input/Output Note TpB2n I/O 129 A13 - - Port-3 Twisted Pair B Negative Input/Output Note PHY Analog *2 PHY Analog PHY Analog PHY Analog PHY Analog PHY Analog PHY Analog PHY Analog PHY Analog PHY Analog PHY Analog PHY Analog Note If unused port, please refer to 4.1.4 Unused Ports. Preliminary Data Sheet S14653EJ1V0DS00 13 µPD72870A (2/2) Name I/O Pin No. LQFP PORTDIS I 105 IOL Volts(V) Function FBGA H16 *3 Port Disable PHY Digital SUS_RESM = 1 This selected state will be loaded to Disabled bit which allocated PHY register Port Status Page. 1:Disable At this time, all ports will be disabled. SUS_RESM = 0 PORTDIS has no effect. SUS_RESM I 106 G15 Suspend/Resume Function Select PHY Digital 1 : Suspend/Resume On (P1394a draft 2.0 compliant) 0 : Suspend/Resume Off (P1394a draft 1.3 compliant) CPS I 123 A15 - - IOL Volts(V) Cable Power Status Input Note PHY Digital Note Please refer to 4.1.3 CPS. 1.3 PHY Signals: (9 pins) Name I/O Pin No. LQFP Function FBGA TpBias0 O 128 C14 - - Port-1 Twisted Pair Bias Voltage Output Note 1 PHY Analog TpBias1 O 127 B14 - - Port-2 Twisted Pair Bias Voltage Output Note 1 PHY Analog - Port-3 Twisted Pair Bias Voltage Output Note 1 PHY Analog Note 2 PHY Analog TpBias2 O 126 A14 - RI0 - 121 A16 - - Resistor0 for Reference Current Setting RI1 - 122 B16 - - Resistor1 for Reference Current Setting Note 2 PHY Analog FIL1 - 114 E15 - - APLL Filter Terminal (No need to assemble) PHY Analog FIL0 - 115 E16 - - APLL Filter GND (No need to assemble) PHY Analog XI I 117 D15 - - X’tal XI PHY Analog XO O 118 D16 - - X’tal XO PHY Analog Notes 1. If unused port, please refer to 4.1.4 Unused Ports. 2. Please refer to 4.6 RI0, RI1. 1.4 PHY Control Signals: (5 pins) Name I/O Pin No. LQFP PC0-PC2 I 93-95 IOL Volts(V) Function - 3.3 Power Class Input Note 1 - 3.3 Configuration Manager Capable Note 1 FBGA K15,L15, PHY Digital L16 CMC I P_RESETB I 96 110 K16 F16 PHY Power on Reset Input Notes 1. Please refer to 4.4 PC0-PC2, CMC. 2. Please refer to 4.5 P_RESETB. 14 Preliminary Data Sheet S14653EJ1V0DS00 Note 2 PHY Digital PHY Digital µPD72870A 1.5 PCI/Cardbus Select Signals: (2 pins) Name I/O Pin No. LQFP IOL Volts(V) Function FBGA CARD_ON I 157 B3 - 3.3 PCI/Card Select (1:Cardbus, 0:PCI bus) Link CIS_ON I 156 A3 - 3.3 CIS Register ON Link CARD_ON CIS_ON CIS PME 0 1 Off PME 0 0 On CSTSCHG 1 X On CSTSCHG 1.6 Serial ROM Interface Signals: (3 pins) Name I/O Pin No. LQFP IOL Volts(V) Function FBGA GROM_SDA I/O 153 A4 6 mA 3.3 Serial EEPROM Data Input / Output Link GROM_SCL O 154 B4 6 mA 3.3 Serial EEPROM Clock Output Link GROM_EN I 155 C4 - 3.3 Serial EEPROM Enable Link (1: GUID Load enabled, 0: GUID Load disabled) 1.7 Miscellaneous Signal: (1 pin) Name I/O Pin No. LQFP PIN_EN I 73 IOL Volts(V) - 5/3.3 Function FBGA P13 Pin Enable Input (High clamped) Link 1.8 IC: (21 pins) Name I/O Pin No. LQFP IC(H) IOL Volts(V) Function FBGA I 75 T13 - - Internally Connected (High clamped) Link I 99,100 J14,J15 - - Internally Connected (High clamped) PHY Digital IC(L) I 89,158,159 C3,D4,M14 - - Internally Connected (Low clamped) Link I 91,101,102 H13,J16,M16 - - Internally Connected (Low clamped) PHY Digital IC(N) - 74,76-79, L14,M13,N15,N16, - - Internally Connected (Open) - 82-84,86-88,92 P14-P16,R13-R15, T14,T15 Preliminary Data Sheet S14653EJ1V0DS00 15 µPD72870A 1.9 VDD Name I/O Pin No. LQFP PCI_VDD - IOL Volts(V) Function - 5/3.3 - 3.3 - 3.3 PHY digital VDD PHY Digital FBGA 10,31,51,70 E3,F3,N3,N6, VDD for PCI I/Os Link VDD for Link digital Core and Link N11,N12,P6 L_VDD - P_DVDD - 1,20,40,46,59,72,81, A2,C5,J4,K4,L4,N5, 151 N9,N10,N13,P3,R16 97,103,107,108,149 A5,G13,G14,G16, Link I/Os H14,K13,K14,L13 P_AVDD - 111 F15 - 3.3 PHY PLL VDD PHY Analog - 116 D14 - 3.3 PHY PLL, OSC VDD PHY Analog - 120,125 C15,D11-D13 - 3.3 PHY Bias VDD PHY Analog - 146-148 B6,C6,D6 - 3.3 PHY Port VDD PHY Analog IOL Volts(V) - - Digital GND 1.10 GND Name I/O Pin No. LQFP DGND - 9,15,21,28,34,41,48, Function FBGA B5,D3,D5,E4,F4,F13, 54,65,71,80,85,90,98, F14,G3,G4,H3,H4, 104,109,150,152,160 H15,J3,J13,K3,L3, M3,M4,M15,N4,N7, N8,N14,P4,P5,P7,P8, P10-P12,T16 AGND - 112 E13 - - PHY PLL GND - 113 E14 - - PHY PLL, OSC GND - 119,124 B15,C16 - - PHY Bias GND - 141 A7 - - PHY Common GND - 142 B7 - - PHY Speed Signal GND - 143,144,145 A6,C7-C13,D7-D10 - - PHY Port GND [Caution] *1: If the Link pin is pulled up, it should be connected to L_VDD. *2: If the PHY Digital pin is pulled up, it should be connected to P_DVDD. *3: If the PHY Analog pin is pulled up, it should be connected to P_AVDD. 16 Preliminary Data Sheet S14653EJ1V0DS00 µPD72870A 2. PHY REGISTERS 2.1 Complete Structure for PHY Registers Figure 2-1. Complete Structure of PHY Registers 0 1 2 RHB IBR 0000 0001 3 4 5 Physical_ID 0010 0011 6 7 R PS Gap_count Extended (7) Reserved Total_ports Delay Max_speed Reserved 0100 Link_active Contender Jitter 0101 Resume_int ISBR Loop Pwr_class Pwr_fail 0110 Timeout Port_event Enab_accel Enab_multi Reserved 0111 Page_select Reserved 1000 Register0 (page_select) 1001 Register1 (page_select) 1010 Register2 (page_select) 1011 Register3 (page_select) 1100 Register4 (page_select) 1101 Register5 (page_select) 1110 Register6 (page_select) 1111 Register7 (page_select) Port_select Table 2-1. Bit Field Description (1/3) Field Size R/W Reset value Physical_ID 6 R 000000 R 1 R 0 Description Physical_ID value selected from Self_ID period. If this bit is 1, the node is root. 1: Root 0: Not root PS 1 R Cable power status. 1: Cable power on 0: Cable power off RHB 1 R/W 0 Root Hold -off bit. If 1, becomes root at the bus reset. IBR 1 R/W 0 Initiate bus reset. Setting to 1 begins a long bus reset. Long bus reset signal duration: 166 µs. Returns to 0 at the beginning of bus reset. Gap_count 6 R/W 111111 Gap count value. It is updated by the changes of transmitting and receiving the PHY configuration packet Tx/Rx. The value is maintained after first bus reset. After the second bus reset it returns to reset value. Preliminary Data Sheet S14653EJ1V0DS00 17 µPD72870A Table 2-1. Bit Field Description (2/3) Field Size R/W Reset value Description Extended 3 R 111 Shows the extended register map. Total_ports 4 R 0011 Supported port number. 0011: 3 ports Max_speed 3 R 010 Indicate the maximum speed that this node supports. 010: 98.304, 196.608 and 393.216 Mbps Delay 4 R 0010 Link_active 1 R/W 1 Indicate worst case repeating delay time. 144 + (2 x 20) = 184 ns Link active. 1: Enable 0: Disable The logical AND status of this bit and LPS. State will be referred to “L bit” of Self-ID Packet#0. The LPS is a PHY/Link interface signal and is defined in P1394a draft 2.0. It is an internal signal in the µPD72870A. Contender 1 R/W See Contender. Description “1” indicate this node support bus manager function. This bit will be referred to “C bit” of Self-ID Packet#0. The reset data is depending on CMC pin setting. CMC pin condition 1: Pull up (Contender) 0: Pull down (Non Contender) Jitter 3 R Pwr_class 3 R/W 010 The difference of repeating time (Max.-Min.). (2+1) x 20 = 60 ns See Power class. Description Please refer to IEEE1394 -1995 [4.3.4.1]. This bit will be referred to Pwr field of Self-ID Packet#0. The reset data will be determined by PC0-PC2 Pin status. Resume_int 1 R/W 0 ISBR 1 R/W 0 Resume interrupt enable. When set to 1, if any one port does resume, the Port_event bit becomes 1. Initiate short (arbitrated) bus reset. Setting to 1 acquires the bus and begins short bus reset. Short bus reset signal output : 1.3 µs Returns to 0 at the beginning of the bus reset. Loop 1 R/W 0 Loop detection output. 1: Detection Writing 1 to this bit clears it to 0. Writing 0 has no effect. Pwr_fail 1 R/W 0 Power cable disconnect detect. It becomes 1 when there is a change from 1 to 0 in the CPS bit. Writing 1 to this bit clears it to 0. Writing 0 has no effect. Timeout 1 R/W 0 Arbitration state machine time-out. Writing 1 to this bit clears it to 0. Writing 0 has no effect. 18 Preliminary Data Sheet S14653EJ1V0DS00 µPD72870A Table 2-1. Bit Field Description (3/3) Field Port_event Size R/W Reset value 1 R/W 0 Description Set to 1 when the Int_Enable bit in the register map of each port is 1 and there is a change in the ports connected, Bias, Disabled and Fault bits. Set to 1 when the Resume_int bit is 1 and any one port does resume. Writing 1 to this bit clears it to 0. Writing 0 has no effect. Enab_accel 1 R/W 0 Enables arbitration acceleration. Ack-acceleration and Fly-by arbitration are enabled. 1: Enabled 0: Disabled If this bit changes while the bus request is pending, the operation is not guaranteed. Enab_multi 1 R/W 0 Enable multi-speed packet concatenation. Setting this bit to 1 follows multi-speed transmission. When this bit is set to 0,the packet will be transmitted with the same speed as the first packet. Page_select 3 R/W 000 Select page address between 1000 to 1111. 000: Port Status Page 001: Vendor Definition Page Others: Unused Port_select 4 R/W 0000 Port Selection. Selecting 000 (Port Status Page) with the page selection selects the port. 0000: Port 0 0001: Port 1 0010: Port 2 Others: Unused Reserved - R 000… Reserved. Read as 0. Preliminary Data Sheet S14653EJ1V0DS00 19 µPD72870A 2.2 Port Status Page (Page 000) Figure 2-2. Port Status Page 0 1 1000 2 AStat 1001 3 BStat Negotiated_speed Int_enable 4 5 Child Connected Fault 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved 6 7 Bias Disabled Reserved Table 2-2. Bit Field Description Field AStat Size R/W Reset value 2 R XX Description A port status value. 00:---, 10: “0” 01: “1”, 11: “Z” BStat 2 R XX B port status value. 00:---, 10: “0” 01: “1”, 11: “Z” Child 1 R Child node status value. 1: Connected to child node 0 : Connected to parent node Connected 1 R 0 Connection status value. 1: Connected 0: Disconnected Bias 1 R Bias voltage status value. 1: Bias voltage 0: No bias voltage Disabled 1 R/W See The reset value is set by the PORTDIS pin. Description Negotiated_ 3 R 1: Disable Shows the maximum data transfer rate of the node connected to this port. Speed 000: 100 Mbps 001: 200 Mbps 010: 400 Mbps Int_enable 1 R/W 0 The Port_event is set to 1 by a change to 1 of the Connected, Bias, Disable, Fault 1 R/W 0 Set to 1 if an error occurs during Suspend/Resume. and Fault bits. Writing 1 to this bit clears it to 0. Writing 0 has no effect. Reserved 20 - R 000… Reserved. Read as 0. Preliminary Data Sheet S14653EJ1V0DS00 µPD72870A 2.3 Vendor ID Page (Page 001) Figure 2-3. Vendor ID Page 0 1 2 3 4 1000 Compliance_level 1001 Reserved 5 6 7 1010 Vendor_ID 1011 1100 1101 Product_ID 1110 1111 Table 2-3. Bit Field Description Field Size R/W Reset value Compliance_level 8 R 00000001 According to IEEE P1394a. Vendor_ID 24 R 00004CH Company ID Code value, NEC IEEE OUI. Product_ID 24 R - R Reserved Description Product code. 000… Reserved. Read as 0. Preliminary Data Sheet S14653EJ1V0DS00 21 µPD72870A 3. CONFIGURATION REGISTERS 3.1 PCI Bus Mode Configuration Register (CARD_ON = Low) 31 24 23 16 15 08 07 00 Device ID Vendor ID 00H Status Command 04H Class Code BIST Header Type Latency Timer Revision ID 08H Cache Line Size 0CH Base Address 0 10H Base Address 1 14H Base Address 2 18H Base Address 3 1CH Base Address 4 20H Base Address 5 24H CardBus CIS Pointer 28H Subsystem ID Subsystem Vendor ID 30H Expansion Rom Base Address Register 000000H Cap_Ptr Min_Gnt Interrupt Pin 22 Interrupt Line 3CH PCI_OHCI_Control 40H 00000000H 44H 00000000H 48H 00000000H 4CH Diagnostic register0 50H Diagnostic register1 54H Diagnostic register2 58H Diagnostic register3 5CH Power Management Capabilities Data 34H 38H 00000000H Max_Lat 2CH Next_Item_Ptr PMCSR_BSE Cap_ID Power Management Control/Status 60H 64H 00000000H 68H 00000000H 6CH 00000000H 70H User Area (GENERAL_RegisterB) 74H User Area (GENERAL_RegisterC) 78H User Area (GENERAL_RegisterD) 7CH 00000000H 80H FCH Preliminary Data Sheet S14653EJ1V0DS00 µPD72870A 3.1.1 Offset_00 Vendor ID Register This register identifies the manufacturer of the µPD72870A. The ID is assigned by the PCI_SIG committee. Bits 15-0 R/W R 3.1.2 Offset_02 Description Constant value of 1033H. Device ID Register This register identifies the type of the device for the µPD72870A. The ID is assigned by NEC Corporation. Bits 15-0 R/W R 3.1.3 Offset_04 Description Constant value of 00CDH. Command Register The register provides control over the device’s ability to generate and respond to PCI cycles. Bits R/W Description 0 R I/O enable Constant value of 0. The µPD72870A does not respond to PCI I/O accesses. 1 R/W Memory enable Default value of 1. It defines if the µPD72870A responds to PCI memory accesses. This bit should be set to one upon power-up reset. 0: The µPD72870A does not respond to PCI memory cycles 1: The µPD72870A responds to PCI memory cycles 2 R/W Master enable Default value of 1. It enables the µPD72870A as bus-master on the PCI-bus. 0: The µPD72870A cannot generate PCI accesses by being a bus-master 1: The µPD72870A is capable of acting as a bus-master 3 R 4 R/W Special cycle monitor enable Constant value of 0. The special cycle monitor is always disabled. Memory write and invalidate enable Default value of 0. It enables Memory Write and Invalid Command generation. 0: Memory write must be used 1: The µPD72870A, when acts as PCI master, can generate the command 5 R VGA color palette invalidate enable Constant value of 0. VGA color palette invalidate is always disabled. 6 R/W Parity error response Default value of 0. It defines if the µPD72870A responds to PERR. 0: Ignore parity error 1: Respond to parity error 7 R 8 R/W Stepping enable Constant value of 0. Stepping is always disabled. System error enable Default value of 0. It defines if the µPD72870A responds to SERR. 0: Disable system error checking 1: Enable system error checking 9 R Fast back-to-back enable Constant value of 0. Fast back-to-back transactions are only allowed to the same agent. 15-10 R Reserved Constant value of 000000. Preliminary Data Sheet S14653EJ1V0DS00 23 µPD72870A 3.1.4 Offset_06 Status Register This register tracks the status information of PCI-bus related events which are relevant to the µPD72870A. “Read” and “Write” are handled somewhat differently. Bits R/W Description 3-0 R Reserved Constant value of 0000. 4 R New capabilities 6,5 R Reserved Constant value of 00. 7 R Constant value of 1. It indicates the existence of the Capabilities List. Fast back-to-back capable Constant value of 1. It indicates that the µPD72870A, as a target, cannot accept fast back-to-back transactions when the transactions are not to the same agent. 8 R/W Signaled parity error Default value of 0. It indicates the occurrence of any “Data Parity”. 0: No parity detected (default) 1: Parity detected 10,9 R DEVSEL timing Constant value of 01. These bits define the decode timing for DEVSEL. 0: Fast (1 cycle) 1: Medium (2 cycles) 2: Slow (3 cycles) 3: undefined 11 R/W Signaled target abort Default value of 0. This bit is set by a target device whenever it terminates a transaction with “Target Abort”. 0: The µPD72870A did not terminate a transaction with Target Abort 1: The µPD72870A has terminated a transaction with Target Abort 12 R/W Received target abort Default value of 0. This bit is set by a master device whenever its transaction is terminated with a “Target Abort”. 0: The µPD72870A has not received a Target Abort 1: The µPD72870A has received a Target Abort from a bus-master 13 R/W Received master abort Default value of 0. This bit is set by a master device whenever its transaction is terminated with “Master Abort”. The µPD72870A asserts “Master Abort” when a transaction response exceeds the time allocated in the latency timer field. 0: Transaction was not terminated with a Master Abort 1: Transaction has been terminated with a Master Abort 14 R/W Signaled system error Default value of 0. It indicates that the assertion of SERR by the µPD72870A. 0: System error was not signaled 1: System error was signaled 15 R/W Received parity error Default value of 0. It indicates the occurrence of any PERR. 0: No parity error was detected 1: Parity error was detected 24 Preliminary Data Sheet S14653EJ1V0DS00 µPD72870A 3.1.5 Offset_08 Revision ID Register This register specifies a revision number assigned by NEC Corporation for the µPD72870A. Bits R/W 7-0 R Description Default value of 02H. It specifies the silicon revision. It will be incremented for subsequent silicon revisions. 3.1.6 Offset_09 Class Code Register This register identifies the class code, sub-class code, and programming interface of the µPD72870A. Bits R/W Description 7-0 R Constant value of 10H. It specifies an IEEE1394 OpenHCI-compliant Host Controller. 15-8 R Constant value of 00H. It specifies an “IEEE1394” type. 23-16 R Constant value of 0CH. It specifies a “Serial Bus Controller”. 3.1.7 Offset_0C Cache Line Size Register This register specifies the system cache line size, which is PC-host system dependent, in units of 32-bit words. The following cache line sizes are supported: 2, 4, 8, 16, 32, 64, and 128. All other values will be recognized as 0, i.e. cache disabled. Bits 7-0 R/W R/W 3.1.8 Offset_0D Description Default value of 00H. Latency Timer Register This register defines the maximum amount of time that the µPD72870A is permitted to retain ownership of the bus after it has acquired bus ownership and initiated a subsequent transaction. Bits 7-0 R/W Description R/W Default value of 00H. It specifies the number of PCI-bus clocks that the µPD72870A may hold the PCI bus as a bus-master. 3.1.9 Offset_0E Bits 7-0 Header Type Register R/W R Description Constant value of 00H. It specifies a single function device. 3.1.10 Offset_0F BIST Register Bits 7-0 R/W R Description Constant value of 00H. It specifies whether the device is capable of Built-in Self Test. Preliminary Data Sheet S14653EJ1V0DS00 25 µPD72870A 3.1.11 Offset_10 Base Address 0 Register This register specifies the base memory address for accessing all the “Operation registers” (i.e. control, configuration, and status registers) of the µPD72870A, while the BIOS is expected to set this value during power-up reset. Bits R/W 11-0 R 31-12 R/W 3.1.12 Offset_20 Description Constant value of 000H. These bits are “read-only”. - Subsystem Vendor ID Register This register identifies the subsystem that contains the NEC’s µPD72870A function. While the ID is assigned by the PCI_SIG committee, the value should be loaded into the register from the external serial ROM after power-up reset. Access to this register through PCI-bus is prohibited. Bits 15-0 R/W R 3.1.13 Offset_22 Description Default value of 1033H. Subsystem ID Register This register identifies the type of the subsystem that contains the NEC’s µPD72870A function. While the ID is assigned by the manufacturer, the value should be loaded into the register from the external serial EEPROM after power-up reset. Access to this register through PCI-bus is prohibited. Bits 15-0 R/W R 3.1.14 Offset_30 Description Default value of 0063H. Expansion Rom Base Address Register This register is not supported by the current implementation of the µPD72870A. Bits 31-0 R/W R 3.1.15 Offset_34 Description Reserved Constant value of 0. Cap_Ptr Register This register points to a linked list of additional capabilities specific to the µPD72870A, the NEC’s implementation of the 1394 OpenHCI specification. Bits 7-0 R/W R Description Constant value of 60H. The value represents an offset into the µPD72870A’s PCI Configuration Space for the location of the first item in the New Capabilities Linked List. 26 Preliminary Data Sheet S14653EJ1V0DS00 µPD72870A 3.1.16 Offset_3C Interrupt Line Register This register provides the interrupt line routing information specific to the µPD72870A, the NEC’s implementation of the 1394 OpenHCI specification. Bits 7-0 R/W R/W Description Default value of 00H. It specifies which input of the host system interrupt controller the interrupt pin of the µPD72870A is connected to. 3.1.17 Offset_3D Interrupt Pin Register This register provides the interrupt line routing information specific to the µPD72870A, the NEC’s implementation of the 1394 OpenHCI specification. Bits 7-0 R/W R 3.1.18 Offset_3E Description Constant value of 01H. It specifies PCI INTA is used for interrupting the host system. Min_Gnt Register This register specifies how long of a burst period the µPD72870A needs, assuming a clock rate of 33 MHz. Resolution is in units of ¼ µs. The value should be loaded into the register from the external serial EEPROM upon power-up reset, and access to this register through PCI-bus is prohibited. Bits 7-0 R/W R 3.1.19 Offset_3F Description Default value of 00H. Its value contributes to the desired setting for Latency Timer value. Max_Lat Register This register specifies how often the µPD72870A needs to gain access to the PCI-bus, assuming a clock rate of 33 MHz. Resolution is in units of ¼ µs. The value should be loaded into the register from the external serial EEPROM after hardware reset, and access to this register through PCI-bus is prohibited. Bits 7-0 R/W R 3.1.20 Offset_40 Description Default value of 00H. Its value contributes to the desired setting for Latency Timer value. PCI_OHCI_Control Register This register specifies the control bits that are IEEE1394 OpenHCI specific. Vendor options are not allowed in this register. It is reserved for OpenHCI use only. Bits 0 R/W Description R/W PCI global SWAP Default value of 0. When this bit is 1, all quadrates read from and written to the PCI Interface are byte swapped, thus a “PCI Global Swap”. PCI addresses for expansion ROM and PCI Configuration registers, are, however, unaffected by this bit. This bit is not required for motherboard implementations. 31-1 R Reserved Constant value of all 0. Preliminary Data Sheet S14653EJ1V0DS00 27 µPD72870A 3.1.21 Offset_60 Cap_ID & Next_Item_Ptr Register The Cap_ID signals that this item in the Linked List is the registers defined for PCI Power Management, while the Next_Item_Ptr describes the location of the next item in the µPD72870A’s Capability List. Bits 7-0 R/W Description R Cap_ID Constant value of 01H. The default value identified the Link List item as being the PCI Power Management registers, while the ID value is assigned by the PCI SIG. 15-8 R Next_Item_Ptr Constant value of 00H. It indicated that there are no more items in the Link List. 3.1.22 Offset_62 Power Management Capabilities Register This is a 16-bit read-only register that provides information on the power management capabilities of the µPD72870A. Bits 2-0 R/W Description R version Constant value of 001. The power management registers are implemented as defined in revision 1.0 of PCI Bus Power Management Interface Specification. 3 R PME clock Constant value of 0. 4 R Auxiliary power source Constant value of 0. The alternative power source is not supported. 5 R DIS Constant value of 0. 8,6 R Reserved Constant value of 000. 9 R D1_support Constant value of 0. The µPD72870A does not support the D1 Power Management state. 10 R D2_support Constant value of 1. The µPD72870A supports the D2 Power Management state. 15-11 R PME_support Constant value of 01100. 28 Preliminary Data Sheet S14653EJ1V0DS00 µPD72870A 3.1.23 Offset_64 Power Management Control/Status Register This is a 16-bit read-only register that provides control status information of the µPD72870A. Bits 1,0 R/W Description R/W PowerState Default value is undefined. This field is used both to determine the current power state of the µPD72870A and to set the µPD72870A into a new power state. As D1 is not supported in the current implementation of the µPD72870A, writing of ‘01’ will be ignored. 00: D0 (DMA contexts: ON, Link Layer: ON) 01: Reserved (D1 state not supported) 10: D2 (DMA contexts: OFF, Link Layer: OFF, LPS: OFF, PME will be asserted upon LinkON being active) 11: D3 (DMA contexts: OFF, Link Layer: OFF, LPS: OFF, PME will be asserted upon LinkON being active, Power can be removed) The LPS is a PHY/Link interface signal and is defined in P1394a draft 2.0. It is an internal signal in the µPD72870A. 7-2 8 R R/W Reserved Constant value of 000000. PME_En Default value of 0. This field is used to enable the specific power management features of the µPD72870A. 12-9 R Data_Select Constant value of 0000. 14,13 R Data_Scale Constant value of 00. 15 R/W PME_Status Default value is undefined. A write of ‘1’ clears this bit, while a write of ‘0’ is ignored. Preliminary Data Sheet S14653EJ1V0DS00 29 µPD72870A 3.2 CardBus Mode Configuration Register (CARD_ON = High) 31 24 23 16 15 08 07 00 Device ID Vendor ID 00H Status Command 04H Class Code BIST Header Type Latency Timer Revision ID 08H Cache Line Size 0CH Base Address 0 10H Base Address 1 (CardBus Status Reg) Note 14H Base Address 2 (CardBus Status Reg) 18H Note Base Address 3 1CH Base Address 4 20H Base Address 5 24H CardBus CIS Pointer Note 28H Subsystem ID Subsystem Vendor ID 30H Expansion Rom Base Address Register 000000H Cap_Ptr Min_Gnt Interrupt Pin 3CH 40H 00000000H 44H 00000000H 48H 00000000H 4CH Diagnostic register0 50H Diagnostic register1 54H Diagnostic register2 58H Diagnostic register3 5CH Next_Item_Ptr PMCSR_BSE Cap_ID Power Management Control/Status 60H 64H 00000000H 68H 00000000H 6CH 00000000H 70H User Area (GENERAL_RegisterB) 74H User Area (GENERAL_RegisterC) 78H User Area (GENERAL_RegisterD) 7CH CIS Area Note 80H FCH Note Different from PCI Bus Mode Configuration Register. 30 Interrupt Line PCI_OHCI_Control Power Management Capabilities Data 34H 38H 00000000H Max_Lat 2CH Preliminary Data Sheet S14653EJ1V0DS00 µPD72870A 3.2.1 Offset_14/18 Bits Base_Address_1/2 Register (Cardbus Status Registers) R/W 7-0 R 31-8 R/W Description Constant value of 00. - (1) Function Event Register (FER) ( Base Address 1 ( 2 )+ 0H ) Bits 0 R/W R Description Write Protect (No Use). Read only as ‘0’ 1 R Ready Status (No Use). 2 R Battery Voltage Detect 2 (No Use). Read only as ‘0’ Read only as ‘0’ 3 R Battery Voltage Detect 1 (No Use). Read only as ‘0’ 4 R/W 14-5 R 15 R/W 31-16 R General Wakeup Reserved. Read only as ‘0’ Interrupt Reserved. Read only as ‘0’ (2) Function Event Mask Register (FEMR) ( Base Address 1 ( 2 )+ 4H ) Bits 0 R/W R Description Write Protect (No Use). Read only as ‘0’ 1 R Ready Status (No Use). Read only as ‘0’ 2 R Battery Voltage Detect 2 (No Use). Read only as ‘0’ 3 R Battery Voltage Detect 1 (No Use). 4 R/W General Wakeup Mask 5 R BAM. Read only as ‘0’ 6 R PWM. Read only as ‘0’ 13-7 R Reserved. Read only as ‘0’ Read only as ‘0’ 14 R/W 15 R/W 31-16 R Wakeup Mask Interrupt Reserved. Read only as ‘0’ Preliminary Data Sheet S14653EJ1V0DS00 31 µPD72870A (3) Function Reset Status Register (FRSR) ( Base Address 1 ( 2 )+ 8H ) Bits R/W Description 0 R Write Protect (No Use). 1 R Ready Status (No Use). Read only as ‘0’ Read only as ‘0’ 2 R Battery Voltage Detect 2 (No Use). Read only as ‘0’ 3 R Battery Voltage Detect 1 (No Use). Read only as ‘0’ 4 R/W 14-5 R 15 R/W 31-16 R General Wakeup Mask Reserved. Read only as ‘0’ Interrupt Reserved. Read only as ‘0’ (4) Function Force Event Register (FFER) ( Base Address 1 ( 2 )+ CH ) Bits R/W Description 0 R Write Protect (No Use). 1 R Ready Status (No Use). 2 R Battery Voltage Detect 2 (No Use). Read only as ‘0’ Read only as ‘0’ Read only as ‘0’ 3 R Battery Voltage Detect 1 (No Use). Read only as ‘0’ 4 R/W 14-5 15 - No Use R/W Interrupt 31-16 R 3.2.2 Offset_28 General Wakeup Mask Reserved. Read only as ‘0’ Cardbus CIS Pointer This register specifies start memory address of the Cardbus CIS Area. Bits R/W 31-0 R Description Starting Pointer of CIS Area. Constant value of 00000080H. 3.2.3 Offset_80 CIS Area The µPD72870A supports external Serial ROM (AT24C02 compatible) interface. CIS Area Register can be loaded from external Serial ROM in the CIS area when CARD_ON is 1. 32 CARD_ON CIS_ON Bus CIS Function 0 1 PCI Off PME 0 0 PCI On CSTSCHG 1 X Cardbus On CSTSCHG Preliminary Data Sheet S14653EJ1V0DS00 µPD72870A 4. PHY FUNCTION 4.1 Cable Interface 4.1.1 Connections Figure 4-1. Cable Interface Connection Detection Current Connection Detection Comparator Common Mode Speed Current driver TpBias + - TpAp Driver Receiver + - TpBp 7 kΩ 56 Ω 56 Ω 7 kΩ 7 kΩ TpAn 56 Ω 56 Ω 7 kΩ TpBn 1 µF 0.01 µF 5.1 kΩ 270 pF Arbitration Comparators + - Driver Receiver + Arbitration Comparators + - + - + - Common Mode Comparators + - Common Mode Comparator + - + - Connection Detection Current Connection Detection Comparator Common Mode Speed Current Driver TpBias TpBp Driver TpAp 7 kΩ 56 Ω 56 Ω 7 kΩ 7 kΩ TpBn 56 Ω 56 Ω 7 kΩ TpAn Receiver + - 270 pF + - 5.1 kΩ 0.01 µF 1 µF Driver Receiver + Arbitration Comparators + - Arbitration Comparators + + - + - Common Mode Comparator + - Common Mode Comparators + + - Preliminary Data Sheet S14653EJ1V0DS00 33 µPD72870A 4.1.2 Cable Interface Circuit Each port is configured with two twisted-pairs of TpA and TpB. TpA and TpB are used to monitor the state of the Transmit/Receive line, control signals, data and cables. During transmission to the IEEE1394 bus, the Data/Strobe signal received from the Link layer controller is encoded, converted from parallel to serial and transmitted. While receiving from the IEEE1394 bus, the Data/Strobe signal from TpA, TpB is converted from serial to parallel after synchronization by SCLK Note, then transmitted to the Link layer controller in 2/4/8 bits according to the data rate of 100/200/400 Mbps. The bus arbitration for TpA and TpB and the state of the line are monitored by the built-in comparator. The state of the 1394 bus is transmitted to the state machine in the LSI. Note The SCLK is a PHY/Link interface signal and is defined in P1394a draft 2.0. It is an internal signal in the µPD72870A. 4.1.3 CPS An external resistance of 390 kΩ is connected in series to the power cable to monitor the power of the power cable. If the cable power falls under 7.5 V there is an indication to the Link layer that the power has failed. 4.1.4 Unused Ports TpAp, TpAn : Not connected TpBp, TpBn : AGND TpBias : Connected to AGND using a 1.0 µF load capacitor No need to assemble the capacitor if using as Suspend/Resume On mode (SUS_RESM = 1). 34 Preliminary Data Sheet S14653EJ1V0DS00 µPD72870A 4.2 Suspend/Resume 4.2.1 Suspend/Resume On Mode (SUS_RESM = 1) There are two ways of transition from the active status to the suspended status. One is when the receipt of a remote command packet that sets the initiate suspend command. After that, the PHY transmits a remote confirmation packet with the ok bit set, subsequently signals TX_SUSPEND to the connected peer PHY with the port which specified by the port field in the remote command packet, and then the PHY port transitions to the suspended state. The other is when the receipt of a RX_SUSPEND or RX_DISABLE_NOTIFY signal. When the port observes RX_SUSPEND, it transmits TX_SUSPEND to the active ports. The TX_SUSPEND transmitted propagates until it reaches a leaf node. The PHY port transitions to the suspended state. The propagation of the suspended domain may be blocked by a PHY compliant with IEEE Std 1394-1995, a disabled or a suspended port. Any one of a number of reasons may cause a suspended port to attempt to resume normal operations: • Bias is detected and there is no fault condition; • A resume packet is received or transmitted by the PHY; • A remote command packet that sets the resume port command is received; or • Either port of a node without active ports detects bias. 4.2.2 Suspend/Resume Off Mode (SUS_RESM = 0) • Remote command packet is ignored. • Resume packet is ignored. • Disabled, Int_enable and resume_int bits in PHY register are ignored. • Responses to Remote access packet. • Detects the connection of the port in TpBias. Preliminary Data Sheet S14653EJ1V0DS00 35 µPD72870A 4.3 PLL and Crystal Oscillation Circuit 4.3.1 Crystal Oscillation Circuit To supply the clock of 24.576 MHz ± 100 ppm, use an external capacitor of 10 pF and a crystal of 50 ppm. 4.3.2 PLL The crystal oscillator multiplies the 24.576 MHz frequency by 16 (393.216 MHz). 4.4 PC0-PC2, CMC CMC shows the bus manager function which corresponds to the c bit of the Self_ID packet and the Contender bit in the PHY register when the input is High. The value of CMC can be changed with software through the Link layer; this pin sets the initial value during Poweron Reset. Use a pull-up or pull-down resistor of 10 kΩ, based on the device’s specification. The PC0-PC2 pin corresponds to the power field of the Self_ID packet and Pwr_class in the PHY register. Refer to Section 4.3.4.1 of the IEEE1394-1995 specification for information regarding the Pwr_class. The value of Pwr can be changed with software through the Link layer; this pin sets the initial value during Power-on Reset. Use a pull-up or pull-down resistor of 10 kΩ based on the application. 4.5 P_RESETB Connect an external capacitor of 0.1 µF between the pins P_RESETB and GND. If the voltage drops below 0 V, a reset pulse is generated. All of the circuits are initialized, including the contents of the PHY register. 4.6 RI0, RI1 Connect an external resistor of 9.1 kΩ ± 0.5 % to limit the LSI’s current. 36 Preliminary Data Sheet S14653EJ1V0DS00 µPD72870A 5. SERIAL ROM INTERFACE The µPD72870A provides a serial ROM interface to initialize the 1394 Global Unique ID Register and the PCI/Cardbus Mode Configuration registers from a serial EEPROM. The table 5-1 shows the serial EEPROM memory map required for initializing their registers. 5.1 Serial EEPROM Register Register Address Register Name R/W Base address + 0x930 SUBID register R/W Base address + 0x934 LATVAL register R/W Base address + 0x938 W_GUIDHi register R/W Base address + 0x93C W_GUIDLo register R/W Base address + 0x940 Parameters Write register R/W Base address + 0x950 W_LAT register R/W Base address + 0x954 W_GENERAL register R/W Base address + 0x960 W_PHYS register R/W Base address + 0x980 W_CIS register R/W Remark Base address : Base Address 0 in Configuration register 5.2 Serial EEPROM Register Description (1) SUBID register (Base address + 0x930) 31 16 15 0 W_SUBSYSID Field W_SUBSYSID W_SUBVNDID Bits R/W Default value 31-16 R/W 0063H Description Subsystem ID value. The value is loaded into Subsystem ID register in Configuration register (Offset+2CH bit 31-16). W_SUBVNDID 15-0 R/W 1033H Subsystem Vendor ID value. The value is loaded into Subsystem Vendor ID register in Configuration register (Offset+2CH bit 15-0). (2) LATVAL register (Base address + 0x934) 31 24 23 W_MAXLAT Field W_MAXLAT 16 15 W_MINGNT Bits R/W Default value 31-24 R/W 00H 12 11 10 -0- 1 4 -0- 3 0 W_MAX_REC Description Max Latency value. The value is loaded into Max Latency register in Configuration register (Offset+3CH bit 31-24). W_MINGNT 23-16 R/W 00H Min Grant value. The value is loaded into Min Grant register in Configuration register (Offset+3CH bit 23-16). - W_MAX_REC 15-12 - - Reserved. Write 0 to these bits. 11 - - Reserved. Write 1 to this bit. 10-4 - - Reserved. Write 0 to these bits. 3-0 R/W 9H MAX_REC value. The value is loaded into the max_rec field of OHCI BusOption register in OHCI register (Offset+020H bit 15-12). Preliminary Data Sheet S14653EJ1V0DS00 37 µPD72870A (3) W_GUIDHi register (Base address + 0x938) 31 0 W_GUIDHi Field Bits R/W Default value W_GUIDHi 31-0 R/W Undefined Description GlobalUniqueIDHi value. The value is loaded into OHCI GlobalUniqueIDHi register in OHCI register (Offset+024H bit 31-0). Please refer to the 1394 Open Host Controller Interface Specification/Release 1.0 [5.5.5]. (4) W_GUIDLo register (Base address + 0x93C) 31 0 W_GUIDLo Field Bits R/W Default value W_GUIDLo 31-0 R/W Undefined Description GlobalUniqueIDLo value. The value is loaded into GlobalUniqueIDLo register in OHCI register (Offset+028H bit 31-0). Please refer to the 1394 Open Host Controller Interface Specification/Release 1.0 [5.5.5]. (5) Parameters Write register (Base address + 0x940) 31 7 -0- Field Bits R/W Default value - 31-7 - - PAGE_S 6-4 R/W 000 6 4 PAGE_S 3 1 -0- 0 PAR _W Description Reserved. Write 0 to these bits. Write register select page. The bit field returns zero when read. 000: Select SUBID register and LATVAL register. 001: Select W_GUIDHi register and W_GUIDLo register. 010: Select W_LAT register and W_GENERAL register (W_GENERAL_0). 011: Select W_GENERAL register (W_GENERAL_1 and W_GENERAL_2). 100: Select W_PHYS register (W_ programPhyEnable, W_aPhyEnhanceEnable). 101: Select W_CIS register (W_CIS_EVEN - W_CIS_ODD). PAR_W 3-1 - - Reserved. Write 0 to these bits. 0 R/W 0 Write control signal. The bit field returns zeros when read. 1: Write the value of select page defined PAGE_S. One write transaction is the units of 8 byte. 0: Ignored. 38 Preliminary Data Sheet S14653EJ1V0DS00 µPD72870A (6) W_LAT register (Base address + 0x950) 31 8 7 -0- Field Bits R/W 31-8 - - W_LAT 7-3 R/W 00000 2 W_LAT Default value - 3 0 -0- Description Reserved. Write 0 to these bits. Latency timer value. The value is loaded into Latency Timer in Configuration register (Offset+0CH bit 15-8) when using as Cardbus mode (CARD_ON = 1). It is not loaded when using as PCI bus mode (CARD_ON = 0). - 2-0 - - Reserved. Write 0 to these bits. (7) W_GENERAL register (Base address + 0x954 - 0x95C) 31 0 W_GENERAL_0 (Base address + 0x954) - W_GENERAL_2 (Base address + 0x95C) Field Bits R/W Default value W_GENERAL_0 - 31-0 R/W Undefined W_GENERAL_2 Description User define value. The value is loaded into GENERAL_registerB - D in Configuration register (Offset+70H - 7BH). (8) W_PHYS register (Base address + 0x960) 31 10 9 8 7 -0- 3 2 -0- 0 -1- W_aPhyEnhanceEnable W_programPhyEnable Field W_programPhyEnable Bits R/W Default value Description 31-10 - - Reserved. Write 0 to these bits. 9 R/W 1 programPhyEnable bit. The bit is loaded into HCControl registers in OHCI register ((Offset+50H bit 23) and (54H bit 23)). Please refer to the 1394 Open Host Controller Interface Specification/Release 1.0 [5.7]. 1: P1394a enhancement is supported. 0. P1394a enhancement is not supported. W_aPhyEnhanceEnable 8 R/W 0 aPhyEnhanceEnable bit. The bit is loaded into HCControl registers in OHCI register ((Offset+50H bit 23) and (54H bit 23)). - 7-3 - - Reserved. Write 0 to these bits. 2-0 - - Reserved. Write 1 to these bits. Preliminary Data Sheet S14653EJ1V0DS00 39 µPD72870A (9) W_CIS register (Base address + 0x980 - 0x984) 31 0 W_CIS_EVEN (Base address + 0x980) - W_CIS_ODD (Base address + 0x984) Field W_CIS_EVEN W_CIS_ODD 40 Bits R/W Default value 31-0 R/W Undefined Description CIS Area value. The value is loaded into CIS Area in Configuration register (Offset+80H - FCH). Preliminary Data Sheet S14653EJ1V0DS00 µPD72870A Table 5-1. Serial EEPROM Memory Map Byte address Bit 7 6 5 4 3 0 W_SUBSYSID(31 : 24) 1 W_SUBSYSID(23 : 16) 2 W_SUBVNDID(15 : 8) 3 W_SUBVNDID( 7 : 0) 4 W_MAXLAT(31 : 24) 5 2 1 0 0 0 0 W_MINGNT(23 : 16) 6 0 0 0 0 7 0 0 0 0 1 W_MAX_REC( 3 : 0) 8 W_GUIDHi(31 : 24) 9 W_GUIDHi(23 : 16) A W_GUIDHi(15 : 8) B W_GUIDHi( 7 : 0) C W_GUIDLo(31 : 24) D W_GUIDLo(23 : 16) E W_GUIDLo(15 : 8) F W_GUIDLo( 7 : 0) 10 0 0 0 0 0 0 0 0 11 0 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 13 W_LAT( 7 : 3) 14 W_GENERAL_0(31 : 24) 15 W_GENERAL_0(23 : 16) 16 W_GENERAL_0(15 : 8) 17 W_GENERAL_0( 7 : 0) : : : : 1C W_GENERAL_2(31 : 24) 1D W_GENERAL_2(23 : 16) 1E W_GENERAL_2(15 : 8) 1F W_GENERAL_2( 7 : 0) 20 0 0 0 0 0 0 21 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 WPE WPEE 23 0 0 0 0 0 1 1 1 : : : : 28 W_CIS_0(31 : 24) 29 W_CIS_0(23 : 16) 2A W_CIS_0(15 : 8) 2B W_CIS_0( 7 : 0) : : : : A4 W_CIS_31(31 : 24) A5 W_CIS_31(23 : 16) A6 W_CIS_31(15 : 8) A7 W_CIS_31( 7 : 0) WPE: W_programPhyEnable, WPEE: W_aPhyEnhanceEnable Preliminary Data Sheet S14653EJ1V0DS00 41 µPD72870A 5.3 Load Control GROM_EN CARD_ON CIS_ON Description 0 X X No loading. 1 0 1 W_SUBSYSID, W_SUBVNDID, W_MAXLAT, W_MINGNT, W_MAX_REC, W_GUIDHi/Lo, W_LAT, W_GENERAL_0 - W_GENERAL_2, W_programPhyEnable, W_aPhyEnhanceEnable are loaded. 1 0 0 1 1 X All parameters (W_SUBSYSID, W_SUBVNDID, W_MAXLAT, W_MINGNT, W_MAX_REC, W_GUIDHi/Lo, W_LAT, W_GENERAL_0 - W_GENERAL_2, W_programPhyEnable, W_aPhyEnhanceEnable, W_CIS_EVEN - W_CIS_ODD) are loaded. 5.4 Programming Sequence Example The example of programming sequence to the serial EEPROM is shown below. (1) Write SUBID register. Note1 (2) Write LATVAL register. Note1 (3) Write PAGE_S = 000 and PAR_W = 1 on Parameters Write register. Note1 (4) Wait over 13 ms for serial EEPROM access time. Note1 (5) Write W_GUIDHi register. Note2 (6) Write W_GUIDLo register. Note2 (7) Write PAGE_S = 001 and PAR_W = 1 on Parameters Write register. Note2 (8) Wait over 13 ms for serial EEPROM access time. Note2 (9) Write W_LAT register. Note3 (10) Write W_GENERAL register (W_GENERAL_0). Note3 (11) Write PAGE_S = 010 and PAR_W = 1 on Parameters Write register. Note3 (12) Wait over 13 ms for serial EEPROM access time. Note3 (13) Write W_GENERAL register (W_GENERAL_1, W_GENERAL_2). Note4 (14) Write PAGE_S = 011 and PAR_W = 1 on Parameters Write register. Note4 (15) Wait over 13 ms for serial EEPROM access time. Note4 (16) Write W_CIS register. Note5 (17) Write PAGE_S = 100 and PAR_W = 1 on Parameters Write register. Note5 (18) Wait over 30 ms for serial EEPROM access time. Note5 (19) Complete to write parameters into Serial EEPROM. (20) Parameters are loaded from serial EEPROM after PCI reset. Notes 1. If none of W_SUBSYSED, W_SUBVNDID, W_MAXLAT, W_MINGNT, W_HOLD_TIMER, W_MAX_REC in serial EEPROM are changed, (1)-(4) transactions don’t need. 2. If none of W_GUIDHi, W_GUIDLo in serial EEPROM are changed, (5)-(8) transactions don't need. 3. If none of W_LAT, W_GENERAL_0 in serial EEPROM are changed, (9)-(12) transactions don't need. 4. If none of W_GENERAL_1, W_GENERAL_2 in serial EEPROM are changed, (13)-(15) transactions don't need. 5. If none of W_CIS_0 - W_CIS_31 in serial EEPROM are changed, (16)-(18) transactions don't need. One write transaction (Parameters Write register : PAGE_S = 100 and PAR_W = 1) is the units of 8 byte . If more than 8 byte write, you need to repeat (16)-(18). * 42 Preliminary Data Sheet S14653EJ1V0DS00 µPD72870A *: • Write W_CIS_0, W_CIS_1 register. • Write PAGE_S = 100 and PAR_W = 1 on Parameters Write register. • Wait over 30 ms for serial EEPROM access time. : • Write W_CIS_30, W_CIS_31 register. • Write PAGE_S = 100 and PAR_W = 1 on Parameters Write register. • Wait over 30 ms for serial EEPROM access time. Preliminary Data Sheet S14653EJ1V0DS00 43 µPD72870A 6. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Parameter Power supply voltage Symbol Condition VDD Input voltage VI Rating Unit –0.5 to +4.6 V LVTTL @ (VI < 0.5 V + VDD) –0.5 to +4.6 V PCI @ (VI < 3.0 V + VDD) –0.5 to +6.6 V LVTTL @ (VO < 0.5 V + VDD) –0.5 to +4.6 V PCI @ (VO < 3.0 V + VDD) Output voltage VO –0.5 to +6.6 V Operating ambient temperature TA 0 to +70 °C Storage temperature Tstg –65 to +150 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Ranges Parameter Power supply voltage Operating ambient temperature 44 Symbol Condition Rating Unit VDD Used to clamp reflection on PCI bus. 4.5 to 5.5 V 3.0 to 3.6 V 0 to +70 °C TA Preliminary Data Sheet S14653EJ1V0DS00 µPD72870A DC Characteristics (VDD = 3.3 V ± 10 %, VSS = 0 V, TA = 0 to +70°°C) Parameter High-level input voltage Symbol Condition VIH Low-level input voltage VIL High-level output current IOH VOH =2.4 V Pin No. MIN. TYP. MAX. Unit 2.0 VDD+0.5 V –0.5 +0.8 V –6 mA –9 mA 6 mA 9 mA LQFP:153,154 FBGA:A4,B4 Pin No. LQFP:74,76-79,83,84,92 FBGA:L14,P15,P16, R13-R15,T14,T15 Low-level output current IOL VOL =0.4 V Pin No. LQFP:153,154 FBGA:A4,B4 Pin No. LQFP:74,76-79,83,84,92 FBGA:L14,P15,P16, R13-R15,T14,T15 Input leakage current IL VIN = VDD or GND Supply current IDD 3 ports, S400, VDD = 3.3 V ±10.0 µA 280 mA PCI interface High-level input voltage VIH 2.0 5.5 V Low-level input voltage VIL –0.5 +0.8 V High-level output current IOH VOH = 2.4 V –2 mA Low-level output current IOL VOL = 0.4 V 9 mA Input leakage current IL VIN = VDD or GND ±10.0 µA Cable interface Differential input voltage TpB common mode input voltage VID VICM Cable input, 100 Mbps operation 142 260 mV Cable input, 200 Mbps operation 132 260 mV Cable input, 400 Mbps operation 118 260 mV 100 Mbps speed signaling off 1.165 2.515 V 200 Mbps speed signaling 0.935 2.515 V 400 Mbps speed signaling 0.523 2.515 V Differential output voltage VOD Cable output (Test load 55Ω) 172.0 265.0 mV TpA common mode output voltage VOCM 100 Mbps speed signaling off 1.665 2.015 V 200 Mbps speed signaling 1.438 2.015 V 400 Mbps speed signaling 1.030 2.015 V 100 Mbps speed signaling off –0.81 +0.44 mA 200 Mbps speed signaling –4.84 –2.53 mA 400 Mbps speed signaling –12.40 –8.10 mA 7.5 V 1.665 2.015 V TpA common mode output current Power status threshold voltage TpBias output voltage ICM VTH CPS VTPBIAS Preliminary Data Sheet S14653EJ1V0DS00 45 µPD72870A Remarks 1. Digital core runs at 3.3 V. 2. PCI Interface can run at 5 or 3.3 V, depending on the choice of 5 V-PCI or 3.3 V-PCI. 3. All other I/Os are 3.3 V driving, and 5 V tolerant. 4. 5 V are used only for 5 V-PCI clamping diode. 3.3 V 5.0 V Protection Circuit AC Characteristics PCI Interface See PCI local bus specification Revision 2.1. Serial ROM Interface See AT24C01A/02/04/08/16 Spec. Sheet. 46 Preliminary Data Sheet S14653EJ1V0DS00 I/O Buffer µPD72870A 7. APPLICATION CIRCUIT EXAMPLE 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF Note Note 33 µF Analog GND 0.1µF Note 0.1µF 0.1µF 1.0µ F 1.0µ F 1.0µ F DGND IC(L) IC(L) CARD_ON CIS_ON GROM_EN GROM_SCL GROM_SDA DGND L_VDD DGND P_DVDD P_AVDD P_AVDD P_AVDD AGND AGND AGND AGND AGND TpA0p TpA0n TpB0p TpB0n TpA1p TpA1n TpB1p TpB1n TpA2p TpA2n TpB2p TpB2n TpBias0 TpBias1 TpBias2 P_AVDD AGND CPS RI1 RI0 L _ VD D CLKRUN PME INTA PRST PCLK GNT REQ DGND P C I _ VD D AD31 AD30 AD29 AD28 DGND AD27 AD26 AD25 AD24 L _ VD D DGND CBE3 IDSEL AD23 AD22 AD21 AD20 DGND AD19 AD18 P C I _ VD D AD17 AD16 DGND CBE2 FRAME IRDY TRDY DEVSEL L _ VD D P _ A VD D 1 2 0 AGND 119 XO 118 XI 1 1 7 P _ A VD D 1 1 6 FIL0 1 1 5 FIL1 1 1 4 AGND 113 AGND 112 P _ A VD D 1 1 1 P_RESETB 110 DGND 109 P _ D VD D 1 0 8 P _ A VD D 1 0 7 SUS_RESM 106 PORTDIS 105 DGND 104 P _ D VD D 1 0 3 IC(L) 1 0 2 IC(L) 1 0 1 IC(H) 1 0 0 IC(H) 9 9 DGND 98 P _ D VD D 9 7 CMC 96 PC2 95 PC1 94 PC0 93 IC(N) 9 2 IC(L) 9 1 DGND 90 IC(L) 8 9 IC(N) 8 8 IC(N) 8 7 IC(N) 8 6 DGND 85 IC(N) 8 4 IC(N) 8 3 IC(N) 8 2 L _ VD D 8 1 10 pF 0.1µF 10 pF 0.1µF 0.1 µF 0.1 µF 0.1µF 0.1µF 0.1µF 0.1µF 3 3 µF Digital GND 0.1µF 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 DGND STOP PERR SERR PAR L_VDD CBE1 DGND AD15 AD14 PCI_VDD AD13 AD12 DGND AD11 AD10 AD9 AD8 L_VDD CBE0 AD7 AD6 AD5 AD4 DGND AD3 AD2 AD1 AD0 PCI_VDD DGND L_VDD PIN_EN IC(N) IC(H) IC(N) IC(N) IC(N) IC(N) DGND 0.1µF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 9.1 kΩ (0.5%) 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 0.1µF 56Ω 56Ω 56Ω 56Ω 56Ω 56Ω 56Ω 56Ω 56Ω 56Ω 56Ω 56Ω 0.1µF Vp (Cable Supply Voltage) 390 kΩ 0.1µF 0.1µF 33 µF Digital GND Analog GND 5.1k Ω 270pF 0.01µ F 5.1k Ω 270pF 5.1k Ω 270pF 0.01µ F 0.01µ F 0.1µF 33 µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 33 µF Digital GND Power (3.3 V) 0.1µF 33 µF Digital GND Note Common mode choke. Recommendation : TOKO Part No. 857CM-0009 (TYPE B5W) : MURATA Part No. PLW3216S161SQ2 Preliminary Data Sheet S14653EJ1V0DS00 47 µPD72870A 8. PACKAGE DRAWINGS 160-PIN PLASTIC LQFP (FINE PITCH) (24x24) A B 81 80 120 121 detail of lead end S C D R Q 41 40 160 1 F G H I J M P K N S S L M NOTE ITEM Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 26.0±0.2 B 24.0±0.2 C 24.0±0.2 D 26.0±0.2 F 2.25 G 2.25 H 0.22 +0.05 −0.04 I J 0.10 0.5 (T.P.) K 1.0±0.2 L 0.5±0.2 M 0.145+0.055 −0.045 N 0.10 P 1.4±0.1 Q 0.125±0.075 R 3° +7° −3° S 1.7 MAX. S160GM-50-8ED-3 48 Preliminary Data Sheet S14653EJ1V0DS00 µPD72870A 192-PIN PLASTIC FBGA (14x14) w D B S B D1 SD ZD 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ZE A E1 E SE T R P NM L K J H G F E DC B A INDEX MARK 4-R0.3 MAX. S A w 4-C1.0 25° A y1 S A2 S y S e 192- φ b A1 φ x M S A B ITEM D MILLIMETERS 14.0±0.1 D1 13.4 E E1 14.0±0.1 13.4 w 0.20 e A 0.8 1.31±0.15 A1 A2 0.35±0.10 0.96 b 0.5 +0.05 −0.10 x 0.08 y y1 0.10 0.2 SD 0.4 SE ZD ZE 0.4 1.0 1.0 P192F1-80-FA2 Preliminary Data Sheet S14653EJ1V0DS00 49 µPD72870A [MEMO] 50 Preliminary Data Sheet S14653EJ1V0DS00 µPD72870A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Preliminary Data Sheet S14653EJ1V0DS00 51 µPD72870A EEPROM and Firewarden are trademarks of NEC Corporation. The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8