ETC VMX51C1016-14-QC

VMX1C1016
Datasheet
Rev 1.0
Versa Mix 8051 Mixed-Signal MCU
Overview
Feature Set
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Applications
Automotive Applications
Industrial Controls / Instrumentation
Consumer Products
Medical Devices
FIGURE 1: VMX51C1016 BLOCK DIAGRAM
FIGURE 2: VMX51C1016-QAC14, QFP-44 PACKAGE PINOUT
8051
µPROCESSOR
SINGLE CYCLE
1 2 -BIT A/D
CONVERTER
OSC1
P3.0 TX0
P3.1 RX0
OSC0
P3.3-CCU0
P3.2-T0IN
P3.4-CCU1
P3.5-T1IN
P3.7 - SCL
A/D input Mu x.
2 UARTs
Serial Ports
P3.6-SDA
In -Circuit
Debugging
through UART 0
VPP
o
o
o
o
8051 Compatible RISC Performance Processor
Enhanced Arithmetic Unit including Barrel Shifter
56KB of Flash Memory
1280 Bytes of RAM
24 General Purpose I/Os
2 UART Serial Ports
2 Baud Rate Generators for UARTs
Diff. Transceiver connected to UART1
J1708/RS-485 compatible)
Enhanced SPI interface (Master/Slave)
o
Fully configurable
o
Control up to 4 Slave devices
I²C interface
1 External Dedicated Interrupt Input
Interrupt on Port 1.0-P1.3 Pin Change
3, 16-bit Timers/Counters
4 Compare Units and 2 Capture Inputs
4 Ch. PWM, 8-bit / 16-bit resolution
5 Ch. 12-bit A/D Converter
o
Conversion rate configurable up to
10KHz
o
Continuous/One-Shot Operation
o
Single or 4-Channel Automatic
Sequential Conversions
On-Chip Voltage Reference
Digitally Controlled Switch
Power Saving Features + Clock Control
Watchdog Timer
Operating Temperature range (0ºC to +70ºC)
Available in QFP-44 package
o
The VMX51C1016 is a fully integrated mixed-signal
microcontroller that provides a “one-chip” solution for
a broad range of control, data acquisition and
processing applications. The VXM1016 is based on a
powerful, single-cycle, RISC-based 8051 processor
with an enhanced MULT/ACCU unit that can be used
to perform complex mathematical operations. The
device includes 56KB of Flash memory and 1280
bytes of RAM.
On-chip analog peripherals such as: an A/D
converter, PWM outputs (that can be used as D/A
converters), a voltage reference and an analog switch
make the VMX51C1020 ideal for analog data
acquisition applications.
The inclusion of a full set of digital interfaces such as
an enhanced, fully configurable SPI, an I²C, UARTs
and a J1708/RS-485 compatible differential
transceiver, enables total system integration.
The VMX51C1016 operates on a 5 volt supply and is
available in a QFP-44 package.
5 6 KB
Program FLASH
(In -Circuit Programmable )
XTVREF Input
33
ADCITA connected to A / D Input
Multiplexer
Band gap
Reference
INT0
1280 B y t e s R A M
PGA
(256 x 8 & 1k X 8)
23
22
34
P2.6-SDO
RESPuW
4 P4W4P
M4
tDpM
u/AtD
ss /A
POW
D
/A
ss
W
MM
8 / 16 bit Resolution
(Can be used as D /A s )
·
·
·
·
·
·
24 I/O s
1 I n t. input
Int. Port1
change
3 Timers ,
2 Baud Rate
Generators
2 CCU inputs
ADCITA
1 DIGITALLY
CONTROLLED
SWITCH
ADCI3
ADCI2
P2.4-SSP2.3-CS0P2.2-CS1P2.1-CS2-
ADCI1
P2.0-CS3-
ADCI0
DGND
XTVREF
AGND
44
12
11
1
P1.3-PWM3
SPI Interface
P1.2-PWM2
P1.1-PWM1
P1.0-PWM0
P0.0-T2IN
P0.1-T2EX
P0.2-TX1
Ramtron International Corporation
1850 Ramtron Drive Colorado Springs
Colorado, USA, 80921
P0.3-RX1
Power On Reset
Circuit
+
WatchDog Timer
RXTX1D+
Clock Control Unit
SW1A
I²C B u s
Interface
RXTX1D-
J 1708 /RS 4 8 5
Compatible
Transceiver
SW1B
XTAL
P2.5-SCK
VMX51C1016
QFP-44
VDDA
[M U L T / A C C U ]
Unit with
BARREL
SHIFTER
VDD
P2.7-SDI
PM
Table 1: Pinout description
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?
?
http://www.ramtron.com
MCU customer service: 1-800-943-4625, 1-514-871-2447, ext. 208
1-800-545-FRAM, 1-719-481-7000
page 1of 76
VMX51C1016
Table 1: Pinout description
PIN
NAME
FUNCTION
34
INT0
External interrupt Input (Negative Level or Edge
Triggered)
Digitally Controlled Switch 1B
35
PM
Mode Control Input
RS-485 Compatible Differential
Transmitter/Receiver, Negative side
36
RES-
Hardware Reset Input (Active low)
37
ADCITA
ADC input 5 and Analog Output
RS-485 Compatible Differential
Transmitter/Receiver, Positive side
38
VDDA
Analog Supply
39
ADCI3
Analog to Digital Converter ext. Input 3
40
ADCI2
Analog to Digital Converter ext. Input 2
41
ADCI1
Analog to Digital Converter ext. Input 1
42
ADCI0
Analog to Digital Converter ext. Input 0
NAME
FUNCTION
1
SW1A
Digitally Controlled Switch 1A
2
SW1B
3
4
5
6
RX1TXD+
P0.3-RX1
P0.2-TX1
I/O - Asynchronous UART1 Receiver Input
I/O - Asynchronous UART1 Transmitter Output
P0.1T2EX
I/O -Timer/Counter 2 Input
8
P0.0-T2IN
I/O -Timer/Counter 2 Input
43
XTVREF
External Reference Voltage Input
9
P1.0PWM0
I/O - Pulse Width Modulator output 0
44
AGND
Analog Ground
10
P1.1PWM1
I/O - Pulse Width Modulator output 1
11
P1.2PWM2
I/O - Pulse Width Modulator output 2
12
P1.3PWM3
I/O - Pulse Width Modulator output 3
13
DGND
Digital Ground
14
P2.0-CS3-
I/O - SPI Chip Enable Output (Master Mode)
15
P2.1-CS2-
I/O - SPI Chip Enable Output (Master Mode)
16
P2.2-CS1-
I/O - SPI Chip Enable Output (Master Mode)
P3.0 TX0
OSC0
P3.1 RX0
P3.3-CCU0
P3.2-T0IN
P3.4-CCU1
P3.5-T1IN
P3.6-SDA
VPP
FIGURE 3: VMX51C1016 PINOUT
P3.7 - SCL
7
RXTX1D-
OSC1
PIN
INT0
34
33 32 31 30 29 28 27 26 25 24 23
22
PM
35
21
P2.7-SDI
RES-
36
20
P2.6-SDO
ADCITA
37
19
P2.5-SCK
18
P2.4-SS-
17
P2.3-CS0-
16
P2.2-CS1P2.1-CS2-
VDD
17
P2.3-CS0-
I/O - SPI Chip Enable Output (Master Mode)
18
P2.4-SS-
I/O - SPI Chip Enable Output (Slave Mode)
19
P2.5-SCK
I/O - SPI Clock (Input in Slave Mode)
VDDA
38
20
P2.6-SDO
I/O - SPI Data Output Bus
ADCI3
39
21
P2.7-SDI
I/O - SPI Data Input Bus
ADCI2
40
22
VDD
Digital Supply
ADCI1
41
15
23
OSC1
Oscillator Crystal Output
ADCI0
42
14
P2.0-CS3-
XTVREF
43
13
DGND
AGND
44
24
OSC0
P3.4CCU1
I/O - Capture and Compare Unit 1 Input
30
P3.5-T1IN
I/O - Timer/Counter 1 Input
31
VPP
Flash Programming Voltage Input
32
P3.6-SDA
I/O - I2C / Prog. Interface Bi-Directional Data
Bus
33
P3.7-SCL
I/O - I2C / Prog. Interface Clock
P1.3-PWM3
10 11
I/O - Asynchronous UART0 Transmitter Output
P1.2-PWM2
29
9
P1.1-PWM1
I/O - Capture and Compare Unit 0 Input
8
P1.0-PWM0
P3.3CCU0
7
P0.1-T2EX
28
6
P0.0-T2IN
I/O - Timer/Counter 0 Input
5
P0.2-TX1
P3.2-T0IN
4
P0.3-RX1
I/O - Asynchronous UART0 Receiver Input
27
3
RXTX1D+
P3.1-RX0
2
SW1A
P3.0-TX0
26
SW1B
25
12
1
RXTX1D-
Oscillator Crystal input/External Clock Source
Input
VMX51C1016
_________________________________________________________________________________________________________
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VMX51C1016
VMX51C1016 Block Diagram
FIGURE 4: VMX51C1016 BLOCK DIAGRAM
8051
µPROCESSOR
SINGLE CYCLE
In -Circuit
Debugging
t h r o u g h U A R T0
A/D input Mux.
2 UARTs
Serial Ports
1 2 -BIT A /D
CONVERTER
56KB
Program FLASH
(In-Circuit Programmable )
XTVREF Input
ADCITA connected to A /D Input
Multiplexer
Band gap
Reference
1280 Bytes RAM
PGA
4POW
PuW
D
4 P4
W4P
MW
tDpMu
ss /A
D
s s
MM
/At/A
8 / 1 6 bit Resolution
(C a n b e u s e d a s D /A s)
(2 5 6x 8 & 1 kX 8 )
·
·
·
·
·
·
2 4 I/O s
1 Int. input
Int. Port 1
change
3 Timers ,
2 Baud Rate
Generators
2 CCU inputs
[M U L T / A C C U ]
Unit with
BARREL
SHIFTER
1 DIGITALLY
CONTROLLED
SWITCH
XTAL
SPI Interface
J1 7 0 8 /R S 4 8 5
Compatible
Transceiver
I²C B u s
Interface
Clock Control Unit
Power On Reset
Circuit
+
WatchDog Timer
_________________________________________________________________________________________________________
page 3 of 76
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VMX51C1016
Absolute Maximum Ratings
VDD to DGND
VDDA to DGND
AGND to DGND
VDD to VDDA
ADCI (0-3) to AGND
XTVREF to AGND
Digital Input Voltage to
DGND
RS485 pin Minimum and
Maximum Voltages
–0.3V, +6V
-0.3V, +6V
–0.3V, +0.3V
-0.3V, +0.3V
-0.3V, VDDA+0.3V
-0.3V, VDDA+0.3V
-0.3V, VDD+0.3V
-2V, +7V
Digital Output Voltage to
DGND
VPP to DGND
Power Dissipation
§
To +75°C
§
Derate above +75°C
Operating Temperature
Range
Storage Temperature Range
–0.3V, VDD+0.3V
+13V
1000mW
10mW/°C
0° to +70°C
–65°C to +150°C
Lead Temperature
(soldering, 10sec)
+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only. The functional operation of the device at these or any other conditions beyond
those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Electrical Characteristics
TABLE 2: ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GENERAL CHARACTERISTICS (VDD = +5V, VDDA = +5V, T A = +25°C, 14.75MHz input clock, unless otherwise noted.)
Power Supply Voltage
VDD
4.75
5.0
5.5
V
VDDA
4.5
5.0
5.5
V
Power Supply Current
IDD (14MHz)
5
45*
mA
*Depends on clock
IDD (1MHz)
0.6
6*
speed and peripheral
use and load
Flash Programming Voltage
DIGITAL INPUTS
Minimum High-Level input
Maximum Low-Level input
Input Current
Input Capacitance
DIGITAL OUTPUTS
Minimum High-Level
Output Voltage
Maximum Low-Level
Output Voltage
Output Capacitance
Tri-state Output Leakage
Current
IDDA
VPP
0.1
11
V
10
V
V
µA
pF
VIH
VIL
IIN
CIN
VDD = +5V
VDD = +5V
VOH
ISOURCE = 4mA
4.2
V
VOL
ISINK = 4mA
0.2
V
COUT
IOZ
2.0
0.8
±0.05
5
5*
13
10
15
0.25
pF
µA
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page 4 of 76
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VMX51C1016
ANALOG INPUTS
ADCI(0-3) Input Voltage Range
ADCI(0-3) Input Resistance
ADCI(0-3) Input Capacitance
ADCI(0-3)
Input
Leakage
Current
Channel-to-Channel Crosstalk
VADCI
RADCI
CADCI
IADCI
0
2.7
100
7
TBD
-72
(12 bit)
INTERNAL REFERENCE
Bandgap Reference Voltage
Bandgap Reference Tempco
EXTERNAL REFERENCE
Input Impedance
RXTVREF
PGA
PGA Gain adjustment
ANALOG TO DIGITAL CONVERTER
1.18
1.23V
100
1.28
150
2.11
V
Mohms (design)
pF
nA
dB
(design)
V
ppm/°C
kOhms
2.29
External Reference, TA=25C, Fosc = 16MHz
ADC Resolution
Differential Non linearity
Integral Non linearity
Full-Scale Error (Gain Error)
Offset Error
Channel-to-Channel Mismatch
Sampling Rate
12
DNL
INL
-1
All channels, ADCI(0-3)
All channels, ADCI(0-3)
All channels, ADCI(0-3)
Single Channel
1
4 Channels
1
UART1 DIFFERENTIAL TRANSCEIVER COMPATIBLE TO J1708/ RS-485
Common mode Input Voltage
VcI
-2
Input Impedance
ZIN
Output Drive Current
Differential Input
DIGITAL SWITCH
Switch on Resistance
50
Input capacitance
Voltage range on Pin
0
Allowable current (DC)
BROWN OUT / RESET CIRCUIT
Brown-out circuit Threshold
3.7
RES- pin internal Pull-Up
±1.5
+4
±4
±1
±1
10k
2.5k
+7
V
MOhms
mA
mV
100
Ohms (+/-10%)
pF
V
mA
1
30
100mV
4
5
5
4.0
20
Bits
LSB
LSB
LSB
LSB
LSB
Hz
V
KOhms
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page 5 of 76
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VMX51C1016
Detailed Description
Memory Organization
The following sections describe the VMX51C1016
architecture and peripherals.
Figure 6 shows the memory organization of the
VMX51C1016.
At power-up/reset, code is executed from the
56Kx8 Flash memory mapped into the processor’s
internal program space.
FIGURE 5: INTERFACE DIAGRAM FOR THE VERSA MIX
+5V Digital
VDD
+5V Analog
VDDA
VERSA
MIX
AGND
T0IN
T1IN
T2IN
T2EX
TIMERS
DGND
ADCI0
ADCI1
ADCI2
ADCI3
EXTERNAL A/D
INPUTS
ISRCOUT
ISRCIN
CURRENT SOURCE
UART 0
UART 0
INTERFACE
UART 1
UART 1
INTERFACE
DIFFERENTIAL
TRANSCEIVER
CCU0
CCU1
CCU2
SW1A
SW1B
DIGITAL
SWITCH
UART1 DIFF.
TRANSCEIVER
J1708/RS-485 /
RS422
COMPARE AND
CAPTURE UNITS
INPUTS
I/O
RESET
OP-AMP
POTENTIOMETERS
POT1A
POT1B
POT2A
SCL
SDA
I2C
INTERFACE
INT0
INT1
EXTERNAL
INTERRUPTS
PWM0
PWM1
PWM2
PWM3
FIGURE 7: LOWER 128 BYTES BLOCK INTERNAL MEMORY MAP
LOWER 128 BYTES OF
INTERNAL DATA MEMORY
7Fh
SDI
POT2B
PWM
OUTPUTS
The following figure describes the access to the
lower block of 128 bytes.
I/Os
RESOPOUT
OPINOPIN+
A 1KB block of RAM is also mapped into the
external data memory of the VMX51C1016. This
block can be used as a general-purpose scratch
pad or storage memory. A 256 byte block of RAM
is mapped to the internal data memory space. This
block of RAM is broken into two sub-blocks, with
the upper block accessible via indirect addressing
only and the lower block accessible via both direct
and indirect addressing.
OSC0 OSC1
SDO
SCK
SSCS0CS1CS2CS3-
DIRECT
RAM
SPI
INTERFACE
30h
2Fh
REGISTER
BANK SELECT
The value of the
RS1, RS0 bits of
PSW SFR
Register (D0h)
defines the
selected R0 -R7
Register Bank
FIGURE 6: MEMORY ORGANIZATION OF THE VERSA MIX
INTERNAL PROGRAM
MEMORY SPACE
DFFFh
56KB
FLASH
MEMORY
8051
COMPATIBLE
µ-PROCESSOR
(SingleCycle)
0000h
EXTERNAL DATA
MEMORY SPACE
03FFh
1KB
RAM
0000h
INTERNAL DATA
MEMORY SPACE
FFh
80h
7Fh
128 Bytes
SFR SPACE RAM
PERIPHERALS
(INDIRECT
(DIRECT
ADDRESSING ADDRESSING)
FFh
BITADDRESSABLE
REGISTERS
11h
10h
01h
00h
20h
1Fh
18h
17h
10h
0Fh
08h
07h
00h
BANK 3
BANK 2
BANK 1
BANK 0
The SFR (special function register) space is also
mapped into the upper 128 bytes of internal data
memory space. This SFR space is only accessible
using direct-access. The SFR space provides the
interface to all the on-chip peripherals. This
interfacing is illustrated in Figure 8.
80h
128 Bytes
RAM
(DIRECT &
INDIRECT
00h ADDRESSING)
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VMX51C1016
FIGURE 8: SFR ORGANIZATION
ADC
CONTROL
The SFR locations and register representations
related to the dual data pointers are outlined as
follows:
SPI BUS
TABLE 3: (DPH0) DATA POINTER HIGH 0 - SFR 83H
DIFF
TRANSCEIVER
INTERNAL DATA
MEMORY SPACE
FFH
SFR SPACE PERIPHERALS
(DIRECT
ADDRESSING)
80H
CLOCK
CONTROL
I2C BUS
15
14
13
12
11
DPH0 [7:0]
I/O CONTROL
8051
PROCESSOR
PERIPHERALS
9
8
2
1
0
10
9
8
2
1
0
1
0
0
SEL
TABLE 4: (DPL0) DATA POINTER LOW 0 - SFR 82H
7
6
5
4
3
DPL0 [7:0]
PERIPHERAL
INTERRUPTS
MAC
10
Bit
15-8
7-0
Mnemonic
DPH0
DPL0
Function
Data Pointer 0 MSB
Data Pointer LSB.
TABLE 5: (DPH1) DATA POINTER HIGH 1 - SFR 85H
15
14
13
12
11
DPH1 [7:0]
TABLE 6: (DPL1) DATA POINTER LOW 1 - SFR 84H
Dual Data Pointers
The VMX51C1016 includes two data pointers.
The first data pointer (DPTR0) is mapped into SFR
locations 82h and 83h. The second data pointer
(DPTR1) is mapped into SFR locations 84h and
85h. The SEL bit in the data pointer select register,
DPS (SFR 86h), selects which data pointer is
active. When SEL = 0, instructions that use the
data pointer will use DPL0 and DPH0. When SEL
= 1, instructions that use the DPTR will use DPL1
and DPH1. SEL is located in bit 0 of the DPS (SFR
location 86h). The remaining bits of SFR location
86h are unused.
All DPTR-related instructions use the currently
selected data pointer. In order to switch the active
pointer, toggle the SEL bit. The fastest way to do
this is to use the increment instruction (INC DPS).
The use of the two data pointers can significantly
increase the speed of moving large blocks of data
because only one instruction is needed to switch
from a source address and destination address.
7
Bit
15-8
7-0
6
5
Mnemonic
DPH1
DPL1
4
3
DPL1 [7:0]
Function
Data Pointer 1 MSB.
Data Pointer 1 LSB.
TABLE 7: (DPS) DATA POINTER SELECT REGISTER - SFR 86H
7
0
Bit
7-1
0
6
0
5
0
Mnemonic
0
SEL
4
0
3
0
2
0
Function
Always zero
0 = DPTR0 is selected
1 = DPTR1 is selected
Used to toggle between both data
pointers
MPAGE Register
The MPAGE register controls the upper 8 bits of
the targeted address when the MOVX instruction is
used for external RAM data transfer. This allows
access to the entire external RAM content without
using the data pointer.
TABLE 8: (MPAGE) MEMORY PAGE - SFR CF H
7
6
5
4
3
2
MPAGE [7:0]
1
0
User Flags
The VMX51C1016 provides an SFR register that
allows the user to define software flags. Each bit of
this register is individually addressable. This
register may also be used as a general-purpose
storage location. Thus, the user flag feature allows
the VMX51C1016 to better adapt to each specific
application. This register is located at SFR address
F8h.
TABLE 9: (USERFLAGS) USER FLAG - SFR F8H
7
UF7
6
UF6
5
UF5
4
UF4
3
UF3
2
UF2
1
UF1
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0
UF0
VMX51C1016
Instruction Set
Mnemonic
Description
Size
(bytes)
Instr.
Cycles
Data Transfer Instructions
All VMX51C1016 instructions are function and
binary code compatible with industry standard
8051s. However, the timing of instruction sets may
be different. The following two tables describe the
VMX51C1016 instruction set.
TABLE 10: LEGEND FOR INSTRUCTION SET TABLE
Symbol
Function
A
Accumulator
Rn
Register R0-R7
Direct
Internal register address
@Ri
Internal register pointed to by R0 or R1 (except MOVX)
rel
Two's complement offset byte
bit
Direct bit address
#data
8-bit constant
#data 16
16-bit constant
addr 16
16-bit destination address
addr 11
11-bit destination address
TABLE 11: VERSA MIX INSTRUCTION SET
Mnemonic
Description
Size
(bytes)
Instr.
Cycles
Arithmetic instructions
ADD A, Rn
Add register to A
1
1
ADD A, direct
Add direct byte to A
2
2
ADD A, @Ri
Add data memory to A
1
2
ADD A, #data
Add immediate to A
2
2
ADDC A, Rn
Add register to A with carry
1
1
ADDC A, direct
Add direct byte to A with carry
2
2
ADDC A, @Ri
Add data memory to A with carry
1
2
ADDC A, #data
Add immediate to A with carry
2
2
SUBB A, Rn
Subtract register from A with borrow
1
1
SUBB A, direct
Subtract direct byte from A with borrow
2
2
SUBB A, @Ri
Subtract data mem from A with borrow
1
2
SUBB A, #data
Subtract immediate from A with borrow
2
2
INC A
Increment A
1
1
INC Rn
Increment register
1
2
INC direct
Increment direct byte
2
3
INC @Ri
Increment data memory
1
3
DEC A
Decrement A
1
1
DEC Rn
Decrement register
1
2
DEC direct
Decrement direct byte
2
3
DEC @Ri
Decrement data memory
1
3
INC DPTR
Increment data pointer
1
1
MUL AB
Multiply A by B
1
5
DIV AB
Divide A by B
1
5
DA A
Decimal adjust A
1
1
ANL A, Rn
AND register to A
1
1
ANL A, direct
AND direct byte to A
2
2
ANL A, @Ri
AND data memory to A
1
2
ANL A, #data
AND immediate to A
2
2
ANL direct, A
AND A to direct byte
2
3
ANL direct, #data
AND immediate data to direct byte
3
4
ORL A, Rn
OR register to A
1
1
ORL A, direct
OR direct byte to A
2
2
ORL A, @Ri
OR data memory to A
1
2
ORL A, #data
OR immediate to A
2
2
ORL direct, A
OR A to direct byte
2
3
ORL direct, #data
OR immediate data to direct byte
3
4
XRL A, Rn
Exclusive-OR register to A
1
1
XRL A, direct
Exclusive-OR direct byte to A
2
2
XRL A, @Ri
Exclusive-OR data memory to A
1
2
XRL A, #data
Exclusive-OR immediate to A
2
2
XRL direct, A
Exclusive-OR A to direct byte
2
3
XRL direct, #data
Exclusive-OR immediate to direct byte
3
4
CLR A
Clear A
1
1
CPL A
Compliment A
1
1
SWAP A
Swap nibbles of A
1
1
RL A
Rotate A left
1
1
RLC A
Rotate A left through carry
1
1
RR A
Rotate A right
1
1
RRC A
Rotate A right through carry
1
1
Logical Instructions
MOV A, Rn
Move register to A
1
1
MOV A, direct
Move direct byte to A
2
2
MOV A, @Ri
Move data memory to A
1
2
MOV A, #data
Move immediate to A
2
2
MOV Rn, A
Move A to register
1
2
MOV Rn, direct
Move direct byte to register
2
4
MOV Rn, #data
Move immediate to register
2
2
MOV direct, A
Move A to direct byte
2
3
MOV direct, Rn
Move register to direct byte
2
3
MOV direct, direct
Move direct byte to direct byte
3
4
MOV direct, @Ri
Move data memory to direct byte
2
4
MOV direct, #data
Move immediate to direct byte
3
3
MOV @Ri, A
Move A to data memory
1
3
MOV @Ri, direct
Move direct byte to data memory
2
5
MOV @Ri, #data
Move immediate to data memory
2
3
MOV DPTR, #data16
Move immediate 16 bit to data pointer
3
3
MOVC A, @A+DPTR
Move code byte relative DPTR to A
1
3
MOVC A, @A+PC
Move code byte relative PC to A
1
3
MOVX A, @Ri
Move external data (A8) to A
1
3-10
MOVX A, @DPTR
Move external data (A16) to A
1
3-10
MOVX @Ri, A
Move A to external data (A8)
1
4-11
MOVX @DPTR, A
Move A to external data (A16)
1
4-11
PUSH direct
Push direct byte onto stack
2
4
POP direct
Pop direct byte from stack
2
3
XCH A, Rn
Exchange A and register
1
2
XCH A, direct
Exchange A and direct byte
2
3
XCH A, @Ri
Exchange A and data memory
1
3
XCHD A, @Ri
Exchange A and data memory nibble
1
3
Branching Instructions
ACALL addr 11
Absolute call to subroutine
2
6
LCALL addr 16
Long call to subroutine
3
6
RET
Return from subroutine
1
4
RETI
Return from interrupt
1
4
AJMP addr 11
Absolute jump unconditional
2
3
LJMP addr 16
Long jump unconditional
3
4
SJMP rel
Short jump (relative address)
2
3
JC rel
Jump on carry = 1
2
3
JNC rel
Jump on carry = 0
2
3
JB bit, rel
Jump on direct bit = 1
3
4
JNB bit, rel
Jump on direct bit = 0
3
4
JBC bit, rel
Jump on direct bit = 1 and clear
3
4
JMP @A+DPTR
Jump indirect relative DPTR
1
2
JZ rel
Jump on accumulator = 0
2
3
JNZ rel
Jump when accumulator not equal to 0
2
3
CJNE A, direct, rel
Compare A, direct JNE relative
3
4
CJNE A, #data, rel
Compare A, immediate JNE relative
3
4
CJNE Rn, #data, rel
Compare reg, immediate JNE relative
3
4
CJNE @Ri, #data, rel
Compare ind, immediate JNE relative
3
4
DJNZ Rn, rel
Decrement register, JNZ relative
2
3
DJNZ direct, rel
Decrement direct byte, JNZ relative
3
4
Bit Operations
CLR C
Clear carry flag
1
1
CLR bit
Clear direct bit
2
3
SETB C
Set carry flag
1
1
SETB bit
Set direct bit
2
3
CPL C
Complement carry Flag
1
1
CPL bit
Complement direct bit
2
3
ANL C,bit
Logical AND direct bit to carry flag
2
2
ANL C, /bit
Logical AND between /bit and carry flag
2
2
ORL C,bit
Logical OR bit to carry flag
2
2
ORL C, /bit
Logical OR /bit to carry flag
2
2
MOC c,bit
Copy direct bit location to carry flag
2
2
MOV bit,C
Copy carry flag to direct bit location
2
3
No operation
1
1
Miscellaneous Instruction
NOP
_________________________________________________________________________________________________
page 8 of 76
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VMX51C1016
Special Function Registers
The special function registers (SFRs) control several features on the VMX51C1016. Many of the device’s
SFRs are identical to the standard 8051 SFRs. However, there are additional SFRs that control the
VMX51C1016’s specific peripheral features that are not available on the standard 8051.
TABLE 12: SPECIAL FUNCTION REGISTERS
SFR Register
P0
SP
DPL0
DPH0
DPL1
DPH1
DPS
PCON
TCON*
TMOD
TL0
TL1
TH0
TH1
Reserved
Reserved
P1*
IRCON
ANALOGPWREN
DIGPWREN
CLKDIVCTRL
ADCCLKDIV
S0RELL
S0RELH
S0CON*
S0BUF
IEN2
P0PINCFG
P1PINCFG
P2PINCFG
P3PINCFG
PORTIRQEN
P2*
PORTIRQSTAT
ADCCTRL
ADCCONVRLOW
ADCCONVRMED
ADCCONVRHIGH
ADCD0LO
ADCD0HI
IEN0*
ADCD1LO
ADCD1HI
ADCD2LO
ADCD2HI
ADCD3LO
ADCD3HI
Reserved
P3*
Reserved
Reserved
BGAPCAL
PGACAL
INMUXCTRL
OUTMUXCTRL
SWITCHCTRL
IP0*
IP1
Reserved
Reserved
SFR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Value
Adrs
80h
1111 1111b
81h
0000 0111b
82h
0000 0000b
83h
0000 0000b
84h
0000 0000b
85h
0000 0000b
86h
0
0
0
0
0
0
0
SEL
0000 0000b
87h
SMOD
GF1
GF0
STOP
IDLE
0000 0000b
88h
TF1
TR1
TF0
TR0
IE0
IT0
0000 0000b
89h
CT1
M11
M01
GATE0
CT0
M10
M00
0000 0000b
8Ah
0000 0000b
8Bh
0000 0000b
8Ch
0000 0000b
8Dh
0000 0000b
8Eh
8Fh
90h
1111 1111b
91h
T2EXIF
T2IF
ADCIF
MACIF
I2CIF
SPIRXIF
SPITXIF
Reserved
0000 0000b
92h
0
0
0
0
TAEN
ADCEN
PGAEN
BGAPEN
0000 0000b
UART1DIFFEN UART1EN
93h
T2CLKEN
WDOGEN
MACEN
I2CEN
SPIEN
UART0EN
0000 0000b
IRQNORMSPD MCKDIV_3 MCKDIV_2 MCKDIV_1 MCKDIV_0
94h
SOFTRST
0000 0000b
95h
0000 0000b
96h
11011001b
97h
0
0
0
0
0
0
0000 0011b
98h
S0M0
S0M1
MCPE0
R0EN
T0B8
R0B8
T0I
R0I
0000 0000b
99h
0000 0000b
9Ah
S1IE
0000 0000b
9Bh
P0.3/RX1INE P0.2/TX1OE P0.1/T2EXINE P0.0/T2INE 0000 0000b
9Ch
PWM3EN
PWM2EN
PWM1EN
PWM0EN
9Dh
SDIEN
SDOEN
SCKEN
SSEN
CS0EN
CS1EN
CS2EN
CS3EN
0000 0000b
9Eh
MSCLEN
MSDAEN
T1INEN
CCU1EN
CCU0EN
T0INEN
RX0EN
TX0EN
0000 0000b
9Fh
0
0
0
0
P13IEN
P12IEN
P11IEN
P10IEN
0000 0000b
A0h
1111 1111b
A1h
P13ISTAT
P12ISTAT
P11ISTAT
P10ISTAT
0000 0000b
A2h ADCIRQCLR XVREFCAP
1
ADCIRQ
ADCIE
ONECHAN
CONT
ONESHOT
0000 0000b
A3h
0000 0000b
A4h
0000 0000b
A5h
0000 0000b
A6h
0000 0000b
A7h
ADCD0HI_3 ADCD0HI_2 ADCD0HI_1 ADCD0HI_0 0000 0000b
A8h
EA
WDT
T2IE
S0IE
T1IE
0
T0IE
INT0IE
0000 0000b
A9h
0000 0000b
AAh
ADCD1HI_3 ADCD1HI_2 ADCD1HI_1 ADCD1HI_0 0000 0000b
ABh
0000 0000b
ACh
ADCD2HI_3 ADCD2HI_2 ADCD2HI_1 ADCD2HI_0 0000 0000b
ADh
0000 0000b
AEh
ADCD3HI_3 ADCD3HI_2 ADCD3HI_1 ADCD3HI_0 0000 0000b
AFh
B0h
1111 1111b
B1h
B2h
B3h
0000 0000b
B4h
0000 0000b
ADCINSEL_2 ADCINSEL_1 ADCINSEL_0 AINEN_3
AINEN_2
AINEN_1
AINEN_0
0000 0000b
B5h
TAOUTSEL_2 TAOUTSEL_1 TAOUTSEL_0 0000 0000b
B6h
B7h
SWITCH1_3 SWITCH1_2 SWITCH1_1 SWITCH1_0 0000 0000b
B8h
UF8
WDTSTAT
IP0.5
IP0.4
IP0.3
IP0.2
IP0.1
IP0.0
0000 0000b
B9h
IP1.5
IP1.4
IP1.3
IP1.2
IP1.1
IP1.0
0000 0000b
BAh
0000 0000b
BBh
0000 0000b
_________________________________________________________________________________________________
page 9 of 76
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VMX51C1016
SFR Register
PGACAL0
Reserved
S1RELL
S1RELH
S1CON*
S1BUF
CCL1
CCH1
CCL2
CCH2
CCL3
CCH3
T2CON*
CCEN
CRCL
CRCH
TL2
TH2
Reserved
MPAGE
PSW*
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
U0BAUD
WDTREL
I2CCONFIG
I2CCLKCTRL
I2CCHIPID
I2CIRQSTAT
I2CRXTX
Reserved
ACC*
SPIRX3TX0
SPIRX2TX1
SPIRX1TX2
SPIRX0TX3
SPICTRL
SPICONFIG
SPISIZE
IEN1*
SPIIRQSTAT
Reserved
MACCTRL1
MACC0
MACC1
MACC2
MACC3
B*
MACCTRL2
MACA0
MACA1
MACRES0
MACRES1
MACRES2
MACRES3
USERFLAGS*
MACB0
MACB1
SFR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Adrs
BCh PGACAL0
BDh
BEh
BFh
C0h
S1M
reserved
MCPE1
R1EN
T1B8
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
T2PS
T2PSM
T2SIZE
T2RM1
T2RM0
C9h
COCAH3
COCAL3
COCAH2
COCAL2
COCAH1
CAh
CBh
CCh
CDh
CEh
CFh
D0h
CY
AC
F0
RS1
RS0
D1h
D2h
D3h
D4h
D5h
D6h
D7h
D8h BAUDSRC
D9h
PRES
WDTREL_6 WDTREL_5 WDTREL_4 WDTREL_3
DAh I2CMASKID I2CRXOVIE I2CRXDAVIE I2CTXEMPIE I2CMANACK
DBh
DCh
I2CID_6
I2CID_5
I2CID_4
I2CID_3
I2CID_2
I2CSDAS I2CDATACK
DDh I2CGOTSTOP I2CNOACK
I2CIDLE
DEh
DFh
E0h
E1h
E2h
E3h
E4h
E5h
SPICK_2
SPICK_1
SPICK_0
SPICS_1
SPICS_0
E6h
SPICSLO
FSONCS3 SPI LOAD
E7h
E8h
T2EXIE
SWDT
ADCPCIE
MACOVIE
I2CIE
SPITXEMPTO SPISLAVESEL
E9h
SPISEL
EAh
EBh LOADPREV PREVMODE OVMODE OVRDVAL ADDSRC_1
ECh
EDh
EEh
EFh
F0h
F1h MACCLR2_2 MACCLR2_1 MACCLR2_0 MACOV32IE
F2h
F3h
F4h
F5h
F6h
F7h
F8h
UF7
UF6
UF5
UF4
UF3
F9h
FAh
-
MACSHIFTCTRL
FBh
SHIFTMODE
MACPREV0
MACPREV1
MACPREV2
MACPREV3
* Bit addressable
FCh
FDh
FEh
FFh
-
Bit 2
Bit 1
Bit 0
Reset Value
R1B8
T2CM
COCAL1
-
T1I
T2IN1
COCAH0
-
R1I
T2IN0
COCAL0
-
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
OV
reserved
P
0000 0000b
0000 0000b
WDTREL_2 WDTREL_1 WDTREL_0
I2CACKMODE I2CMSTOP I2CMASTER
I2CID_1
I2CID_0
I2CWID
I2CRXOV
I2CRXAV I2CTXEMP
-
-
-
-
-
-
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
SPICKPH SPICKPOL SPIMA_SL
0000 0001b
SPIRXOVIE SPIRXAVIE SPITXEMPIE 0000 0000b
0000 0111b
SPIRXOVIE
SPITEIE
reserved
0000 0000b
SPIOV
SPIRXAV SPITXEMP
00011001b
ADDSRC_0 MULCMD_1 MULCMD_0
MACOV16 MACOV32
UF2
UF1
UF0
-
ALSHSTYLE SHIFTAMPL_5 SHIFTAMPL_4 SHIFTAMPL_3 SHIFTAMPL_2 SHIFTAMPL_1 SHIFTAMPL_0
-
-
-
-
0000 0000b
0000 0000b
0000 0010b
0000 0000b
0100 0010b
0010 1001b
0000 0000b
-
-
-
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
_________________________________________________________________________________________________
page 10 of 76
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VMX51C1016
Peripheral Activation Control
Analog Peripherals Power Enable
Digital Peripherals Power Enable
The analog peripherals, such as the A/D,
bandgap and PGA analog-to-digital converter,
have a shared dedicated register used for
enabling and disabling these peripherals. By
default, these peripherals are powered down
when the device is reset.
To save power upon reset, many of the digital
peripherals of the VMX51C1016 are not
activated. The peripherals affected by this are:
o
o
o
o
o
o
o
o
Timer 2 / Port1
Watchdog timer
MULT/ACCU unit
I²C interface
SPI interface
UART0
UART1
Differential transceiver
TABLE 14: (ANALOGPWREN) ANALOG PERIPHERALS POWER ENABLE REGISTER SFR 92H
Before using any of the above-listed peripherals,
they must first be enabled by setting the
corresponding bit of the DIGPWREN SFR
register to 1.
The same rule applies when accessing a given
peripheral’s SFR register(s). The targeted
peripheral must have been powered on
(enabled) first, otherwise the SFR register
content will be ignored
The following table demonstrates the structure
of the DIGPWREN register.
7
0
6
0
5
0
4
0
3
0
2
ADCEN
1
PGAEN
0
BGAPEN
Bit
7
6
5
4
Mnemonic
0
0
0
0
3
TAEN
2
ADCEN
1
PGAEN
0
BGAPEN
Note:
Function
Reserved, Keep at 0
Reserved, Keep at 0
Reserved, Keep at 0
Reserved, Keep at 0
1 = TA Output Enable
0 = TA Output Disable
1 = ADC Enable
0 = ADC Disable
1 = PGA Enable
0 = PGA Disable
1 = Bandgap Enable
0 = Bandgap Disable
The SFR registers associated with all
analog peripherals are activated when
one or more analog peripherals are
enabled.
TABLE 13: (DIGPWREN) DIGITAL PERIPHERALS POWER ENABLE REGISTER - SFR
93H
7
T2CLKEN
3
SPIEN
Bit
6
WDOGEN
2
UART1DIFFEN
Mnemonic
7
T2CLKEN
6
WDOGEN
5
MACEN
4
I2CEN
3
SPIEN
2
UART1DIFFEN
1
UART1EN
0
UART0EN
5
MACEN
4
I2CEN
1
UART1EN
0
UART0EN
Function
Timer 2 / PWM Enable
0 = Timer 2 CLK stopped
1 = Timer 2 CLK Running
Watch Dog Enable
0 = Watch Dog Disable
1 = Watch Dog Enable
1 = MULT/ACCU Unit Enable
0 = MULT/ACCU Unit Disable
1= I2C Interface Enable
0 = I2C Interface Disable
This bit is merged with CLK STOP bit
1 = SPI interface is Enable
0 = SPI interface is Disable
UART1 Differential mode
0 = Disable
1 = Enable
0 = UART1 Disable
1 = UART1 Enable
0 = UART0 Disable
1 = UART0 Enable
_________________________________________________________________________________________________
page 11 of 76
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VMX51C1016
General Purpose I/O
FIGURE 10: T YPICAL I/O VOUT VS. SOURCE CURRENT
5.00
At reset, all the VMX51C1016 I/O ports are
configured as inputs. The I/O ports are bidirectional and the CPU can write or read data
through any of these ports.
4.90
I/O output voltage (Volts)
The VMX51C1016 provides 24 general-purpose
I/O pins. The I/Os are shared with digital
peripherals and can be configured individually.
4.80
4.70
4.60
I/O Port Structure
4.50
The VMX51C1016 I/O port structure is shown in
the following figure.
0.0
2.0
4.0
6.0
8.0
10.0
8.0
10.0
I/O current source (mA)
FIGURE 11: T YPICAL I/O VOUT VS. SINK CURRENT
FIGURE 9 – I/O PORT STRUCTURE
0.50
I/O output voltage (Volts)
0.40
VCC
OE
VCC
Driver
I/O
Control
logic
0.30
0.20
0.10
I/O
0.00
0.0
TTL
Each I/O pin includes pull-up circuitry
(represented by the internal pull-up resistor) and
a pair of internal protection diodes internally
connected to VCC and ground, providing ESD
protection.
The I/O operational configuration is defined in
the I/O control logic block.
I/O Port Drive Capability
2.0
4.0
6.0
I/O current sink (mA)
The maximum recommended driving current of a
single I/O on a given port is 10mA. The
recommended limit when more than one I/O on
a given port is driving current is 5mA on each
I/O. The total current drive of all I/O ports should
be limited to 40mA
The following figure shows a typical I/O rise time
when driving a 20pF capacitive load. In this
case, rise time is about 14ns.
FIGURE 12: I/O RISE T IME WITH A 20PF LOAD
Each I/O port pin, when configured as an output,
can source or sink up to 4mA. The following
graphs show typical I/O output voltage versus
source and I/O output voltage versus sink
current.
_________________________________________________________________________________________________
page 12 of 76
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VMX51C1016
Input Voltage vs. Ext. Device Sink
The I/Os of the VMX51C1016, when configured
as inputs, include an internal pull-up resistor
made up of a transistor, which ensures that the
level present at input is stable when the I/O pins
are disconnected.
Due to the presence of the pull-up resistor on
the digital inputs, the external device driving the
I/O must be able to sink enough current to bring
the I/O pin low.
The following figure shows the VMX51C1016
input port voltage versus the external device
sink current.
The following registers are used to configure
each of the ports as either general-purpose
inputs, outputs or alternate peripheral functions.
For example, when bit 5 of Port 2 is configured
as an output, it will output the SCK signal if the
SPI interface is enabled and working.
The only exception to this rule is the I2C clock
and data bus signals. In these two cases, the
VMX51C1016 configures the pins automatically
as inputs or outputs.
The P0PINCFG register controls the I/O access
to UART1 and Timer 2’s input and output, and
defines the direction of P0 when used as a
general purpose I/O.
TABLE 15: (P0PINCFG) PORT 0 PORT CONFIGURATION REGISTER - SFR 9BH
FIGURE 13: INPUT PORT VOLTAGE
6
5
4
P06IO
P05IO
P04IO
VS . EXT DEVICE SINK CURRENT
5.0
4.0
I/O Input Voltage (Volts)
7
P07IO
3
2
1
0
P0.3/RX1INE
P0.2/TX1OE
P0.1/T2EXINE
P0.0/T2INE
Bit
7:4
3
Mnemonic
P0xIO
P0.3/RX1INE
2
P0.2/TX1OE
1
P0.1/T2EXINE
0
P0.0/T2INE
3.0
2.0
1.0
0.0
0
20
40
60
80
100
120
140
160
180
Ext. device sink current (uA)
I/O Port Configuration Registers
The VMX51C1016’s I/O port operation is
controlled by two sets of four registers:
o
o
Function
Not connected on VMX51C1016
0: General purpose input or
UART1 RX
1: General purpose output
When using UART1 you must
set this bit to 0.
0: General purpose input
1: General purpose output or
UART1 TX
When using UART1 you must
set this bit to 1.
0: General purpose input or
Timer 2 EX
1: General purpose output
When using Timer 2EX input
you must set this bit to 0.
0: General purpose input or
Timer 2 IN
1: General purpose output
When using Timer 2 input you
must set this bit to 0.
Port pin configuration registers
Port access registers
The port pin configuration registers combined
with specific peripheral configuration will define
whether a given pin acts as a general purpose
I/O or provides the alternate peripheral
functionality.
Before using a peripheral that is shared with
I/Os, the pin corresponding to the peripheral
output must be configured as an output and the
pins that are shared with the peripheral inputs
must be configured as inputs.
_________________________________________________________________________________________________
page 13 of 76
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VMX51C1016
The P1PINCFG register controls access from
the PWM to the I/O pins and defines the
direction of P1 when the PWM’s are not used.
The P2PINCFG register controls I/O access to
the SPI interface and defines the direction of P2
when used as a general purpose I/O.
TABLE 16: (P1PINCFG) PORT 1 PORT CONFIGURATION REGISTER - SFR 9C H
TABLE 17: (P2PINCFG) PORT 2 PORT CONFIGURATION REGISTER - SFR 9D H
7
6
5
4
P1[7:4]
3
2
1
0
P1.3/PWM3EN
P1.2/PWM2EN
P1.1/PWM1EN
P1.0/PWM0EN
Bit
7:4
Mnemonic
P1[7:4]
3
P1.3/PWM3OE
2
1
0
P1.2/PWM2OE
P1.1/PWM1OE
P1.0/PWM0OE
Function
Not connected on
VMX51C1016
0: General purpose input
1: General purpose output
or PWM bit 3 output
7
6
5
4
P2.7/SDIEN
P2.6/SDOEN
P2.5/SCKEN
P2.4/SSEN
Bit
7
When using PWM you
must set this bit to 1.
0: General purpose input
1: General purpose output
or PWM bit 2 output
6
When using PWM you
must set this bit to 1
0: General purpose input
1: General purpose output
or PWM bit 1 output
5
When using PWM you
must set this bit to 1
0: General purpose input
1: General purpose output
or PWM bit 0 output
4
When using PWM you
must set this bit to 1
3
2
1
0
3
2
1
0
CS0EN
CS1EN
CS2EN
CS3EN
Mnemonic
P2.7/SDIEN
Function
0: General purpose input or SDI
1: General purpose output
P2.6/SDOEN
When using SPI you must set
this bit to 0.
0: General purpose input
1: General purpose output or
SDO
P2.5/SCKEN
When using SPI you must set
this bit to 1.
0: General purpose input or
SCK
1: General purpose output
P2.4/SSEN
When using SPI you must set
this bit to 0.
0: General purpose input or
Slave Select
1: General purpose output
P2.3/CS0EN
When using SPI SS you must
set this bit to 0.
0: General purpose input
1: General purpose output or
Chip Select bit 0 output
P2.2/CS1EN
When using SPI CS0 you
must set this bit to 1.
0: General purpose input
1: General purpose output or
Chip Select bit 1 output
P2.1/CS2EN
When using SPI CS1 you
must set this bit to 1.
0: General purpose input
1: General purpose output or
Chip Select bit 2 output
P2.0/CS3EN
When using SPI CS2 you
must set this bit to 1.
0: General purpose input
1: General purpose output or
Chip Select bit 3 output
When using SPI CS3 you
must set this bit to 1.
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VMX51C1016
The P3PINCFG register controls I/O access to
UART0, the I²C interface, capture and compare
inputs 0 and 1 and timer 0/1’s inputs, and
defines the direction of P3 when used as a
general purpose I/O.
TABLE 18: (P3PINCFG) PORT 3 PORT CONFIGURATION REGISTER - SFR 9EH
7
P3.7/MSCLEN
6
5
4
P3.6/MSDAEN
P3.5/T1INE
N
P3.4/CCU1E
N
3
2
1
0
P3.3/CCU0EN
P3.2/T0INEN
P3.1/RX0EN
P3.0/TX0EN
Bit
7
Mnemonic
P3.7/MSCLEN
6
P3.6/MSDAEN
5
P3.5/T1INEN
Function
0: General purpose input
1: General purpose output or
Master I2C SCL output
location is defined. These registers are bit
addressable, providing the ability to control the
I/O lines individually. The upper 4 bits of Port 0
and Port 1 are not pinned out.
When the port pin configuration register value
defines the pin as an output, the value written
into the port register will be reflected at the pin
level.
Reading the I/O pin configured as input is done
by reading the contents of its associated port
register.
TABLE 19:
PORT 0 - SFR 80H
7
6
5
When using the I2C you must
set this bit to 1.
0: General purpose input
1: General purpose output or
Master I2C SDA
PORT 1 - SFR 90H
When using the I2C you must
set this bit to 1.
0: General purpose input or
Timer1 Input
1: General purpose output
PORT 3 - SFR B0H
7
6
4
2
1
0
5
4
3
P1 [7:0]
2
1
0
5
4
3
P2 [7:0]
2
1
0
5
4
3
P3 [7:0]
2
1
0
PORT 2 - SFR A0H
7
7
Bit
7-0
6
6
Mnemonic
P0, 1, 2, 3
When using Timer 1 you must
set this bit to 0.
0: General purpose input or
CCU1 Input
1: General purpose output
4
3
P0 [7:0]
Function
When the Port is configured as an
output, setting a port pin to 1 will
make the corresponding pin to
output logic high.
When set to 0, the corresponding
pin will set a logic low.
P3.4/CCU1EN
When using the Compare and
Capture unit you must set this
bit to 0.
0: General purpose input or
CCU0 Input
1: General purpose output
3
P3.3/CCU0EN
2
P3.2/T0INEN
1
P3.1/RX0EN
0
P3.0/TX0EN
When using the Compare and
Capture unit you must set this
bit to 0.
0: General purpose input or
Timer 0 Input
1: General purpose output
When using Timer 0 you must
set this bit to 0.
0: General purpose input or
UART0 Rx
1: General purpose output
When using UART0 you must
set this bit to 0.
0: General purpose input
1: General purpose output or
UART0 Tx
I/O usage example
The following example demonstrates the configuration of the VMX51C1016 I/Os.
//--------------------------------------------------------------------------//This example continuously reads the P0 and writes its contents into //P1 and it
toggle P2 and P3.
//--------------------------------------------------------------------------#pragma TINY
#pragma UNSIGNEDCHAR
#include <VMIXReg.h>
at 0x0000 void main (void)
{
DIGPWREN = 0x80;
P0PINCFG = 0x00;
P1PINCFG = 0x0F;
P2PINCFG = 0xFF;
P3PINCFG = 0xFF;
while(1)
{
P1 = P0;
P2 = ~P2;
P3 = ~P3;
}
}//end of main() function
// Enable Timer 2 to activate P1
//Output
// Configure all P0 as Input
//Configure P1 as Output
//Configure P2 as Output
//Configure P3 as Output
//Write P0 into P1
//Toggle P2 & P3
When using UART0 you must
set this bit to 1.
Using General Purpose I/O Ports
The VMX51C1016’s 24 I/Os are grouped into
four ports. For each port an SFR register
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VMX51C1016
Using Port 1.0-3 as General Purpose
Output
Port 1.0-P1.3 can be used as standard digital
output. In order to do this, the Timer 2 clock
must be enabled by setting the T2CLKEN bit of
the DIGPWREN register. In addition, the Timer 2
CCEN register must also have the reset value.
Interrupt on Port 1 Change Feature
The VMX51C1016 includes ann interrupt on Port
1 change feature. This can be used to monitor
the activity on each I/O Port 1 pin (individually),
and trigger an interrupt when the state of the pin
on which this feature has been activated
changes. This is equivalent to having eight
individual external interrupt inputs. The interrupt
on Port 1 change shares the interrupt vector of
the ADC peripheral at address 006Bh.
See the interrupt section for more details on how
to use this feature.
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VMX51C1016
MULT/ACCU Control Registers
MULT/ACCU - Multiply
Accumulator Unit
With the exception of the barrel shifter, the
MULT/ACCU unit operation is controlled by two
SFR registers:
MULT/ACCU Features
The VMX51C1016 includes a hardware based
multiply-accumulator unit, which allows the user
to perform fast and complex arithmetic
operations.
MULT/ACCU unit features:
o Hardware calculation engine
o Calculation result is ready as soon as
the input registers are loaded
o Signed mathematical calculations
o Unsigned MATH operations are possible
if the MUL engine operands are limited
to 15 bits in size
o Auto/Manual reload of MAC_RES
o Enhanced VMX51C1016 MULT/ACCU
unit
o Easy implementation of complex MATH
operations
o 16-bit and 32-bit overflow flag
o 32-bit overflow can trigger an interrupt
o MULT/ACCU operand registers can be
cleared individually or all together
o Overflow flags can be configured to stay
active until manually cleared
o Can store and use results from previous
operations
o MULT/ACCU can be configured to
perform the following operations:
FIGURE 13: VMX51C1016 MULT/ACCU OPERATION
ADD32 + ADD32
MACCTRL1
MACTRLC2
The following two tables describe these control
registers:
TABLE 20: (MACCTRL1) MULT/ACCU U NIT C ONTROL REGISTER - SFR EBH
7
LOADPREV
6
PREVMODE
3
2
ADDSRC [1:0]
Bit
7
6
Mnemonic
LOADPREV
PREVMODE
5
OVMODE
4
OVRDVAL
3:2
ADDSRC[1:0]
1:0
MULCMD[1:0]
(MACA, MACB) + MACC = MAC_RESULT
(MACA x MACB) + MACC = MAC_RESULT
(MACA x MACB) + 0
= MAC_RESULT
(MACA x MACB) + MAC_PREV
= MAC_RESULT
MULT16 + ADD32
o
o
(MACA x MACA) + MACC = MAC_RESULT
(MACA x MACA) + 0
= MAC_RESULT
(MACA x MACA) + MAC_PREV
= MAC_RESULT
(MACA x MAC_PREV(16lsb) + MACC
(MACA x MAC_PREV(16lsb) + 0
= MAC_RESULT
= MAC_RESULT
(MACA x MAC_PREV(16lsb) + MAC_PREV
= MAC_RESULT
Where MACA (multiplier), MACB (multiplicand),
MACACC (accumulator) and MACRESULT
(result) are 16, 16, 32 and 32 bits, respectively.
5
OVMODE
4
OVRDVAL
1
0
MULCMD [1:0]
Function
MACPREV manual Load control
1 = Manual load of the
MACPREV register content if
PREVMODE = 1
Loading method of MACPREV
register
0 = Automatic load when
MACA0 is written.
1 = Manual Load when 1 is
written into LOADPREV
0 = Once set by math operation,
the OV16 and OV32 flag will
remain set until the overflow
condition is removed.
1= Once set by math operation,
the OV16 and OV32 flag will
stay set until it is cleared
manually.
0 = The value on MACRES is
the calculation result.
1 = the value on MACRES is the
32LSB of the MACRES when
the OV32 overflow occurred
32-bit Addition source
B Input
00 = 0 (No Add)
01 = C (std 32-bit reg)
10 = RES –1
11 = C (std 32-bit reg)
A Input
00=Multiplication
01=Multiplication
10=Multiplication
11= Concatenation of {A, B} for
32-bit addition
Multiplication Command
00 = MACA x MACB
01 = MACA x MACA
10 = MACA x MACPREV (16 LSB)
11 = MACA x MACB
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VMX51C1016
TABLE 21: (MACCTRL2) MULT/ACCU U NIT C ONTROL REGISTER 2 -SFR F1H
7
6
MACCLR2 [2:0]
3
Bit
7:5
2
Mnemonic
MACCLR[2:0]
4
MACOV32IE
3
2
1
MACOV16
0
MACOV32
5
1
MACOV16
4
MACOV32IE
0
MACOV32
Function
MULT/ACCU Register Clear
000 = No Clear
001 = Clear MACA
010 = Clear MACB
011 = Clear MACC
100 = Clear MACPREV
101 = Clear All MAC regs +
Overflow Flags
110 = Clear Overflow Flags only
MULT/ACCU 32-bit Overflow
IRQ Enable
16-bit Overflow Flag
0 = No 16 overflow
1 = 16-bit MULT/ACCU
Overflow occurred
32-bit Overflow Flag
1 = 32-bit MULT/ACCU
Overflow
This automatically loads the
MAC32OV register.
The MACOV32 can generate a
MULT/ACCU interrupt when
enabled.
TABLE 22: (MACA0) MULT/ACCU UNIT A OPERAND, LOW BYTE - SFR F2H
7
Bit
7:0
6
5
4
Mnemonic
MACA0
3
MACA0 [7:0]
2
1
0
Function
Lower segment of the MACA
operand
TABLE 23: (MACA1) MULT/ACCU UNIT A OPERAND, HIGH BYTE - SFR F3 H
7
Bit
15:8
6
5
Mnemonic
MACA1
4
3
MACA1 [15:8]
2
1
0
Function
Upper segment of the MACA
operand
TABLE 24: (MACB0) MULT/ACCU UNIT B OPERAND, LOW BYTE - SFR F9H
7
Bit
7:0
6
5
Mnemonic
MACB0
4
3
MACB0 [7:0]
2
1
0
Function
Lower segment of the MACB
operand
TABLE 25: (MACB1) MULT/ACCU UNIT B OPERAND, HIGH BYTE - SFR FA H
7
Bit
6
5
Mnemonic
7:0
MACB1
4
3
MACB1 [7:0]
2
1
0
Function
Upper segment of the MACB
operand
MACC Input Register
The MACC register is a 32-bit register used to
perform 32-bit addition.
MULT/ACCU Unit Data Registers
The MULT/ACCU data registers include operand
and result registers that serve to store the
numbers being manipulated in mathematical
operations. Some of these registers are uniquely
for addition (such as MACC), while others can
be used for all operations. The MULT/ACCU
operation registers are represented below.
MACA and MACB Multiplication
(Addition) Input Registers
The MACA and MACB register serves as 16-bit
input operands when performing multiplication.
When the MULT/ACCU is configured to perform
32-bit addition, the MACA and the MACB
registers are concatenated to represent a 32-bit
word. In such cases, the MACA register contains
the upper 16-bit of the 32-bit operand and the
MACB contains the lower 16 bits.
It is possible to substitute the MACPREV
register for the MACC register or 0 in the 32-bit
addition.
TABLE 26: (MACC0) MULT/ACCU U NIT C OPERAND, LOW BYTE - SFR ECH
7
Bit
6
5
Mnemonic
7:0
MACC0
4
3
MACC0 [7:0]
2
1
0
Function
Lower segment of the 32-bit addition
register
TABLE 27: (MACC1) MULT/ACCU U NIT C OPERAND, BYTE 1 - SFR EDH
7
Bit
6
5
Mnemonic
15:8
MACC1
4
3
MACC1 [15:8]
2
1
0
Function
Lower middle segment of the 32-bit
addition register
TABLE 28: (MACC2) MULT/ACCU U NIT C OPERAND, BYTE 2 - SFR EEH
7
Bit
23:16
6
5
Mnemonic
MACC2
4
3
MACC2 [23:16]
2
1
0
Function
Upper middle segment of the 32-bit
addition register
_________________________________________________________________________________________________
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VMX51C1016
TABLE 29: (MACC3) MULT/ACCU U NIT C OPERAND, HIGH BYTE - SFR EFH
7
Bit
6
5
Mnemonic
31:24
MACC3
4
3
MACC3 [31:24]
2
1
0
Function
Upper segment of the 32-bit addition
register
As previously mentioned, there are two ways to
load the MACPREV register controlled by the
PREVMODE bit value:
MACRES Result Register
PREVMODE = 0:
Auto MACPREV load, by writing into the MACA0
register. Selected when PREVMODE = 0.
The MACRES register, which is 32 bits wide,
contains the result of the MULT/ACCU
operation. In fact, the MACRES register is the
output of the barrel shifter.
PREVMODE = 1:
Manual load of MACPREV
LOADPREV bit is set to 1.
TABLE 30: (MACRES0) MULT/ACCU UNIT RESULT, LOW BYTE - SFR F4H
7
Bit
7:0
6
5
Mnemonic
MACRES0
4
3
MACRES0 [7:0]
2
1
0
Function
Lower segment of the 32-bit
MULT/ACCU result register
when
the
A good example demonstrating the auto loading
of the MACPREV feature is the implementation
of a FIR filter. In that specific case, it is possible
to save a total of 8 MOV operations per tap
calculation.
TABLE 31: (MACRES1) MULT/ACCU UNIT RESULT, BYTE 1 - SFR F5H
7
6
5
4
3
MACRES1 [15:8]
2
1
0
TABLE 34: (MACPREV0) MULT/ACCU UNIT PREVIOUS OPERATION RESULT, LOW
BYTE - SFR FCH
7
Bit
15:8
Mnemonic
MACRES1
Function
Lower middle segment of the 32-bit
MULT/ACCU result register
Bit
7:0
6
5
Mnemonic
MACPREV0
TABLE 32: (MACRES2) MULT/ACCU UNIT RESULT, BYTE 2 - SFR F6H
7
Bit
23:16
6
5
Mnemonic
MACRES2
4
3
MACRES2 [23:16]
2
1
0
Bit
31:24
6
5
Function
Upper middle segment of the 32-bit
MULT/ACCU result register
Mnemonic
MACRES3
4
3
MACRES3 [31:24]
2
1
0
Function
Lower segment of 32-bit
MULT/ACCU previous result register
TABLE 35: (MACPREV1) MULT/ACCU UNIT PREVIOUS OPERATION RESULT, BYTE
1 - SFR FDH
2
1
7
Bit
15:8
TABLE 33: (MACRES3) MULT/ACCU UNIT RESULT, HIGH BYTE - SFR F7 H
7
4
3
MACPREV0 [7:0]
6
5
Mnemonic
MACPREV1
0
Function
Upper segment of the 32-bit
MULT/ACCU result register
MACPREV Register
The MACPREV register provides the ability to
automatically or manually save the contents of
the MACRES register and re-inject it into the
calculation. This feature is especially useful in
applications where the result of a given
operation serves as one of the operands of the
next one.
4
3
MACPREV1 [7:0]
2
1
0
Function
Lower middle segment of 32-bit
MULT/ACCU previous result register
TABLE 36: (MACPREV2) MULT/ACCU UNIT PREVIOUS OPERATION RESULT, BYTE
2 - SFR FEH
7
Bit
23:16
6
5
Mnemonic
MACPREV2
4
3
MACPREV2 [15:8]
2
1
0
Function
Upper middle segment of 32-bit
MULT/ACCU previous result register
TABLE 37: (MACPREV3) MULT/ACCU UNIT PREVIOUS OPERATION RESULT, HIGH
BYTE - SFR FFH
7
Bit
31:24
6
5
Mnemonic
MACPREV3
4
3
MACPREV3 [7:0]
2
1
0
Function
Upper segment of 32-bit
MULT/ACCU previous result register
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VMX51C1016
FIGURE 14: VMX51C1016 MULT/ACCU FUNCTIONAL DIAGRAM
addsrc
SFR registers
Concatenation (A,B)
ov32
B
ov16a
MACA1 (MSB)
A
MACA
MACA0 (LSB)
SFR registers
shiftmode
ADD
MSB
ov16b
MUL
(Signed)
MACB
SHIFT
MACRES
MACRES
(SFR regs)
B
MACRES2
ADD
LSB
MACB1 (MSB)
A
ovrdval
MACRES1
mulcmd
MACC
MACB0 (LSB)
MACRES3 (MSB)
prevmode
0
MACRES0 (LSB)
Maca0 load
loadprev
MACC3 (MSB)
addsrc
MAC32OV3 (MSB)
(16 LSB)
MACPREV
MAC32OV
(stored)
MACC2
load
MACC1
1
MAC32OV1
rst
ov32F
ov32
MACC0 (LSB)
rst
OVCLR
ov32F / IRQ
ov32
1
MAC32OV2
1
ovmode
MAC32OV0 (LSB)
ovmode
rst
Ov16a+b
MAC Control SFR
ov16F
Ov16a+b
MACCTRL
MACCTRL2
MACSHIFTCTRL
The block diagram above shows the interaction
between the registers and the other components
that comprise the MULT/ACCU unit on the
VMX51C1016.
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VMX51C1016
MULT/ACCU Barrel Shifter
// MULT/ACCU example use
The MULT/ACCU includes a 32-bit barrel shifter
at the output of the 32-bit addition unit. The
barrel shifter can perform right/left shift
operations in one cycle, which is useful for
scaling the output result of the MULT/ACCU.
MACA0 = 0xFF;
MACA1 = 0x7F;
MACB0 = 0xFF;
MACB1 = 0xFF;
MACC0 = 0xFF;
MACC1 = 0xFF;
MACC2 = 0xFF;
MACC3 = 0x7F;
The shifting range is adjustable from 0 to 16 in
both directions. The “shifted” addition unit output
can be routed to:
o
o
o
MACRES
MACPREV
MACOV32
TABLE 38: (MACSHIFTCTRL) MULT/ACCU UNIT BARREL SHIFTER CONTROL
REGISTER - SFR FBH
6
ALSHSTYLE
Bit
7
Mnemonic
SHIFTMODE
6
ALSHSTYLE
5:0
SHIFTAMPL[5:0]
5
4
3
2
1
SHIFTAMPL [5:0]
0
Function
0 = Logical SHIFT
1 = Arithmetic SHIFT
Arithmetic Shift Left Style
0= Arithmetic Left Shift: Logical Left
1= Arithmetic Left Shift: Keep sign bit
Shift Amplitude 0 to 16 (5 bits to
provide 16 bits shift range)
Neg. Number = Shift Right
(2 complements)
Pos. Number = Shift Left
MULT/ACCU Unit Setup and OV32
Interrupt Example
In order to use the MULT/ACCU unit, the user
must first set up and configure the module. The
following provides setup code examples. The
first part of the code is the interrupt setup and
module configuration, while the second part is
the interrupt function itself.
Sample C code for MULT/ACCU unit interrupt
setup and module configuration:
//--------------------------------------------------------------------------// Sample C code to setup the MULT/ACCU unit
//--------------------------------------------------------------------------//--- Program initialisation omitted…
(…)
void main(void){
// MULT/ACCU setup
IEN0 |= 0x80;
IEN1 |= 0x10;
DIGPWREN |= 0x20;
MACCTRL1 = 0x0C;
MACCTRL2 = 0x10;
//--------------------------------------------------------------------------------// MAC 32 bit overflow Interrupt Function
void int_5_mac (void) interrupt 12
{
IEN0 &= 0x7F;
The barrel shifter can perform both arithmetic
and logical shifts: The shift left operation can be
configured as an arithmetic or logical shift. In the
latter, the sign bit is discarded.
7
SHIFTMODE
//--- as soon as the MAC input registers are loaded the result is available in the
MACRESx registers.
}//end of main
// Disable all interrupts
//Put MAC 32 bit Overflow Interrupt code here.*/
//Note that when a 32bit overflow occurs, the 32 least significant bit of the current
//result are stored into the MAC32OVx registers and can be read at the location
of MACRESx by setting to 1 the OVRDVAL bit of the MACCTRL register
IRCON &= 0xEF;
// Clear flag (IEX5)
IEN0 |= 0x80;
// Enable all interrupts
}
//--------------------------------------------------------------------------------
MULT/ACCU Application Example:
FIR Filter Function
The following ASM code shows the
implementation of an FIR filter computation
function for one iteration, followed by the data
shifting operation and the definition of the FIR
filter coefficient table. The FIR computation is
simple to implement, however, it is quite
demanding in terms of processing power. For
each new data point, the multiplication with
associated coefficients plus addition operation
must be performed N times (N=number of filter
tapps).
Since it is hardware based and provides an
automatic reload of the result of the previous
operation
feature,
the
VMX51C1016
MULT/ACCU unit is very efficient in performing
operations such as FIR filter computation.
In the code example below, the COMPUTEFIR
loop forms the “heart” of the FIR computation. It
is clear that use of the MULT/ACCU unit implies
very few instructions to perform mathematical
operations.
The net result is a dramatic
performance improvement when compared with
manual calculations done solely via the standard
8051 instruction set.
// Enable all interrupts
// Enable MULT/ACCU interrupt
// Enable MULT/ACCU unit
// {A,B}+C
// Enable INT overflow_32
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VMX51C1016
VMX51C1016 FIR Filter Example
The example below shows how to use the
VMX51C1016’s MULT/ACCU unit to perform
FIR filter computing. To minimize the example
size, only the FIR computing function and the
coefficient table are presented.
;----------------------------------------------------//
;** FIR Filter Computing Function
//
;---------------------------------------------------//
FIRCOMPUTE: MOV R0,#NPOINTSBASEADRS
;INPUT ADC RAW DATA
;AT Xn LOCATIONS...
;Saving acquired data from calling function into RAM for computation
MOV
MOV
MOV
INC
MOV
VARH,DATAH
VARL,DATAL
@R0,VARH
R0
@R0,VARFL
;(MSB)
;(LSB)
;** Prepare to compute Yn...
;***Define Base ADRS of input values
MOV
R0,#NPOINTSBASEADRS
;***Define Base Address of coefficients
MOV
R1,#COEFBASEADRS
MOV
R7,#NPOINTS
;DEFINE COUNTER
;***Configure the MULT/ACCU unit as Follow:
MOV
MACCTRL,#00001000B
;BIT7 LOADPREV = 0
;BIT6 PREVMODE = 0
;
;BIT5 OVMODE = 0
;
;BIT4 OVRDVAL = 0
;
;BIT3:2 ADDSRC = 10
;BIT1:0 MULCMD = 00
No manual Previous result
Automatic Previous result save when
MULT/ACCUA0 is loaded
Overflow flag remains ON until overflow
condition exist
The value of MACRES is the calculation
result
MACPREV is the Addition Source
Mul Operation = MACAxMACB
;**Clear the MULT/ACCU registers content
MOV
MACCTRL2,#0A0H
;** COMPUTE Yn...
;*** Second part
;-------------------------------------------------------------------------------------------------------//
;** SHIFT PREVIOUS INPUT VALUES TO LET PLACE FOR NEXT ONE...
;-------------------------------------------------------------------------------------------------------//
SHIFTPAST:
MOV
R7,#(NPOINTS -1)*2
;Define # of datashift
;To perform (N-1)*2
;***COMPUTE FIRST FETCH ADDRESS
MOV
R0,#(NPOINTSBASEADRS - 1 + 2*(NPOINTS-1))
;***COMPUTE FIRST DESTINATION ADDRESS
MOV
R1,#(NPOINTSBASEADRS + 1 + 2*(NPOINTS-1))
SHIFTLOOP: MOV
A,@R0
;Shift Given LSB input...
MOV
@R1,A
;To next location
DEC
R0
;Prepare pointer for moving LSB
DEC
R1
DJNZ
R7,SHIFTLOOP
;** PERFORM TRANSFORMATION OF Yn HERE AND PUT INTO BINH, BINL
;** IN THIS CASE THE COEFFICIENTS HAVE BEEN MULTIPLIED BY 65536
;** SO THE RESULT IS ON 32-BITS
;** DIVISING YN BY 65536 MEAN ONLY TAKING THE UPPER 16-BITS
MOV
MOV
DATAH,MACRES3
DATAL,MACRES2
LCALL
MOV
RET
SENDLTC1452
P3,#00
;---------------------------------------------------;* FIR Filter Coefficients Table
*
;---------------------------------------------------;FSAMPLE 480HZ, N=16, LOW PASS 0.1HZ -78DB @ 60HZ
COEFTABLE:
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
023DH
049DH
086AH
0D2DH
1263H
1752H
1B30H
1D51H
1D51H
1B30H
1752H
1263H
0D2DH
086AH
049DH
023DH
0FFFFH
;END OF TABLE
COMPUTEFIR: MOVMACB1,@R1
INC
MOV
INC
;Put a given Coefficient into
;MULT/ACCUB
R1
MACB0,@R1
R1
MOV
MACA1,@R0 ; Put a given Xn Input into
INC
R0
MOV
MACA0,@R0
;This last instruction load the MACPREV register for next Operation
INC
R0
DJNZ
R7,COMPUTEFIR ;Do the Computation for N taps
_________________________________________________________________________________________________
page 22 of 76
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VMX51C1016
VMX51C1016 Timers
The VMX51C1016 includes three generalpurpose timer/counters
o
o
o
Timer 0
Timer 1
Timer 2
TABLE 39: (TL0) TIMER 0 LOW BYTE - SFR 8AH
7
6
5
4
3
TL0 [7:0]
2
1
0
2
1
0
2
1
0
2
1
0
TABLE 40: (TH0) TIMER 0 HIGH BYTE - SFR 8CH
7
6
5
4
3
TH0 [7:0]
TABLE 41: (TL1) TIMER 1 LOW BYTE - SFR 8BH
7
6
5
4
3
TL1 [7:0]
TABLE 42: (TH1) TIMER 1 HIGH BYTE - SFR 8DH
7
6
5
4
3
TH1 [7:0]
Timer 0 and Timer 1 are general purpose timers
that can operate as either a timer with a clock
rate based on the system clock, or an event
counter that monitors events occurring on an
external timer input pin (T0IN for Timer 0 and
T1IN for Timer 1).
With the exception of their associated interrupts,
the configuration and control of timers 0 and 1
are performed via the TMOD and TCON SFR
registers.
Timers 0 and 1 are similar to standard 8051
timers. In addition to operating as a timer based
on a system clock or as an event counter, Timer
2 is also the heart of the PWM counter outputs
and the compare and capture units.
The following table shows the TCON special
function register of the VMX51C1016. This
register contains the Timer 0/1 overflow flags,
Timer 0/1 run control bits, INT0 edge flags and
INT0 interrupt type control bits.
Each of the VMX51C1016’s timers has a
dedicated interrupt vector, which can be
triggered when the timers overflow.
TABLE 43: (TCON) TIMER 0, TIMER 1 TIMER/COUNTER CONTROL - SFR 88H
Timer 0 and Timer 1
Timer 0 and Timer 1 are similar in their structure
and operation. The main differences between
them is that the Timer 1 serves as a baud rate
generator for UART0 and shares some of its
resources when Timer 0 is used in Mode 3.
Timer 0 and Timer 1 each consist of a 16-bit
register, for which content is accessible as two
independent SFR registers: TLx and THx.
7
6
5
4
TF1
TR1
TF0
TR0
3
2
1
0
-
-
IE0
IT0
Bit
7
Mnemonic
TF1
6
TR1
5
TF0
4
TR0
3
2
1
IE0
0
IT0
Function
Timer 1 overflow flag.
Set by hardware when Timer 1 overflows.
It is automatically cleared when the
Timer 1 interrupt is serviced.
This flag can also be cleared by software.
Timer 1 Run control bit.
TR1 = 0, Stop Timer 1
TR1 = 1, Start Timer 1
Timer 0 overflow flag.
Set by hardware when Timer 0 overflows.
It is automatically cleared when the
Timer 0 interrupt is serviced.
This flag can also be cleared by software.
Timer 0 Run control bit.
TR0 = 0, Stop Timer 0
TR0 = 1, Start Timer 0
Reserved
Reserved
INT0 edge flag configuration
Set by hardware when falling edge on
external pin INT0 is observed.
It is cleared when interrupt is processed.
INT0 interrupt event type control bit.
IT0 = 0,
interrupt will be caused by
a Low Level on INT0
IT0 = 1,
Interrupt will be caused by a
High to Low transition on INT0.
_________________________________________________________________________________________________
page 23 of 76
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VMX51C1016
The TMOD register is used mainly to set the
timers’ operating mode and allows the user to
enable the external gate control as well as select
a timer or counter operation.
TABLE 44: (TMOD) TIMER MODE CONTROL - SFR 89H
Bit
7
7
6
5
4
-
CT1
M11
M01
3
2
1
0
GATE0
CT0
M10
M00
Mnemonic
Reserved
CT1
Function
Selects TIMER1 Operation.
CT1 = 0, Sets the Timer 1 as a Timer
which value is incremented
by SYSCLK events.
CT1 = 1,
5
4
3
M11
M01
GATE0
The Timer 1 operates as a
counter which counts the
High to Low transition on
that occurs on the T1IN
input.
Selects mode for Timer/Counter 1, as
shown in the Table below.
GATE0 = 0,
The level present on the INT0 pin has
no affect on Timer1 operation.
GATE0 = 1,
The level of INT0 pin serves as a Gate
control on to Timer/Counter operation
provided the TR1 bit is set. Applying a
Low Level on the INT0 pin makes the
Timer stop.
2
CT0
Selects Timer 0 Operation.
CT1 = 0, Sets the Timer 0 as a Timer
which value is incremented
by SYSCLK events.
CT1 = 1,
1
0
M10
M00
The Timer 0 operates as a
counter which counts the
High to Low transition on
that occurs on the T1IN
input.
Selects mode for Timer/Counter 0, as
shown in the Table below.
Timer 0, Timer 1 Gate Control
Gate control makes it possible for an external
device to control the Timer 0 operation through
the interrupt (INT0) pins.
When the GATE0 and TR0 bits of the TMOD
register are set to 1:
o
o
INT0 = Logic low, Timer 0 stops
INT0 = Logic high, Timer 0 runs
When the gate bit equals 0, the logic level
presented at the INT0 pin has no affect on the
Timer 0 operation.
Gate control is not possible on Timer 1 because
the INT1 is not pinned out and an internal pullup resistor keeps its level high.
FIGURE 15: T IMER 0, T IMER 1 CTX & GATE CONTROL
SYSCLK
÷12
0
CT0=0
CLK
1
CT0=1
0
CT1=0
T0IN
TR0
GATE0
INT0
SYSCLK
÷12
Timer 0/Timer 1/Counter Operation
CLK
1
The CT0 and CT1 bits of the TMOD register
control the clock source for Timer 0 and Timer 1,
respectively. When the CT bit is set to 0 (timer
mode), the timer is sourced from the system
clock divided by 12.
CT1=1
T1IN
TR1
Setting the CTx bit to 1 configures the timer to
operate in event counter mode. In this mode,
high to low transitions on the TxIN pin of the
VMX51C1016 increment the timer value.
Note that when Timer 0 and Timer 1 operate in
timer mode, they use the system clock as their
source. Therefore, configuring the CLKDIVCTRL
register will affect the timers’ operation.
_________________________________________________________________________________________________
page 24 of 76
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VMX51C1016
Timer 0, Timer 1 Operation Modes
The operating mode of Timer 0 and Timer 1 is
determined by the value of the M1x and M0x bits
in the TMOD register. The table below
summarizes the four modes of operation for
timers 0 and 1.
Timers 0, Timer 1: Mode 0 - Overflow Rate (Hz)
CTx = 0
Timer overflow rate (Hz) =
CTx = 1
Timer overflow rate (Hz) =
TABLE 45: TIMER/COUNTER MODE DESCRIPTION S UMMARY
M1
0
0
1
1
M0
0
1
0
1
Mode
Mode 0
Mode 1
Mode 2
Mode 3
Function
13-bit Timer / Counter, with 5
lower bits in TL0 or TL1 register
and bits in TH0 or TH1 register
(for timer 0 and timer 1,
respectively). The 3 high order
bits of TL0 and TL1 are held at
0.
16-bit Timer / Counter
8-bit auto reload Timer /
Counter. The reload value is
kept in TH0 or TH1, while TL0
or TL1 is incremented every
machine cycle. When TLx
overflows, a value from THx is
copied to TLx.
If Timer 1 M1 and M0 bits are
set to 1, Timer 1 stops. If Timer
0 M1 and M0 bits are set to 1,
Timer
0
acts
as
two
independent 8-bit Timers /
Counters.
fSYSCLK_________
12 x [8192-(THx, TLx)]
fTxIN_________
[8192-(THx,TLx)]
Mode 1 (16-bit)
The Mode 1 operation is the same for Timer 0
and Timer 1. In Mode 1, the timer is configured
as a 16-bit counter. Besides rollover at FFFFh,
Mode 1 operation is the same as Mode 0.
FIGURE 16 : T IMER 0 MODE 0 & MODE 1
SYSCLK
÷12
0
TH0
CT0=0
CLK
1
0
4
7
Mode = 0
CT0=1
P3.2-T0IN
Mode = 1
TR0
GATE0
TL0
0
7
INT0
Mode 0, 13-bit Timer/Counter
TF0
Mode 0 operation is the same for Timer 0 and
Timer 1.
In Mode 0, the timer is configured as a 13-bit
counter that uses bits 0-4 of the TLx register and
all 8 bits of the THx register. The timer run bit
(TRx) of the TCON SFR starts the timer. The
value of the CTx bit defines if the timer will
operate as a timer (CTx = 0), deriving its source
from the system clock, or if the timer will count
the high to low transitions (CTx = 1) that occur
on the external timer input pin (TxIN). When the
13-bit count increments from 1FFFh (all ones) to
all zeros, the TF0 (or TF1) bit will be set in the
TCON SFR.
The state of the upper 3 bits of the TLx register
is indeterminate in Mode 0 and must be masked
when the software evaluates the register’s
contents.
INT
FIGURE 17: T IMER 1 MODE 0 & MODE 1
SYSCLK
÷12
0
TH1
CT1=0
CLK
1
CT1=1
0
4
7
Mode = 0
P3.5-T1IN
Mode = 1
TR1
TL1
0
TF1
7
INT
To UART0
The Timer 0 and Timer 1 overflow rate in Mode
1 can be calculated using the following
equations:
Timers 0, Timer 1: Mode 1 - Overflow Rate (Hz)
CTx = 0
Timer overflow rate (Hz) =
fSYSCLK_________
12 x [65536-(THx, TLx)]
CTx = 1
Timer overflow rate (Hz) =
fTxIN_________
[65536-(THx, TLx)]
_________________________________________________________________________________________________
page 25 of 76
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VMX51C1016
Mode 2 (8-bit)
Using the Timer 1 as Baud Rate generator
The operation of Mode 2 is the same for Timer 0
and Timer 1. In Mode 2, the timer is configured
as an 8-bit counter, with automatic reload of the
start value. The LSB of the timer register, TLx, is
the counter itself and the MSB portion of the
timer (THx) stores the timer reload value.
Using Timer 1 in Mode 2 is recommended as the
best approach when using Timer 1 as the
UART0 baud rate generator.
The Mode 2 counter control is the same as for
Mode 0 and Mode 1. However, in Mode 2, when
TLx rolls over from FFh, the value stored in THx
is reloaded into TLx.
Mode 3 (2 x 8-bit)
In Mode 3, Timer 0 operates as two 8-bit
counters and Timer 1 stops counting and holds
its value.
FIGURE 20: T IMER0, T IMER 1 STRUCTURE IN MODE 3 USING
CLK
0
TH0
7
FIGURE 18 : T IMER 0 MODE 2
SYSCLK
TR1
÷12
0
CT0 = 0
1
CT0 = 1
TF1
TL0
0
SYSCLK
÷12
P3.2 - T0IN
0
CT0 = 0
1
CT0 = 1
CLK
0
INT
To UART0
7
0
TL0
7
P3.2-T0IN
7
TH0
TR0
TR0
TF0
GATE0
GATE0
TF0
INT
INT
INT0
INT0
The Timer 0 overflow rate in Mode 3 can be
calculated using the following equations:
FIGURE 19: T IMER 1 MODE 2
SYSCLK
Timers 0, Timer 1: Mode 3 - Overflow Rate (Hz)
TH0, CTx = 0 or 1
÷12
0
CT1 = 0
1
CT1 = 1
TL1
0
Timer overflow rate (Hz) =
7
fSYSCLK_____
12 x 256
P3.5 - T1IN
TL0, CTx = 0
0
7
TH1
Timer overflow rate (Hz) =
TR1
TF1
fSYSCLK_____
12 x 256
INT
TL0, CTx = 1
To UART0
Timer overflow rate (Hz) =
The Timer 0 and Timer 1 overflow rate in Mode
2 can be calculated using the following
equations:
Timers 0, Timer 1: Mode 2 - Overflow Rate (Hz)
CTx = 0
Timer overflow rate (Hz) =
__ fTxIN_____
256
In Mode 3, the values present in the TH1 and
TL1 registers and CT1 control bits have no
impact on the timer operation.
fSYSCLK_________
12 x [256-(THx)]
CTx = 1
Timer overflow rate (Hz) =
__ f TxIN________
[256--(THx)]
_________________________________________________________________________________________________
page 26 of 76
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VMX51C1016
/*------------------------*/
/*Put Interrupt code here*/
/*------------------------*/
Timer 0 and Timer 1 Interrupts
Timer 0 and Timer 1 each have dedicated
interrupt vectors located at:
o
o
000Bh for the Timer 0
001Bh for the Timer 1
The natural priority of Timer 0 is higher than that
of Timer 1.
The following table summarizes the interrupt
control and flag bits associated with the Timer 0
and Timer 1 interrupts.
Bit Name
Location
Description
EA
IEN0.7
T0IE
IEN0.1
General interrupt control bit
0, Interrupt Disabled
1, Enabled Interrupt active
Timer 0 Overflow Interrupt
1 = Enable
0 = Disable
Timer 1 Overflow Interrupt
1 = Enable
0 = Disable
TF0 Flag is set when Timer 0
Overflow occurs.
Automatically cleared when
Timer 0 interrupt is serviced.
This flag can also be cleared
by software
TF1 Flag is set when Timer 1
Overflow occurs.
Automatically cleared when
Timer 1 interrupt is serviced.
This flag can also be cleared
by software
T1IE
IEN0.3
TF0
TCON.5
TF1
TCON.7
IEN0 |= 0x80;
// Enable all interrupts
}
//---------------------------------------------------------------------------
Setting Up Timer 1 Examples
The following code provides an example of how
to configure Timer 1 (the first part of the code is
the interrupt setup and module configuration,
while the second part is the interrupt function).
Example1: Delay function
//------------------------------------------------------------------------// Sample C code using the Timer 1: Delay function
//------------------------------------------------------------------------VOID DELAY 1MS( UNSIGNED CHAR DLAIS) {
IDATA UNSIGNED CHAR X=0;
TMOD = 0X10;
TL1 = 0X33;
TH1 = 0XFB;
;//TIMER1 RELOAD VALUE FOR
TCON = 0X40;
WHILE (DLAIS > 0)
{
DO{
X=TCON;
X= X&0X80;
}WHILE(X==0);
TCON = TCON&0X7F;
TL1 = 0X33;
TH1 = 0XFB;
;//TIMER1 RELOAD VALUE FOR
DLAIS = DLAIS-1;
}
}//END OF DELAY 1MS
Example2: Timer 1 interrupt example
//------------------------------------------------------------------------// Sample C code using the Timer 1: Interrupt
//------------------------------------------------------------------------// (…) PROGRAM INITIALIZATION OMITTED
at 0xo100 void main(void){
// TIMER 1 setup
Setting Up Timer 0 Example
To use Timer 0, first setup the interrupt and then
configure the module. This is described in the
following code example.
Sample C code to set up Timer 0:
//--------------------------------------------------------------------------// Sample C code to setup Timer 0
//--------------------------------------------------------------------------// (…) PROGRAM INITIALIZATION OMITTED
IEN0 |= 0x80;
IEN0 |= 0x08;
TMOD = 0x20;
TCON = 0x40;
TL1 = 0xFC;
// Enable all interrupts
// Enable interrupt Timer1
// Timer 1 mode 2
// Start Timer 1
// Timer1 offset
do {
}while(1);
}//end of main() function
//---------------------------------------// Timer 1 Interrupt function
//---------------------------------------void int_timer_1 (void) interrupt 3
{
IEN0 &= 0x7F;
//Wait Timer 1 interrupt
// Disable all interrupts
AT 0X0100 VOID MAIN( VOID){
/* Put Interrupt code here*/
// INTERRUPT + TIMER 0 SETUP
IEN0 |= 0X80;
IEN0 |= 0X02;
TMOD = 0X02;
TCON = 0X10;
DO{}WHILE(1);
// ENABLE ALL INTERRUPTS
// ENABLE INTERRUPT TIMER 0
// TIMER 0 MODE 2
// START TIMER 0
IEN0 |= 0x80;
}
// Enable all interrupts
//WAIT FOR TIMER 0 INTERRUPT
}//END OF MAIN()
//--------------------------------------------------------------------------// INTERRUPT FUNCTION
VOID INT_ TIMER_0 ( VOID) INTERRUPT 1
{
IEN0 &= 0X7F;
// DISABLE ALL INTERRUPTS
_________________________________________________________________________________________________
page 27 of 76
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VMX51C1016
The T2CON register controls:
Timer 2
The VMX51C1016 Timer 2 and its associated
peripherals include the following capabilities:
o
o
o
o
16-bit timer
16-bit auto-reload timer
Compare and capture units
8/16 PWM outputs
o
o
o
o
TABLE 50: (T2CON) TIMER 2 CONTROL REGISTER -SFR C8 H
TABLE 46: (TL2) TIMER 2, LOW BYTE - SFR CCH
7
6
5
4
3
TL2 [7:0]
2
1
0
TABLE 47: (TH2) TIMER 2, HIGH BYTE - SFR CDH
7
6
5
4
3
TH2 [7:0]
2
1
Timer 2 Registers
Timer 2 consists of a 16-bit register, whose
upper and lower bytes are accessible via two
independent SFR registers (TL2, TH2).
TABLE 48: (TL2) TIMER 2 LOW BYTE - SFR CCH
6
5
4
3
TL2 [7:0]
2
1
0
2
1
0
TABLE 49: (TH2) TIMER 2 HIGH BYTE - SFR CDH
7
6
5
4
3
TH2 [7:0]
7
T2PS
6
T2PSM
5
T2SIZE
4
T2RM1
3
T2RM0
2
T2CM
1
T2IN1
0
T2IN0
Bit
7
Mnemonic
T2PS
6
T2PSM
5
T2SIZE
4
3
T2RM1
T2RM0
2
T2CM
1
0
T2IN1
T2IN0
0
Figure 21 shows the Timer 2/compare and
capture unit block diagram. The following
paragraphs will describe how these blocks work.
7
T2 clock source prescaler
T2 count size (8/16-bits)
T2 reload mode
T2 input selection
Function
Prescaler select bit:
0 = Timer 2 is clocked with 1/12 of
the oscillatory frequency
1 = Timer 2 is clocked with 1/24 of
the oscillatory frequency
0 = Prescaler
1 = clock/2
Timer 2 Size
0 = 16-bit
1 = 8-bit
Timer 2 reload mode selection
0X = Reload disabled
10 = Mode 0
11 = Mode 1
Timer 2 compare mode selection
0 = Mode 0
1 = Mode 1
Timer 2 input selection
00 = Timer 2 stops
01 = Input frequency f/2, f/12 or f/24
10 = Timer 2 is incremented by
external signal at pin T2IN
11 = Internal clock is gated to the
T2IN input.
Timer 2 Control Register
Most of Timer 2’s control is accomplished via the
T2CON register located at SFR address C8h.
_________________________________________________________________________________________________
page 28 of 76
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VMX51C1016
FIGURE 21: T IMER 2 AND COMPARE/CAPTURE UNIT
CCH3
10
T2IN
COCAH3
COCAH3
Sync
Enable
Capture
Capture
Data
Latch
Comp
Capture COCAH3
16-bit
Comparator
11
Enable
Capture
Compare
Capture
CCL2
CCH1
COCAH1
Enable
1
Capture
Data
Latch
Comp
Capture COCAH1
÷12
00
0
T2PSM
Compare
COCAH0
Enable
Sync
Capture
Capture
16-bit
Comparator
T2SIZE
Timer 2
T2PS
T2EX
Data
Latch
16-bit
Comparator
T2INxx
01
÷2
0
Capture
Comp
Capture COCAH2
1
SYSCLK
COCAH2
COCAH2
÷2
CCL3
CCH2
Compare
TL2
TH2
Capture
Comp
Capture COCAH0
16-bit
Comparator
Data
Latch
COCAH0
COCAH1
Capture
Compare
Reload
Capture
CCL1
CRCH
Compare
COCAH0
Data
Latch
Reload
CRCL
INPUT/OUTPUT Control
T2EXIF
T2IF
T2EXIE
Interrupt Request
INTCOMP3
INTCOMP2
INTCOMP1
INTCOMP0
CCU0
CCU1
CCU2
P1.0-PWM0
P1.1-PWM1
P1.2-PWM2
P1.3-PWM3
Timer 2 Clock Sources
Timer 2 Operating Modes
As previously stated, Timer 2 can operate in
timer mode, in which case it derives its source
from the system clock (SYSCLK), or it can be
configured as an event counter where the high
to low transition on the T2IN input causes Timer
2 to increment.
When the T2IN1 bit is set to 0 and the T2IN0 bit
is set to 1, the Timer 2 register may or may not
derive its source from the internal pre-scaled
clock, depending on the T2PSM bit value.
Event Counter Mode
T2IN1
T2IN0
Selected Timer 2 input
0
0
Timer 2 Stop
When operating in event counter mode, the
timer is incremented as soon as the external
signal T2IN transitions from a 1 to a 0. A sample
of the T2IN input is taken at every machine
cycle. Timer 2 is incremented in the cycle
following the one in which the transition was
detected.
0
1
Standard Timer mode using internal
clock with or without prescaler
Gated Timer Mode
1
0
External T2IN pin clock Timer2
1
1
Internal Clock is gated by the T2IN input
When T2IN = 0, the Timer2 stop
The T2IN0 and T2IN1 bits of the T2CON register
serve to define the selected Timer 2 input and
the operating mode (see the following table):
T IMER 2 CLOCK SOURCE
When in timer mode, Timer 2 derives its source
from the system clock and the CLKDIVCTRL
register will affect Timer 2’s operation.
Timer 2 Stop
In the gated timer mode, the internal clock,
which serves as the Timer 2 clock source, is
gated by the external signal T2IN. In other
words, when T2IN is high, the internal clock is
allowed to pass through the AND gate. A low
value of T2IN will disable the clock pulse. This
allows an external device to control the Timer 2
operation or to use Timer 2 to monitor the
duration of an event.
When both the T2IN1 and T2IN0 bits are set to
0, Timer 2 is in STOP mode.
_________________________________________________________________________________________________
page 29 of 76
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VMX51C1016
Timer 2 Clock Prescaler
Timer 2 Mode 1
When Timer 2 is configured to derive its clock
source from the system clock, the clock
prescaling value can be controlled by software
using the t2psm and T2PS bits of the T2CON
register.
In Mode 1, a 16-bit reload from the CRCx
register on the falling edge of T2EX occurs. This
transition will set T2EXIF if T2EXIE is set. This
action will cause an interrupt (providing that the
Timer 2 interrupt is enabled) and the T2IF flag
value will not be affected.
The different system clock prescaling values are
shown in the table below:
T2PSM
T2PS
Timer 2 input clock
1
X
SYSCLK / 2
0
0
SYSCLK / 12
0
1
SYSCLK / 24
The value of T2SIZE does not affect reload in
Mode 1. Also, the reload operation is performed
independently of the state of the T2EXIE bit.
FIGURE 22: T IMER 2 RELOAD MODE
T2EX
Timer 2 Count Size
Reload Mode 1
Reload Mode 0
T2EXIE
TL2
Timer 2 can be configured to operate in 8-bit or
16-bit format. The T2SIZE bit of the T2CON
register selects the Timer 2 count size.
CRCL
Input
Clock
Data Bus
Data Bus
Data Latch
Reload
Data Latch
o
o
If T2SIZE = 0, Timer 2 size is 16 bits
If T2SIZE = 1, Timer 2 size is 8 bits
Data Bus
TH2
Data Bus
CRCH
EXF2
T2IF
Timer 2 Reload Modes
The Timer 2 reload mode is selected by the
T2RM1 and T2RM0 bits of the T2CON register.
The following figure shows the reload operation.
Timer 2 must be configured as a 16-bit
timer/counter for the reload modes to be
operational by clearing the T2SIZE bit.
Timer 2 Mode 0
When the timer overflows, the T2IF overflow flag
is set. Concurrently, this overflow causes Timer
2 to be reloaded with the 16-bit value contained
in the CRCx register, (which has been preset by
software). This reload operation will occur during
the same clock cycle in which T2IF was set.
Timer 2 interrupt
request
Timer 2 Overflows and Interrupts
Timer 2’s interrupt is enabled when the Timer 2
counter, the T2IF flag, is set and a Timer 2
interrupt occurs.
A Timer 2 interrupt may also be raised from
T2EX if the T2EXIE bit of the IEN1 register is
set.
The exact source of a Timer 2 interrupt can be
verified by checking the value of the T2IF and
T2EXIF bits of the IRCON register.
Timer 2’s interrupt vector is located at address
002Bh.
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VMX51C1016
Timer 2 Setup Example
To use Timer 2, the user must first set up and
configure the module (see the following code
example).
//--------------------------------------------------------------------------// Sample C code to setup Timer 2
//--------------------------------------------------------------------------// (…) PROGRAM INITIALIZATION OMITTED
at 0x100 void main(void){
// TIMER 2 & Interrupt setup
DIGPWREN = 0x80;
T2CON = 0x01;
TL2 = 0xE0;
TH2 = 0xFF;
// Enable Timer2,
// Set timer 2 to OSC/12
IEN0 |= 0x80;
IEN0 |= 0x20;
// Enable all interrupts
// Enable interrupt Timer 2
do{
}while(1);
//wait for Timer 2 interrupt
}//end of main()
//--------------------------------------------------------------------------// Timer 2 Interrupt Function
//--------------------------------------------------------------------------void int_timer_2 (void) interrupt 5
{
IEN0 &= 0x7F;
// Disable all interrupts
/*------------------------*/
/*Interrupt code here*/
/*------------------------*/
IEN0 |= 0x80;
}
For general timing/counting operations, the
VMX51C1016 Timer 2 includes four compare
and capture units that can be used to monitor
specific events and drive PWM outputs. Each
compare and capture unit provides three specific
operating modes that are controlled by the
CCEN register:
o
Mnemonic
COCAH0
Bit
Mnemonic
COCAL0
0
0
0
1
1
1
0
1
COCAH1
COCAL1
0
0
0
1
1
1
0
1
COCAH2
COCAL2
0
0
0
1
1
1
0
1
COCAH3
COCAL3
0
0
1
1
0
1
0
1
// Enable all interrupts
Timer 2 Special Modes
o
o
configuration bit is described in the following
table:
Compare modes enable
Capture on write into CRCL/CCLx
registers
Capture on transitions at CCU input pins
level
Function
Compare and Capture mode
for CRC register
Compare/capture disabled
Capture on a falling edge at
pin CCU0 (1 cycle)
Compare enabled (PWM0)
Capture on write operation
into register CRC1
Compare/capture mode for
CC register 1
Compare/capture disabled
Capture on a rising edge at
pin CCU1 (2 cycles)
Compare enabled (PWM1)
Capture on write operation
into register CCL1
Compare/capture mode for
CC register 2
Compare/Capture disabled
Capture on a rising edge at
pin CCU2 (2 cycles)
Compare enabled (PWM2)
Capture on write operation
into register CCL2
Compare/Capture mode for
CC register 3
Compare/capture disabled
N/A - CCU3 not pinned out
Compare enabled (PWM)
Capture on write operation
into register CCL3
This allows individual configuring and operation
of each compare and capture unit..
Compare/Capture, Reload Registers
Each compare and capture unit has a specific
16-bit register accessible via two SFR
addresses.
Note that the CRCHx/CRCLx registers
associated with Compare/Capture Unit 0 are the
only ones that can be used to perform a reload
of the Timer 2 operation.
TABLE 51: (CCEN) COMPARE/C APTURE E NABLE REGISTER -SFR C9H
7
COCAH3
6
COCAL3
5
COCAH2
4
COCAL2
3
COCAH1
2
COCAL1
1
COCAH0
0
COCAL0
The following tables describe the different
registers that may be captured or compared to
the value of Timer 2.
TABLE 52: (CRCL) COMPARE/RELOAD/CAPTURE REGISTER, LOW BYTE - SFR CAH
7
The CCEN register bits are grouped in pairs of
COCAHx/COCALx bits. Each pair corresponds
to one compare and capture unit. The compare
and capture unit operating mode versus the
6
5
4
3
CRCL [7:0]
2
1
0
TABLE 53: (CRCH) COMPARE/RELOAD /C APTURE REGISTER, HIGH BYTE - SFR CB H
7
6
5
4
3
CRCH [7:0]
2
1
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0
VMX51C1016
TABLE 54: (CCL1) COMPARE/C APTURE REGISTER 1, LOW BYTE - SFR C2H
7
6
5
4
3
CCL1 [7:0]
2
1
0
Capture Mode 0
TABLE 55: (CCH1) COMPARE/C APTURE REGISTER 1, HIGH BYTE - SFR C3 H
7
6
5
4
3
CCH1 [7:0]
The two capture modes are:
2
1
0
In Capture Mode 0, the transition on a given
CCU pin triggers the latching of Timer 2’s data
into the associated compare/capture register.
TABLE 56: (CCL2) COMPARE/C APTURE REGISTER 2, LOW BYTE - SFR C4H
7
6
5
4
3
CCL2 [7:0]
2
1
0
TABLE 57: (CCH2) COMPARE/C APTURE REGISTER 2, HIGH BYTE - SFR C5 H
7
6
5
4
3
CCH2 [7:0]
2
1
0
TABLE 58: (CCL3) COMPARE/C APTURE REGISTER 3, LOW BYTE - SFR C6H
7
6
5
4
3
CCL3 [7:0]
2
1
0
TABLE 59: (CCH3) COMPARE/C APTURE REGISTER 3, HIGH BYTE - SFR C7 H
7
6
5
4
3
CCH3 [7:0]
2
1
0
Capture Mode 1
In Capture Mode 1, a capture of the Timer 2
value will occur upon writing to the low byte of
the chosen capture register.
Note: On the VMX51C1016, the CCU2 and
CCU3 input is not pinned out.
FIGURE 23:T IMER 2 CAPTURE MODE 0 FOR CRCL AND CRCH BLOCK DIAGRAM
Write to CRCL, CCLx
CCUx Pin
Capture
Mode 0
TL2
Compare/Capture Data Line Width
The VMX51C1016 is capable of comparing and
capturing data using data lines up to 16 bits
wide. When comparing two registers or
capturing one register, the T2SIZE bit of the
T2CON register must be set to 1. This adjusts
the line width to 8 bits.
When comparing two pairs of registers, for
example, CCH1 and CCL1 to TH2 and TL2, the
T2SIZE bit must be set to 0. This adjusts the line
width to 16 bits.
Timer 2 Capture Modes
Timer 2 capture modes makes it possible to
acquire and store the 16-bit content of Timer 2
into a capture/compare registers following a
MOV SFR operation or the occurrence of an
external event on one of the CCU pins, as
described below:
Capture input
CCU0
CCU1
CCU2
Timer2 Capture triggering event
High to Low Transition on CCU0
Low to High Transition on CCU1
Low to High Transition on CCU2
Timer 2 capture is done without affecting the
Timer 2 operation.
Each individual compare and capture unit can
be configured for capture mode by configuring
the appropriate bit pair of the CCEN register.
Capture
Mode 1
Input
Clock
CRCL / CCLx
Data Bus
Data Bus
Data Latch
Reload
Data Latch
Data Bus
Data Bus
T2IF
TH2
Timer 2 interrupt
request
CRCH / CCHx
The capture modes can be especially useful for
external event duration calculations with the
ability to latch the timer value at a given time
(computation can be performed at a later time).
When operating in capture mode, the compare
and capture units do not affect the
VMX51C1016 interrupts.
Timer 2 Compare Modes
In compare mode, a Timer 2 count value is
compared to a value that is stored in the
CCHxx/CCLx or CRCHx/CRCLx registers. If the
values compared match (i.e. when the pulse
changes state), a compare/capture interrupt is
generated, if enabled. Varying the value of the
CCHx/CCLx or the CRCHx/CRCLx allows a
variation of the rectangular pulse generated at
the output. This variation can be used to perform
pulse width modulation. (See PWM in the
following section.)
To activate the compare mode on one of the
four compare and capture units, the associated
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VMX51C1016
COCAHx bit must be set to 1 and the associated
COCALx bit must be set to 0.
When compare mode is enabled, the
corresponding output pin value is controlled by
the internal timer circuitry.
On the VMX51C1016, two compare modes are
possible. In both modes, the new value arrives
at Port Pin 1 in the same clock cycle as the
internal compare signal is activated. The T2CM
of the T2CON register defines the compare
mode and is described below:
Compare Mode 0
Compare Mode 1
When a given compare capture unit is operating
in Mode 1, any write operations to the
corresponding output register of the port P1.x
(x=0 to3) will not appear on the physical port pin
until the next compare match occurs.
Like Compare Mode 0, the compare signal in
Mode 1 can also generate an interrupt (if
enabled).
The figure below shows the operating structure
of a given capture and compare unit operating in
Compare Mode 1.
FIGURE 25: T IMER 2 COMPARE MODE 1 BLOCK DIAGRAM
A functional diagram of Compare Mode 0 is
shown below. A comparison is made between
the 16-bit value of the compare/capture
registers and the TH2, TL2 registers. When the
Timer 2 value exceeds the value stored in the
CRCH, CRCL/CCHx and CCLx registers, a high
compare
signal
is
generated
and
a
compare/capture interrupt is activated if
enabled. If T2SIZE = 1, the comparison is made
between the TL2 and CRCL/CCLx registers.
CRCL,
CCLX
CRCH,
CCHX
Comparator
FIGURE 24: T IMER 2 COMPARE MODE 0 BLOCK DIAGRAM
CRCH,
CCHX
Compare
Signal
TL2
Port Register
Circuit
Data
Latch
Timer 2
Output Register
Overflow
Timer 2
Interrupt
P1.0PWM0
P1.1PWM1
P1.2PWM2
P1.3PWM3
Timer 2 Compare Mode Interrupt
Configuration of the compare and capture units
for the “Compare Mode” through the CCEN
register impacts on the interrupt structure of the
VMX51C1016. In that specific mode each
compare and capture unit controls one interrupt
line.
CRCL,
CCLX
Comparator
COMPxINT
Interrupt
Shadow Register
TH2
This compare signal is then propagated to the
corresponding P1.x Pin(s) and to the associated
COMPINTx interrupt (if enabled). The
corresponding P1.x pin is reset when a Timer 2
overflow occurs.
Compare
Signal
When using the PWM output device, care must
be exercised to avoid other peripheral interrupts
from being blocked by this mechanism.
COMPxINT
Interrupt
Set
Register
TH2
TL2
Timer 2
Overflow
Reset
Timer 2 Register
Interrupt
P1.0PWM0
P1.1PWM1
P1.2PWM0
P1.3PWM0
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VMX51C1016
mode). As long as the value present in the
compare and capture register is greater than the
Timer 2 value, the compare unit will output a
logic low.
FIGURE 26: COMPARE AND CAPTURE UNIT INTERRUPT CONTROL
COMPINT0
Interrupt
1
SPI Rx &
RxOV INT
0
Interrupt Vector
0053h
CCEN(1,0) = 1,0
COMPINT1
Interrupt
1
I2C INT
When the value of Timer 2 equals the value of
the compare and capture register, the compare
unit will change from a logic low to a logic high.
Interrupt Vector
005Bh
0
CCEN(3,2) = 1,0
COMPINT2
Interrupt
1
MAC
Overflow INT
0
The clock source for the PWM is derived from
Timer 2, which is incremented at every signal
pulse of the appropriate source. The source is
selected by the T2IN1 and T2IN0 bits of the
T2CON register.
Interrupt Vector
0063h
CCEN(5,4) = 1,0
COMPINT3
Interrupt
1
ADC & Port
Change INT
0
Interrupt Vector
006Bh
CCEN(7,6) = 1,0
Using Timer 2 for PWM Outputs
Configuring the compare and capture units in
Compare Mode 0 allows PWM output generation
on the Port1 I/O pins. This mode can be used for
PWM applications, such as:
o
o
o
D/A conversion
Motor control
Light control, etc.
When a specific compare and capture unit is
configured for this mode, its associated I/O pin is
reserved for this operation only and any write
operations to the associated I/O pin of the P1
register will have no affect.
The following table shows the association
between the compare and capture units,
associated registers and I/O pins.
TABLE 60: COMPARE AND C APTURE UNIT PWM ASSOCIATION
Compare
Capture
Unit
0
1
2
3
Registers
The T2SIZE bit of the T2CON register allows
configuring the PWM output for 8 or 16-bit
operation. The Timer 2 size affects all the PWM
outputs.
When the Timer 2 size is 8 bits, the comparison
is performed between Timer 2 and the LSB of
the compare and capture unit register. The
resulting PWM resolution is 8 bits.
When the Timer 2 size is configured for a 16-bit
operation, the comparison is performed between
Timer 2 and the contents of the entire compare
and capture unit register. The resulting PWM
resolution is 16 bits, but the PWM frequency is
consequently low.
When the system clock is used as the Timer 2
clock source, the PWM output frequency equals
the Timer 2 overflow rate. Note that the
CLKDIVCTRL register content affects the Timer
2 operation and, thus, the PWM output
frequency.
I/O pin
Fosc
CRCH / CRCL
CCH1 / CCL1
CCH2 / CCL2
CCH3 / CCL3
P1.0
P1.1
P1.2
P1.3
PWM signal generation is derived from the
comparison result between the values stored in
the compare and capture registers and the
Timer 2 value.
14.74MHz
T2CON
T2PSM
1
1
0
0
0
0
T2CON
T2PS
X
x
0-12
0-12
1-24
1-24
T2CON
T2SIZE
0
1
1-8
0-16
1-8
0-16
When a digital value is written into one of the
compare and capture registers, a comparison is
performed between this register and the Timer 2
value (providing that Timer 2 is in compare
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Freq
PWM
112.5Hz
28.8KHz
4.8KHz
18.8Hz
2.4KHz
9.38Hz
VMX51C1016
The duty cycle of the PWM output is proportional
to the ratio of the compare and capture unit
register’s content versus Timer 2’s maximum
number of cycles before overflow: 256 or 65536
depending on the T2SIZE bit value.
PWM Duty Cycle Calculation: 8-bit
PWM duty cycle CCU0 (%) =
100% x
PWM duty cycle CCU1-3 (%) = 100% x
(256-CRCL)_
256
(256-CCLx)_
256
Using the PWM as a D/A Converter
One of the popular uses of the PWM is to
perform D/A conversion by low pass filtering its
modulated square wave output. The greater the
duty cycle of the square wave, the greater the
DC value is at the output of the low pass filter
and vice versa.
Variations in the duty cycle of the PWM when
filtered can therefore generate arbitrary
waveforms.
PWM Duty Cycle Calculation: 16-bit
PWM duty cycle CCU0 (%) = 100% x 65536–(CRCH, CRCL)
(CRCH, CRCL)
PWM duty cycle CCU1-3 (%) = 100% x 65536–(CRCH, CRCL)
(CRCH, CRCL)
PWM Configuration Example
The following example shows how to configure
the Timer 2 based PWM in 8-bit mode.
(…)
DIGPWREN = 0x80;
T2CON = 0x61;
//ENABLE TIMER 2 MODULE
//BIT 7 - Select 0=1/12, 1=1/24 of Fosc
//BIT 6 - T2 clk source: 0 = Presc,
1=clk/2
//BIT 5 - T2 size: 0=16-bit, 1=8-bit
//BIT 4,3 - T2 Reload mode:
//BIT 2 - T2 Compare mode
//BIT 1,0 - T2 input select: 01= input
derived from osc.
//W HEN THE PWM IS CONFIGURED IN 16-BIT FORMAT, THE PWM OUTPUT
FREQUENCY IS GIVEN BY //THE FOLLOWING EXPRESSION:
// PWM Freq = [(FOSC/2)] / 65536
// W ITH A 14.7456MHZ CRYSTAL PWM FREQUENCY = 112.5HZ
//When the PWM is configured in 8-bit its output freq = [(Fosc/2)] / 256
//USING A 14.7456MHZ CRYSTAL PWM FREQUENCY = 28.8KHZ
CCEN = 0x0AA;
//Enable Compare on 4 PWM outputs
// In 16-bit PWM resolution both LSB and MSB of compare unit are used
//In 8-bit PWM Resolution, only the LSB of compare units are used
// and MSB is kept to 00h
CRCL = 0x0E6;
x100%
CRCH = 0x000;
CCL1 = 0x0C0;
x100%
CCH1 = 0x000;
CCL2 = 0x080;
CCH2 = 0x000;
CCL3 = 0x033;
CCH3 = 0x000;
P1PINCFG = 0x0F;
//PWM0 duty = [(256-CRCL)/256]
//E6h => 10.1%
//PWM1 duty = [(256-CCL1)/256]
//C0h => 25%
//PWM2 duty = [(256-CCL2)/256] x100%
//80h => 50%
//PWM3 duty = [(256-CCL3)/256] x100%
//33h => 80%
//Configure P1 LSQ as output to enable
PWM
(…)
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VMX51C1016
Serial UART Interfaces
UART0 Control Register
The VMX51C1016 includes two serial UART
interface ports (UART0 and UART1). Each serial
port has a 10-bit timer devoted to baud rate
generation.
UART0 configuration is performed mostly via the
S0CON SFR register located at address 98h.
TABLE 62: (S0CON) SERIAL PORT 0, CONTROL REGISTER - SFR 98H
Both serial ports can operate in full duplex
asynchronous mode. The VMX51C1016 also
includes a double buffer, enabling the UART to
accept an incoming word before the software
has read the previous value.
7
S0M0
6
S0M1
5
MPCE0
4
R0EN
3
T0B8
2
R0B8
1
T0I
0
R0I
Bit
7
6
5
Mnemonic
S0M0
S0M1
MPCE
4
R0EN
3
T0B8
UART0 can derive its clock source from a 10-bit
dedicated baud rate generator or from the Timer
1 overflow.
2
R0B8
UART0 transmit and receive buffers are
accessed through a unique SFR register
(S0BUF).
1
T0I
0
R0I
UART0 Serial Interface
The operation of the UART0 on the
VMX51C1016 is similar to a standard 8051
UART.
UART0 S0BUF has a double buffering feature
on reception, which allows the UART to accept
an incoming word before the software has read
the previous value from the S0BUF.
TABLE 61: (S0BUF) SERIAL PORT 0, DATA B UFFER - SFR 99H
7
6
5
4
3
S0BUF [7:0]
2
1
0
Function
Sets Serial Port Operating Mode
See Table
1 = Enables the multiprocessor
communication feature.
1 = Enables serial reception.
Cleared by software to disable
reception.
th
The 9 transmitted data bit in Modes
2 and 3. Set or cleared by the CPU,
depending on the function it
performs (parity check,
multiprocessor communication etc.)
th
In Modes 2 and 3, it is the 9 data bit
received. In Mode 1, if sm20 is 0,
RB80 is the stop bit. In Mode 0, this
bit is not used. Must be cleared by
software.
Transmit interrupt flag set by
hardware after completion of a serial
reception. Must be cleared by
software.
Receive interrupt flag set by
hardware after completion of a serial
reception. Must be cleared by
software.
UART0 Operating Modes
UART0 can operate in four distinct modes,
which are defined by the SM0 and SM1 bits of
the S0CON register (see the following table):
TABLE 63: SERIAL PORT 0 MODES
SM0
0
0
1
1
SM1
0
1
0
1
MODE
0
1
2
3
DESCRIPTION
Shift Register
8-bit UART
9-bit UART
9-bit UART
BAUD RATE
Fosc/12
Variable
Fclk/32 or /64
Variable
**Note
that the speed in mode 2 depends on SMOD bit in the Special
Function Register PCON when SMOD = 1 fclk/32
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VMX51C1016
UART0 - Mode 0
In this mode, pin RX0 is used as an input and an
output, while TX0 is used only to output the shift
clock. For an operation in this mode, 8 bits are
transmitted with the LSB as the first bit. In
addition, the baud rate is fixed at 1/12 of the
crystal oscillator frequency. In order to initialize
reception in this mode, the user must set bits
R0I and R0EN in the S0CON register to 0 and 1,
respectively. Note that in other modes, when
R0EN=1, the interface begins to receive data.
UART0 - Mode 1
In this mode, the RX0 pin serves uniquely as an
input and the TX0 pin serves as a serial output
and no external shift clock is used. In Mode 0,
10 bits are transmitted:
UART0 - Baud Rate Generator Source
As mentioned previously, the UART0 baud rate
clock can be sourced from either Timer 1 or the
10-bit dedicated baud rate generator
Selection between these two clock sources is
enabled via the BAUDSRC bit of the U0BAUD
register (see the following table).
TABLE 64: (U0BAUD) UART0 BAUD RATE SOURCE SELECT - SFR D8H
7
BAUDSRC
6
-
7
BAUDSRC
,6:0
-
5
-
4
-
3
-
2
-
1
-
Baud rate generator clock source
0 = Timer 1
1 = Use UART0 dedicated baud rate
generator
-
One*** Start bit (active low)
8 bits of data starting with the LSB;
One logical high Stop bit
o
o
o
The Start bit synchronizes data reception with
the 8 bits of received data available in the
S0BUF register. Reception is complete once the
Stop bit sets the R0B8 flag in the S0CON
register.
UART0 - Mode 2
In this mode, the RX0 pin is used as an input
and as an output, while the TX0 pin is used to
output the shift clock. In Mode 2, 11 bits are
transmitted or received. These 11 bits consist of:
One logic low Start bit
8 bits of data (LSB first)
th
One programmable 9 bit
One logic high Stop bit
o
o
o
o
0
-
th
The 9 bit is used for parity. In the case of data
transmission, bit TB80 of the S0CON is output
as the 9th bit. For reception, the 9th bit is
captured in the RB80 bit of the S0CON register.
UART0 - Mode 3
Mode 3 is essentially identical to Mode 2, the
difference being that in Mode 3, the internal
baud rate generator or Timer 1 can be used to
set the baud rate.
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VMX51C1016
Using the UART0 dedicated baud rate generator
frees up Timer 1 for other uses.
The S0RELH and S0REL registers are used to
store the 10-bit reload value of the UART0 baud
rate generator.
TABLE 65: (S0RELL) SERIAL PORT 0, RELOAD REGISTER, LOW BYTE - SFR 96H
7
6
5
4
3
S0RELL [7:0]
2
1
6
5
4
3
S0RELH [15:8]
When the baud rate clock source is derived from
Timer 1, the baud rate and the timer reload
values can be calculated using the following
formulas (examples follow):
0
TABLE 69: EQUATION TO CALCULATE BAUD R ATE FOR SERIAL 0
TABLE 66: (S0RELH) SERIAL PORT 0, RELOAD REGISTER, HIGH BYTE - SFR 97 H
7
Timer 1 can also be used as the baud rate
generator for the UART0. Set BAUDSRC to 0
and assign Timer 1’s output to UART0.
2
1
Serial 0: mode 1 and 3
Mode 1: ForU0BAUD.7=0 (standard mode)
0
Baud Rate =
The following equations should be used to
calculate the reload value for the SOREL
register (examples follow).
TH1 = 256 -
SMOD
2
x fclk
_
32 x 12 x (256-TH1)
SMOD
2
x fclk____
32x12x Baud Rate
Mode 3: For BAUDSRC=1
SOREL = 1024 –
SMOD
2
x fclk_______
64 x Baud Rate
TABLE 70: UART0 BAUD R ATE SAMPLE VALUES BAUDSRC =0, SMOD = 1
Baud Rate =
SMOD
2
x fclk____
64 x (1024 – S0REL)
TABLE 67: SERIAL 0 BAUD R ATE SAMPLE VALUES BAUDSRC = 1, SMOD = 1
Desired
Baud Rate
500.0 kbps
460.8 kbps
230.4 kbps
115.2 kbps
57.6 kbps
19.2 kbps
9.6 kbps
2.4 kbps
1.2 kbps
300 bps
S0REL @ fclk=
11.059 MHz
3FDh
3FAh
3EEh
3DCh
370h
2E0h
-
S0REL @ fclk=
14.746 MHz
3FFh
3FEh
3FCh
3F8h
3E8h
3D0h
340h
280h
-
TABLE 68: SERIAL 0 BAUD R ATE SAMPLE VALUES BAUDSRC =1, SMOD = 0
Desired
Baud Rate
115.2 kbps
57.6 kbps
19.2 kbps
9.6 kbps
2.4 kbps
1.2 kbps
300 bps
S0REL @ fclk=
11.059 MHz
3FDh
3F7h
3EEh
3B8h
370h
1C0h
Desired
Baud Rate
115.2 kbps
57.6 kbps
19.2 kbps
9.6 kbps
2.4 kbps
1.2 kbps
300 bps
TH1 @ fclk=
11.059 MHz
FFh
FDh
FAh
E8h
D0h
40h
TH1 @ fclk=
14.746 MHz
FCh
F8h
E0h
C0h
-
TABLE 71:UART0 B AUD RATE SAMPLE VALUES BAUDSRC =0, SMOD = 0
Desired
Baud Rate
115.2 kbps
57.6 kbps
19.2 kbps
9.6 kbps
2.4 kbps
1.2 kbps
300 bps
TH1 @ fclk=
11.059 MHz
FDh
F4h
E8h
A0h
TH1 @ fclk=
14.746 MHz
FEh
FCh
F0h
E0h
80h
S0REL @ fclk=
14.746 MHz
3FEh
3FCh
3F4h
3E8h
3A0h
340h
100
_________________________________________________________________________________________________
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VMX51C1016
Example of UART0 Setup and Use
In order to use UART0, the following operations
must be performed:
o
o
o
o
Enable UART0 interface
Set I/O pad direction TX=output, RX=Input
Enable reception (if required)
Configure the UART0 controller S0CON
The following are configuration and transmission
code examples for UART0.
//----------------------------------------------------------------------------------------//
// UART0 CONFIG with S0REL
//
// Configure the UART0 to operate in RS232 mode at 19200bps
// with a crystal of 14.7456MHz
//
//----------------------------------------------------------------------------------------//
void uart0ws0relcfg()
{
P3PINCFG |= 0x01;
// pads for uart 0
DIGPWREN |= 0x01;
// enable uart0/timer1
S0RELL = 0xF4;
//com speed = 19200bps
S0RELH = 0x03;
S0CON = 0x50;
// Uart0 in mode1, 8 bit, var. baud rate
U0BAUD = 0x80;
//Set S0REL is source for UART0
//Baud rate clock
}//end of uart0ws0relcfg() function
//----------------------------------------------------------------------------------------//
// UART0 CONFIG with Timer 1
//
// Configure the UART0 to operate in RS232 mode at 19200bps
// with a crystal of 14.746MHz
//
//----------------------------------------------------------------------------------------//
void uart0wTimer1cfg()
{
P3PINCFG |= 0x01;
// pads for uart0
DIGPWREN |= 0x01;
// enable uart0/timer1
TMOD &= 0x0F;
TMOD =0x20;
//Set Timer 1, Gate 0, Mode 2
TH1 = 0xFE;
//Com Speed = 19200bps
TCON &= 0x0F;
TCON =0x40;
//Start Timer 1
U0BAUD = 0x00;
//Set Timer 1 Baud rate
//generator for UART0
PCON = 0x00;
S0CON = 0x50;
//Set SMOD = 0
// Config Uart0 in mode 1,
//8 bit, variable baud rate
}//end of uart1Config() function
//----------------------------------------------------------------------------------------//
// Txmit0()
//
// One Byte transmission on UART0
//----------------------------------------------------------------------------------------//
// - Constants definition
sbit UART_TX_EMPTY = USERFLAGS^1;
void txmit0( unsigned char charact){
S0BUF = charact;
USERFLAGS = S0CON;
//Wait TX EMPTY flag to be raised
while (!UART_TX_EMPTY) {USERFLAGS = S0CON;} S0CON =
//clear both R0I & T0I bits
S0CON & 0xFD;
}//end of txmit0() function
See the interrupt section for examples of how to
setup UART0 interrupts.
_________________________________________________________________________________________________
page 39 of 76
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VMX51C1016
UART1 Serial Interface
UART1: Operating Modes
The UART1 serial interface is based on a subset
of UART0. It provides two operating modes and
its clock source is derived exclusively from a
dedicated 10-bit baud rate generator.
The VMX51C1016 UART1 provides two
operating modes, Mode A and Mode B, which
provide 8 or 9-bit operation, respectively.
The UART1 transmit and receive buffers are
accessed via a unique SFR register named
S1BUF.
TABLE 72: (S1BUF) SERIAL PORT 1, DATA B UFFER - SFR C1H
7
6
5
4
3
S1BUF [7:0]
2
1
0
As is the case with UART0, UART1 has a
double buffering feature in order to avoid an
overwriting of the receive register.
UART1 Control Register
UART1 is controlled by the S1CON register. The
following table provides a description of the
UART 1 control register.
TABLE 73: (S1CON) SERIAL PORT 1, CONTROL REGISTER - SFR C0H
7
S1M
6
Reserved
5
MPCE1
4
R1EN
3
T1B8
2
R1B8
1
T1I
0
R1I
Bit
7
6
5
Mnemonic
S1M
Reserved
MPCE1
4
R1EN
3
T1B8
2
R1B8
1
T1I
0
R1I
Function
Operation Mode Select
1 = Enables multiprocessor
communication feature.
If set, enables serial reception.
Cleared by software to disable
reception.
th
The 9 transmitted data bit in mode
A. Set or cleared by the CPU,
depending on the function it performs
(parity check, multiprocessor
communication, etc.)
th
In Mode A, it is the 9 data bit
received. In Mode B, if SM21 is 0,
RB81 is the stop bit. Must be cleared
by software.
Transmit interrupt flag, set by
hardware after completion of a serial
transfer. Must be cleared by software
Receive interrupt flag, set by
hardware after completion of a serial
reception. Must be cleared by
software
Below is a summary table of operating modes of
UART1.
TABLE 74: UART1 MODES
SM
MODE
DESCRIPTION
BAUD RATE
0
1
A
B
9-bit UART
8-bit UART
Variable
Variable
UART1 - Mode A
In this mode, 11 bits are transmitted or received.
These 11 bits are composed of:
o
o
o
o
A Start bit (logic low)
8-bits of data (LSB first)
A programmable 9th bit
A Stop bit (logic low )
As in modes 2 and 3 of UART0, the 9th bit is
used for parity control. For data transmission,
the TB81 bit of the S1CON register holds the 9th
bit. In the case of reception, the 9th bit will be
captured into the R1B8 bit of the S1CON
register.
UART1 - Mode B
In this
of:
o
o
o
mode, 10 bits are transmitted and consist
A Start bit (logic low)
8-bits of data (LSB first)
A Stop bit (logic low)
Received data (8 bits) is read via the S1BUF
register. Reception is completed once the Stop
bit sets the R1B8 flag in the S1CON register.
UART1 - Baud Rate Generator
As mentioned previously, the UART1 clock
source is derived from a dedicated 10-bit baud
rate generator module.
_________________________________________________________________________________________________
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VMX51C1016
The S1REL registers are used to adjust the
baud rate of UART 1.
TABLE 75: (S1RELL) UART1, RELOAD REGISTER, LOW BYTE - SFR BEH
7
6
5
4
3
S1RELL [7:0]
2
1
0
TABLE 76: (S1RELH) UART 1, RELOAD REGISTER, HIGH BYTE - SFR BFH
7
6
5
4
3
S1RELH [7:0]
2
1
0
The following formulas are used to calculate the
baud rate, S1RELL and S1RELH values:
Serial 1
Baud Rate=
f clk__________
32 x (1024-S1REL)
Note: S1REL.9-0 = S1RELH.1-0 + S1RELL.7-0
S1REL = 1024 -
fclk__________
32 x Baud Rate
TABLE 77: SERIAL 1 BAUD R ATE SAMPLE VALUES
Desired
Baud Rate
500.0 kbps
460.8 kbps
230.4 kbps
115.2 kbps
57.6 kbps
19.2 kbps
9.6 kbps
2.4 kbps
1.2 kbps
S1REL @ fclk=
11.059 MHz
S1REL @ fclk=
14.746 MHz
3FDh
3FAh
3EEh
3DCh
370h
2E0h
3FFh
3FEh
3FCh
3F8h
3E8h
3D0h
34Fh
280h
Example of UART1 Setup and Use
The following are C code examples of UART1
configuration, serial byte transmission and
interrupt usage.
//----------------------------------------------------------------------------------------//
// UART1 CONFIG
//
// Configure the UART1 to operate in RS232 mode at 115200bps
// with a crystal of 14.746MHz
//----------------------------------------------------------------------------------------//
void uart1Config(void)
{
P0PINCFG |= 0x04;
// pads for uart 1
DIGPWREN |= 0x02;
// enable uart1
S1RELL = 0xFC;
// Set com speed = 115200bps
S1RELH = 0x03;
S1CON = 0x90;
// Mode B, receive enable
}//end of uart1Config() function
//----------------------------------------------------------------------------------------//
// TXMIT1 -- Transmit one byte on the UART1
//----------------------------------------------------------------------------------------//
void txmit1( unsigned char charact){
S1BUF = charact;
USERFLAGS = S1CON;
while (!UART_TX_EMPTY) {USERFLAGS = S1CON;}
//Wait TX EMPTY flag
S1CON = S1CON & 0xFD;
//clear both R1I & T1I bits
}//end of txmit1() function
//----------------------------------------------------------------------------------------//
// Interrupt configuration
//---------------------------------------------------------------------------------------//
IEN0 |= 0x80;
IEN2 |= 0x01;
//----------------------------------------------------------------------------------------//
// Interrupt function
//----------------------------------------------------------------------------------------//
void int_serial_1 (void) interrupt 16
{
IEN0 &= 0x7F;
Setting Up and Using UART1
In order to use UART1, the following operations
must be performed:
o
o
o
o
Enable UART1 interface
Set I/O pad direction TX= output, RX=Input
Enable reception (if required)
Configure UART1 controller S1CON
// Enable all interrupts
// Enable interrupt UART 1
// Disable all interrupts
/*------------------------*/
/*Interrupt code here*/
/*------------------------*/
if (S1CON&0x01==0x01)
{
S1CON &= 0xFE;
}
else
{
S1CON &= 0xFD;
}
IEN0 |= 0x80;}
// Clear RI (it comes
// before T1I)
// Clear T1I
// Enable all interrupts
}
}
/-----------------------------------------------------------------------
_________________________________________________________________________________________________
page 41 of 76
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VMX51C1016
UART1 Driven Differential
Transceiver
Using the UART 1 Differential
Transceiver
The VMX51C1016 includes a differential
transceiver compatible with the standard
J1708/RS-485. These are driven by UART1.
To use the differential transceiver interface, the
following operations must be performed:
o
The transceiver’s signals are differential,
providing high electrical noise immunity. The
differential
interface
is
capable
of
transferring/receiving data over hundreds of feet
of twisted pair wires.
A number of devices can be connected in
parallel to the differential bus in order to
implement a multi-drop network. The number of
devices that can be networked depends on bus
length and configuration.
The admissible common mode voltage range of
the differential interface is –2.0 to +7.0 volts.
When implementing this type of transmission
network over long distances in noisy
environments,
appropriate
protection
is
recommended to prevent the common mode
voltage from causing any damage to the
VMX51C1016.
FIGURE 28: DIFFERENTIAL INTERFACE (RS485 CONFIG)
o
o
o
Enable both UART1 and the differential
interface by setting bits 1 and 2 of the
DIGPWREN
Configure UART1’s operating mode via
the S1CON register
Set the baud rate via the S1RELH and
S1RELL registers
Enable UART1’s interrupt (if required)
Use UART1’s S1BUF register to transmit and
receive data through the differential transceiver.
If the P0.2 pin is configured as an output, the
signal corresponding to the TX1 signal of
UART1 will appear on this pin (note that the
P0.3-RX1 pin can be used as a regular digital
output).
When the transceiver is connected in half-duplex
mode (RX1D+ connected to TX1D+ and RX1Dconnected to TX1D-) and the UART1 interrupts
are enabled, careful management of the UART1
interrupts will be required as every byte
transmitted will generate a local Rx interrupt.
+5V
Versa Mix
TX1D+
TX1D-
RX1D+
RX1D-
From a software point of view, the differential
transceiver is viewed as a differential UART.
The differential transceiver I/Os are connected
to UART1 of the VMX51C1016, therefore,
communication parameters such as the data
length, communication speed, etc. are managed
by the UART1 peripheral interface/registers.
_________________________________________________________________________________________________
page 42 of 76
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VMX51C1016
Differential Interface Use Example
The following code provides an example of
configuration and use of the VMX51C1016
differential interface.
#pragma SMALL
#pragma UNSIGNEDCHAR
#include <vmixreg.h>
int x=0;
idata unsigned char
//disable ext0 interrupt
cptr = cptr-1;
while( irq0msg[cptr] != '\n')
//Send a text string over the differential interface
{
txmit1( irq0msg[cptr]);
cptr = cptr +1;
}
// - global variables
// - Constants definition
sbit UART_TX_EMPTY = USERFLAGS^1;
code char irq0msg[]="Ramtron inc”;
//---------------------------------------------------------------------------------------------//
//
MAIN FUNCTION
//---------------------------------------------------------------------------------------------//
at 0x0100 void main (void) {
//Config UART1 diff interface
// Warning: The Clock Control circuit does affect the dedicated baud rate
//
generator S0REL, S1REL and Timer1 operation
//*** Configure the interrupts
IEN0 |= 0x81;
IEN2 |= 0x01;
Txmit1(“A’);
//Enable interrupts + Ext. 0 interrupt
//Enable UART1 Interrupt
//Transmit one character on UART1
do
{
}while(1);
//Wait for UART1 Rx interrupt
}// End of main()...
//---------------------------------------------------------------------------------------------//
// UART1 Differential interface interrupt
//
// In this example, the source of UART1 interrupt would be caused
// by bytes reception on the differential interface
//----------------------------------------------------------------------------------------------//
void int_uart1 (void) interrupt 16 {
unsigned char charact;
IEN0 &= 0x7F;
IEN0 = 0x81;
//Enable all interrupts + int_0
//----------------------------------------------------------------------------------------------------//
//------------------------------- Individual Functions ----------------------------------------//
//----------------------------------------------------------------------------------------------------//
//----------------------------------------------------------------------------------------------------//
// UART1 DIFFERENTIAL CONFIG
//
// Configure the UART1 differential interface to operate in
// RS232 mode at 115200bps with a crystal of 14.746MHz
//
//----------------------------------------------------------------------------------------------------//
void uart1differential(void)
{
DIGPWREN |= 0x06;
// enable uart1 & differential transceiver
P0PINCFG |= 0x04;
// pads for uart1
P0PINCFG = 0x00;
S1RELL = 0xFC;
// Set com speed = 115200bps
S1RELH = 0x03;
S1CON = 0x90;
// Mode B, receive enable
}//end of uart1differential() function
//-----------------------------------------------------------------------------------------------//
// TXMIT1
//
// Transmit one byte on the UART1 Differential interface
//
//-----------------------------------------------------------------------------------------------//
void txmit1( unsigned char charact){
S1BUF = charact;
USERFLAGS = S1CON;
//Wait TX EMPTY flag to be raised
while (!UART_TX_EMPTY) {USERFLAGS = S1CON;}
// -- Put you code here…
S1CON = S1CON & 0xFC;
IEN0 |= 0x80;
cptr=0x01;
IEN0 &= 0x7F;
// --- function prototypes
void txmit1( unsigned char charact);
void uart1differential(void);
// Enable and configure the UART1
uart1differential();
//---------------------------------------------------------------------------------------------//
// EXT INT0 interrupt
//
//
// when the External interrupt 0 is triggered A Message string is sent over the
// the serial UART1
//---------------------------------------------------------------------------------------------//
void int_ext_0 (void) interrupt 0 {
//clear both R1I & T1I bits
// enable all interrupts
S1CON = S1CON & 0xFD;
}//end of txmit1() function
//clear both R1I & T1I bits
}// end of uart1 INTERRUPT
_________________________________________________________________________________________________
page 43 of 76
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VMX51C1016
FIGURE 29: SPI INTERFACE BLOCK DIAGRAM
SPI Interface
SPI SFRs
VERSA MIX SPI
INTERFACE
Serial Data IN
SDI
Serial Data OUT
The VMX51C1016 SPI peripheral is a highly
configurable and powerful interface enabling
high speed serial data exchange with external
devices such as A/Ds, D/As, EEPROMs, etc.
SDO
Serial Clock IN/OUT
SCK
Chip Select Output
CS0
To Slave Device #1
Chip Select Output
CS1
The SPI interface can operate as either a master
or a slave device. In master mode, it can control
up to four slave devices connected to the SPI
bus.
The following lists a number
VMX51C1016’s SPI features:
o
o
o
o
of
To Slave Device #2
Chip Select Output
CS2
Processor
CS3
SPI IRQs
SS
To Slave Device #3
Chip Select Output
Slave Select Input
To Slave Device #4
From Master Device
the
Permits
synchronous
serial
data
transfers
Transaction size is configurable from 1
to 32 bits and more
Full duplex support
SPI modes 0, 1, 2, 3, 4-supported (full
SPI Transmit/Receive Buffer
Structure
When receiving data bytes, the first byte
received is stored in the SPIRX0 buffer. As bits
continue to arrive, the data already present in
the buffer is shifted toward the least significant
byte end of the receive registers.
clock polarity and phase control)
o
o
o
o
o
o
o
Up to four slave devices can be
connected to the SPI bus when
configured in master mode
Slave mode operation
Data transmission speed is configurable
Double 32-bit buffers in transmission
and reception
3 dedicated interrupt flags
• TX-Empty
• RX Data Available
• RX Overrun
Automatic/Manual control of the chip
selects lines
SPI operation is not affected by the
clock control unit
For example (see the following figure), assume
the SPI is about to receive four consecutive
bytes of data: W, X, Y and Z, where the first
byte received is byte W. The first received byte
(W) will be placed in the SPIRX0 register. Upon
reception of the next byte (X), the contents of
SPIRX0 will be shifted into SFR register SPIRX1
and byte X will be placed in the SPIRX0
registers. Following this same procedure, bytes
W, X, Y and Z will end up in RX data buffer
registers SPIRX0, SPIRX1, SPIRX2 and
SPIRX3, respectively.
The case where the SDO and SDI pins are
shorted together is represented in the following
diagram.
The following provides a block diagram view of
the SPI interface.
_________________________________________________________________________________________________
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VMX51C1016
FIGURE 30 : SPI INTERFACE RECEIVE T RANSMIT SCHEMATIC
TABLE 80: (SPIRX1TX2) SPI DATA BUFFER, BYTE 2 - SFR E3H
BEFORE A RECEPTION
LSBit
7
lsb
Bit
22:16
SPITX3
W
SPITX2
X
SPITX1
Y
SPITX0
Z
msb
msb
SPIRX2
SPIRX1
7
AFTER A RECEPTION
SPITX3
SPITX2
Z
Y
SPIRX2
SPITX1
X
SPIRX1
6
Bit
31:24
W
o
SPIRX0
o
Bytes are Shifted 1 byte position
at a time each time a new byte is
received
o
5
Mnemonic
SPITX3
SPIRX0
Close-Up View of how the bits within
the byte is placed after it has been
received
When using the SPI interface, it is important to
keep in mind that a transmission is started when
the SPIRX3TX0 register is written to.
Bit
7-0
Mnemonic
SPITX0
SPIRX3
4
3
2
SPIRX3TX0 [7:0]
1
Bit
15:8
6
5
Function
SPI Transmit Data Bits 7:0
SPI Receive Data Bits 31:24
Mnemonic
SPITX1
SPIRX2
4
3
2
SPIRX2TX1 [15:8]
Function
SPI Transmit Data Bits 31:24
SPI Receive Data Bits 7:0
5
4
SPICS_1
3
SPICS_0
2
SPICKPH
1
SPICKPOL
0
SPIMA_SL
Bit
7:5
Mnemonic
SPICK[2:0]
4:3
SPICS[1:0]
2
1
SPICKPH
SPICKPOL
0
SPIMA_SL
0
TABLE 79: (SPIRX2TX1) SPI DATA BUFFER, BYTE 1 - SFR E2H
7
0
6
SPICK [2:0]
TABLE 78: (SPIRX3TX0) SPI DATA BUFFER, LOW BYTE - SFR E1H
5
1
7
From an SFR point of view, the transmission
and reception buffers of the SPI interface
occupy the following addresses:
6
4
3
2
SPIRX0TX3 [31:24]
TABLE 82: (SPICTRL) SPI CONTROL REGISTER - SFR E5H
LSBit
7 6 5 4 3 2 1 0
7
Function
SPI Transmit Data Bits 22:16
SPI Receive Data Bits 15:8
SPI operating speed (master mode)
Active chip select output (master mode)
SPI clock phase (master/slave modes)
SPI clock polarity (master/slave modes)
o
lsb
MSBit
0
The SPI control registers are used to define:
SPITX0 msb
msb
SPIRX3
1
SPI Control Registers
TX Data Buffer
RX Data Buffer
Mnemonic
SPITX2
SPIRX1
SPIRX0
First Byte Received is
Placed in the least
significant byte register
lsb
4
3
2
SPIRX1TX2 [23:16]
TABLE 81: (SPIRX0TX3) SPI DATA BUFFER, HIGH BYTE - SFR E4H
lsb
RX Data Buffer
SPIRX3
5
First Byte to be
Transmitted
MSBit
0 1 2 3 4 5 6 7
TX Data Buffer
6
1
Function
SPI 1 Transmit Data Bits 15:8
SPI Receive 1 Data Bits 22:16
0
Function
SPI Clock control
000 = OSC Ck Div 2
001 = OSC Ck Div 4
010 = OSC Ck Div 8
011 = OSC Ck Div 16
100 = OSC Ck Div 32
101 = OSC Ck Div 64
110 = OSC Ck Div 128
111 = OSC Ck Div 256
Active CS line in Master Mode
00 = CS0- Active
01 = CS1- Active
10 = CS2- Active
11 = CS3- Active
SPI Clock Phase
SPI Clock Polarity
0 – CK Polarity is Low
1 – CK Polarity is High
Master / -Slave
1 = Master
0 = Slave
_________________________________________________________________________________________________
page 45 of 76
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VMX51C1016
FIGURE 31 : SPI MODE 0
SPI Operating Speed
Three bits in the SPICTRL register serve to
adjust the communication speed of the SPI
interface.
SPI MODE 0: SPICKPOL =0,SPICKPH =0
CSX
SCK
SPICK[2:0]
Div Ratio
Clk Div 2
Clk Div 4
Clk Div 8
Clk Div 16
Clk Div 32
Clk Div 64
Clk Div 128
Clk Div 256
Fosc =
14.74MHz
7.37 MHz
3.68 MHz
1.84 MHz
922 kHz
461 kHz
230 kHz
115 kHz
57.6 kHz
Fosc =
11.059MHz
SDO
5.53 MHz
2.76 MHz
1.38 MHz
691 kHz
346 kHz
173 kHz
86 kHz
43.2 kHz
LSB
SDI
*Arrows indicate the edge where the data acquisition occurs
SPI Mode 1
o
o
SPI Master Chip Select Control
When the SPI is configured in master mode, the
value of the SPICS[1:0] bits define which chip
select pins will be active during the transaction.
MSB
Data is placed on the SDO pin at the
falling edge of the clock
Data is sampled on the SDI pin at the
rising edge of the clock
FIGURE 32: SPI MODE 1
SPI MODE 1: SPICKPOL =0,SPICKPH =1
CSX
The following sections describe how the SPI
clock polarity and phase affects the read and
write operations of the SPI interface.
SCK
SDO
MSB
LSB
SDI
SPI Operating Modes
*Arrows indicate the edge where the data acquisition occurs
The SPI interface can operate in four distinct
modes defined by the value of the SPICKPH
and SPICKPOL bits of the SPICTRL register.
SPICKPH defines the SPI clock phase and
SPICKPOL defines the clock polarity for data
exchange.
SPICKPOL
bit value
0
0
1
1
SPICKPH
bit value
0
1
0
1
SPI Operating Mode
SPI Mode 0
SPI Mode 1
SPI Mode 2
SPI Mode 3
SPI Mode 0
o
o
Data is placed on the SDO pin at the
rising edge of the clock.
Data is sampled on the SDI pin at the
falling edge of the clock
_________________________________________________________________________________________________
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VMX51C1016
SPI Transaction Size
SPI Mode 2
Data is placed on the SDO pin at the
falling edge of the clock
Data is sampled on the SDI pin at the
rising edge of the clock
o
o
FIGURE 33: SPI MODE 2
SPI MODE 2: SPICKPOL =1,SPICKPH =0
CS X
SCK
SDO
MSB
LSB
SDI
TABLE 83: (SPISIZE) SPI SIZE CONTROL REGISTER - SFR E7H
SPI Mode 3
o
The VMX51C1016 SPI interface includes a
transaction size control register (SPISIZE) that
enables different sized transactions to be
performed. The SPI interface also automatically
controls the chip select line.
The following table describes the SPISIZE
register:
*Arrows indicate the edge where the data acquisition occurs
o
Many microcontrollers only allow a fixed SPI
transaction size of 8 bits. However, most
devices requiring SPI
control demand
transactions of more than 8 bits, giving way to
alternate inefficient methods of dealing with SPI
transactions.
7
Data is placed on the SDO pin at the
rising edge of the clock.
Data is sampled on the SDI pin at the
falling edge of the clock
Bit
7:0
6
5
4
3
SPISIZE[7:0]
Mnemonic
SPISIZE[7:0]
2
1
0
Function
Value of the SPI packet size
The following formula is used to calculated the
SPI transaction size:
FIGURE 34: SPI MODE 3
SPI MODE 3: SPICKPOL =1,SPICKPH =1
For SPISIZE from 0 to 31:
CSX
SPI Transaction Size = [SPISIZE + 1]
SCK
SDO
MSB
SDI
*Arrows indicate the edge where the data acquisition occurs
LSB
For SPISIZE from 32 to 255*:
SPI Transaction Size = [SPISIZE*8 - 216]
An SPI transaction size greater than 32 bits is
possible when using the VMX51C1016 SPI
interface, however, data packets of this size
require careful management of the associated
interrupts in order to avoid buffer overwrites.
SPI Interrupts
The SPI
interrupts:
o
o
o
interface
has
three
associated
SPI RX Overrun
SPI RX Data Available
SPI TX Empty
_________________________________________________________________________________________________
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VMX51C1016
The SPIRXOVIE, SPIRXAVIE and SPITXEMPIE
bits of the SPICONFIG register allow individual
enabling of the above interrupt sources at the
SPI interface level.
At the processor level, two interrupt vectors are
dedicated to the SPI interface:
o
o
SPI RX data available and overrun
interrupt
SPI TX empty interrupt
In order to have the processor jump to the
associated interrupt routine, one or both of these
interrupts in the IEN1 register must be enabled,
and the EA bit of the IEN0 register must be set
(see interrupt section).
TABLE 84: (SPICONFIG) SPI CONFIG REGISTER - SFR E6H
7
6
5
4
SPICSLO
-
FSONICS3
SPILOAD
3
-
2
SPIRXOVIE
1
SPIRXAVIE
0
SPITXEMPIE
Bit
7
Mnemonic
SPICSLO
6
5
FSONCS3
4
SPILOAD
3
2
SPIRXOVIE
1
SPIRXAVIE
0
SPITXEMPIE
Function
Manual CS up (Master mode)
0 = The CSx goes low when
transmission begins and returns
to high when it ends.
1 = The CSx stays low after
transmission ends. The user
must clear this bit for the CSx
line to return high.
This bit sends the frame select
pulse on CS3.
This bit sends load pulse on
CS3.
SPI Receiver overrun interrupt
enable.
SPI Receiver available interrupt
enable.
SPI Transmitter empty interrupt
enable.
The SPIIRQSTAT register contains
interrupts flags associated with the
interface.
TABLE 85: (SPIIRQSTAT) SPI INTERRUPT STATUS REGISTER - SFR E9H
7
-
6
-
3
SPISEL
2
SPIOV
Bit
7:6
Mnemonic
-
5
SPITXEMPTO
4
SPISLAVESEL
3
SPISEL
2
1
SPIOV
SPIRXAV
0
SPITXEMP
5
SPITXEMPTO
1
SPIRXAV
4
SPISLAVESEL
0
SPITXEMP
Function
Flag that indicates that we have
not reloaded the transmit buffer
fast enough (only used for
packets greater than 32 bits.).
Slave Select “NOT” (SSN)
This bit is the result of the
logical AND operation between
CS0, CS1, CS2 and CS3.
(Indicates if one chip is
selected.)
SPI Receiver overrun
SPI Receiver available
SPI Transmit buffer is ready to
receive mode data. It does not
flag that the transmission is
completed.
SPI Manual Chip Select Control
In some applications, manual control of the
active select line can be useful. Setting the
SPICSLO bit of the SPICONFIG register forces
the active chip select line to stay low when the
SPI transaction is completed in master mode.
When the SPICSLO bit is cleared, the chip
selected line returns to its active state.
SPI Manual Load Control
The SPI can generate a LOAD pulse on the CS3
pin when the SPILOAD bit is set. This is useful
for some D/A converters and avoids having to
use a separate I/O pin for this purpose.
the
SPI
Monitoring these bits enables polling the control
of the SPI interface.
_________________________________________________________________________________________________
page 48 of 76
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VMX51C1016
SPI Frame Select Control
while(1){
do{
dacvall = dacvall + 1;
if( dacvall==0xff)
{
dacvalh = dacvalh +1;
dacvall = 0x00;
}
It is also possible to generate a positive pulse on
the CS3 pin of the SPI interface by setting the
FSONCS3 bit of the SPICONFIG register. This
feature can be used to generate a frame select
signal required by some DSP compatible
devices without requiring the use of a separate
I/O pin.
send16-bitdac( dacvalh, dacvall);
}while( (dacvall != 0xff) && (dacvalh != 0xff) );
do{
dacvall = dacvall - 1;
if( dacvall==0x00)
{
dacvalh = dacvalh - 1;
dacvall = 0xff;
}
send16-bitdac( dacvalh, dacvall);
}while( (dacvall != 0x00) && (dacvalh != 0x00) );
};
Note that when both the SPILOAD and
FSONCS3 are selected, the internal logic gives
priority to the frame select pulse.
SPI Interface to 16-bit D/A Example
}// End of main()...
The following is a code for executing 16-bit
transfers over the SPI interface.
//---------------------------------------------//
// VMIX_SPI_to_dac_interface. c //
//---------------------------------------------//
//
// This demonstration program show the how to interface a 16-bit D/A
// to the VMX51C1016 SPI interface.
//
#pragma SMALL
#include <vmixreg.h>
//-----------------------------------------------------------------------//
// Send16-bitdac - Send data to 16 bit D/A Converter //
//-----------------------------------------------------------------------//
void send16-bitdac( unsigned char valhigh, unsigned char vallow){
//
//
USERFLAGS = 0x00;
while(!SPI_TX_EMPTY){USERFLAGS = SPIIRQSTAT;}
SPIRX2TX1 = vallow;
SPIRX3TX0 = valhigh;
do{
// --- function prototypes
//Function Prototype: Send Data to the 16 bit D/A
void send16bitdac( unsigned char valhigh, unsigned char vallow);
//Put LSB of value in SPI transmit buffer
//-> trigger transmission
//Put MSB of value in SPI transmit buffer
//-> trigger transmission
//Wait SPI TX empty flag to be activated
USERFLAGS = P2;
USERFLAGS &= 0x08;
}while( USERFLAGS == 0);
}//end of send16-bitdac
// Bit definition
sbit SPI_TX_EMPTY = USERFLAGS^0;
//------------------------------------------------------------------------------//
//
MAIN FUNCTION
//
//-----------------------------------------------------------------------------//
at 0x0100 main (void) {
unsigned char dacvall=0;
unsigned char dacvalh=0;
DIGPWREN |= 0x08;
//LSB of current DAC value
//MSB of current DAC value
//ENABLE SPI INTERFACE
//*** Initialise the SPI interface ****
P2PINCFG |= 0x68;
// config I/O port to allow the SPI
//interface to access the pins
// In this application we only need to configure the 5 upper bit of P2PINCFG
// P2PINCFG bit 7 - SDIEN = 0 -> INPUT (NOT USED)
// P2PINCFG bit 6 - SDOEN = 1 -> OUTPUT TO DAC SDI PIN
// P2PINCFG bit 5 - SCKEN = 1 -> OUTPUT TO DAC SCK PIN
// P2PINCFG bit 4 - SSEN = 0 -> INPUT (NOT USED)
// P2PINCFG bit 3 - CS0EN = 1 -> OUTPUT TO DAC CS PIN
// P2PINCFG bit 2 - CS1EN = 0 -> INPUT (NOT USED)
// P2PINCFG bit 1 - CS2EN = 0 -> INPUT (NOT USED)
// P2PINCFG bit 0 - CS3EN = 0 -> INPUT (NOT USED)
SPICTRL = 0x25;
// SPI ctrl: OSC/16, CS0, phase=0, pol=0, master
// SPICK BIT 7:5 = 001 -> SPI CLK SPEED = OSC/2
// SPICS BIT 4:3 = 00 -> CS0 LINE IS ACTIVE
// SPICKPH BIT 2 = 1 SPI CLK PHASE
// SPICKPOL BIT 1 = 0 SPI CLOCK POLARITY
// SPIMA_SL BIT 0 = 1 -> SET SPI IN MASTER MODE
SPICONFIG = 0x00;
// SPI CONFIG: auto CSLO, no FS, NO Load, clear IRQ flags
// SPICSLO BIT 7 = 0 AUTOMATIC CHIP SELECT CONTROL
// UNSUSED BIT 6 = 0
// FSONCS3 BIT 5 = 0 Do not send FrameSelect Signal on CS3
// SPILOAD BIT 4 = 0 do not Sen the Low pulse on CS3
// UNUSED BIT 3 = 0
// SPIRXOVIE BIT 2 = 0 Dont enable SPI RX Overrun IRQ
// SPIRXAVIE BIT 1 = 0 Dont enable SPI RX AVAILLABLE IRQ
// SPITXEMPIE BIT 0 = 0 Dont Enable SPI TX EMPTY IRQ
SPISIZE = 0x0F;
// SPI SIZE: 16-bits
// GENERATE A TRIANGLE WAVE ON THE DAC OUTPUT
_________________________________________________________________________________________________
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VMX51C1016
SPI Interrupt Example
The following provides an example of basic SPI
configuration and interrupt handling.
//-------------------------------------------------------------------------------//
// Sample C code for SPI RX & TX interrupt set-up
//-------------------------------------------------------------------------------//
//
#pragma SMALL
#include <vmixreg.h>
The SPI also includes double buffering for data
reception. Once a data reception is completed,
the RX interrupt is activated and the data is
transferred into the SPI RX buffer. At this point,
the SPI interface can receive more data.
However, the processor must have retrieved the
first data stream before the second data stream
reception is complete, otherwise a data overrun
will occur and the SPI RX overrun interrupt will
be activated if enabled.
at 0x0100 main (void) {
DIGPWREN = 0x08;
P2PINCFG = 0x4F;
SPICONFIG = 0x03;
SPISIZE = 0x07;
// Enable SPI
// Set pads direction
// Enable Rx_avail + TX_empty
// SPI SIZE: 8 bits
IEN0 |= 0x80;
IEN1 |= 0x06;
// Enable all interrupts
// Enable SPI Txempty + RXavail interrupt
SPIRX3TX0 = valhigh;
//Put MSB of value in SPI transmit buffer
//-> trigger transmission
Do{
}while(1)
}//end of main()
//---------------------------------------------------------------------------//
// SPI TX Empty Interrupt function
//---------------------------------------------------------------------------//
void int_2_spi_tx (void) interrupt 9
{
IEN0 &= 0x7F;
// Disable all interrupts
/*-------------------------*/
/* Interrupt code here*/
/*-------------------------*/
IRCON &= 0xFD;
IEN0 |= 0x80;
}
// Clear flag SPITXIF
// Enable all interrupts
//---------------------------------------------------------------------------//
// SPI RX availlable function
//---------------------------------------------------------------------------//
void int_2_spi_rx (void) interrupt 10
{
IEN0 &= 0x7F;
// Disable all interrupts
/*-------------------------*/
/* Interrupt code here*/
/*-------------------------*/
IRCON &= 0xFB;
IEN0 |= 0x80;
}
// Clear flag SPIRXIF
// Enable all interrupts
//---------------------------------------------------------------------------//
Due to the double buffering of the SPI interface,
an SPI TX empty interrupt will be activated as
soon as the data to be transmitted is written into
the SPI interface transmit buffer. If data is
subsequently written into the SPI transmit buffer
before the original data has been transmitted,
the TX empty interrupt will only be activated
when the original data has been fully
transmitted.
_________________________________________________________________________________________________
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VMX51C1016
I²C Interface
The VMX51C1016 includes an I²C compatible
communication interface that can be configured
in master or slave mode.
The I2CIRQSTAT register provides the status of
the I²C interface operation and monitors the I²C
bus status.
TABLE 88: (I2CIRQSTAT) I2C INTERRUPT STATUS - SFR DDH
7
6
5
4
I2CGOTSTOP
I2CNOACK
I2CSDA
I2CDATACK
I²C Control Registers
The I2CRXTX SFR register is used to retrieve
and transmit data on the I²C interface.
3
2
1
0
I2CIDLE
I2CRXOV
I2CRXAV
I2CTXEMP
Bit
Mnemonic
7
I2CSGOTSTOP
6
I2CNOACK
T ABLE86: (I2CRXTX) I2C DATA BUFFER - SFR DEH
7
6
Bit
5
4
3
I2CRXTX [7:0]
Mnemonic
7:0
2
1
0
Function
I2C Data Receiver / Transmitter
buffer
I2CTX[7:0]
The I2CCONFIG register serves to configure the
operation of the VMX51C1016 I²C interface.
The following table describes the I2CCONFIG
register bits:
TABLE 87: (I2CCONFIG) I2C CONFIGURATION - SFR DA H
7
6
5
4
I2CMASKID
I2CRXOVIE
I2CRXDAVIE
I2CTXEMPIE
3
2
1
0
I2CMANACK
I2CACKMODE
I2CMSTOP
I2CMASTER
Bit
Mnemonic
7
I2CMASKID
6
I2CRXOVIE
5
I2CRXDAVIE
4
I2CTXEMPIE
3
I2CMANACK
2
I2CACKMODE
1
I2CMSTOP
0
I2CMASTER
Function
This is used to mask the chip ID
when you have only two devices.
Therefore in a transaction, rather
that receiving the chip ID first,
you will receive the first packet of
data.
I2C Receiver overrun interrupt
enable
I2C Receiver available interrupt
enable
I2C Transmitter empty interrupt
enable
1= Manual acknowledge line
goes to 0
0= Manual acknowledge line
goes to 1
Used only with Master Rx, Master
Tx, and Slave Rx.
1= Manual Acknowledge on
0= Manual Acknowledge off
I2C Master receiver stops at next
acknowledge phase. (read during
data phase)
I2C Master mode enable
1= I2C interface is Master
0= I2C interface is Slave
Function
This means that the slave
has received a stop (this bit is
read only). Reset only when
the master begins a new
transmission.
Flag that indicates that no
acknowledge has been
received. Is reset at the start
of the next transaction
Value of SDA line.
5
I2CSDA
4
I2CDATACK
Data acknowledge phase.
3
2
1
0
I2CIDLE
I2CRXOV
I2CRXAV
I2CTXEMP
Indicates that I2C is idle
I2C Receiver overrun
I2C Receiver available
I2C Transmitter empty
The I2CCHIPID register holds the VMX51C1016
I²C interface ID as well as the status bit that
indicates whether the last byte monitored on the
I²C interface was destined for the VMX51C1016
or not.
The reset value of this register is 0x42,
corresponding to an I²C chip ID of 0x21. The
chip ID value of the VMX51C1016 can be
dynamically changed by writing the desired ID
value into the I2CCHIPID register (see the
following table).
TABLE 89: (I2CCHIPID) I2C C HIP ID - SFR DCH
7
6
5
4
3
I2CID [6:0]
Bit
7:1
Mnemonic
I2CID[6:0]
0
I2WID
2
1
0
I2CWID
Function
The value of this chip’s ID
Read only and is used only in
slave mode
0: The ID received corresponds
to the I2CID
1: The ID received does not
correspond to the I2CID
The I2WID bit is “read only”, is used only in
slave mode and is an indicator of whether the
transaction is targeted to the VMX51C1016
device.
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VMX51C1016
I²C Clock Speed
I²C Interface Interrupts
The
VMX51C1016’s
I²C
interface
communication speed is fully configurable. This
provides the ability to adjust the speed to
various I²C bus configurations.
The I²C interface has a dedicated interrupt
vector located at address 0x5B. Three flags (see
below) share the I²C interrupt vector and can be
used to monitor the I²C interface status making it
possible to activate the I²C interrupt.
Control of the I²C interface communication
speed is enabled via the I2CCLKCTRL register.
The following formula is used to calculate the I2C
clock frequency in master mode:
I2CTXEMP:
I2CRXAV:
I2CRXOV:
I2C Clk =
________fosc__________
[8 x (I2CCLKCTRL)]
The table below provides I²C clock (on SCL pin)
speeds for various settings of the I2CCLKCTRL
register when using a 14.75MHz crystal
oscillator to the drive the VMX51C1016.
I2CCLKCTRL Value
01h
03h
07h
13h
27h
C7h
I2C Clock (SCL Value)
920KHz
461KHz
230KHz
92.1KHz
46KHz
9.2KHz
When the I2C interface is configured for slave
mode, the I2CCLKCTRL is not used.
TABLE 90: (I2CCLKCTRL) I2C CLOCK CONTROL - SFR DBH
7
Bit
7:0
6
5
4
3
2
I2CCLKCTRL [7:0]
Mnemonic
I2CCLKCTRL
1
Function
I2C Clock speed control
0
Is set to 1 when the transmit buffer is
empty
Is set to 1 when data byte reception is
completed
Is set to 1 if a new byte reception is
completed before the previous data in
the reception buffer is read, resulting in
a data overrun
These flags can all trigger an I²C interrupt if their
corresponding bit in the I2CCONFIG register is
set to one.1
In the case where more than one of these flags
can activate an I²C interrupt, the interrupt
service routine is left to determine which
condition generated the interrupt.
Note that the I2CRXAV, I2CTXEMP and
I2CRXOV flags can still be polled if their
corresponding interrupt enable flags are cleared.
Therefore, they can still be used to monitor the
status.
Master I²C Operation
In master mode, the VMX51C1016 I²C interface
controls the I²C bus transfers. In order to
configure the I²C interface as a master, the
I2CMASTER bit of the I2CCONFIG register
must be set to 1.
Once the I²C interface is configured, sending
data to a slave device connected to the bus is
done by writing the data into the I2CRXTX
register.
Before sending data to a slave device, a byte
containing the target device’s chip ID and a
read/write bit must be sent to it.
A master mode data read is triggered by reading
the I2CRXAV (bit 1) of the I2CIRQSTAT
register. The data is present on the I2CRXTX
register when the I2CRXAV bit is set.
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VMX51C1016
Reading the value of the I2CRXTX register
resets the I2CRXAV bit. Once started, the I²C
byte read process will continue until the master
generates a STOP condition.
When the I²C interface is configured as a
master, setting the I2CMSTOP bit of the
I2CCONFIG register to 1 will result in the
interface generating a STOP condition after the
reception of the next byte.
In master mode, it is possible to manually
control the operation of the acknowledged timing
when receiving data. To do this, the
I2CMANACK bit of the I2CCONFIG register
must be set to 1. Once you have received a
byte, you can manually control the acknowledge
level by clearing or setting the I2CMANACK bit.
Note:
The VMX51C1016 I²C interface is not
compatible with I²C the multi-master
mode.
Errata:
The VMX1016 I2C interface has a critical timing
issue when the device is configured as a slave
and transmits multiple data bytes. Single byte
transmission in slave mode is not affected.
The condition arises if the master device
releases the SDA line at the same time it brings
the SCL line low for the acknowledge phase.
In order for the VMX1016 I2C slave transmission
to work properly for multiple bytes, the master
device MUST release the SDA line AFTER the
SCL negative edge.
For this reason it is not possible to have a
VMX1016 device configured as an I2C master
and VMX1016 devices configured as I2C slaves
on the same I2C bus, unless data transmitted
from VMX1016 I2C slaves to the I²C master is
done one byte at a time.
Slave I2C Operation
The VMX51C1016 I²C interface can be
configured as a slave by clearing the
I2CMASTER bit of the I2CCONFIG register.
In slave mode, the VMX51C1016 has no control
over the rate or the timing of the data exchange
that occurs on the I²C bus. Therefore, in slave
mode it is preferable to manage the transactions
using the I²C interrupts.
The I2CMASKID bit, when set, will configure to
the slave device mask the received ID byte and
receive the data directly. This is useful when
only two devices are present on the I²C bus.
Note:
When
the
VMX51C1016
starts
transmitting data in slave mode, it will
continually transmit the value present in
the I²C transmit register as long as the
master provides the clock signal or until
the master device generates a STOP
condition
_________________________________________________________________________________________________
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VMX51C1016
I²C EEPROM Interface Example
Program
The following provides an example program
using the VMX51C1016 interface to perform
read and write operations to an externally
connected EEPROM device.
#pragma SMALL
#include <vmixreg.h>
// --- Function prototypes
unsigned char eeread(idata unsigned char, idata unsigned char);
void eewrite(idata unsigned char, idata unsigned char, unsigned char);
// - Global variables
idata unsigned char
sbit
sbit
sbit
sbit
I2CCONFIG = 0x03;
//I2C MASTER MODE NO INTERRUPT
I2CRXTX = 0xA8;
//SEND 24LC64 ADRS + write COMMAND
USERFLAGS = 0x00;
while(!I2C_TX_EMPTY){USERFLAGS = I2CIRQSTAT;}
I2CRXTX = adrsh;
//SEND 24LC64 ADRSH
USERFLAGS = 0x00;
while(!I2C_TX_EMPTY){USERFLAGS = I2CIRQSTAT;}
I2CRXTX = adrsl;
//SEND 24LC64 ADRSL
USERFLAGS = 0x00;
while(!I2C_TX_EMPTY){USERFLAGS = I2CIRQSTAT;}
USERFLAGS = 0x00;
//wait for I2C interface to be idle
while(!I2C_IS_IDLE){USERFLAGS = I2CIRQSTAT;}
irqcptr=0x00;
I2C_TX_EMPTY = USERFLAGS^0;
I2C_RX_AVAIL = USERFLAGS^1;
I2C_IS_IDLE = USERFLAGS^3;
I2C_NO_ACK = USERFLAGS^6;
I2CCONFIG &= 0xFD;
I2CCONFIG |= 0x02;
I2CRXTX = 0xA9;
//-------------------------------------------------------------------------------//
//
MAIN FUNCTION
//
//------------------------------------------------------------------------------//
void main (void){
unsigned char x=0;
DIGPWREN = 0x13;
//Enable the I2C peripheral
//*** configure I2C Speed.
I2CCLKCTRL = 0x013;
//…To about 100KHZ...
//*** Configure the interrupts
IEN0 |= 0x81;
//Enable Ext INT0 interrupt + main
//*** infinite loop waiting for ext IRQ
while(1){
};
}// End of main()...
//-------------------------------------------------------------------------------//
// EXT INT0 interrupt
//
// When the External interrupt 0 is triggered read and write
// operations are performed on the EEPROM
//-------------------------------------------------------------------------------//
void int_ext_0 (void) interrupt 0 {
// Local variables declaration
idata unsigned char eedata;
idata unsigned char adrsh =0;
idata unsigned char adrsl =0;
idata int adrs =0;
//
IEN0 &= 0x7F;
//disable ext0 interrupt
//(Masked for debugger compatibility)
//Write irqcptr into the EEPROM at adrs 0x0100
eewrite( 0x01,0x00,irqcptr);
irqcptr = irqcptr + 1;
//Increment the Interrupt counter
//Perform an EEPROM read at address 0x100
eedata = eeread(0x01, 0x00);
//
delay1ms(100);
IEN0 = 0x81;
//Debo delay for the switch on INT0
// enable all interrupts + int_0 (Removed
//for debugger compatibility)
//set Master Rx Stop, only 1 byte to receive
// Chip ID read
USERFLAGS = 0x00;
while(!I2C_RX_AVAIL){USERFLAGS = I2CIRQSTAT;}
readvalue = I2CRXTX;
USERFLAGS = 0x00;
while(!I2C_IS_IDLE){USERFLAGS = I2CIRQSTAT;}
//Wait for I2C IDLE
return
readvalue;
}//End of EEREAD
//----------------------------------------------------------------//
// EEWRITE - EEPROM Random WRITE //
//----------------------------------------------------------------//
void eewrite(idata unsigned char adrsh, idata unsigned char adrsl, unsigned char
eedata)
{
idata unsigned char x;
I2CCONFIG = 0x01;
//I2C MASTER MODE NO INTERRUPT
I2CRXTX = 0xA8;
//SEND EEPROM ADRS + READ
//COMMAND
USERFLAGS = 0x00;
while(!I2C_TX_EMPTY){USERFLAGS = I2CIRQSTA T;}
I2CRXTX = adrsh;
//SEND ADRSH
USERFLAGS = 0x00;
while(!I2C_TX_EMPTY){USERFLAGS = I2CIRQSTAT;}
I2CRXTX = adrsl;
//SEND ADRSL
USERFLAGS = 0x00;
while(!I2C_TX_EMPTY){USERFLAGS = I2CIRQSTAT;}
I2CRXTX = eedata;
//SEND 24LC64 DATA and wait
//for I2C bus IDLE
USERFLAGS = 0x00;
while(!I2C_IS_IDLE){USERFLAGS = I2CIRQSTAT;}
///--Wait Write operation to end
I2CCONFIG = 0x01;
//I2C Master Mode no Interrupt
do{
I2CRXTX = 0xA8;
//Send 24LC64 Adrs +read Command
USERFLAGS = 0x00;
while(!I2C_TX_EMPTY){USERFLAGS = I2CIRQSTAT;}
USERFLAGS = I2CIRQSTAT;
}while(I2C_NO_ACK);
delay1ms(5);
//5ms delay for EEPROM write
}// End of EEPROM Write
}// end of EXT INT 0
//---------------------------------------------------------------------------------//
//
INDIVIDUALS FUNCTIONS
//
//--------------------------------------------------------------------------------//
//-----------------------------------------------------------------//
// EEREAD - EEPROM Random Read //
//----------------------------------------------------------------//
unsigned char eeread(idata unsigned char adrsh, idata unsigned char adrsl)
{
idata unsigned char x=0;
idata unsigned char readvalue=0;
_________________________________________________________________________________________________
page 54 of 76
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VMX51C1016
The VMX51C1016 implements a complete
single chip acquisition system by integrating the
following analog peripherals:
Both the bandgap and the PGA are calibrated
during production and their associated
calibration registers are automatically loaded
with the appropriate calibration vectors when the
device is reset.
12-bit, A/D converter with 5 external
inputs. The ADC conversion rate is
programmable up to 10KHz
Internal bandgap reference and PGA
Digital switch
The bandgap and PGA calibration vectors are
stored into the BGAPCAL and PGACAL SFR
registers when a reset occurs. It is possible for
the user program to overwrite the contents of
these registers. .
Analog Signal Path
o
o
o
TABLE 91: (BGAPCAL) BAND-GAP C ALIBRATION VECTOR REGISTER - SFR B3H
The following figure provides a block diagram of
the VMX51C1016 analog peripherals and their
connections.
7
6
Bit
7:0
5
Mnemonic
BGAPCAL
4
3
BGAPCAL [7:0]
2
1
0
Function
Band-gap data calibration
FIGURE 35: ANALOG S IGNAL PATH OF THE VMX51C1016
TABLE 92: (PGACAL) PGA CALIBRATION VECTOR REGISTER - SFR B4H
BANDGAP
7
PGA
AIN0
AIN1
AIN2
AIN3
VBGAP
Reserved
unused
unused
XTVREF
ADCTA
AIN3
Reserved
Reserved
Total of 5 A/D inputs
AIN1
Reserved
Bit
7:0
5
Mnemonic
PGACAL
4
3
PGACAL [7:0]
2
1
0
Function
8 MSBs of PGA Calibration
Vector (LSBit is on PGACAL0)
Using the VMX51C1016 Internal
Reference
AIN0
AIN2
6
A/D
ADCTA
SW1
The on-chip calibrated bandgap or the external
reference provides the reference for the ADC.
Analog Peripherals Power Control
Selection of the internal/external reference, the
ADC control and their respective power downs
are controlled via the ANALOGPWREN SFR
registers.
The configuration and setup up of the
VMX51C1016 internal reference is achieved by
setting bits 0 and 1 of the ANALOGPWREN
register to 1. This powers-on the bandgap and
the PGA, respectively.
Use of the internal reference requires the
addition of two external tank capacitors on the
XTVREF pin. These capacitors consist of one
4.7uF to 10uF tantalum capacitor in parallel with
one 0.1uF ceramic capacitor.
The next figure shows the connection of the tank
capacitors to the XTVREF pin.
FIGURE 36: T ANK CAPACITORS CONNECTION TO THE XTVREF PIN
Internal Reference and PGA
The VMX51C1016 provides a temperature
calibrated internal bandgap reference coupled
with a programmable gain amplifier.
The programmable gain amplifier’s role is to
amplify the bandgap output and bring it to 2.7
volts and to provide the drive required for the
ADC reference input.
2.7V
XTVREF
4.7uF
to
10uF
0.1uF
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VMX51C1016
The VMX51C1016 internal reference can also
be used as an external reference,,provided that
the load on the XTVREF pin is kept to a
minimum. The following table shows the typical
affect of loading on the XTVREF voltage.
The VMX51C1016 includes a feature rich and
highly configurable on-chip 12-bit A/D converter.
The A/D conversion data is output as an
unsigned 12-bit binary with 1 LSB = Full
Scale/4096. The following figure describes the
ideal transfer function for the ADC.
FIGURE 37: T ANK CAPACITORS CONNECTION TO THE XTVREF PIN
2.75
XTVREF reference voltage (Volts)
A/D Converter
2.70
FIGURE 39: IDEAL A/D CONVERTER T RANSFER FUNCTION
2.65
0.0
1.0
2.0
3.0
4.0
5.0
OUTPUT
CODE
1111_1111_1111
1111_1111_1110
1111_1111_1101
1111_1111_1100
1 LSB = XTVREF / 4096
Load current on XTVREF (mA)
It is recommended that the external load on the
XTVREF pin to be less than 1mA.
Note: A stabilization delay of more than 1ms
should be provided between the activation of the
bandgap, the PGA and the first A/D conversion.
Using an External Reference
An external reference can be used to drive the
VMX51C1016 ADC instead of the internal
reference.
The external reference voltage source can be
set from 0.5 to 3.5 volts and must provide
sufficient drive to operate the ADC load.
FIGURE 38: EXTERNAL REFERENCE CONNECTION TO THE XTVREF PIN
0000_0000_0011
0000_0000_0010
0000_0000_0001
0000_0000_0000
0V
XTVREF
The A/D converter includes a system that
provides the ability to trigger automatic periodic
conversions of up to 10kHz without processor
intervention.
Once the conversion is complete, the A/D
system can activate an interrupt that can wakeup the processor (assuming it has been put into
idle mode) or automatically throttle the
processor clock to full speed.
The VMX51C1016 ADC can also be configured
to perform conversion on one specific channel or
on four consecutive channels (in round-robin
fashion).
These features make the A/D
adaptable for many applications.
XTVREF
4.7uF
to
10uF
0.1uF
V
converter
The following paragraphs describe the A/D
converter register features.
ADC Data Registers
Warning:
When an external reference source is
applied to the XTVREF pin, it is
mandatory not to power-on the PGA.
The internal bandgap reference should
also remain deactivated.
The ADC data registers hold the ADC
conversion results. The ADCDxLO register(s)
hold the eight least significant bits (LSBs) of the
conversion results, while the ADCDxHI
register(s) hold the four most significant bits
(MSB) of the conversion results.
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VMX51C1016
TABLE 93: (ADCD0LO) ADC CHANNEL 0 DATA REGISTER, LOW BYTE - SFR A6H
Bit
7:0
Mnemonic
ADCD0LO
Function
ADC channel 0 low
setting the corresponding bits of the lower
quartet (AIEN [3:0]) of the INMUXCTRL register
to 1.
TABLE 94: (ADCD0HI) ADC C HANNEL 0 DATA REGISTER, HIGH BYTE - SFR A7H
Bit
3:0
Mnemonic
ADCD0HI
Function
ADC channel 0 high
TABLE 101: (INMUXCTRL) ANALOG INPUT M ULTIPLEXER CONTROL REGISTER SFR B5H
7
-
TABLE 95: (ADCD1LO) ADC CHANNEL 1 DATA REGISTER, LOW BYTE - SFR A9H
7
6
Bit
7:0
5
4
3
2
ADCD1LO [7:0]
Mnemonic
ADCD1LO
1
6
5
4
ADCINSEL [2:0]
6
-
Function
ADC channel 1 low
Bit
3:0
5
-
4
-
Mnemonic
ADCD1HI
3
2
1
ADCD1HI [3:0]
Bit
7
6:4
Mnemonic
ADCINSEL[2:0]
3:0
AINEN[3:0]
0
Function
ADC channel 1 high
TABLE 97: (ADC2LO) ADC CHANNEL 2 DATA REGISTER, LOW BYTE - SFR ABH
7
6
Bit
7:0
5
4
3
ADCD2LO [7:0]
Mnemonic
ADCD2LO
2
1
0
Function
ADC channel 2 low
TABLE 98: (ADCD2HI) ADC C HANNEL 2 DATA REGISTER, HIGH BYTE - SFR ACH
7
-
6
-
Bit
7:4
3:0
5
-
4
-
Mnemonic
ADCD2HI
3
2
1
ADCD2HI [3:0]
0
Function
ADC channel 2 high
6
Bit
7:0
5
4
3
ADCD3LO [7:0]
Mnemonic
ADCD3LO
2
1
Bit
7:4
3:0
6
-
5
Mnemonic
ADCD3HI
3
ADC Input Select
000 - AIN0
001 - AIN1
010 - AIN2
011 - AIN3
111 - ADCTA
Analog Input Enable
The upper four bits of the INMUXCTRL register
are used to define the channel on which the
conversion will take place when the ADC is set
to perform the conversion on one specific
channel.
ADC Control Register
The ADCCTRL register is the main register used
for control and operation of the ADC operating
mode.
2
1
ADCD3HI [3:0]
7
ADCIRQCLR
3
ADCIE
Function
ADC channel 3 low
4
-
Function
6
XVREFCAP
5
1
4
ADCIRQ
0
TABLE 100: (ADCD3HI) ADC C HANNEL 3 DATA REGISTER, HIGH BYTE - SFR AEH
7
-
0
TABLE 102: (ADCCTRL) ADC CONTROL REGISTER - SFR A2 H
TABLE 99: (ADCD3LO) ADC CHANNEL 3 DATA REGISTER, LOW BYTE - SFR ADH
7
2
1
AINEN [3:0]
0
TABLE 96: (ADCD1HI) ADC C HANNEL 1 DATA REGISTER, HIGH BYTE - SFR AAH
7
-
3
0
Function
ADC channel 3 high
2
ONECHAN
Bit
7
Mnemonic
ADCIRQCLR
6
5
4
XVREFCAP
Reserved = 1
ADCIRQ
3
2
ADCIE
ONECHAN
1
CONT
0
ONESHOT
ADC Input Selection
A/D conversions can be performed on a single
channel, sequentially on the four lower channels
or sequentially on the four upper channels of the
ADC input multiplexer.
1
CONT
0
ONESHOT
Function
ADC interrupt clear
Writing 1 Clears interrupt
Always keep this bit at 1
Keep this bit = 1
Read ADC Interrupt Flag
Write 1 generate ADC IRQ
ADC interrupt enable
1 = Conversion is performed on
one channel
Specified ADCINSEL
0 = Conversion is performed on
4 ADC channels
1 = Enable ADC continuous
conversion
1 = Force a single conversion
on 1 or 4 channels
An input buffer is present on each of the four
external ADC inputs (ADIN0 to AIN3).
ADC Continuous / One Shot Conversion
These buffers must be enabled before a
conversion can take place on the ADC AIN0AIN3 inputs. These buffers are enabled by
The CONT bit sets the ADC conversion mode.
When the CONT bit is set to 1, the ADC will
implement continuous conversions at a rate
defined by the conversion rate register.
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VMX51C1016
When the CONT bit is set to 0, the A/D operates
in “one shot” mode, initiating a conversion when
the ONESHOT bit of the ADCCONTRL register
is set.
ADC One Channel/Four Channel Conversion
The VMX51C1016’s ADC includes a feature that
renders it possible to perform a conversion on
one specific channel or on four consecutive
channels.
This feature minimizes the load on the processor
when reading more than one ADC input is
required.
The ONECHAN bit of the ADCCTRL register
controls this feature. When the ONECHAN is set
to 1, the conversion will take place on the
channel selected by the INMUXCTRL register.
Once the conversion is complete, the result will
be placed into the ADCD0LO and ADCD0HI
registers
When the ONECHAN bit is set to 0, the
conversion, once triggered, will be done
sequentially on four channels and the
conversion results will be placed into the
ADCDxLO and ADCDxHI registers.
Bit 6 of the INMUXCTRL register controls
whether the conversion will take place on the
four upper channels of the input multiplexer or
on the four lower channels.
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VMX51C1016
ADC Clock Source Configuration
ADC Conversion Rate Configuration
The A/D converter derives its clock source from
the main VMX51C1016 clock. .The frequency of
the ADC clock should be set between 250kHz
and 1.25MHz.
The VMX51C1016’s ADC conversion rate, when
configured in continuous mode, is defined by the
value present in a 24-bit A/D conversion rate
register that serves as the time base for
triggering the ADC conversion process.
Configuration of the ADC clock source
frequency is done by adjusting the value of the
ADCCLKDIV register. The following equation is
used to calculate the ADC reference clock.
The following equation is used to calculate the
value of the conversion rate.
Conversion Rate Equation:
ADC Clock Reference Equation:
Conversion rate registers value (24-bit) =
ADC Clk ref =
f OSC
4x (ADCCDIV +1)
The ADC conversion requires 111 ADC clock
cycles to perform the conversion on one
channel.
The following table provides recommended
ADCCLKDIV register values versus conversion
rate. The numbers given are conservative
figures and derived from a 14.74MHz clock.
ADCCLKDIV
0x02
0x03
0x05
0x07
0x08
0x09
0x0B
0x0D, 0x0E, 0x0F
Maximum Conv. Rate*
10500 Hz
8000 Hz
5000 Hz
4000 Hz
3500 Hz
3200 Hz
2500 Hz
2200 Hz
* The maximum conversion rate is for the single
channel condition. If the conversion is performed
on four channels, divide the maximum
conversion rate by 4. For example, performing
the conversion at 25KHz on four channels, the
ADCCLKDIV register should be set to 0x02 (4 x
2500Hz = 10KHz).
fOSC
Conv_Rate
The conversion rate register is accessible using
three SFR registers as follows:
TABLE 104: (ADCCONVRLOW) ADC CONVERSION R ATE REGISTER LOW BYTE SFR A3H
Bit
7:0
Mnemonic
ADCCONVRLOW
Function
Conversion rate low byte
TABLE 105: (ADCCONVERMED) ADC CONVERSION R ATE REGISTER MED BYTE SFR A4H
Bit
7:0
Mnemonic
ADCCONVRMED
Function
Conversion rate medium byte
TABLE 106: (ADCCONVRHIGH) ADC CONVERSION RATE REGISTER HIGH BYTE SFR A5H
Bit
7:0
Mnemonic
ADCCONVRHIGH
Function
Conversion rate high byte
The following table provides examples of typical
values versus conversion rate.
Conversion
Rate
1Hz
10Hz
100Hz
1kHz
2.5kHz
5kHz
8kHz
10kHz
Fosc= 14.74MHz
E10000h
168000h
024000h
003999h
00170Ah
000B85h
000733h
0005C2h
TABLE 103: (ADCCLKDIV) ADC CLOCK DIVISION CONTROL REGISTER - SFR 95 H
7
Bit
7:0
6
5
4
3
2
ADCCLKDIV [7:0]
Mnemonic
ADCCLKDIV[7:0]
1
0
Function
ADC clock divider
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VMX51C1016
ADC Status Register
The ADC shares interrupt vector 0x6B with the
interrupt on Port 1 change and Compare and
Capture Unit 3. To enable the ADC interrupt, the
ADCIE bit of the ADCCTRL register must be set.
Before or at the same time this bit is set, the
ADCIRQCLR and ADCIRQ bits must be cleared.
The ADCPCIE bit of the IEN1 register must also
be set, as well as the EA bit of the IEN0 register.
Once the ADC interrupt occurs, the ADC
interrupt must be cleared by writing a ‘1’ into the
ADCINTCLR bit of the ADCCTRL register. The
ADCIF flag in the IRCON register must also be
cleared.
A/D Converter Use Example
The following provides example code for the A/D
converter. The first section of the code is the
interrupt setup/module configuration, whereas
the second section is the interrupt function itself.
//*** Configure the interrupts
IEN0 |= 0x80;
//enable main interrupt
IEN1 |= 0x020;
//Enable ADC Interrupt
while(1);
//Infinite loop waiting ADC interrupts
}// End of main()...
//-----------------------------------------------------------------------//
//
ADC INTERRUPT ROUTINE
//-----------------------------------------------------------------------//
void int_adc (void) interrupt 13 {
idata int value = 0;
IEN0 &= 0x7F;
ADCCTRL |=0x80;
//disable ext0 interrupts
//Clear ADC interrupt
// Read ADC channel 0
value = ADCD0HI;
value = valeur*256;
value = valeur + ADCD0LO;
(…)
// Read ADC channel 3
value = ADCD3HI;
value = valeur*256;
value = valeur + ADCD3LO;
(…)
IRCON &= 0xDF;
ADCCTRL |=0xFA;
IEN0 |= 0x80;
//Clear adc irq flag
//prepare adc for next acquisition
// enable all interrupts
}// End of ADC IRQ
(…)
Warning:
When using the ADC, make sure the
output multiplexer controlled by the
TAEN bit of the ANALOGPWREN
register (92h) is powered-down at all
times, otherwise, the signal present on
the ISRCOUT can be routed back to the
selected ADC input, causing conversion
errors.
Sample C code to setup the A/D converter:
//-----------------------------------------------------------------------//
//
MAIN FUNCTION
//-----------------------------------------------------------------------//
(…)
at 0x0100 void main (void) {
//*** Initialize the Analog Peripherals ***
ANALOGPWREN = 0x07;
//Configure the ADC and Start it
ADCCLKDIV=0x0F;
ADCCONVRLOW=0x00;
ADCCONVRMED=0x40;
ADCCONVRHIGH =0x02;
INMUXCTRL=0x0F;
ADCCTRL=0xEA;
//Enable the following analog
//peripherals: ADC, PGA,
// BGAP. TA = OFF (mandatory)
//SET ADC CLOCK SOURCE
//CONFIGURE CONVERSION RATE
//= 100Hz @ 14.74 MHz
//Enable All ADC External inputs
//buffers and select ADCI0
//Configure the ADC as follow:
//bit 7: =1 ADCIRQ Clear
//Bit 6: =1 XVREFCAP (always)
//Bit 5: =1 (always)
//Bit 4: =0 = ADCIRQ (don’t care)
//Bit 3: =1 = ADC IRQ enable
//Bit 2: =0 conversion on 4
//channels
//Bit 1: =1 Continuous conversion
//Bit 0: =0 No single shot mode
TABLE 107: (PGACAL0) PGA CALIBRATION BIT 0 VALUE - SFR BC H
7
PGACAL0
Bit
7
6:0
6
Mnemonic
PGACAL0
--
5
4
3
2
Reserved
1
Function
Bit 0 of PGACAL
Reserved
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0
VMX51C1016
Digitally Controlled Switches
Analog Output Multiplexer
On the VMX51C1016 includes a digital switch
composed of four sub-switches connected in
parallel. These sub-switches can be individually
controlled by writing to the SFR register at B7h.
The VMX51C1020’s analog output multiplexer is
used for production test purposes and provides
access to internal test points of the analog signal
path. It can however, be used in applications,
but due to its high intrinsic impedance, care
must be taken with respect to loading.
FIGURE 42: SWITCH FUNCTIONAL DIAGRAM
SW1A
SW1B
We recommend not accessing this SFR register.
TABLE 109: (OUTMUXCTRL) A NALOG OUTPUT M ULTIPLEXER CONTROL REGISTER
- SFR B6H
7
x
x x
x
Bit
7:3
2:0
sw1d sw1c sw1b sw1a
SWITCHCTRL register
The “ON” switch resistance is between 50 and
100 Ohms, depending on the number of subswitches being used. If, for example, one subswitch is closed, the switch resistance will be
about 100 Ohms, and if all four switches are
closed, the switch resistance will go down to
about 50 Ohms.
6
-
5
-
4
-
Mnemonic
Unused
TAOUTSEL[2:0]
3
-
2
1
0
TAOUTSEL [2:0]
Function
Unused
Signal output on TA
000 – AIN0
001 – AIN1
010 – AIN2
011 – AIN3
100 – VBGAP
101 – reserved
110 – unused
111 – unused
TABLE 108: (SWITCHCTRL) USER SWITCHES CONTROL REGISTERS - SFR B7H
7
6
5
4
Not Used but implemented
Bit
Mnemonic
7:4
User Flags
3:0
SWITCH1[3:0]
3
2
1
SWTCH1 [3:0]
0
Function
Not used but implemented bits
Can be used as general
purpose storage
Switch 1 control (composed of 4
individual switches each bit
controlled)
The upper 4 bits of the SWITCHCTRL register
are not used but they are implemented. They
can be used as general purpose flags.
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VMX51C1016
VMX51C1016 Interrupts
The VMX51C1016 is a highly integrated device
incorporating a vast number of peripherals for
which a comprehensive set of 24 interrupt
sources sharing 11 interrupt vectors is available
to ease system program development. Most of
the VMX51C1016 peripherals can generate an
interrupt, providing feedback to the MCU core
that an event has occurred or a task has been
completed.
The following are key VMX51C1016 interrupt
features:
o
o
o
o
Each
digital
peripheral
on
the
VMX51C1016 has an interrupt channel
The SPI, UARTs and I²C all have event
specific flag bits
When the processor is in IDLE mode, an
interrupt may be used to wake it up
The processor can run at full speed
during interrupt routines
The following table summarizes the interrupt
sources, natural priority and associated interrupt
vector addresses on the VMX51C1016.
TABLE 110: INTERRUPT SOURCES AND NATURAL PRIORITY
Interrupt
Reserved
INT0
UART1
TIMER 0
SPI TX Empty
Reserved
SPI RX & SPI RX OVERRUN
/ COMPINT0
TIMER 1
I2C (Tx, Rx, Rx Overrun)
/ COMPINT1
UART0
MULT/ACCU 32bit Overflow /
COMPINT2
TIMER 2: T2 Overflow, T2EX
ADC and interrupt on Port 1
change (8 int.) / COMPINT3
Interrupt Vector
0E43h
0003h
0083h
000Bh
004Bh
0013h
Interrupt Enable Registers
The following tables describe the interrupt
enable registers and their associated bit
functions:
TABLE 111: (IEN0) INTERRUPT E NABLE REGISTER 0 - SFR A8H
7
EA
6
WDT
5
T2IE
4
S0IE
3
T1IE
2
0
1
T0IE
0
INT0IE
Bit
7
Mnemonic
EA
6
WDT
5
T2IE
4
S0IE
3
T1IE
2
1
Reserved
T0IE
0
INT0IE
Function
General Interrupt control
0 = Disable all Enabled interrupts
1 = Authorize all Enabled interrupts
Watch Dog timer refresh flag. This bit
is used to initiate a refresh of the
watchdog timer. In order to prevent
an unintentional reset, the watchdog
timer the user must set this bit
directly before SWDT.
Timer 2 Overflow / external Reload
interrupt
0 = Disable
1 = Enable
Uart0 interrupt.
0 = Disable
1 = Enable
Timer 1 overflow interrupt
0 = Disable
1 = Enable
Always keep this bit to 0
Timer 0 overflow interrupt
0 = Disable
1 = Enable
External Interrupt 0
0 = Disable
1 = Enable
0053h
001Bh
005Bh
0023h
0063h
002Bh
006Bh
It is also possible to program the interrupts to
wake-up the processor from an IDLE condition
or force its clock to throttle up to full speed when
an interrupt condition occurs.
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VMX51C1016
T ABLE 112: (IEN1) INTERRUPT E NABLE 1 REGISTER -SFR E8H
7
T2EXIE
6
SWDT
5
ADCPCIE
4
MACOVIE
3
I2CIE
2
SPIRXOVIE
1
SPITEIE
0
reserved
Bit
7
Mnemonic
T2EXIE
6
SWDT
5
ADCPCIE
4
MACOVIE
3
I2CIE
2
SPIRXOVIE
1
SPITEIE
0
Function
T2EX interrupt Enable
0 = Disable
1 = Enable
Watch Dog timer start/refresh flag.
Set to activate/refresh the watchdog
timer. When directly set after setting
WDT, a watchdog timer refresh is
performed. Bit SWDT is reset.
ADC and Port change interrupt
0 = Disable
1 = Enable
MULT/ACCU Overflow 32 bits
interrupt
0 = Disable
1 = Enable
I2C Interrupt
0 = Disable
1 = Enable
SPI Rx avail + Overrun
0 = Disable
1 = Enable
SPI Tx Empty interrupt
0 = Disable
1 = Enable
reserved
Bit
7-1
0
6
-
The SPI RX (and RXOV), I²C, MULT/ACCU and
ADC interrupts are shared with the four Timer 2
compare and capture unit interrupts.
When the compare and capture units of Timer 2
are configured in compare mode via the CCEN
register, the compare and capture unit takes
control of one interrupt vector as shown in the
next figure.
FIGURE 43: COMPARE CAPTURE INTERRUPT STRUCUTRE
COMPINT0
Interrupt
1
SPI Rx &
RxOV INT
0
5
-
Mnemonic
S1IE
4
-
3
-
2
-
1
-
Function
UART 1 Interrupt
0 = Disable UART 1 Interrupt
1 = Enable UART 1 Interrupt
0
S1IE
Interrupt Vector
0053h
CCEN(1,0) = 1,0
COMPINT1
Interrupt
1
I2C INT
0
Interrupt Vector
005Bh
CCEN(3,2) = 1,0
COMPINT2
Interrupt
1
MAC
Overflow INT
Interrupt Vector
0063h
0
CCEN(5,4) = 1,0
COMPINT3
Interrupt
TABLE 113: (IEN2) INTERRUPT E NABLE 2 REGISTER - SFR 9AH
7
-
Timer 2 Compare Mode Impact on
Interrupts
1
ADC & Port
Change INT
Interrupt Vector
006Bh
0
CCEN(7,6) = 1,0
The impact of this is that the corresponding
peripheral interrupt, if enabled, will be blocked.
The output signal from the comparison module
will be routed to the interrupt system and the
control lines will be dedicated to the compare
and capture unit.
This interrupt control “take over” is specific to
each individual compare and capture unit. For
example if Compare and Capture Unit 2 is
configured to generate a PWM signal on P1.2,
the MULT/ACCU overflow interrupt, if enabled,
will be dedicated to Compare and Capture Unit 2
and the SPI, I²C and ADC interrupts won’t be
affected.
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VMX51C1016
Interrupt Status Flags
TABLE 115: (IP0) INTERRUPT PRIORITY REGISTER 0 - SFR B8H
The IRCON register is used to identify the
source of an interrupt. Before exiting the
interrupt service routine, the IRCON register bit
that corresponds with the serviced interrupt
should be cleared.
7
UF8
6
WDTSTAT
Bit
7
6
Mnemonic
UF8
WDTSTAT
4
MACIF
5
IP0.5
0
Reserved
4
3
2
IP0.4
IP0.3
IP0.2
1
IP0.1
0
IP0.0
TABLE 114: (IRCON) INTERRUPT REQUEST CONTROL REGISTER - SFR 91H
7
T2EXIF
6
TF2IF
3
I2CIF
2
SPIRXIF
Bit
7
Mnemonic
T2EXIF
6
5
TF2IF
ADCIF /
COMPINT3
4
MACIF /
COMPINT2
I2CIF /
COMPINT1
SPIRXIF /
COMPINT0
SPITXIF
Reserved
3
2
1
0
5
ADCIF
1
SPITXIF
Function
Timer 2 external reload flag
This bit informs the user
whether an interrupt has been
generated from T2EX, if the
T2EXIE is enabled.
Timer 2 overflow flag
A/D converter interrupt request
flag/ port 0 change.
/ COMPINT3
MULT/ACCU unit interrupt
request flag / COMPINT2
2
I C interrupt request flag
/ COMPINT1
RX available flag SPI + RX
Overrun / / COMPINT0
TX empty flag SPI
Reserved
Interrupt Priority Register
All of the VMX51C1016’s interrupt sources are
combined into groups with four levels of priority.
These groups can be programmed individually
to one of the four priority levels: from Level 0 to
Level 3, with Level 3 being the highest priority.
The IP0 and IP1 registers serve to define the
specific priority of each of the interrupt groups.
By default, when the IP0 and IP1 registers are at
reset state 00h, the natural priority order of the
interrupts described above is in force.
5
4
3
2
IP0 [5:0]
1
0
Function
User Flag bit
Watch Dog Timer status flag. Set to 1
by hardware when the Watch Dog
Timer overflows. Must be cleared
manually
Port1
Timer 2
ADC
Change
UART0
MULT/ACCU
Timer 1
I2C
SPI RX
available
Timer 0
SPI TX
Interrupt
Empty
External
External
UART1
INT0
INT 0
Table 116: (IP1) Interrupt Priority Register 1 - SFR B9h
7
6
5
4
3
2
1
IP1 [5:0]
Bit
7
6
Mnemonic
-
5
IP1.5
4
3
2
IP1.4
IP1.3
IP1.2
UART0
Timer 1
1
IP1.1
0
IP1.0
Timer 0
Interrupt
External
INT0
0
Function
-
Timer 2
-
Port1
Change
UART1
ADC
MULT/ACCU
I2C
SPI RX
available
SPI TX
Empty
External
INT 0
Configuring the IP0 and IP1 registers makes it
possible to change the priority order of the
peripheral interrupts in order to give higher
priority to a specified interrupt that belongs to a
specified group.
TABLE 117: INTERRUPT GROUPS
Bit
IP1.5, IP0.5
Interrupt Group
Timer 2
IP1.4, IP0.4
IP1.3, IP0.3
IP1.2, IP0.2
UART0
Timer 1
IP1.1, IP0.1
Timer 0
Interrupt
External
INT0
IP1.0, IP0.0
-
Port1
Change
UART1
ADC
MULT/ACCU
I2C
SPI RX
available
SPI TX
Empty
External
INT 0
_________________________________________________________________________________________________
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VMX51C1016
The respective values of the IP1.x and IP0.x bits
define the priority level of the interrupt group vs.
the other interrupt groups as follows:
TABLE 118: INTERRUPT PRIORITY LEVEL
IP1.x
0
0
1
1
IP0.x
0
1
0
1
Priority Level
Level 0 (Low)
Level 1
Level 2
Level 3 (High)
The WDTSTAT bit of the IP0 register is the
watchdog status flag, which is set to 1 by the
hardware whenever a watchdog timer overflow
occurs. This bit must be cleared manually.
Finally, bit 7 of the IP0 register can be used as a
general purpose user flag.
_________________________________________________________________________________________________
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VMX51C1016
Setting up INT0 Interrupts
INT0 example
The IT0 bit of the TCON register defines
whether external interrupt 0 will be edge or level
triggered.
The following provides example code for
interrupt setup and module configuration:
When an interrupt condition occurs on INT0, the
associated interrupt flag IE0 will be set. The
interrupt flag is automatically cleared when the
interrupt is serviced.
//--------------------------------------------------------------------------// Sample C code to setup INT0
//--------------------------------------------------------------------------#pragma TINY
#include <vmixreg.h>
at 0x0100 void main (void) {
// INT0 Config
TCON |= 0x01; //Interrupt on INT0 will be caused by a High->Low
//edge on the pin
TABLE 119: (TCON) TIMER 0, TIMER 1 TIMER/COUNTER CONTROL - SFR 88H
Bit
7
7
6
5
4
TF1
TR1
TF0
TR0
3
2
1
0
--
--
IE0
IT0
Mnemonic
TF1
6
TR1
5
TF0
4
TR0
3
2
1
--IE0
0
IT0
Function
Timer 1 overflow flag set by hardware
when Timer 1 overflows. This flag can be
cleared by software and is automatically
cleared when interrupt is processed.
Timer 1 Run control bit. If cleared Timer 1
stops.
Timer 0 overflows flag set by hardware
when Timer 0 overflows. This flag can be
cleared by software and is automatically
cleared when interrupt is processed.
Timer 0 Run control bit. If cleared timer 0
stops.
Reserved
Reserved
Interrupt 0 edge flag. Set by hardware
when falling edge on external pin INT0 is
observed. Cleared when interrupt is
processed.
Interrupt 0 type control bit. Selects falling
edge or low level on input pin to cause
interrupt.
// Enable INT0 interrupts
IEN0 |= 0x80;
IEN0 |= 0x01;
// Wait for INT0…
do
{
}while(1);
// Enable all interrupts
// Enable interrupt INT0
//Wait for INT0 interrupts
}//end of main function
//--------------------------------------------------------------------------// Interrupt Function
void int_ext_0 (void) interrupt 0
{
IEN0 &= 0x7F;
// Disable all interrupts
/* Put the Interrupt code here*/
IEN0 |= 0x80;
// Enable all interrupts
}
//---------------------------------------------------------------------------
_________________________________________________________________________________________________
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VMX51C1016
UART0 and UART1 Interrupt Example
Interrupt on P1 change
The following program example demonstrates
how to initialize the UART0 and UART1
interrupts.
The VMX51C1016 includes an interrupt on the
port change feature, which is available on the
Port 1 pins of the VMX51C1016.
//------------------------------------------------------------------------------// Sample C code for UART0 and UART1 interrupt example
//------------------------------------------------------------------------------#pragma TINY
#include <vmixreg.h>
// --- function prototypes
void txmit0( unsigned char charact);
void txmit1( unsigned char charact);
void uart1Config(void);
void uart0ws0relcfg(void);
// - Constants definition
sbit UART_TX_EMPTY = USERFLAGS^1;
//--------------------------------------------------------------------------//
MAIN FUNCTION
//--------------------------------------------------------------------------at 0x0100 void main (void) {
This feature is like having eight extra external
interrupt inputs sharing the ADC interrupt vector
at address 006Bhc and can be very useful for
applications such as switches, keypads, etc.
To activate this interrupt, the bits corresponding
to the pins being monitored must be set in the
PORTIRQEN register. The ADCPCIE bit in the
IEN1 register must be set as well as the EA bit
of the IEN0 register.
TABLE 120: (PORTIRQEN) PORT C HANGE IRQ CONFIGURATION - SFR 9FH
7
--
6
--
5
--
4
--
3
P13IEN
2
P12IEN
1
P11IEN
0
P10IEN
// Enable and configure the UART0 & UART1
uart0ws0relcfg();
//Configure UART0
uart1Config();
//Configure UART1
//*** Configure the interrupts
IEN0 |= 0x91;
IEN2 |= 0x01;
do
{
}while(1);
// End of main()...
//Enable UART0 Int + enable all int
//Enable UART1 Interrupt
//Wait for UARTs interrupts
//--------------------------------------------------------------------------//
INTERRUPT ROUTINES
//--------------------------------------------------------------------------//--------------------------------------------------------------------------// UART0 interrupt
//
// Retrieve character received in S0BUF and transmit it
// back on UART0
// //------------------------------------------------------------------------void int_uart0 (void) interrupt 4 {
IEN0 &= 0x7F;
//--- The only UART0 interrupt source is Rx...
txmit0(S0BUF);
S0CON = S0CON & 0xFC;
IEN0 |= 0x80;
}// end of UART0 interrupt
//--- The only UART1 interrupt source is Rx...
txmit1(S1BUF);
S1CON = S1CON & 0xFC;
IEN0 |= 0x80;
Mnemonic
----P13IEN
2
P12IEN
1
P11IEN
0
P10IEN
//disable All interrupts
// Return the character
//received on UART0
//clear R0I & T0I bits
// enable all interrupts
//--------------------------------------------------------------------------// UART1 interrupt
//
// Retrieve character received in S1BUF and transmit it
// back on UART1
// //--------------------------------------------------------------------------void int_uart1 (void) interrupt 16 {
IEN0 &= 0x7F;
Bit
7
6
5
4
3
Function
Reserved, Keep at 0
Reserved, Keep at 0
Reserved, Keep at 0
Reserved, Keep at 0
Port 1.3 IRQ on change enable
0 = Disable
1 = Enable
Port 1.2 IRQ on change enable
0 = Disable
1 = Enable
Port 1.1 IRQ on change enable
0 = Disable
1 = Enable
Port 1.0 IRQ on change enable
0 = Disable
1 = Enable
The PORTIRQSTAT register monitors the
occurrence of the interrupt on port change.
This register serves to define which P1 pin has
changed when an interrupt occurs.
//disable All interrupts
// Return the character
// received on UART1
// clear both R1I & T1I bits
// enable all interrupts
}// end of UART1 interrupt
Note:
See UART0 / UART1 section for configuration examples and
TXMITx functions
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VMX51C1016
TABLE 121: (PORTIRQSTAT) PORT C HANGE IRQ STATUS - SFR A1H
7
P17ISTAT
6
P16ISTAT
5
P15ISTAT
4
P14ISTAT
3
P13ISTAT
2
P12ISTAT
1
P11ISTAT
0
P10ISTAT
Bit
7
6
5
4
3
Mnemonic
----P13ISTAT
2
P12ISTAT
1
P11ISTAT
0
P10ISTAT
Function
Unused
Unused
Unused
Unused
Port 1.3 changed
0 = No
1 = Yes
Port 1.2 changed
0 = No
1 = Yes
Port 1.1 changed
0 = No
1 = Yes
Port 1.0 changed
0 = No
1 = Yes
FIGURE 44: APPLICATION EXAMPLE OF PORT CHANGE INTERRUPT
Numeric Keypad
The following provides an assembler example
for configuration of the interrupt on Port 1 pin
change and how it is shared with the ADC
interrupt.
include VMIXreg.INC
;*** INTERRUPT VECTORS JUMP TABLE *
ORG 0000H
;BOOT ORIGIN VECTOR
LJMP
START
ORG 006BH
;INT ADC and P1 change interrupt
LJMP
INT_ADC_P1
;*** MAIN PROGRAM
ORG 0100h
START:
MOV
MOV
DIGPWREN,#01H
P2PINCFG,#0FFH
;ENABLE TIMER 2
;*** Initialise Port change interrupt on P1.0 - P1.7
MOV
PORTIRQSTAT,#00H
MOV
PORTIRQEN,#11111111B
;*** Initialise the ADC, BGAP, PGA Operation
MOV
ANALOGPWREN,#07h
;Select CH0 as ADC input + Enable input buffer + Adc clk
MOV
INMUXCTRL,#0Fh
MOV
ADCCLKDIV,#0Fh
MOV
ADCCONVRLOW,#000h
;*** configure ADC Conversion Rate
MOV
ADCCONVRMED,#080h
MOV
ADCCONVRHIGH,#016h
MOV
ADCCTRL,#11111010b
;***Activate All interrupts + (serial port for debugger support)
MOV
IEN0,#090H
;*** Enable ADC interrupt
MOV
IEN1,#020H
1
2
3
P1.3
4
5
6
P1.2
;***Wait IRQ…
WAITIRQ: LJMP
7
8
9
P1.1
*
0
#
P1.0
ORG 0200h
;************************************************************************
;* IRQ ROUTINE:
IRQADC + P1Change
;************************************************************************
INT_ADC_P1:
;MOV
IEN0,#00h ;DISABLE ALL INTERRUPT
VMX51C1016
P2.0
P2.1
P2.2
WAITIRQ
;***Check if IRQ was caused by Port Change
;***If PORTIRQSTAT = 00h -> IRQ comes from ADC
MOV
A,PORTIRQSTAT
JZ
CASE_ADC
;*** If interrupt was caused by Port 1, change
CASE_P0CHG:
MOV
PORTIRQSTAT,#00H
;*** Perform other instructions related to Port1 change IRQ
;(...)
;*** Jump to Interrupt end
AJMP
ENDADCP1INT
;*** If interrupt was caused by ADC
CASE_ADC:
ANL
ADCCTRL,#11110011b
;***Reset ADC interrupt flags & Reset ADC for next acquisition
ORL
ADCCTRL,#080h
ORL
ADCCTRL,#11111010b
;*** Perform other instructions related to Port1 change IRQ
;(...)
;** End of ADC and Port 1 Change interrupt
ENDADCP0INT:
ANL
IRCON,#11011111b
;***Enable All interrupts before exiting
; MOV
IEN0,#080H
RETI
END
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VMX51C1016
speed when an interrupt occurs (see the
following figure).
The Clock Control Circuit
The VMX51C1016’s clock control circuit allows
dynamic adjustment of the clock from which the
processor and the peripherals derive their clock
source. This enables reduction of overall power
consumption by modulating the operating
frequency according to processing requirements
or peripheral use.
A typical application for this is a portable
acquisition system, in which significant power
savings can be achieved by lowering the
operating frequency between A/D conversions,
and automatically throttling it to full speed when
an A/D converter interrupt is generated. Note
that the ADC operation is not affected by the
clock control unit.
The clock control circuit allows adjusting the
system clock from [Fosc/1] (full speed) down to
[Fosc/512]. The clock division control is done via
the CLKDIVCTRL register located at address
94h of the SFR register area.
TABLE 122: (CLKDIVCTRL) CLOCK DIVISION CONTROL REGISTER -SFR 94 H
7
SOFTRST
6
-
3
Bit
5
2
1
MCKDIV [3:0]
Mnemonic
7
SOFTRST
6:5
-
4
IRQNORMSPD
3:0
MCKDIV [3:0]
4
IRQNORMSPD
0
FIGURE 45: CLOCK TIMING W HEN AN INTERRUPT OCCURS
INTERNAL
CLOCK
INTERRUPT
INTERRUPT
SET
INTERRUPT
CLEARED
Once the interrupt is cleared, the VMX51C1016
returns to the selected operating speed as
defined by the MCKDIV [3:0] bits of the
CLKDIVCTRL register.
When the IRQNORMSPD bit is set the
VMX51C1016 will continue to operate at the
selected speed as defined by the MCKDIV [3:0]
bits of the CLKDIVCTRL register.
Note
With the exception of the A/D converter,
all the peripheral operating speeds are
affected by the clock control circuit.
Software Reset
Software reset can be generated by setting the
SOFTRST bit of the CLKDIVCTRL register to 1.
Function
Writing 1 into this bit location
provokes a reset. Read as a 0
0 = Full Speed in IRQ
1 = Selected speed during
IRQs
Master Clock Divisor
0000 – Sys CLK
0001 = SYS /2
0010 = SYS /4
0011 = SYS /8
0100 = SYS /16
0101 = SYS /32
0110 = SYS /64
0111 = SYS /128
1000 = SYS /256
1001 = SYS /512
(…)
1111 = SYS /512
The value written into the lower nibble of the
CLKDIVCTRL register, MCKDIV [3:0], defines
the clock division ratio.
When the IRQNORMSPD bit is cleared, the
VMX51C1016 will run at the maximum operating
_________________________________________________________________________________________________
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VMX51C1016
Power-on/Brown-Out Reset
The VMX51C1016 includes a power-onreset/brown-out detector circuit that ensures the
VMX51C1016 enters and stays in the reset state
as long as the supply voltage is below the reset
threshold voltage (in the order of 3.7 – 4.0 volts).
In most applications, the VMX51C1016 requires
no external components to perform a power-on
reset when the device is powered-on.
The VMX51C1016 also has a reset pin for
applications in which external reset control is
required. The reset pin includes an internal pullup resistor. When a power-on reset occurs, all
SFR locations return to their default values and
peripherals are disabled.
Errata:
The VMX51C1016 may fail to exit the reset state
if the supply voltage drops below the reset
threshold, but not below 3 volts. For
applications where this condition can occur, use
an external supply monitoring circuit to reset the
device.
Processor Power Control
The processor power management unit has two
modes of operation: IDLE mode and STOP
mode.
IDLE Mode
shuts down. The CPU will exit this state only
when a non-clocked external interrupt or reset
occurs (internal interrupts are not possible
because they require clocking activity).
The following interrupts can restart the
processor from STOP mode: Reset, INT0, SPI
Rx/Rx Overrun, and the I²C interface.
FIGURE 46: POWER MANAGEMENT ON THE VMX51C1016
IDLE
STOP
CLKCPU
GATE
CLK FOR
CPU
CLKPER
GATE
CLK FOR
PERIPHERALS
INTERRUPT
REQUEST
CLK
The following table describes the power control
register of the VMX51C1016.
TABLE 123: (PCON) POWER CONTROL (CPU) - SFR 87 H
7
SMOD
6
-
5
-
4
-
3
GF1
2
GF0
1
STOP
0
IDLE
Bit
7
Mnemonic
SMOD
Function
The speed in Mode 2 of Serial Port 0
is controlled by this bit. When
SMOD= 1, fclk /32. This bit is also
significant in Mode 1 and 3, as it
adds a factor of 2 to the baud rate.
6
5
4
-
-
3
2
1
GF1
GF0
STOP
0
IDLE
Not used for power management
Not used for power management
Stop mode control bit. Setting this bit
turns on the STOP Mode. STOP bit
is always read as 0.
IDLE mode control bit. Setting this bit
turns on the IDLE mode. IDLE bit is
always read as 0.
When the VMX51C1016 is in IDLE mode, the
processor clock is halted. However, the internal
clock and peripherals continue to run. The
power consumption drops because the CPU is
not active. As soon as an interrupt or reset
occurs, the CPU exits IDLE mode.
In order to enter IDLE mode, the user must set
the IDLE bit of the PCON register. Any enabled
interrupts will force the processor to exit IDLE
mode.
STOP Mode
In order to enter STOP mode, the user must set
the STOP bit of the PCON register. In this mode,
in contrast to IDLE mode, all internal clocking
_________________________________________________________________________________________________
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VMX51C1016
Watchdog Timer
TABLE 125: (IP0) INTERRUPT PRIORITY REGISTER 0 - SFR B8H
The VMX51C1016’s watchdog timer is used to
monitor program operation and reset the
processor in cases where the code could not
refresh the watchdog before it’s timeout period
has lapsed. This can come about from an event
that results in the program counter executing
faulty or incorrect code and inhibiting the device
from doing its intended job.
The watchdog timer consists of a 15-bit counter
composed of two registers (WDTL and WDTH)
and a reload register (WDTREL). See the
following figure.
7
UF8
6
WDTSTAT
Bit
7
6
Mnemonic
UF8
WDTSTAT
5
IP0.5
4
3
2
IP0.4
IP0.3
IP0.2
1
IP0.1
0
IP0.0
FIGURE 47: W ATCH DOG TIMER
SYSCLK ÷ 12
÷2
0
WDTL
7
8
WDTH
14
WDTR
÷16
5
4
3
2
IP0 [5:0]
1
0
Function
User Flag bit
Watchdog timer status flag. Set to 1
by hardware when the Watch Dog
timer overflows. Must be cleared
manually
Port1
Timer 2
ADC
Change
UART0
MULT/ACCU
Timer 1
I2C
SPI RX
availlable
Timer 0
SPI TX
Interrupt
Empty
External
External
UART1
INT0
INT 0
The WDTSTAT bit of the IP0 register is the
watchdog status flag. This bit is set to 1 by the
hardware whenever a watchdog timer overflow
occurs. This bit must be cleared manually.
Setting-up the Watchdog Timer
0
WDTREL
Control of the watchdog timer is enabled by the
following bits;
7
Control Logic
WDTR
WDTS
(Refresh)
(Start)
The WDTL and WDTH registers are not
accessible from the SFR register. However, the
WDTREL register makes it possible to load the
upper 6 bits of the WDTH register.
The PRES bit of the WDTREL register selects
the prescaler clock that is fed into the watchdog
timer.
Bit
WDOGEN
WDTR
WDTS
Location
DIGPWREN.6
IEN0.6
IEN1.6
Role
Watchdog timer enable
Watchdog timer refresh flag
Watchdog timer Start bit
In order for the watchdog to begin counting, the
user must set the WDOGEN bit (bit 6) of the
DIGPWREN register as follows:
MOV
DIGPWREN,#x1xxxxxxB
;x=0 or 1 depending
;of other peripherals
;to enable
When PRES = 0, the clock prescaler = 24
When PRES = 1, the clock prescaler = 384
TABLE 124: (WDTREL) W ATCHDOG TIMER RELOAD REGISTER - SFR D9H
7
PRES
6
Bit
7
Mnemonic
PRES
6-0
WDTREL
5
4
3
2
WDTREL [6:0]
1
0
Function
Prescaler select bit. When set, the
watchdog is clocked through an
additional divide-by-16 prescaler.
7-bit reload value for the high-byte
of the watchdog timer. This value
is loaded into the WDT when a
refresh is triggered by a
consecutive setting of the WDT
and SWDT bits.
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VMX51C1016
The value written into the WDTREL register
defines the delay time of the watchdog timer as
follows:
WDT delay when the WDTREL bit 7 is cleared
WDT Delay =
24*[ 32768–(WDTREL(6:0) x 256)]
Fosc
WDT delay when the WDTREL bit 7 is set
WDT Delay =
*** The Simple way ***
MOV
IEN0,#x1xxxxxxB
MOV
IEN1,#x1xxxxxxB
;DIRECT WRITE THAT SET BIT
;WDTR (x = 0 or 1)
;DIRECT WRITE THAT SET BIT
;WDTS (x = 0 or 1)
In the case where the program makes use of the
interrupts, it is recommended to deactivate the
interrupts before the watchdog refresh is
performed and reactivate them afterward.
b) Watchdog timer refresh example 2:
384*[ 32768–(WDTREL(6:0) x 256)]
*** If Interrupts are used: ***
Fosc
The following table demonstrates WDT reload
values and their corresponding delay times:
Fosc
14.74MHz
14.74MHz
14.74MHz
WDTREL
00h
4Fh
CCh
WDT Delay
53.3ms
20.4ms
347ms
Note: The value present in the CLKDIVCTRL
register affects the watchdog timer delay time.
The above equations and examples assume that
the CLKDIVCTRL register content is 00h.
CLR
MOV
ORL
XCH
MOV
ORL
MOV
MOV
SETB
IEN0.7
A,IEN0
A,#01000000B
A,R1
A,IEN1
A,#01000000B
IEN0,R1
IEN1,A
IEN0.7
;Deactivate the interrupt
;Retrieve IEN0 content
;set the bit 6 (WDTR)
;Store IENO New Value
;Retrieve IEN1 content
;Set bit 6, (WDTS)
; Set WDTR BIT
;Set WDTS BIT
;Reactivate the Interrupts
Watchdog Timer Reset
To determine whether the reset condition was
caused by the watchdog timer, the state of the
WDTSTAT bit of the IP0 register should be
monitored. On a standard power-on reset
condition, this bit is cleared.
Starting the Watchdog Timer
To start the watchdog timer using the hardware
automatic start procedure, the WDTS (IEN1)
and WDTR (IEN0) bits must be set. The
watchdog will begin to run with default settings
i.e. all registers will be set to zero.
;*** Do a Watchdog Timer Refresh / Start sequence
SETB
SETB
;WDTS bit
IEN0.6
IEN1.6
;Set the WDTR bit first
;Then without delay set the
When the WDT registers enter the state 7FFFh,
the asynchronous signal, WDTS will become
active. This signal will set bit 6 in the IP0 register
and trigger a reset.
To prevent the watchdog timer from resetting the
VMX51C1016, reset it periodically by clearing
the WDTR and clear the WDTS bit immediately
afterward,.
As a security feature to prevent an inadvertent
clearing of the watchdog timer, no delay
(instruction) is allowed between the clearing of
the WDTR and WDTS bits.
a) Watchdog timer refresh example 1:
_________________________________________________________________________________________________
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VMX51C1016
WDT Initialization and Use Example
Program
ORG 0000H
LJMP
START
;RESET & WD IRQ VECTOR
;*************************************
;* MAIN PROGRAM BEGINNING *
;*************************************
ORG 0100h
;*** Initialize WDT and other peripherals***
MOV
DIGPWREN,#40H
;ENABLE WDT OPERATION
;*** INITIALIZE WATCHDOG TIMER RELOAD VALUE
MOV
WDTREL,#04FH
;The WDTREL register is used to
;define the Delay Time WDT.
;Bit 7 of WDTREL define clock
;prescalng value
;Bit 6:0 of WDTREL defines the
;upper 7 bits reload value of the
;watchdog Timer 15-bit timer
;*** PERFORM A WDT REFRESH/START SEQUENCE
SETB
IEN0.6
;Set the WDTR bit first
SETB
IEN1.6
;Then without delay (instruction)
;set the WDTS bit right after.
;No Delays are permitted between
;setting of the WDTR bit and
;setting of the WDTS bit.
;This is a security feature to
;prevent inadvertent reset/start of
;the WDT
VMX51C1016 Programming
When the PM pin is set to 1, the I²C interface
becomes the programming interface for the
VMX51C1016’s Flash memory.
An in-circuit programming interface is easy to
implement at the board level. See VMIX APPNote001.
Erasing and programming the VMX51C1016’s
Flash
memory
requires
an
external
programming voltage of 12 volts. The voltage is
supplied/controlled
by
the
programming
hardware/tools.
The VMX51C1016 can be programmed using
Ramtron in-circuit programmers.
FIGURE 48: VMX51C1016 PROGRAMMING
;IF other interrupt are enabled,
;It is recommended to disable
;interrupts before refreshing the
;WDT and reactivate them after
;*** Wait WDT Interrupt
WAITWDT:
NOP
;*** If the two following code lines below are put "in-comment", the ;***WDT will
trigger a reset, and the program will restart.
RS-232
;*** PERFORM A WATCHDOG TIMER REFRESH/START SEQUENCE
;SETB
IEN0.6
;Set the WDTR bit first
;SETB
IEN1.6
;Then without delay (instruction)
LJMP
WAITWDT
;set the WDTS bit right after.
;No Delays are permitted between
;setting of the WDTR bit and
;setting of WDTS bit.
;This is a security feature to
;prevent inadvertent reset/start of
;the WDT
;It is recommended to disable
;interrupts before refreshing the ;WDT
and reactivate them after
Target PC Board
5V (optional)
SCL
SDA
VERSA-ICP
VPP 12V
PM
RES - (RESET)
GND
_________________________________________________________________________________________________
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VMX51C1016
VMX51C1016 Debugger
FIGURE 49: VMX51C1016 DEBUGGER HARDWARE INTERFACE
VERSA WARE
In-Circuit
Debugger
Software
The VMX51C1016 includes hardware debugging
features that can help speed up embedded
software development time.
RS-232
The
VMX51C1016
debugger
supports
breakpoints and single-stepping of the user
program. It supports retrieval and editing of the
SFR register and RAM memory contents when a
breakpoint is reached or when the device
operates in single-step mode. Unlike ROM
monitor programs that execute user program
instructions at a much lower speed, the
VMX51C1016 debugger does not affect program
operating speed when in “Run Mode” before
encountering a breakpoint.
RS-232
Debugger Features
RS232
Transceiver
To UART0
VERSA-ICP
Target PC Board
Debugger Software Interface
Debugger Hardware Interface
The VMX51C1016’s development system
provides the ideal platform for running the
VMX51C1016
debugger.
Interfacing
the
VMX51C1016 debugger is done via the UART0
serial interface.
It is possible to run the VMX51C1016 debugger
on the end user’s PCB providing that access to
the VMX51C1016 UART0 is available.
However, a connection to a stand alone in-circuit
programmer (ICP) will be required to perform
Flash programming, control the reset line and
activate the debugger on the target
VMX51C1016 device.
The Versa Ware VMX51C1016 software running
on Windows™ provides an easy-to-use user
interface for in-circuit debugging.
For more details on the VMX51C1016 debugger,
consult the “Versa Ware VMX51C1016 – V1
Software User Guide.pdf”
All documents are also accessible on the
Ramtron web site at http://www.ramtron.com/
_________________________________________________________________________________________________
page 74 of 76
www.ramtron.com
VMX51C1016
VMX51C1016 - 44 pin Quad Flat Package
L
R1
e
VMX51C1016
QFP-44
D2 D1 D
R2
b
A2
E2
A1
E1
E
A
e1
Seating
cop
Plane
T ABLE 126: DIMENSIONS OF QFP-44 CHIP CARRIER
Symbol
A
Al
A2
b
e1
D
D1
E
E1
e
L
cop
R1
R2
Dimension in
mm
Minimal/Maximal
-/2.45
0.25/0.50
1.95/2.10
0.30/0.40
10º typ
13.20 BSC
10.00 BSC
13.20 BSC
10.00 BSC
0.80
0.78/1.03
-/0.10
0.2 RAD typ.
0.3 RAD typ.
_________________________________________________________________________________________________
page 75 of 76
www.ramtron.com
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