VP2614 VP2614 H.261 Video De-Multiplexer Supersedes version in June 1995 Digital Video & DSP IC Handbook, HB3923-2 DS3735 - 3.2 October 1996 FEATURES DESCRIPTION ■ Fully integrated H.261 video de-multiplexer ■ Inputs an H.261 bitstream. Outputs error corrected run length coded coefficients. ■ Interfaces directly to the VP2615 H.261 decoder ■ Extracts side information and status for transfer to a System Controller ■ User definable system level options for proprietary applications ■ Average input rates between 40 Kbit /sec and 2Mbit / sec. Maximum peak input rates of 4 Mbit / sec. ■ 100 pin quad flatpack The VP2614 Video De-Multiplexer forms part of the Mitel Semiconductor chip set for video conferencing, video telephony, and multimedia applications. It extracts video parameters and run length coded DCT coefficients from an H.261 bitstream. Elements of the data which have been variable length coded according to the specification are decoded within the device. It produces tagged data, aligned to a macroblock timing structure, in the format needed by the VP2615 Decoder. Side information and status bits are separately made available for the system controller. The VP2614 will accept data up to a peak rate of 4 Mbits per second, but with an average rate up to 2 Mbits per second. The bursty nature of the input, together with the fact that each coded picture does not use the same number of bits, requires the provision of a received data buffer. Since the VP2615 Decoder accepts macroblock data as it becomes available, it is not necessary to provide storage for a complete coded picture. Worst case analysis has shown that a buffer size of 256K bits is adequate in practice for bit rates up to 2Mb/sec. The incoming sequence is coded with a strict syntax, and the VP2614 must identify and align with this sequence before correct decoding is possible. Storage for this alignment is contained within the external buffer. The device monitors that lock is always valid, and reports to the system controller. Error correction bits are ignored. ASSOCIATED PRODUCTS ■ VP2611 H.261 Encoder ■ VP2612 H.261 Video Multiplexer ■ VP2615 H.261 Decoder ■ VP520S CIF / QCIF Converter ■ VP510 Colour Space Converter HD7:0 HA3:0 CEN WR RD VMUX ERROR VMUX EVENT HOST INTERFACE DATA PMD 2:0 SIDE INFORMATION STROBE DATA VALID FRAME NOT READY ALIGNMENT VALIDITY CHECK VARIABLE LENGTH DECODE D7:0 VP2615 INTER FACE DM3:0 DCLK RECEIVE CNTRL BUFFER DATA 32K X 8 ADDR BUFFER INTERFACE VP2614 Fig 1 : Simplified Block Diagram 1 VP2614 OPERATION OF THE MAJOR BLOCKS PIN DESCRIPTION SIG TYPE LD LEN LCLK LRED I I I O DBUS7:0 DMODE3:0 O O PM2:0 O DCLK O SCLK I HD7:0 HA3:0 WR I/O I I RD I CEN I ERR O EVT O B7:0 I/O A14:0 WS O O BCS O BEN O TCK TMS TDI TDO TRST TOE I I I O I I RES I FUNCTION Line input data When low, the line input data is valid. Line input strobe When low, line data cannot be ac cepted. Data and control bus to the VP2615. These outputs identify the data on DBUS7:0. Identifiers for the additional information on DBUS7:0 .Not used by the VP2615. Continuous O/P strobe for the DBUS7:0 bus which is derived from SCLK. System clock. Must be 27 MHz for 30 Hz frame rates. Bi-directional data bus. Four system controller address bits. An active low write strobe from the system controller. An active low read strobe from the system controller. An active low chip select from the sys tem controller. An active low output which Indicates framing and decoding errors. An active low output which Indicates that new picture status data is available. Bi-directional data bus to the receive buffer. Address bus to the receive buffer. An active low write strobe for the receive buffer. An active low select for the receive buffer. An active low output enable for the buffer. JTAG test clock JTAG mode select JTAG I/P data JTAG O/P data JTAG reset When low all outputs are high impedance An active low power on reset NOTE: "Barred" active low signals do not appear with a bar in the main body of the text. 2 FRAME ALIGNMENT The H.261 continuous bitstream is split into frames of 512 bits the first bit in each frame being part of an 8 bit frame alignment pattern. Only the sequence in the pattern is important and detection can start from any bit. To avoid false detection within the actual data, this pattern must be repeated at least three times before " frame lock " can be considered to have been achieved. The detection of frame lock thus requires data from 24 consecutive 512 bit frames, and a section of the Received Data Buffer is reserved for this purpose. This external RAM is supported by a small internal buffer which allows eight consecutive bits ( obtained from reading a byte ) to be simultaneously checked for alignment with the corresponding bits in seven other bytes spaced apart by complete frames. The search for alignment over 512 bits takes less than 250 microseconds with a 27 MHz clock, this being less than the time taken to receive 512 bits at the maximum rate of 2Mb/ second. Thus the buffer area for frame lock does not overflow. Once frame lock has been achieved it is continually monitored using the appropriate bit in each frame. If a mismatch occurs then the next four frame alignment bits will be checked for errors. If any one of these four bits is also in error then loss of frame alignment is declared by setting a Status Register Bit, and a search for a new alignment position will commence. If none are in error then a random bit error is assumed and no further action is taken. The check done on loss of alignment is a compromise between falsely believing that alignment has been lost and not detecting that frame alignment has been lost. The probability of two random bit errors in the five frames used in the check is dependent on the bit rate and also the error rate. With a high error rate of 1:100000, and a bit rate of 2Mb/sec, false detection is possible once per week. The probability of detecting a change in the frame alignment ( caused by switching in a new bitstream ) is 46.9% in the first five frames, but this rises to 97.4% after 12 frames have been processed. Control Bits allow H261 framing to be either identified or ignored. In the latter case Frame Lock will always be indicated and data is still buffered and processed. The datastream is then expected to contain pure data and a search will be made to find picture start codes. When framing is enabled the 18 parity bits are extracted from the data, but single bits in error can still go un-detected in some circumstances. VP2614 VIDEO LOCK Once the VP2614 has locked to the H261 frames it will begin searching for the 20 bit unique Picture Start Code. Once this has been identified the "Video Lock" status bit will be set, and the bitstream will be translated on a code by code basis. Video lock will be lost and translation process interrupted under the following conditions: 1) A Picture Start Code or Group of Blocks ( GOB ) Start Code is not present when expected. 2) The codeword is not valid for its context, causing no match to be obtained. Each variable length code in the bitstream is analysed by the VP2614, and invalid patterns will force Video Lock to be lost. 3) Too many coefficients are transferred for the current macroblock because the End of Block code was missing. 4) GOB number is not in the correct range for the operating mode. 5) A GOB number not in sequence will cause lock to be lost and then regained. Note that only the most frequently occurring coefficients are variable length coded, the others being represented by an escape sequence followed by a fixed length code. The Intra DC coefficient is also a fixed length code. These fixed length codes have bit patterns which are forbidden in the H.261 specification, but they could appear due to bit errors. These invalid codes are trapped by the VP2614, but do not cause Video Lock to be lost. Instead the run length coefficient is replaced by a default value of magnitude 1. When video lock has been lost the DMODE 3:0 outputs indicate a WAIT state. When lock is regained any missing macroblocks are replaced with Fixed Macroblocks. A count is maintained of up 256 occurrences of faults 1 3, and a status bit is set when lock is lost ( the Video Lock Achieved bit is also cleared ). An output signal is also provided which can, if required, be used to interrupt the system controller. This indicates any of the above errors which cause Video Lock to be lost and also frame alignment errors; alternatively it can be used to just indicate framing errors. When Video Lock has been achieved, the detection of a Picture or GOB start code when it is not expected will not cause lock to be lost. Instead the VP2614 will resynchronize to the new start code, and dummy macroblocks will be generated for the missing GOB's. These dummy blocks will be Fixed Macroblocks, and will cause the VP2615 Decoder to use data from the previously decoded picture. Note that Video LINE STROBE I/P (LCLK) LINE I/P DATA 0ns min 2Ø +10ns min DATA VALID Lock is actually lost and re-gained under these conditions. The status bit will momentarily be set and then reset, and the Video Lock Lost Counter will be incremented. Similarly any errors in the actual GOB number will not cause lock to be lost and then gained again. Since sequential GOB numbers are always produced by the encoder, then the Decoder generates its own GOB numbers and ignores those in the bitstream. A Control Bit allows the system controller to take one of two actions when Video Lock is lost. Either the VP2614 can be forced to re-initialize to the next Picture Start Code, or it can abandon the decoding operation until the next GOB Start Code is detected. When lock has been lost, and a new start code has been found, the VP2614 assumes its number to be initially correct and starts its own sequence from that number. If, however, the next number in the bitstream is not in sequence then this new number is used to start a new sequence. This process continues until two sequential numbers are obtained, and then no further checks on the GOB numbers are made until Video Lock is again lost. The VP2614 will generate "Fixed Macroblocks " for the missing GOB numbers since Video Lock was lost, and will output these to the VP2615 decoder. This then uses data from the previous decoded picture for those macroblocks. A Video Hold bit is provided in one of the System Control Registers which forces Video Lock to be lost immediately. No further data is passed to the VP2615 whilst this bit is set, but the Received Data Buffer is not allowed to fill unnecessarily. Incoming data will be flushed out and lost. When the hold bit is cleared a Picture Start Code must be detected to re-gain Video Lock. The VP2615 will then be provided with any missing GOB's as described above, before GOB's in the new picture are processed. A Freeze Frame Control Bit is also provided. This has a similar action to the Video Hold Bit, except that it is only actioned when PTYPE has been decoded in the picture layer, and it also sets a Freeze Frame status bit. If Video Lock is lost before the start of a new frame then Freeze Frame will become active and a search will commence for a picture start code. Even though Freeze Frame causes Video Lock to be lost, the VP2614 will still search for picture start codes and will extract PTYPE and Temporal Reference values. If clear, a Release Mode Control Register Bit will allow the freeze condition to be released when the Freeze Bit is cleared, but is only actioned when the next Picture Header is decoded. If the Release Mode Bit is set, then the freeze condition is only released when the PTYPE bit in the H.261 stream specifies that this is to occur. Even when automatic release has been selected the system controller can still monitor the length of time that the freeze has been in effect. It can then force a release after a time out period by setting the Release Mode Bit and clearing the Freeze Bit. DE-MUX CORE DATA ENABLE (LEN) NOT READY O/P (LRED) Asynchronous Note. Ø is the system clock period Fig 2 : Line Interface Timing Once Video Lock has been achieved, the core of the VP2615 will convert the H.261 bitstream into video parameters and run length coded coefficients. A state machine, which is a hardware manifestation of the H.261 coding structure, maintains the current position in the bitstream. When necessary variable length de-coding is performed, and side information such as temporal reference and Picture Type Information is stored in registers. 3 VP2614 DMODE3:0 SCLK ADDRESS O/P ADDRESS VALID 20ns max 10ns min CHIP ENABLE/ O/P ENEBALE Tac VALID DATA I/P READ CYCLE WRITE CYCLE ADDRESS O/P 20ns max 20ns max CHIP ENABLE DATA O/P DATA VALID 20ns max GOB Number MB Number Control Decisions Quant Value Horizontal MV Vertical MV Coded Blk Pattern Sub-Block No Zero Run Count RLC Coefficient Not used Not used Not used Not used Not used Wait State 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0ns min 20ns max WRITE ENABLE FUNCTION Fig 3 : External Buffer Timing Not all this side information is used by the VP2615 Decoder, but is still made available on the data output bus DBUS7:0. This is described in the section on Additional Information. In addition the side information can be examined by the system controller. Requirements for the complete decoder system are such that it is desirable for the VP2614 /15 pair to free run, and to ignore the Temporal References embedded in the video bitstream. The pair then always process the bitstream, whenever code bits are available, using the processing rate needed for the full 30 Hz frame rate. Operating in this manner allows the de-mux core to be closely coupled to the VP2615 Interface circuitry, and no additional buffering is necessary. The demultiplexing process is then locked to the macroblock timing structure needed by the VP2615. LINE INTERFACE Bitstream inputs to the device are controlled by an asynchronous line input strobe, which when data is valid is enabled by a Data Valid signal. Detailed timing information is given in Figure 2. Maximum input frequency is 4 MHz and the rising edge of the strobe is used to internally latch the data. The VP2614 generates a Ready signal which goes invalid when data cannot be accepted. This, for example, occurs during system reset or if the Received Data Buffer overflows. EXTERNAL BUFFER REQUIREMENTS The external buffer must be a 32K x 8 bit static RAM, and must comply with the timing requirements given in Figure 3. Under normal operating conditions the buffer will not overflow, however it is conceivable that under some unforseen condition the buffer may fill and then overflow. For this reason a Buffer Full Flag is provided in one of the Status Registers. This is asserted when the buffer is 90% full, and is not itself an error condition. If the buffer continues to fill and eventually overflows, then the Ready Signal to the line interface goes invalid. The effect of overflow is to also clear the buffer and the Buffer Empty Flag will be raised. There is no status bit to indicate overflow, but an extended period of Buffer Full followed by Buffer Empty can be used to infer the condition. 4 Table 1. Output Codes VP2615 INTERFACE The VP2614 provides a glueless interface to the VP2615 Decoder. Run length coded coefficients and control information are transmitted over the DBUS7:0 bus, and are identified by the code on the DMODE3:0 bus given in Table 1. The VP2614 produces a continuous DCLK which is used to strobe data into the VP2615. This is derived by dividing the system clock by two, and when no data is actually available the DMODE3:0 bus will indicate a wait state. Timing is shown in Figure 4. The VP2615 expects a macroblock and its control information to be transferred over a minimum period, nominally equivalent to 2048 system clock cycles but with allowance for the asynchronous DCLK. Wait states are thus inserted as necessary by the VP2614 in order to enforce this macroblock period. Under normal circumstances the VP2614 will not take longer than 2048 clock periods to produce a macroblock, but some 10% extra time is available for each macroblock before the 30 Hz frame rate becomes impossible to maintain. The start of a macroblock transfer is identified by the presence of the Control Decisions Byte ( DMODE3:0 = 0010). Each macroblock slot must at least consist of this Control Decisions Byte, followed by the GOB number and then the Macroblock number. No further bytes are mandatory. When high, Bit 0 in the Control Decisions Byte indicates a Fixed Macroblock, and a high on Bit 1 indicates Inter Mode coding. A high on Bit 2 indicates that the macroblock was filtered, and a high on Bit 3 indicates that Motion CompensaSCLK DCLK O/P 25ns max 25ns max 25ns max DATA FROM VP2614 DATA VALID DMODE 3:0 DATA VALID Fig 4 : Output Timing VP2614 tion was used. When Bit 7 is high this indicates that CIF resolution is in use, but the VP2615 does not use this information. Instead the host controller must supply this information. The VP2615 is essentially a Macroblock Processor which produces decoded data for the position on the screen defined by the GOB and Macroblock number. Since the H.261 specification allows macroblocks to be skipped, then the VP2614 generates dummy Fixed Macroblocks if necessary ( see below ) which are still separated by 2048 clock cycles. Similarly after Video lock has been re-gained the VP2614 will generate Fixed Macroblocks for those missing in the sequence, even if this wraps around into the next picture. These steps ensure that a complete picture, containing dummy data when necessary, is always supplied by the VP2614. The Fixed Macroblock bit in the Control Decisions Byte is set when dummy data is needed, and Intra Mode decoding is specified. This causes the VP2615 to output macroblock data from the previously decoded picture, which was already in the frame store. ADDITIONAL INFORMATION Picture Type, PSPARE and GSPARE information is not used by the VP2615 decoder. In future or proprietary uses of H.261 this information could become considerable and be useful to other devices in the system. This can conveniently be supplied by using the DBUS7:0 bus when the DMODE3:0 bus indicates that a wait state is present and there is no useful information for the VP2615. An additional control bus PM2:0 defines the additional information that is present, with the coding given below: PM2:0 000 001 010 011 100 111 ADDITIONAL PARAMETER Temporal Reference GSPARE transfer PSPARE transfer PTYPE transfer Quantizer step value Data present is that defined by DMODE3:0 SYSTEM CONTROLLER INTERFACE A conventional microprocessor interface is used consisting of a byte wide bi-directional data bus, four address bits, a chip enable and separate read and write strobes. Detailed timing is given in Figure 5. In addition two outputs are available which can be used as interrupts if necessary. These can be disabled by control bits. When the Error Interrupt Source Bit is set, the ERROR signal indicates that an error has occurred in the FEC frame alignment module. The Frame Lock Lost Status Bit is also set. The output signal is cleared by reading the status register and will be set again when frame alignment is again achieved. If the host has forced a loss of alignment then ERROR does not go active when lock is lost, but it will still go active when lock is regained. When the Error Interrupt Source Bit is cleared, then the ERR output also goes active when Video Lock is lost. Reading the Status Register will detemine the actual cause of the ERR interrupt. The EVT signal allows the controller to synchronize with picture related parameters extracted from the bitstream. It goes active when new picture status data is available, as does the Picture Ready bit in Status Register A. This bit and the output signal are cleared when any Status Register is read. The pipeline delay of two macroblock periods through the VP2615 decoder will give the controller time to react to changes in PTYPE affecting the final output of the picture in question. When PTYPE specifies a change between CIF and QCIF, the controller has an amount of time equivalent to that needed to decode the first GOB before it needs inform the VP2615 of the change in operation. The addresses and functions of the various control and status registers are given below. Setting a Control Bit always performs the function specified, and a high in a Status Register indicates the state is true. All error counters saturate at their maximum values, and are prevented from changing whilst being read. WRITE CYCLE READ CYCLE ADDRESS ADDRESS Tsh Tsh CHIP SELECT Tas Tah Tas CHIP SELECT Trs Tah Tws Tri WRITE STROBE READ STROBE Thz Tac DATA OUT Tds DATA IN Data Valid Tlz CHARACTERISTIC Addresss Set Up Time Address Hold Time Cip Select Set Up Time Chip Select Hold Time Strobe In active Time Data Access Time Delay to O/P's low Z Delay to O/P's high Z Twi Twa SYMBOL MIN Tas Tah Trs Tsh Tri Tac Tlz Thz 10ns 10ns 10ns 2ns Øns 6Øns MAX 10 +7Øns 25ns 25ns Data Valid CHARACTERISTIC SYMBOL MIN Addresss Set Up Time Address Hold Time Chip Select Set Up Time Chip Select Hold Time Strobe In active Time Strobe Active Time Data Set Up Time Data Hold Time Tas Tah Tws Tsh Twi Twa Tds Tdh 10ns 10ns 10ns 2ns 3Øns 2Øns 10ns 10ns NOTE Ø is the period of the input clock Tdh Fig 5 : Host Controller Timing MAX 5 VP2614 SUPPLEMENTARY NOTE: To avoid problems with register loading, the VP2614 requires two write operations with no read strobe in between. The absence of chip enable with the read strobe does not prevent this problem. Thus if I/Os are memory mapped it will be necessary to externally gate the read strobe with chip enable for the VP2614 and to do two writes for every load operation. PICTURE STATUS REGISTERS STATUS REGISTER A ( ADDRESS 0 ) PICTURE INFORMATION REGISTER ( ADDRESS 11) BIT FUNCTION BIT FUNCTION 0 1 2 3 4 5-7 GSPARE Byte Available ( FIFO not Empty ) Freeze Frame Buffer Full Buffer Empty Picture Information Ready Unassigned 7 6 5 4 3 2 1:0 [Bit 0 is LSB] PSPARE Byte 2 Valid (cleared by reading byte) PSPARE Byte 1 Valid (cleared by reading byte) Split screen Document camera Freeze frame CIF/QCIF Set to one STATUS REGISTER B ( ADDRESS 1 ) BIT FUNCTION 0 1 2 3 4 -7 Frame Lock Lost Frame Lock Achieved Video Lock Lost Video Lock Achieved Unassigned CONTROL REGISTER A ( ADDRESS 2 ) BIT FUNCTION ( when the bit is set ) 0 1 2 3 4 5 6 7 Freeze Frame released by bit stream Force Freeze Frame Error interrupt only from Frame Lock Enable EVT Interrupt Enable ERR Interrupt Video Hold Clear Buffer System Re-start CONTROL REGISTER B ( ADDRESS 3 ) BIT FUNCTION ( when the bit is set ) 0 1-2 4 5:3 6 7 Re-lock to Picture Start Code Unassigned FEC Framing Off FEC Framing On Clear Video Lock Lost Counter Clear other Counters apart from above 000 101 Note: Control Register B must be loaded with the required values before Register A is programmed. USER READABLE COUNTERS ADDRESS FUNCTION 4 5 9 FEC Frame Count Filled Frames Count Video Lock Lost Count 6 10 11 12 13 14 Temporal Reference Register Picture Information ( see below ) First PSPARE Byte Second PSPARE Byte Top of GSPARE Stack A master - slave arrangement is used for the Picture Status Registers, and the slave is not updated for the duration of the host read operation plus 32 system clock cycles. Reading any of the counter values ( address 4-9 ) or any Picture Status Register ( address 10-13 ) causes all values in the respective blocks to be frozen for 32 clocks, thus allowing a complete snapshot to be taken of the respective values. Two bytes of PSPARE data are stored and further bytes will be lost. Note that the VP2612 Video Multiplexer presently only provides one byte of PSPARE information. A FIFO is provided to provide storage for 12 GSPARE bytes, and a status bit is provided to indicate that this FIFO is not empty, and that the byte at the top of the stack should be read. RESET OPERATION In addition to the hardware reset there are several software reset options which are selective in their action. The hardware reset input will initialize all the internal circuit blocks, and will clear all status registers, error counters, and address pointers. The bits in Control Registers A and B are cleared except that the Video Hold Bit in Register A is set, and Bits 0,4, and 5 are set in Register B. The device will thus re-lock to a Picture Start Code, will correct 2 bit errors, and FEC Framing will be on. The circuit which interfaces to the VP2615 Decoder is reset to the end of picture condition ( Macroblock 33 in GOB 12 ). The System Re-start bit ( Bit 7 in Control Register A ) will clear all status bits and will initialize the bitstream decoder, the forward error corrector, and the buffer alignment modules. It should be used if there has been an interruption in the bitstream, and does not affect the circuit producing GOB's and macroblocks for the VP2615 Decoder. Thus, after the re-start, Video Lock can be obtained on a GOB boundary, and Fixed macroblocks can be generated for missing macroblocks within the same picture. The Clear Buffer bit ( Bit 6 in Control Register A ) will reset the read and write address pointers for the external buffer. A full software restart requires both Bit 7 and Bit 6 to be set. Two bits are also provided in Control Register B for reset operations. One will clear the Video Lock Lost counter, the other clears the FEC frame counter, the Filled Frames counter, and the three error counters in the error detection circuit. VP2614 Instructions are clocked into the 8 bit instruction register (no parity bit) and the following instructions are available. JTAG Test Interface The VP2614 includes a test interface consisting of a boundary scan loop of test registers placed between the pads and the core of the chip. The control of this loop is fully JTAG/ IEEE 1149-1 1990 compatible. Please refer to this document for a full description of the standard. The interface has five dedicated pins: TMS, TDI, TDO, TCK and TRST. The TRST pin is an independent reset for the interface controller and should be pulsed low, soon after power up; if the JTAG interface is not to be used it can be tied low permanently. The TDI pin is the input for shifting in serial instruction and test data; TDO the output for test data. The TCK pin is the independent clock for the test interface and registers, and TMS the mode select signal. TDI and TMS are clocked in on the rising edge of TCK, and all output transitions on TDO happen on its falling edge. PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FUNC N/C N/C N/C TOE N/C DMODE0 DMODE1 DMODE2 DMODE3 GND VDD DBUS0 DBUS1 DBUS2 DBUS3 DBUS4 DBUS5 DBUS6 DBUS7 VDD PIN 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 FUNC GND DCLK LD PM0 PM1 PM2 N/C N/C N/C N/C HA0 HA1 HA2 HA3 SCLK GND VDD HD0 HD1 HD2 PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Instruction Register ( MSB first ) Name 11111111 00000000 10XXXXXX 01XXXXXX BYPASS EXTEST (No inversion) INTEST (Product test only) SAMPLE/PRELOAD The positions of the test registers in the boundary loop, and their corresponding functional names, are detailed in Table 3. INTEST is non-standard and is used for production testing and also to invoke the overall output enable function (TOE) via the scan chain. FUNC HD3 HD4 HD5 HD6 HD7 VDD GND WR RD CEN N/C N/C B7 B6 B5 B4 B3 B2 GND VDD PIN 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 FUNC B1 B0 A14 A13 A12 A11 A10 A9 A8 A7 VDD GND A6 A5 A4 A3 A2 N/C N/C N/C PIN 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 FUNC A1 A0 BEN BCS GND VDD WS LRED TDI TMS TRST TCK TDO VDD GND RES LEN LCLK ERR EVT Table 2. Pinout 7 VP2614 SIGNAL DIRECTION JTAG Bit Number SIGNAL DIRECTION JTAG Bit Number TOE testoeout DMODE0 DMODE1 DMODE2 DMODE3 DBUS0 DBUS1 DBUS2 DBUS3 DBUS4 DBUS5 DBUS6 DBUS7 DCLK LD PM0 PM1 PM2 HA0 HA1 HA2 HA3 SCLK HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 oeout WR RD IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT IN OUT OUT OUT IN IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT IN IN 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 CEN B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 nroeout LRED WS BCS BEN A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 RES LEN LCLK ERR EVT IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT IN IN IN OUT OUT 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 3. Boundary scan allocations Those signals labelled testoeout, oeout, and nroeout, are not connected to ASIC output pins, but are provided on the JTAG boundary scan to enhance the device testability. 8 VP2614 ABSOLUTE MAXIMUM RATINGS [See Notes] NOTES ON MAXIMUM RATINGS Supply voltage VDD -0.5V to 7.0V Input voltage VIN -0.5V to VDD + 0.5V Output voltage VOUT -0.5V to VDD+ 0.5V Clamp diode current per pin IK (see note 2) 18mA Static discharge voltage (HMB) 500V Storage temperature TS -65°C to 150°C Ambient temperature with power applied TAMB 0°C to 70°C Junction temperature 100°C Package power dissipation 1000mW 1. Exceeding these ratings may cause permanent damage. Functional operation under these conditions is not implied. 2. Maximum dissipation or 1 second should not be exceeded, only one output to be tested at any one time. 3. Exposure to absolute maximum ratings for extended periods may affect device reliablity. 4. Current is defined as negative into the device. STATIC ELECTRICAL CHARACTERISTICS Operating Conditions (unless otherwise stated) Tamb = 0 C to +70°C VDD = 5.0v ± 5% Characteristic Symbol Min. Output high voltage Output low voltage Input high voltage Input low voltage Input leakage current Input capacitance Output leakage current Output S/C current VOH VOL VIH VIL IIN CIN IOZ ISC Value Typ. 2.4 2.0 -10 Units 0.4 0.8 +10 10 -50 10 Conditions Max. +50 300 V V V V µA pF µA mA IOH = 4mA IOL = -4mA 3.0V for SYSCLK and LCLK 0.6V for SYSCLK and LCLK GND < VIN < VDD GND < VOUT < VDD ORDERING INFORMATION VP2614 CG GPFR (Commercial - plastic QFP package) 9 http://www.mitelsemi.com World Headquarters - Canada Tel: +1 (613) 592 2122 Fax: +1 (613) 592 6909 North America Tel: +1 (770) 486 0194 Fax: +1 (770) 631 8213 Asia/Pacific Tel: +65 333 6193 Fax: +65 333 6192 Europe, Middle East, and Africa (EMEA) Tel: +44 (0) 1793 518528 Fax: +44 (0) 1793 518581 Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. 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