ES3210 Video CD Processor Product Brief A ESS Technology, Inc. DESCRIPTION FEATURES The ES3210 Video CD processor is a highly integrated, high quality and cost-effective single-chip solution for Video CD players. Based upon ESS’s Programmable Multimedia Processor (PMP) architecture, the ES3210 integrates MPEG1 video and audio processing and a full MPEG system stream parser. The ES3210 is fully programmable and incorporates a RISC-based 32-bit processor as an onchip video controller (VC) and a supporting 64-bit processor core that functions as an on-chip video processor (VP). • Single-chip Video CD processor in a 100-pin TQFP The VC module can be used as a microcontroller to provide system and user interface controls, while also being able to support embedded systems applications. The VP module performs MPEG audio and video processing operations such as arbitrary scaling, video standards conversion and video filtering. The MPEG1 system layer bitstream is decoded at up to 9 Mb/s at Standard Intermediate Format (SIF) resolution with a picture rate of 30 f/s. Two channels of MPEG layer 1 or audio layer 2 are decoded simultaneously. The ES3210 includes SmartScaleTM technology for advanced scaling techniques, SmartStreamTM technology for video error concealment, and SmartZoomTM technology for enabling in/out zooming of a particular area of a still picture. Additional features include DiscScan, TrackScan, QuickScan, OnScreen-Display (OSD), Karaoke, Playback Control (PBC) for Video CD 2.0, Smart Art and entertainment game software. The incoming MPEG1 bit stream from a video CD is passed to the ES3210 through its five-wire TDM serial bus, parses the system layer and demultiplexes the video and audio channels. Video is decoded and output as YUV or RGB digital pixels to an NTSC or PAL video DAC/encoder, then to the screen. Audio is decoded and passed to the speakers via the audio serial bus, then to an audio DAC. The ES3210 also has general-purpose auxiliary pins and an integrated audio Digital-to-Analog Converter (DAC) interface to reduce the need for external audio glue logic. When coupled with the ES3207 Video CD Companion Chip, echo cancellation and vocal reverb are also supported. The echo cancellation feature removes unwanted acoustic reflection from the audio output, while the vocal reverb feature simulates a theater acoustic environment. The ES3210 is available in an industry-standard 100-pin Thin Quad Flat Pack (TQFP) device package. ESS Technology, Inc. • • • • • • • • • • package. Programmable Multimedia Processor (PMP) architecture. MPEG1 video/audio decoder and system parser. Video CD 1.1 and 2.0, and Audio CD compatible. On-chip video interlacing hardware incorporated. Color Space Conversion (CSC) function supported. STC interpretation and video/audio Phase-lock Loop (PLL) Power management 3.3V power supply with 5V tolerant I/Os. 8- and 16-bit YUV output supported. On-chip On Screen Display (OSD) controller supports karaoke lyric and subtitle text display functions. Video • Playback Control (PBC) for Video CD 2.0 supported. • Trick mode functions such as Repeat, Goto, and Set A-B supported. • SmartScaleTM for NTSC to PAL conversion and vice versa supported. • SmartZoomTM for motion zoom and pan supported. • SmartStreamTM for video error concealment supported. • Video Fader for fading video image in and out supported. Audio • • • • • CD block decoder functions supported. 256/384 frame sync audio system clocks supported. Programmable master clock for external audio DAC. Independent bit clock for audio transmit and receive. 3DSound and surround sound supported. Software Support • Software stack support for the TCP/IP protocols defined by RFC 791 and RFC 793. • Software stack support for the POP3, SMTP and SNMP Internet e-mail protocols defined by RFC 821, RFC 1157and RFC 2449. • Software stack support provided for the HTTP Web browsing protocol defined by RFC 1945, RFC 2068 and RFC2616. • Software stack support provided for RTP payload format for MPEG-1/2 and H.261 video streaming protocols defined by Character generation and software support for English, Big 5/GB Chinese and Japanese fonts. • Software support for infrared remote control and wireless keyboard. SAM0417-051701 1 ES3210 PRODUCT BRIEF A ES3210 PINOUT ES3210 PINOUT VDD AUX6 AUX5 AUX7 LD0 LD1 LD2 LD3 LD4 LD6 LD5 LD7 LWR# LOE# LCS3# LCS1# LCS0# LA0 LA1 LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 LA11 VSS Figure 1 shows the ES3210 device pinout. 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VPP 81 50 VSS LA12 82 49 AUX4 LA13 83 48 AUX3 LA14 84 47 AUX2 LA15 85 46 AUX1 LA16 86 45 AUX0 LA17 87 44 PCLK ACLK 88 43 PCLK2X AOUT/SEL_PLL0 89 CPUCLK ATCLK 90 42 41 ATFS/SEL_PLL1 91 40 VSYNC DOE# 92 39 YUV7 AIN 93 38 YUV6 ARCLK 94 37 YUV5 ARFS 95 36 YUV4 TDMCLK 96 YUV3 TDMDR 97 35 34 TDMFS 98 33 YUV1 CAS# 99 32 31 YUV0 ES3210 100-pin PQFP YUV2 VDD VSS RESET# DBUS15 DBUS14 DBUS13 DBUS12 DBUS11 DBUS9 DBUS10 DBUS8 DBUS7 DBUS6 DBUS5 DBUS4 DBUS3 DBUS2 DBUS1 DBUS0 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 DWE# VDD RAS# 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 VSS HSYNC Figure 1 ES3210 Pinout Diagram ES3210 PIN DESCRIPTION Table 1 lists the ES3210 pin descriptions. Table 1 ES3210 Pin Description Name Number I/O Definition VDD 1, 31, 51 I Voltage supply for 3.3V. RAS# 2 O DRAM row address strobe (active low). DWE# 3 O DRAM write enable (active low). MA[8:0] 12:4 O DRAM multiplexed row and column address bus. DBUS[15:0] 28:13 I/O DRAM data bus I/O [15:0]. 29 I System reset (active low). 30, 50, 80, 100 I Ground. RESET# VSS YUV[7:0] 39:32 O YUV[7:0] pixel output data. VSYNC 40 I/O Vertical sync for screen video interface, programmable for rising or falling edge. HSYNC 41 I/O CPUCLK 42 I PCLK2X 43 I/O 2 SAM0417-051701 Horizontal sync for screen video interface, programmable for rising or falling edge. RISC and system clock input. CPUCLK is used only if SEL_PLL[1:0] = 00. Pixel clock; two times the actual pixel clock for screen video interface. ESS Technology, Inc. ES3210 PRODUCT BRIEF A ES3210 PIN DESCRIPTION Table 1 ES3210 Pin Description (Continued) Name Number I/O PCLK 44 I/O AUX[7:0] Definition Pixel clock qualifier in for screen video interface. 54:52, 49:45 I/O Auxiliary control pins (AUX0 and AUX1 are open collectors). LD[7:0] 62:55 I/O RISC interface data bus. LWR# 63 O RISC interface write enable (active low). LOE# 64 O RISC interface output enable (active low). LCS[3,1,0]# LA[17:0] 65:67 O RISC interface chip select (active low). 87:82, 79:68 O RISC interface address bus. VPP 81 I ACLK 88 I/O Master clock for external audio DAC (8.192 MHz, 11.2896 MHz, 12.288 MHz, 16.9344 MHz, and 18.432 MHz). AOUT/ 89 O Dual-purpose pin. AOUT is the audio interface serial data output I Select PLL[0] input. The matrix below lists the available clock frequencies and their respective PLL bit settings. SEL_PLL0 Digital supply voltage for 5V. SEL_PLL1 SEL_PLL0 Clock Output 0 0 Bypass PLL 0 1 54.0 MHz 1 0 67.5 MHz 1 1 81.0 MHz ATCLK 90 I/O Audio transmit bit clock. ATFS 91 O Audio transmit frame sync. I Refer to the description and matrix for SEL_PLL0 pin 89. SEL_PLL1 DOE# 92 O DRAM output enable (active low). AIN 93 I Audio serial data input. ARCLK 94 I Audio receive bit clock. ARFS 95 I Audio receive frame sync. TDMCLK 96 I TDM interface serial clock. TDMDR 97 I TDM interface serial data receive. TDMFS 98 I TDM interface frame sync. CAS# 99 O DRAM column address strobe bank 0 (active low). ESS Technology, Inc. SAM0417-051701 3 ES3210 PRODUCT BRIEF MECHANICAL DIMENSIONS MECHANICAL DIMENSIONS Figure 2 shows the mechanical dimensions of the ES3210 package. D D1 A2 E E1 A1 ES3210 e e1 b L L1 1 Symbol Description D D1 E E1 A1 A2 b e e1 L L1 - Min 23.65 19.90 17.65 13.90 0.10 2.57 0.20 0.24 0.65 1.88 0° - Lead to lead, X-axis Package’s outside, X-axis Lead to lead, Y-axis Package’s outside, Y-axis Board standoff Package thickness Lead width Lead pitch Lead gap Foot length Lead length Foot angle Coplanarity Leads in X-axis Leads in Y-axis Total leads Package type Millimeters Nom 23.90 20.00 17.90 14.00 0.25 2.71 0.30 0.65 0.80 1.95 30 20 100 PQFP Max 24.15 20.10 18.15 14.10 0.36 2.87 0.40 0.95 2.02 7° 0.102 - Figure 2 ES3210 Mechanical Dimensions ORDERING INFORMATION Part Number Description Package ES3210 Video CD processor 100-pin PQFP A ESS Technology, Inc. 48401 Fremont Blvd. Fremont, CA 94538 Tel: 510 - 492-1088 Fax: 510 - 492-1098 4 No part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without the prior written permission of ESS Technology, Inc. ESS Technology, Inc. assumes no responsibility for any errors contained herein. (P) U.S. Patent 4,214,125 and others, other patents pending. ESS Technology, Inc. makes no representations or warranties regarding the content of this document. VideoDrive® is a registered trademark of ESS Technology, Inc. All specifications are subject to change without prior notice. All other trademarks are owned by their respective holders and are used for identification purposes only. © 1997-2001 ESS Technology, Inc. All rights reserved SAM0417-051701