W6811 SINGLE-CHANNEL VOICEBAND CODEC (5V Analog, 3V Digital) Preliminary Data Sheet -1- Publication Release Date: October 23, 2003 Revision A10 W6811 1. GENERAL DESCRIPTION The W6811 is a general-purpose single channel PCM CODEC with pin-selectable µ-Law or A-Law companding. The device is compliant with the ITU G.712 specification. It operates off of a separated analog (5V) and digital (3V) power supplies and is available in 24-pin PDIP, SOG, SSOP, and TSSOP package options. Functions performed include digitization and reconstruction of voice signals, and band limiting and smoothing filters required for PCM systems. The filters are compliant with ITU G.712 specification. W6811 performance is specified over the industrial temperature range of –40°C to +85°C. The W6811 includes an on-chip precision voltage reference and an additional power amplifier, capable of driving 300Ω loads differentially up to a level of 6.3V peak-to-peak. The analog section is fully differential, reducing noise and improving the power supply rejection ratio. The data transfer protocol supports both long-frame and short-frame synchronous communications for PCM applications, and IDL and GCI communications for ISDN applications. W6811 accepts seven master clock rates between 256 kHz and 4.096 MHz, and an on-chip pre-scaler automatically determines the division ratio for the required internal clock. 2. FEATURES APPLICATIONS • • Digital Telephone Systems • Central Office Equipment Switches, Routers) • PBX Systems (Gateways, Switches) • PABX/SOHO Systems Power supply: Analog 4.5 – 5.5V Digital 2.7 – 3.3V • Typical power dissipation of 25 mW, power-down mode of 0.5 µW • Fully-differential analog circuit design • Local Loop card • On-chip precision reference of 1.575 V for a 0 dBm TLP at 600 Ω • SOHO Routers • • VoIP Terminals Push-pull power amplifiers with external gain adjustment with 300 Ω load capability • Enterprise Phones • Seven master clock rates of 256 kHz to 4.096 MHz • ISDN Terminals • Analog line cards • Pin-selectable µ-Law and A-Law companding (compliant with ITU G.711) • Digital Voice Recorders • CODEC A/D and D/A filtering compliant with ITU G.712 • Industrial temperature range (–40°C to +85°C) • Four packages: 24-pin PDIP, SOG, SSOP, and TSSOP -2- (Gateways, W6811 3. BLOCK DIAGRAM Re Int PC cei erf M ve ace Receive PCM Interface BCLKR FSR PCMR G.712 CODEC G.711 µ/A -Law Tra Int ns PC erf mitM ace Transmit PCM Interface BCLKT FST PCMT PAO+ PAOPAI RO AO AI+ AI- µ/A-Law V REF 512 kHz 256 kHz Voltage reference V AG 8 kHz PUI VDDD -3- VSSD Power Conditioning VDDA 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz Pre -scaler Saler VSSA MCLK Publication Release Date: October 23, 2003 Revision A10 W6811 4. TABLE OF CONTENTS 1. GENERAL DESCRIPTION ................................................................................................................. 2 2. FEATURES ......................................................................................................................................... 2 3. BLOCK DIAGRAM .............................................................................................................................. 3 4. TABLE OF CONTENTS ...................................................................................................................... 4 5. PIN CONFIGURATION ....................................................................................................................... 6 6. PIN DESCRIPTION ............................................................................................................................. 7 7. FUNCTIONAL DESCRIPTION............................................................................................................ 9 7.1. Transmit Path............................................................................................................................. 9 7.2. Receive Path............................................................................................................................ 10 7.3. Power Management................................................................................................................. 11 7.3.1. Analog Supply ................................................................................................................ 11 7.3.2. Digital Supply ................................................................................................................. 11 7.3.3. Analog Ground Reference Bypass................................................................................. 11 7.3.4. Analog Ground Reference Voltage Output .................................................................... 11 7.4. PCM Interface .......................................................................................................................... 11 7.4.1. Long Frame Sync ........................................................................................................... 12 7.4.2. Short Frame Sync .......................................................................................................... 12 7.4.3. GCI Interface .................................................................................................................. 12 7.4.4. IDL Interface................................................................................................................... 13 7.4.5. System Timing................................................................................................................ 13 8. TIMING DIAGRAMS.......................................................................................................................... 14 9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 21 9.1. Absolute Maximum Ratings ................................................................................................... 21 9.2. Operating Conditions ............................................................................................................. 21 10. ELECTRICAL CHARACTERISTICS ............................................................................................... 22 10.1. General Parameters .............................................................................................................. 22 10.2. Analog Signal Level and Gain Parameters............................................................................ 23 10.3. Analog Distortion and Noise Parameters .............................................................................. 24 10.4. Analog Input and Output Amplifier Parameters ..................................................................... 25 10.5. Digital I/O ............................................................................................................................... 27 10.5.1. µ-Law Encode Decode Characteristics........................................................................ 27 10.5.2. A-Law Encode Decode Characteristics ....................................................................... 28 10.5.3. PCM Codes for Zero and Full Scale ............................................................................ 29 10.5.4. PCM Codes for 0dBm0 Output .................................................................................... 29 11. TYPICAL APPLICATION CIRCUIT ................................................................................................. 30 -4- W6811 12. PACKAGE SPECIFICATION .......................................................................................................... 32 12.1. 24L TSSOP – 4.4X7.8mm ..................................................................................................... 32 12.2. 24L SOP – 300mil.................................................................................................................. 33 12.3. 24L SSOP – 209mil ............................................................................................................... 34 12.4. 24L PDIP – 300 mil ................................................................................................................ 35 13. ORDERING INFORMATION........................................................................................................... 36 14. VERSION HISTORY ....................................................................................................................... 37 -5- Publication Release Date: October 23, 2003 Revision A10 W6811 5. PIN CONFIGURATION VREF 1 VREF 24 V AG VAG RO - 2 RO- AI+ 23 23 AI+ PAI 3 PAI AI 22- AI- PAO - 4 PAO - AO PAO+ VDDA 5 PAO+ AO 21 /A 20 µ 6 VDDA V 19 SSA VSSA NC VDDD 7 NC 8 VDDD NC 18 V 17 SSD NC VSSD FSR 9 FSR PCMI PCMR 10 PCMI BCLKR 11 BCLKR PUI 12 PUI µ/A-Law FSX 16 16 PCMO 15 FST PCMT BCLKT 14 BCLKT MCLK 13 MCLK PDIP/SOP/SSOP/TSSOP -6- W6811 6. PIN DESCRIPTION Pin Name Pin No. VDD* Functionality VREF 1 A This pin is used to bypass the on-chip 2.5V voltage reference. It needs to be decoupled to VSSA through a 0.1 µF ceramic decoupling capacitor. No external loads should be tied to this pin. RO- 2 A Inverting output of the receive smoothing filter. This pin can typically drive a 2 kΩ load to 1.575 volt peak referenced to the analog ground level. PAI 3 A This pin is the inverting input to the power amplifier. Its DC level is at the VAG voltage. PAO- 4 A Inverting power amplifier output. This pin can drive a 300 Ω load to 1.575 volt peak referenced to the VAG voltage level. PAO+ 5 A Non-inverting power amplifier output. This pin can drive a 300 Ω load to 1.575 Volt peak referenced to the VAG voltage level. VDDA 6 A Analog power supply. This pin should be decoupled to VSSA with a 0.1µF ceramic capacitor. NC 7 VDDD 8 D Digital power supply. This pin should be decoupled to VSSD with a 0.1µF ceramic capacitor. For correct operation, VDDD value should always be lower then VDDA. FSR 9 D 8 kHz Frame Sync input for the PCM receive section. This pin also selects channel 0 or channel 1 in the GCI and IDL modes. It can also be connected to the FST pin when transmit and receive are synchronous operations. PCMR 10 D PCM input data receive pin. The data needs to be synchronous with the FSR and BCLKR pins. BCLKR 11 D PCM receive bit clock input pin. This pin also selects the interface mode. The GCI mode is selected when this pin is tied to VSSD. The IDL mode is selected when this pin is tied to VDDD. This pin can also be tied to the BCLKT when transmit and receive are synchronous operations. PUI 12 D Power up input signal. When this pin is tied to VDDD, the part is powered up. When tied to VSSD, the part is powered down. MCLK 13 D System master clock input. Possible input frequencies are 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz. For a better performance, it is recommended to have the MCLK signal synchronous and aligned to the FST signal. This is a requirement in the case of 256 and 512 kHz frequency. BCLKT 14 D PCM transmit bit clock input pin. PCMT 15 D PCM output data transmit pin. The output data is synchronous with the FST and BCLKT pins. FST 16 D 8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes. Not Connected -7- Publication Release Date: October 23, 2003 Revision A10 W6811 Pin Name Pin No. VDD* Functionality VSSD 17 D This is the digital supply ground. This pin should be connected to 0V. NC 18 VSSA 19 A This is the analog supply ground. This pin should be connected to 0V. µ/A-Law 20 D Compander mode select pin. µ-Law companding is selected when this pin is tied to VDDD. A-Law companding is selected when this pin is tied to VSSD. AO 21 A Analog output of the first gain stage in the transmit path. AI- 22 A Inverting input of the first gain stage in the transmit path. AI+ 23 A Non-inverting input of the first gain stage in the transmit path. VAG 24 A Mid-Supply analog ground pin, which supplies a 2.5 Volt reference voltage for all-analog signal processing. This pin should be decoupled to VSSA with a 0.01µF capacitor. This pin becomes high impedance when the chip is powered down. Not Connected * These columns represent whether the pin Is driven by Analog (‘A’) or Digital (‘D’) power supply. -8- W6811 7. FUNCTIONAL DESCRIPTION W6811 is a single-rail, single channel PCM CODEC for voiceband applications. The CODEC complies with the specifications of the ITU-T G.712 recommendation. The CODEC also includes a complete µLaw and A-Law compander. The µ-Law and A-Law companders are designed to comply with the specifications of the ITU-T G.711 recommendation. The block diagram in section 3 shows the main components of the W6811. The chip consists of a PCM interface, which can process long and short frame sync formats, as well as GCI and IDL formats. The pre-scaler of the chip provides the internal clock signals and synchronizes the CODEC sample rate with the external frame sync frequency. The power conditioning block provides the internal power supply for the digital and the analog section, while the voltage reference block provides a precision analog ground voltage for the analog signal processing. The main CODEC block diagram is shown in section 3. VA VAG G + Receive Path - PAO+ + PAO PAI 8 µ/Aµ/ACont Control ol + D/A Converter w fC= 3400Hz H Smoot Smoothing n Filter 1 RO - Smoothing Smoot nFilter 2 Transmit Path AO 8 A/D Converter µ/A µ/A- Control Cont ++ ffCC = = 200Hz 200 High H Pass High Filt Filter Pas fC== 3400Hz AntH-Aliasi Aliasing Ant i Filter n AI+ AI - Ant-Aliasi Ant-Aliasing Filter Figure 7.1 The W6811 Signal Path 7.1. TRANSMIT PATH The A-to-D path of the CODEC contains an analog input amplifier with externally configurable gain setting (see application examples in section 11). The device has an input operational amplifier whose output is the input to the encoder section. If the input amplifier is not required for operation it can be powered down and bypassed. In that case a single ended input signal can be applied to the AO pin or the AI- pin. The AO pin becomes high input impedance when the input amplifier is powered down. The input amplifier can be powered down by connecting the AI+ pin to VDDA or VSSA. The AO pin is selected as an input when AI+ is tied to VDDA and the AI- pin is selected as an input when AI+ is tied to VSSA (see Table 7.1). -9- Publication Release Date: October 23, 2003 Revision A10 W6811 AI+ Input Amplifier Input VDDA Powered Down AO 1.2 to VDDA-1.2 Powered Up AI+, AI- VSSA Powered Down AI- Table 7.1 Input Amplifier Modes of operation When the input amplifier is powered down, the input signal at AO or AI- needs to be referenced to the analog ground voltage VAG. The output of the input amplifier is fed through a low-pass filter to prevent aliasing at the switched capacitor 3.4 kHz low pass filter. The 3.4 kHz switched capacitor low pass filter prevents aliasing of input signals above 4 kHz, due to the sampling at 8 kHz. The output of the 3.4 kHz low pass filter is filtered by a high pass filter with a 200 Hz cut-off frequency. The filters are designed according to the recommendations in the G.712 ITU-T specification. From the output of the high pass filter the signal is digitized. The signal is converted into a compressed 8-bit digital representation with either µ-Law or ALaw format. The µ-Law or A-Law format is pin-selectable through the µ/A-Law pin. The compression format can be selected according to Table 7.2. µ/A-Law Pin Format VSSA A-Law VDDA µ-Law Table 7.2. Pin-selectable Compression Format The digital 8-bit µ-Law or A-Law samples are fed to the PCM interface for serial transmission at the sample rate supplied by the external frame sync FST. 7.2. RECEIVE PATH The 8-bit digital input samples for the D-to-A path are serially shifted in by the PCM interface and converted to parallel data bits. During every cycle of the frame sync FSR, the parallel data bits are fed through the pin-selectable µ-Law or A-Law expander and converted to analog samples. The mode of expansion is selected by the µ/A-Law pin as shown in Table 7.2. The analog samples are filtered by a low-pass smoothing filter with a 3.4 kHz cut-off frequency, according to the ITU-T G.712 specification. A sin(x)/x compensation is integrated with the low pass smoothing filter. The output of this filter is buffered to provide the receive output signal RO-. The RO- output can be externally connected to the PAI pin to provide a differential output with high driving capability at the PAO+ and PAO- pins. By using external resistors (see section 11 for examples), various gain settings of this output amplifier can be achieved. If the transmit power amplifier is not in use, it can be powered down by connecting PAI to VDDA. - 10 - W6811 7.3. POWER MANAGEMENT 7.3.1. Analog Supply The power supply for the analog part of the W6811 needs to be 5V +/- 10%. This supply voltage is connected to the VDDA pin. The VDDA pin needs to be decoupled to ground through a 0.1 µF ceramic capacitor. 7.3.2. Digital Supply The power supply for the digital part of the W6811 needs to be 3V +/- 10%. This supply voltage is connected to the VDDD pin. The VDDD pin needs to be decoupled to ground through a 0.1 µF ceramic capacitor. 7.3.3. Analog Ground Reference Bypass The system has an internal precision voltage reference which generates the 2.5V mid-supply analog ground voltage. This voltage needs to be decoupled to VSSA at the VREF pin through a 0.1 µF ceramic capacitor. 7.3.4. Analog Ground Reference Voltage Output The analog ground reference voltage is available for external reference at the VAG pin. This voltage needs to be decoupled to VSSA through a 0.01 µF ceramic capacitor. The analog ground reference voltage is generated from the voltage on the VREF pin and is also used for the internal signal processing. 7.4. PCM INTERFACE The PCM interface is controlled by pins BCLKR, FSR, BCLKT & FST. The input data is received through the PCMR pin and the output data is transmitted through the PCMT pin. The modes of operation of the interface are shown in Table 7.3. BCLKR FSR Interface Mode 8 kHz Long or Short Frame Sync VSSD VSSD ISDN GCI with active channel B1 VSSD VDDD ISDN GCI with active channel B2 VDDD VSSD ISDN IDL with active channel B1 VDDD VDDD ISDN IDL with active channel B2 64 kHz MHz to 4.096 Table 7.3 PCM Interface mode selections - 11 - Publication Release Date: October 23, 2003 Revision A10 W6811 7.4.1. Long Frame Sync The Long Frame Sync or Short Frame Sync interface mode can be selected by connecting the BCLKR or BCLKT pin to a 64 kHz to 4.096 MHz clock and connecting the FSR or FST pin to the 8 kHz frame sync. The device synchronizes the data word for the PCM interface and the CODEC sample rate on the positive edge of the Frame Sync signal. It recognizes a Long Frame Sync when the FST pin is held high for two consecutive falling edges of the bit-clock at the BCLKT pin. The length of the Frame Sync pulse can vary from frame to frame, as long as the positive frame sync edge occurs every 125 µsec. During data transmission in the Long Frame Sync mode, the transmit data pin PCMT will become low impedance when the Frame Sync signal FST is high or when the 8 bit data word is being transmitted. The transmit data pin PCMT will become high impedance when the Frame Sync signal FST becomes low while the data is transmitted or when half of the LSB is transmitted. The internal decision logic will determine whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every power down state. More detailed timing information can be found in the interface timing section. 7.4.2. Short Frame Sync The W6811 operates in the Short Frame Sync Mode when the Frame Sync signal at pin FST is high for one and only one falling edge of the bit-clock at the BCLKT pin. On the following rising edge of the bit-clock, the W6811 starts clocking out the data on the PCMT pin, which will also change from high to low impedance state. The data transmit pin PCMT will go back to the high impedance state halfway the LSB. The Short Frame Sync operation of the W6811 is based on an 8-bit data word. When receiving data on the PCMR pin, the data is clocked in on the first falling edge after the falling edge that coincides with the Frame Sync signal. The internal decision logic will determine whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every power down state. More detailed timing information can be found in the interface timing section. 7.4.3. General Circuit Interface (GCI) The GCI interface mode is selected when the BCLKR pin is connected to VSSD for two or more frame sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The GCI interface consists of 4 pins : FSC (FST), DCL (BCLKT), Dout (PCMT) & Din (PCMR). The FSR pin selects channel B1 or B2 for transmit and receive. Data transitions occur on the positive edges of the data clock DCL. The Frame Sync positive edge is aligned with the positive edge of the data clock DCLK. The data rate is running half the speed of the bit-clock. The channels B1 and B2 are transmitted consecutively. Therefore, channel B1 is transmitted on the first 16 clock cycles of DCL and B2 is transmitted on the second 16 clock cycles of DCL. For more timing information, see the timing section. - 12 - W6811 7.4.4. Interchip Digital Link (IDL) The IDL interface mode is selected when the BCLKR pin is connected to VDDD for two or more frame sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The IDL interface consists of 4 pins : IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (PCMT) & IDL RX (PCMR). The FSR pin selects channel B1 or B2 for transmit and receive. The data for channel B1 is transmitted on the first positive edge of the IDL CLK after the IDL SYNC pulse. The IDL SYNC pulse is one IDL CLK cycle long. The data for channel B2 is transmitted on the eleventh positive edge of the IDL CLK after the IDL SYNC pulse. The data for channel B1 is received on the first negative edge of the IDL CLK after the IDL SYNC pulse. The data for channel B2 is received on the eleventh negative edge of the IDL CLK after the IDL SYNC pulse. The transmit signal pin IDL TX becomes high impedance when not used for data transmission and also in the time slot of the unused channel. For more timing information, see the timing section. 7.4.5. System Timing The system can work at 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz master clock rates. The system clock is supplied through the master clock input MCLK and can be derived from the bit-clock if desired. An internal pre-scaler is used to generate a fixed 256 kHz and 8 kHz sample clock for the internal CODEC. The pre-scaler measures the master clock frequency versus the Frame Sync frequency and sets the division ratio accordingly. If the Frame Sync is low for the entire frame sync period while the MCLK and BCLK pin clock signals are still present, the W6811 will enter the low power standby mode. Another way to power down is to set the PUI pin to low. When the system needs to be powered up again, the PUI pin needs to be set to high and the Frame Sync pulse needs to be present. It will take two Frame Sync cycles before the pin PCMT will become low impedance. - 13 - Publication Release Date: October 23, 2003 Revision A10 W6811 8. TIMING DIAGRAMS T FTR H M T FTR SM TM CK L TM CK H T R ISE T FA LL M C LK TM CK T FS T FSL FST T FTR H B C LK T 0 T FTR S 1 T FTFH 2 3 T FD TD TBCK H 4 5 6 7 T B D TD PC M T D7 D6 8 T H ID D5 D4 D3 D2 TBCK L 0 1 TBCK T H ID D1 D0 M SB LSB T FS T FSL FSR T FR R H B C LK R 0 T FR R S 1 T FR FH 2 3 TBCK H 4 5 6 7 8 TBCK L 0 TBCK PC M R D7 M SB TD RS D6 D5 D4 D3 D2 D1 D0 LSB TD RH Figure 8.1 Long Frame Sync PCM Timing - 14 - 1 W6811 SYMBOL DESCRIPTION 1/TFS FST, FSR Frequency 1 MIN TYP MAX UNIT --- 8 --- kHz TFSL FST / FSR Minimum Low Width TBCK sec 1/TBCK BCLKT, BCLKR Frequency 64 --- 4096 kHz TBCKH BCLKT, BCLKR High Pulse Width 50 --- --- ns TBCKL BCLKT, BCLKR Low Pulse Width 50 --- --- ns TFTRH BCLKT 0 Falling Edge to FST Rising Edge Hold Time 20 --- --- ns TFTRS FST Rising Edge to BCLKT 1 Falling edge Setup Time 80 --- --- ns TFTFH BCLKT 2 Falling Edge to FST Falling Edge Hold Time 50 --- --- ns TFDTD FST Rising Edge to Valid PCMT Delay Time --- --- 60 ns TBDTD BCLKT Rising Edge to Valid PCMT Delay Time --- --- 60 ns THID Delay Time from the Later of FST Falling Edge, or 10 --- 60 ns BCLKT 8 Falling Edge to PCMT Output High Impedance TFRRH BCLKR 0 Falling Edge to FSR Rising Edge Hold Time 20 --- --- ns TFRRS FSR Rising Edge to BCLKR 1 Falling edge Setup Time 80 --- --- ns TFRFH BCLKR 2 Falling Edge to FSR Falling Edge Hold Time 50 --- --- ns TDRS Valid PCMR to BCLKR Falling Edge Setup Time 0 --- --- ns TDRH PCMR Hold Time from BCLKR Falling Edge 50 --- --- ns Table 8.1 Long Frame Sync PCM Timing Parameters 1 TFSL must be at least ≥ TBCK - 15 - Publication Release Date: October 23, 2003 Revision A10 W6811 T FTR H M T FTR SM TM CK L TM CK H T R ISE T FA LL M C LK TM CK T FS T FTFH T FTFS FST T FTR S T FTR H B C LK T -1 0 TBCK H 1 2 3 T B D TD PC M T D7 4 5 6 7 0 8 T B D TD D6 D5 D3 D2 1 TBCK T H ID D4 TBCK L D1 D0 M SB LSB T FS T FR FH T FR FS FSR T FR R S T FR R H B C LK R -1 0 TBCK H 1 2 3 4 5 6 7 8 TBCK L 0 TBCK PC M R D7 M SB TD RS D6 D5 D4 D3 D2 D1 D0 LSB TD RH Figure 8.2 Short Frame Sync PCM Timing - 16 - 1 W6811 SYMBOL DESCRIPTION MIN TYP MAX UNIT 1/TFS FST, FSR Frequency --- 8 --- kHz 1/TBCK BCLKT, BCLKR Frequency 64 --- 4096 kHz TBCKH BCLKT, BCLKR High Pulse Width 50 --- --- ns TBCKL BCLKT, BCLKR Low Pulse Width 50 --- --- ns TFTRH BCLKT –1 Falling Edge to FST Rising Edge Hold Time 20 --- --- ns TFTRS FST Rising Edge to BCLKT 0 Falling edge Setup Time 80 --- --- ns TFTFH BCLKT 0 Falling Edge to FST Falling Edge Hold Time 50 --- --- ns TFTFS FST Falling Edge to BCLKT 1 Falling Edge Setup Time 50 --- --- ns TBDTD BCLKT Rising Edge to Valid PCMT Delay Time 10 --- 60 ns THID Delay Time from BCLKT 8 Falling Edge to PCMT Output High Impedance 10 --- 60 ns TFRRH BCLKR –1 Falling Edge to FSR Rising Edge Hold Time 20 --- --- ns TFRRS FSR Rising Edge to BCLKR 0 Falling edge Setup Time 80 --- --- ns TFRFH BCLKR 0 Falling Edge to FSR Falling Edge Hold Time 50 --- --- ns TFRFS FSR Falling Edge to BCLKR 1 Falling Edge Setup Time 50 --- --- ns TDRS Valid PCMR to BCLKR Falling Edge Setup Time 0 --- --- ns TDRH PCMR Hold Time from BCLKR Falling Edge 50 --- --- ns Table 8.2 Short Frame Sync PCM Timing Parameters - 17 - Publication Release Date: October 23, 2003 Revision A10 W6811 T FS FST T FSFH T FSR S T FSR H B C LK T -1 0 1 TBCK H 2 3 4 5 T B D TD PC M T 6 8 9 10 T H ID TBD TD D7 D6 D5 D4 D3 D2 D1 D0 M SB LSB TD RS PC M R 7 11 12 13 14 LSB 17 18 T H ID TBD TD D7 D6 D5 D4 D3 D2 D1 D0 LSB M SB TD RS D7 D6 D5 D4 D3 D2 D1 D0 16 TBCK T B D TD TD RH M SB 15 TBCK L TD RH D7 D6 D5 D4 D3 D2 D1 D0 M SB LSB BCH = 0 B 1 C hannel BCH = 1 B 2 C hannel Figure 8.3 IDL PCM Timing SYMBOL DESCRIPTION MIN TYP MAX UNIT 1/TFS FST Frequency --- 8 --- kHz 1/TBCK BCLKT Frequency 256 --- 4096 kHz TBCKH BCLKT High Pulse Width 50 --- --- ns TBCKL BCLKT Low Pulse Width 50 --- --- ns TFSRH BCLKT –1 Falling Edge to FST Rising Edge Hold Time 20 --- --- ns TFSRS FST Rising Edge to BCLKT 0 Falling edge Setup Time 60 --- --- ns TFSFH BCLKT 0 Falling Edge to FST Falling Edge Hold Time 20 --- --- ns TBDTD BCLKT Rising Edge to Valid PCMT Delay Time 10 --- 60 ns THID Delay Time from the BCLKT 8 Falling Edge (B1 channel) or BCLKT 18 Falling Edge (B2 Channel) to PCMT Output High Impedance 10 --- 50 ns TDRS Valid PCMR to BCLKT Falling Edge Setup Time 20 --- --- ns TDRH PCMR Hold Time from BCLKT Falling Edge 75 --- --- ns Table 8.3 IDL PCM Timing Parameters - 18 - W6811 T FS FST T FSR H T FSFH T FSR S TBCK H TBCK L B C LK T 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 T FD TD PC M T T B D TD D7 D6 D5 D4 D3 D2 D1 D0 T B D TD TD RS D7 D6 D5 D4 D3 D2 D1 D0 LSB TD RS TD RH TD RH D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 M SB T H ID T B D TD T B C K LSB M SB M SB PC M R T H ID D1 D0 LSB M SB BCH = 0 B 1 C hannel LSB BCH = 1 B 2 C hannel Figure 8.4 GCI PCM Timing SYMBOL DESCRIPTION MIN TYP MAX UNIT 1/TFST FST Frequency --- 8 --- kHz 1/TBCK BCLKT Frequency 512 --- 6176 kHz TBCKH BCLKT High Pulse Width 50 --- --- ns TBCKL BCLKT Low Pulse Width 50 --- --- ns TFSRH BCLKT 0 Falling Edge to FST Rising Edge Hold Time 20 --- --- ns TFSRS FST Rising Edge to BCLKT 1 Falling edge Setup Time 60 --- --- ns TFSFH BCLKT 1 Falling Edge to FST Falling Edge Hold Time 20 --- --- ns TFDTD FST Rising Edge to Valid PCMT Delay Time --- --- 60 ns TBDTD BCLKT Rising Edge to Valid PCMT Delay Time --- --- 60 ns THID Delay Time from the BCLKT 16 Falling Edge (B1 channel) or BCLKT 32 Falling Edge (B2 Channel) to PCMT Output High Impedance 10 --- 50 ns TDRS Valid PCMR to BCLKT Rising Edge Setup Time 20 --- --- ns TDRH PCMR Hold Time from BCLKT Rising Edge --- --- 60 ns Table 8.4 GCI PCM Timing Parameters - 19 - Publication Release Date: October 23, 2003 Revision A10 W6811 SYMBOL DESCRIPTION MIN 1/TMCK Master Clock Frequency --- TYP 256 MAX UNIT --- kHz 512 1536 1544 2048 2560 4096 TMCKH / TMCK MCLK Duty Cycle for 256 kHz Operation 45% TMCKH Minimum Pulse Width High for MCLK(512 kHz or Higher) 50 --- --- ns TMCKL Minimum Pulse Width Low for MCLK (512 kHz or Higher) 50 --- --- ns TFTRHM MCLK falling Edge to FST Rising Edge Hold Time 50 --- --- ns TFTRSM FST Rising Edge to MCLK Falling edge Setup Time 50 --- --- ns TRISE Rise Time for All Digital Signals --- --- 50 ns TFALL Fall Time for All Digital Signals --- --- 50 ns Table 8.5 General PCM Timing Parameters - 20 - 55% W6811 9. ABSOLUTE MAXIMUM RATINGS 9.1. ABSOLUTE MAXIMUM RATINGS Condition Value Junction temperature 1500C Storage temperature range -650C to +1500C Voltage Applied to any pin Voltage applied to any pin (Input current limited to +/-20 mA) Lead temperature (soldering (VSSA - 0.3V) to (VDDA + 0.3V) Digital (VSSD - 0.3V) to (VDDD + 0.3V) Analog (VSSA – 1.0V) to (VDDA + 1.0V) Digital (VSSD – 1.0V) to (VDDD + 1.0V) 3000C – 10 seconds) VDDA - VSSA ; VDDD - VSSD VDDD – Analog -0.5V to +6V VDDA2 < 0.3V 1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings may affect device reliability. Functional operation is not implied at these conditions. 2. At any time, the digital power supply should not be higher the 0.3V from the analog power supply. 9.2. OPERATING CONDITIONS Condition Value 0 0 Industrial operating temperature -40 C to +85 C Analog supply voltage (VDDA) +4.5V to +5.5V Digital supply voltage (VDDD) +2.7V to +3.3V Ground voltage (VSSA, VSSD) 0V Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. - 21 - Publication Release Date: October 23, 2003 Revision A10 W6811 10. ELECTRICAL CHARACTERISTICS 10.1. GENERAL PARAMETERS Typ (1) Max (2) Units 0.5 V Parameters VIL Input Low Voltage VIH Input High Voltage VOL PCMT Output Low Voltage IOL = 1.6 mA VOH PCMT Output High Voltage IOL = -1.6 mA IDDA VDDA Current (Operating) -ADC+DAC PUI = 1 5.5 8 mA FSX running MCLK running 25 1000 µA PUI = 1 200 500 nA FSX = 0 MCLK running 0.2 100 µA IDDD ISBA VCCA Current (Standby) ISBD Conditions Min (2) Symbol 2.2 V 0.4 VDDD – 0.5 V V IPDA VCCA Current (Power Down) PUI = 0 200 500 nA IPDD VCCD Current (Power Down) PUI = 0 200 500 nA IIL Input Leakage Current VSSD<VIN<VDDD +/-10 µA IOL PCMT Output Leakage Current VSSA<PCMT<VDDA +/-10 µA 10 pF 15 pF High Z State CIN Digital Input Capacitance COUT PCMT Output Capacitance PCMT High Z 1. Typical values: TA = 25°C , VDDA = 5.0 V, VDDD = 3.0 V 2. All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100 percent tested. - 22 - W6811 10.2. ANALOG SIGNAL LEVEL AND GAIN PARAMETERS VDDA=5V ±10%; VSSA=0V; TA=-40°C to +85°C; all analog signals referred to VAG; PARAMETER SYM. CONDITION TYP. TRANSMIT (A/D) MIN. RECEIVE (D/A) MAX. MIN. MAX. UNIT Absolute Level LABS 0 dBm0 = 0dBm @ 600Ω 1.096 --- --- --- --- VPK Max. Transmit Level TXMAX 3.17 dBm0 for µ-Law 1.579 --- --- --- --- VPK 3.14 dBm0 for A-Law 1.573 --- --- --- --- VPK Absolute Gain (0 dBm0 @ 1020 Hz; TA=+25°C) GABS 0 dBm0 @ 1020 Hz; TA=+25°C 0 -0.25 +0.25 -0.25 +0.2 5 dB Absolute Gain variation with Temperature GABS TA=0°C to TA=+70°C 0 -0.03 +0.03 -0.03 dB T TA=-40°C to TA=+85°C -0.05 +0.05 -0.05 +0.0 3 Frequency Response, GRTV Relative to 0dBm0 @ 1020 Hz +0.0 5 15 Hz --- --- -40 -0.5 0 50 Hz --- --- -30 -0.5 0 60 Hz --- --- -26 -0.5 0 200 Hz --- -1.0 -0.4 -0.5 0 300 to 3000 Hz --- -0.20 +0.15 -0.20 3300 Hz --- -0.35 +0.15 -0.35 +0.1 5 3400 Hz --- -0.8 0 -0.8 3600 Hz --- --- 0 --- 4000 Hz --- --- -14 --- 4600 Hz to 100 kHz --- --- -32 --- dB +0.1 5 0 0 -14 -30 Gain Variation vs. Level Tone (1020 Hz relative to –10 dBm0) GLT +3 to –40 dBm0 --- -0.3 +0.3 -0.2 +0.2 -40 to –50 dBm0 --- -0.6 +0.6 -0.4 +0.4 -50 to –55 dBm0 --- -1.6 +1.6 -1.6 +1.6 - 23 - dB Publication Release Date: October 23, 2003 Revision A10 W6811 10.3. ANALOG DISTORTION AND NOISE PARAMETERS VDDA=5V ±10%; VSSA=0V; TA=-40°C to +85°C; all analog signals referred to VAG; PARAMETER SYM. CONDITION TRANSMIT (A/D) MIN. Total Distortion vs. Level Tone (1020 Hz, µ-Law, C-Message Weighted) Total Distortion vs. Level Tone (1020 Hz, A-Law, Psophometric Weighted) DLTµ TYP. MAX . 36 --- --- 36 --- -40 dBm0 29 -45 dBm0 25 TYP. MAX. 34 --- --- --- 36 --- --- --- --- 30 --- --- --- --- 25 --- --- +3 dBm0 36 --- --- 34 --- --- 36 --- --- 36 --- --- -40 dBm0 29 --- --- 30 --- --- -45 dBm0 25 --- --- 25 --- --- +3 dBm0 0 dBm0 to -30 dBm0 DLTA 0 dBm0 to -30 dBm0 Spurious Out-Of-Band at RO- (300 Hz to 3400 Hz @ 0dBm0) DSPO Spurious In-Band (700 Hz to 1100 Hz @ 0dBm0) RECEIVE (D/A) MIN. UNIT dBC dBp 4600 Hz to 7600 Hz --- --- --- --- --- -30 7600 Hz to 8400 Hz --- --- --- --- --- -40 8400 Hz to 100000 Hz --- --- --- --- --- -30 DSPI 300 to 3000 Hz --- --- -47 --- --- -47 dB Intermodulation Distortion (300 Hz to 3400 Hz –4 to –21 dBm0 DIM Two tones --- --- -41 --- --- -41 dB Crosstalk (1020 Hz @ 0dBm0) DXT --- --- -75 --- --- -75 dBm0 Absolute Group Delay τABS 1200 Hz --- --- 360 --- --- 240 µsec Group Delay Distortion (relative to group delay @ 1200 Hz) τD 500 Hz --- --- 750 --- --- 750 µsec 600 Hz --- --- 380 --- --- 370 1000 Hz --- --- 130 --- --- 120 2600 Hz --- --- 130 --- --- 120 2800 Hz --- --- 750 --- --- 750 µ-Law; C-message --- --- 5 --- --- 13 dBrnc A-Law; Psophometric --- --- -69 --- --- -79 dBm0p Idle Channel Noise NIDL - 24 - dB W6811 10.4. ANALOG INPUT AND OUTPUT AMPLIFIER PARAMETERS VDDA=5V ±10%; VSSA=0V; TA=-40°C to +85°C; all analog signals referred to VAG; PARAMETER SYM. CONDITION MIN. TYP. MAX. UNIT. AI Input Offset Voltage VOFF,AI AI+, AI- --- --- ±25 mV AI Input Current IIN,AI AI+, AI- --- ±0.1 ±1.0 µA AI Input Resistance RIN,AI AI+, AI- to VAG 10 --- --- MΩ AI Input Capacitance CIN,AI AI+, AI- --- --- 10 pF AI Common Mode Input Voltage Range VCM,AI AI+, AI- 1.2 --- VDDA-1.2 V AI Common Mode Rejection Ratio CMRRTI AI+, AI- --- 60 --- dB AI Amp Gain Bandwidth Product GBWTI AO, RLD≥10kΩ --- 2150 --- kHz AI Amp DC Open Loop Gain GTI AO, RLD≥10kΩ --- 95 --- dB AI Amp Equivalent Input Noise NTI C-Message Weighted --- -24 --- dBrnC AO Output Voltage Range VTG RLD=10kΩ to VAG 0.5 1.0 --- VDDA-0.5 V --- VDDA-1.0 RLD=2kΩ to VAG Load Resistance RLDTGRO AO, RO to VAG 2 --- --- kΩ Load Capacitance CLDTGRO AO, RO --- --- 100 pF AO & RO Output Current IOUT1 0.5 ≤AO,RO-≤ VDDA-0.5 ±1.0 --- --- mA RO- Output Resistance RRO- RO-, 0 to 3400 Hz --- 1 --- Ω RO- Output Offset Voltage VOFF,RO- RO- to VAG --- --- ±25 mV Analog Ground Voltage VAG Relative to VSSA 2.429 2.5 2.573 V VAG Output Resistance RVAG Within ±25mV change --- 2.5 12.5 Ω Power Supply Rejection Ratio (0 to 100 kHz to VDDA, Cmessage) PSRR Transmit 30 80 --- dBC Receive 30 75 --- PAI Input Offset Voltage VOFF,PAI PAI --- --- ±20 mV PAI Input Current IIN,PAI PAI --- ±0.05 ±1.0 µA PAI Input Resistance RIN,PAI PAI to VAG 10 --- --- MΩ PAI Amp Gain Bandwidth Product GBWPI PAO- no load --- 1000 --- kHz - 25 - Publication Release Date: October 23, 2003 Revision A10 W6811 PARAMETER SYM. CONDITION MIN. TYP. MAX. UNIT. Output Offset Voltage VOFF,PO PAO+ to PAO- --- --- ±50 mV Load Resistance RLDPO PAO+, PAOdifferentially 300 --- --- Ω Load Capacitance CLDPO PAO+, PAOdifferentially --- --- 1000 pF PO Output Current IOUTPO 0.5 ≤AO,RO-≤ VDDA-0.5 ±10.0 --- --- mA PO Output Resistance RPO PAO+ to PAO- --- 1 --- Ω PO Differential Gain GPO RLD=300Ω, +3dBm0, 1 kHz, PAO+ to PAO- -0.2 0 +0.2 dB PO Differential Signal to Distortion C-Message weighted DPO ZLD=300Ω 45 60 --- dBC ZLD=100nF + 100Ω --- 40 --- ZLD=100nF + 20Ω --- 40 --- 0 to 4 kHz 40 55 --- 4 to 25 kHz --- 40 --- PO Power Supply Rejection Ratio (0 to 25 kHz to VDDA, Differential out) PSRRPO - 26 - dB W6811 10.5. DIGITAL I/O 10.5.1. µ-Law Encode Decode Chatacteristics Normalized Encode Decision Levels 8159 7903 Normalized Digital Code D7 D6 D5 D4 D3 D2 D1 D0 Sign Chord Chord Chord Step Step Step Step 1 0 0 0 0 0 0 0 4063 1 0 0 0 1 1 1 1 2015 1 0 0 1 1 1 1 1 991 1 0 1 0 1 1 1 1 479 1 0 1 1 1 1 1 1 223 1 1 0 0 1 1 1 1 95 1 1 0 1 1 1 1 1 31 1 1 1 0 1 1 1 1 1 0 33 : : 3 99 : : 35 231 : : 103 495 : : 239 1023 : : 511 2079 : : 1055 4191 : : 2143 8031 : : 4319 Decode Levels 1 1 1 1 1 1 1 0 2 1 1 1 1 1 1 1 1 0 Notes: Sign bit = 0 for negative values, sign bit = 1 for positive values - 27 - Publication Release Date: October 23, 2003 Revision A10 W6811 10.5.2. A-Law Encode Decode Characteristics Normalized Encode Decision Levels 4096 3968 Digital Code Normalized D7 D6 D5 D4 D3 D2 D1 D0 Sign Chord Chord Chord Step Step Step Step 1 0 1 0 1 0 1 0 2048 1 0 1 0 0 1 0 1 1024 1 0 1 1 0 1 0 1 512 1 0 0 0 0 1 0 1 256 1 0 0 1 0 1 0 1 128 1 1 1 0 0 1 0 1 64 1 1 1 0 0 1 0 1 0 66 : : 2 132 : : 68 264 : : 136 528 : : 272 1056 : : 544 2112 : : 1088 4032 : : 2048 Decode Levels 1 1 0 1 0 1 Notes: 1. Sign bit = 0 for negative values, sign bit = 1 for positive values 2. Digital code includes inversion of all even number bits - 28 - 0 1 1 W6811 10.5.3. PCM Codes for Zero and Full Scale µ-Law Level A-Law Sign bit Chord bits Step bits Sign bit Chord bits Step bits (D7) (D6,D5,D4) (D3,D2,D1,D0) (D7) (D6,D5,D4) (D3,D2,D1,D0) + Full Scale 1 000 0000 1 010 1010 + Zero 1 111 1111 1 101 0101 - Zero 0 111 1111 0 101 0101 - Full Scale 0 000 0000 0 010 1010 10.5.4. PCM Codes for 0dBm0 Output µ-Law Sample A-Law Sign bit Chord bits Step bits Sign bit Chord bits Step bits (D7) (D6,D5,D4) (D3,D2,D1,D0) (D7) (D6,D5,D4) (D3,D2,D1,D0) 1 0 001 1110 0 011 0100 2 0 000 1011 0 010 0001 3 0 000 1011 0 010 0001 4 0 001 1110 0 011 0100 5 1 001 1110 1 011 0100 6 1 000 1011 1 010 0001 7 1 000 1011 1 010 0001 8 1 001 1110 1 011 0100 - 29 - Publication Release Date: October 23, 2003 Revision A10 W6811 11. TYPICAL APPLICATION CIRCUIT 0.01 µF 0.1 µF 27k Ω 27k Ω V AUDIOOUT + V DDA V DDD 0.1 µF 0.1 µF 1 V REF V AG 24 2 RO - AI+ 23 3 PAI AI- 22 4 PAO - AO 21 5 PAO+ µ/A 20 6 V DDA V SSA 19 7 NC 8 V DDD NC 18 V SSD 17 9 FSR Power Control 10 PCMR PCMI FSX 16 FST 16 PCMT 15 PCMO 15 11 BCLKR BCLKT 14 12 PUI MCLK 13 V AUDIOIN+ 27k Ω 27k Ω 27k Ω 27k Ω 1.0 µF 1.0 µF V AUDIOIN V DDD 8 kHz PCM OUT 2.048 MHz PDIP/SOG/SSOP/TSSOP PCM IN Figure 11.1 Typical circuit for Differential Analog I/O’s AUDIO OUT RL ≥ 2kΩ 0.01µF 0.1µF AUDIO OUT RL ≥ 150Ω 27kΩ 27kΩ VAG 24 2 RO- AI+ 23 3 PAI AI- 22 5 PAO+ 0.1µF 0.1µF 27kΩ 27kΩ 27kΩ 27kΩ AO 21 µ/A 20 4 PAO- 100µF VDDA VDDD 1 VREF 6 VDDA VSSA 19 7 NC 8 VDDD NC 18 VSSD 17 9 FSR FST 16 FSX 16 PCMO 15 PCMT 15 10 PCMR PCMI 11 BCLKR BCLKT 14 Power Control 12 PUI 1.0 µF 1.0 µF VAUDIOIN VDD 8 kHz PCM OUT 2.048 MHz MCLK 13 PDIP/SOG/SSOP/TSSOP PCM IN Figure 11.2 Typical circuit for Single Ended Analog I/O’s - 30 - W6811 1k Ω 200 p F Electret Microphone WM-54B Panasonic 0.01 µF 0.1 µF Speake 27k Ω 27k Ω 1 V REF VAG 24 2 RO - AI+ 23 3 PAI AI- 22 4 PAO VDDA 0.1 µF VDDD 0.1 µF 5 PAO+ AO 21 µ/A 20 6 V DDA VSSA 19 7 NC 8 V DDD NC 18 VSSD 17 9 FSR Power Control 10 PCMR PCMI FSX 16 FST 16 PCMT 15 PCMO 15 11 BCLKR BCLKT 14 12 PUI MCLK 13 100k Ω 100k Ω 1k Ω 1k Ω 1.5kΩ 1.0 µF 1.0 µF VDD 1.5kΩ 8 kHz PCM OUT 2.048 MHz 27k Ω PDIP/SOG/SSOP/TSSOP PCM IN Figure 11.3 Handset Interface 0.01µF 0.1µF TIP 600 Ω 600Ω N= 1 27kΩ 27kΩ N= 1 1 VREF VAG 24 2 RO- AI+ 23 3 PAI AI- 22 6 VDDA AO 21 µ/A 20 VSSA 19 7 NC 8 VDDD NC 18 VSSD 17 9 FSR FSX 16 FST 16 PCMT 15 PCMO 15 4 PAO5 PAO+ RI NG 0.1µF VDDD 0.1µF 10 PCMR PCMI 27kΩ 11 BCLKR BCLKT 14 Power Control 12 PUI 27kΩ 1.0 µF VDD 8 kHz PCM OUT 4.096 MHz MCLK 13 PDIP/SOG/SSOP/TSSOP PCM IN B1 – 0V B2 - +5V Figure 11.4 Transformer Interface Circuit in GCI mode - 31 - Publication Release Date: October 23, 2003 Revision A10 W6811 12. PACKAGE SPECIFICATION 12.1. 24L TSSOP - 4.4X7.8MM PLASTIC THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) DIMENSIONS DIMENSION IN MM SYMBOL MIN NOM A DIMENSION IN INCH MAX MIN NOM 1.20 A1 0.05 A2 0.80 L 0.50 E MAX 0.043 0.15 0.002 0.90 1.05 0.031 0.035 0.041 0.60 0.75 0.020 0.024 0.030 6.40 BSC. 0.006 0.252 BSC. HE 4.30 4.40 4.50 0.169 0.173 0.177 D 7.70 7.80 7.90 0.303 0.307 0.311 b 0.19 0.30 0.007 c 0.09 0.20 0.004 0.012 0.008 L1 1.0 REF. 0.039 REF e 0.65 BSC. 0.026 BSC 01 0 8 - 32 - 0 8 W6811 12.2. 24L SOP-300MIL SMALL OUTLINE PACKAGE (SAME AS SOG & SOIC) DIMENSIONS 11 20 E 10 1 GAUGE PLANE SEATING PLANE DIMENSIONS IN MM SYMBOL DIMENSIONS IN INCH MIN MAX MIN MAX A 2.35 2.65 0.093 0.104 A1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 E 7.40 7.60 0.291 0.299 D 12.60 13.00 0.946 0.512 e HE 1.27 BSC. 10.00 Y 0.050 BSC. 1065 0.394 0.10 0.419 0.004 L 0.40 1.27 0.016 0.050 0 0 8 0 8 - 33 - Publication Release Date: October 23, 2003 Revision A10 W6811 12.3. 24L SSOP-209 MIL SHRINK SMALL OUTLINE PACKAGE DIMENSIONS - 34 - W6811 12.4. 24L PDIP – 300 MIL PLASTIC DUAL INLINE PACKAGE DIMENSIONS D 24 13 1 12 1 E E S c 1 2 AA A L Base Plane Mounting Plane B e1 DIMENSION IN MM SYMBOL MIN NOM A A1 eA á B1 DIMENSION IN INCH MAX MIN NOM 4.45 0.25 MAX 0.175 0.010 A2 3.18 3.30 3.43 0.125 0.130 0.135 B 0.41 0.46 0.56 0.016 0.018 0.022 B1 1.47 1.52 1.63 0.058 0.060 0.064 c 0.20 0.25 0.36 0.008 0.010 0.014 31.95 32.26 1.258 1.270 D E 7.37 7.62 7.87 0.290 0.300 0.310 E1 6.43 6.55 6.68 0.253 0.258 0.263 e1 2.29 2.54 2.79 0.090 0.100 0.110 L 3.05 3.30 3.56 0.120 0.130 0.140 á 0° 15° 0° eA 8.38 9.40 0.330 S 8.89 2.29 - 35 - 15° 0.350 0.370 0.090 Publication Release Date: October 23, 2003 Revision A10 W6811 13. ORDERING INFORMATION Part Number Description W6811I _ Package Type: Product Family W6811 Product W = 24-Lead Plastic Thin Small Outline Package (TSSOP) Type 1 S = 24-Lead Plastic Small Outline Package (SOG/SOP) R = 24-Lead Plastic Small Outline Package (SSOP) E = 24-Lead Plastic Dual Inline Package (PDIP) When ordering W6811 series devices, please refer to the following part numbers. Part Number W6811IW W6811IS W6811IR W6811IE - 36 - W6811 14. VERSION HISTORY VERSION DATE A7 August 9, 2002 A8 Septembe r 26, 2002 A9 October 10, 2002 A10 October 23, 2003 PAGE DESCRIPTION Preliminary 34 Changed the package dimention of the SSOP24 package The information contained in this datasheet may be subject to change without notice. It is the responsibility of the customer to check the Winbond USA website (www.winbond-usa.com) periodically for the latest version of this document, and any Errata Sheets that may be generated between datasheet revisions. Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd. III Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 http://www.winbond-usa.com/ 27F, 299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62356998 Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd. 9F, No. 480, Pueiguang Rd. Neihu District, Taipei, 114, Taiwan TEL: 886-2-81777168 FAX: 886-2-87153579 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. - 37 - Publication Release Date: October 23, 2003 Revision A10