Preliminary W83178S 100 MHZ 3-DIMM SDRAM BUFFER 1. GENERAL DESCRIPTION The W83178S is a 13 outputs SDRAM clock buffer for 3-DIMMs models incorporate with W83196S14 which is the clock synthesizer especially for the 100 MHz models such as Intel BX chipsets. (Refer the datasheet fo Winbond W83196S-14) The W83178S receives the clock from chipset by the Buffer_In pin and provides almost zero-delay (less than 4 nS propagation delay) SDRAM buffer outputs for the 13 SDRAM clocks which are synchronous with the CPU clock outputs priovided by W83196S-14. The clock skew between any two clock outputs is less than 250 pS and the output buffer impedance is about 15 ohms. The W83178S also provides I2C serial bus interface to program the registers to enable or disable each SDRAM clock outputs. 2. FEATURES • Supports Intel Pentium II CPUs for BX chipset • 13 SDRAM clocks for 3-DIMMs • Clock skew less than 250 pS • Almost none delay Buffer-in controlling SDRAM clocks(<4 nS propagation delay) • I2C 2-wire serial interface • Programmable registers to enable/stop each output • Incorporate with W83196S-14 • Packaged in 28-pin SOP 3. PIN CONFIGURATION VDD SDRAM 0 SDRAM 1 Vss VDD SDRAM 2 SDRAM 3 Vss BUFFER_IN SDRAM 4 SDRAM 5 SDRAM12 VDD *SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 -1- VDD SDRAM11 SDRAM10 Vss VDD SDRAM 9 SDRAM 8 Vss VDD SDRAM 7 SDRAM 6 Vss Vss *SCLOCK Publication Release Date: March 1999 Revision A1 Preliminary W83178S 4. BLOCK DIAGRAM SDATA Serial port device Control SCLK SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 Buffer_In SDRAM8 SDRAM9 SDRAM10 SDRAM11 SDRAM12 5. PIN DESCRIPTION IN - Input OUT - Output I/O - Bi-directional Pin * - Internal 250K Ω pull-up SYMBOL PIN I/O 2, 3, 6, 7, 10, 11, 12, 18, 19, 22, 23, 26, 27 O SDRAM clock outputs which have the same frequency as CPU clocks. *SDATA 14 I/O Serial data of I2C 2-wire control interface *SDCLK 15 IN Serial clock of I2C 2-wire control interface BUFFER_IN 9 IN Clock Input from the chipset VDD 1, 5, 13, 20, 24, 28 - Power supply Vss 4, 8, 16, 17, 21, 25 - Circuit ground SDRAM [ 0:12] FUNCTION -2- Preliminary W83178S 6. FUNCTIONAL DESCRIPTION 6.1 2-Wire I2C Control Interface The clock generator is a slave I2C component which can be read back the data stored in the latches for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire control interface allows each clock output individually enabled or disabled. On power up, the W83178S initializes with default register settings, and then it’optional to use the 2-wire control interface. The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-tohigh transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated. Byte writing starts with a start condition followed by 7-bit slave address and [1101 0010], command code checking [0000 0000], and byte count checking. After successful reception of each byte, an acknowledge (low) on the SDATA wire will be generated by the clock chip. Controller can start to write to internal I2C registers after the string of data. The sequence order is as follows: Bytes sequence order for I2C controller: Clock Address A(6:0) & R/W Ack 8 bits dummy Command code Ack 8 bits dummy Byte count Ack Byte0,1,2... until Stop Ack Byte2, 3, 4... until Stop Set R/W to 1 when read back the data sequence is as follows: Clock Address A(6:0) & R/W Ack Byte 0 Ack Byte 1 6.2 Serial Control Registers The Pin column lists the affected pin number and the @PowerUp column gives the state at true power up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and acknowledged. 6.2.1 Register 0: (1 = Active, 0 = Inactive) BIT 7 6 5 4 3 2 1 0 @POWERUP 1 1 1 1 1 1 PIN 11 10 7 6 3 2 DESCRIPTION SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) Reserved Reserved SDRAM3 (Active/Inactive) SDRAM2 (Active/Inactive) SDRAM1 (Active/Inactive) SDRAM0 (Active/Inactive) -3- Publication Release Date: March 1999 Revision A1 Preliminary W83178S 6.2.2 Register 1: (1 = Active, 0 = Inactive) BIT @POWERUP PIN DESCRIPTION 7 1 27 SDRAM11 (Active/Inactive) 6 1 28 SDRAM10 (Active/Inactive) 5 1 23 SDRAM9 (Active/Inactive) 4 1 22 SDRAM8 (Active/Inactive) 3 1 - Reserved 2 1 - Reserved 1 1 19 SDRAM7 (Active/Inactive) 0 1 18 SDRAM6 (Active/Inactive) 6.2.3 Register 2: (1 = Active, 0 = Inactive) BIT @POWERUP PIN DESCRIPTION 7 x - 6 1 12 5 x - Reserved 4 x - Reserved 3 x - Reserved 2 x - Reserved 1 x - Reserved 0 x - Reserved Reserved SDRAM12 (Active/Inactive) 7.0 SPECIFICATIONS 7.1 Absolute Maximum Ratings Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD). PARAMETER SYMBOL RATING VDD, VIN -0.5V to +7.0V Storage Temperature TSTG -65° C to +150° C Ambient Temperature TB -55° C to +125° C Operating Temperature TA 0° C to +70° C Voltage on any pin with respect to GND Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. -4- Preliminary W83178S 7.2 AC Characteristics VDD = 3.3V ±5 % , TA = 0° C to +70° C, Test load = 30 pF PARAMETER SYM. MIN. Input Frequency FIN Output Rise Time Output Fall Time TYP. MAX. UNITS 0 150 MHz TR 1.5 4.0 V/nS Measured from 0.4V to 2.4V TF 1.5 4.0 V/nS Measured from 0.4V to 2.4V Output Skew, Rising Edges TSR 250 pS Output Skew, Falling Edges TSF 250 pS Output Enable Time TEN 1.0 8.0 nS Output Disable Time TDIS 1.0 8.0 nS Rising Edge Propagation Delay TPR 1.0 <4.0 nS Falling Edge Propagation Delay TPF 1.0 <4.0 nS Duty Cycle TD 45 55 % AC Output Impedance ZO TEST CONDITIONS Measure at 1.5V Ω 15 7.3 DC Characteristics VDD = 3.3V ±5 %, TA = 0° C to +70° C PARAMETER SYM. MIN. Input Low Voltage VIL Input High Voltage TYP. MAX. UNITS TEST CONDITIONS Vss -03 0.8 Vdc VIH 2.0 VDD +0.5 Vdc Input Leakage Current, BUFFER_IN IIL -5 +5 µA Input Leakage Current IIL -20 +5 µA 50 mVdc IOL = 1 mA Vdc IOH = -1 mA Output Low Voltage VOL Output High Voltage VOH 3.1 Output Low Current IOL 65 100 160 mA VOL = 1.5V Output High Current IOH 70 110 185 mA VOH = 1.5V Input Pin Capacitance CIN 5 pF COUT 6 pF LIN 7 nH Output Pin Capacitance Input Pin Inductance -5- Publication Release Date: March 1999 Revision A1 Preliminary W83178S 8. ORDERING INFORMATION PART NUMBER PACKAGE TYPE PRODUCTION FLOW W83178S 28-pin SOP Commercial, 0° C to +70° C 9. HOW TO READ THE TOP MARKING W83178S 28051234 814GBB 1st line: Winbond logo and the type number: W83178S 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G B B 814: packages made in '98, week 14 G: assembly house ID; A means ASE, S means SPIL, G means GR BB: IC revision All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. -6- Preliminary W83178S 10. PACKAGE DIMENSIONS 28-pin SOP Headquarters Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792646 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale. -7- Publication Release Date: March 1999 Revision A1