XICOR X28HC64PM-50

X28HC64
X28HC64
64K
8K x 8 Bit
5 Volt, Byte Alterable E2PROM
•
FEATURES
•
•
•
•
•
•
55ns Access Time
Simple Byte and Page Write
—Single 5V Supply
—No External High Voltages or VPP Control
Circuits
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
Low Power CMOS
—40 mA Active Current Max.
—200 µA Standby Current Max.
Fast Write Cycle Times
—64 Byte Page Write Operation
—Byte or Page Write Cycle: 2ms Typical
—Complete Memory Rewrite: 0.25 sec. Typical
—Effective Byte Write Cycle Time: 32µs Typical
Software Data Protection
End of Write Detection
—DATA Polling
—Toggle Bit
•
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
JEDEC Approved Byte-Wide Pinout
DESCRIPTION
The X28HC64 is an 8K x 8 E2PROM, fabricated with
Xicor’s proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable nonvolatile memories the X28HC64 is a 5V only device. The
X28HC64 features the JEDEC approved pinout for bytewide memories, compatible with industry standard RAMs.
The X28HC64 supports a 64-byte page write operation,
effectively providing a 32µs/byte write cycle and enabling the entire memory to be typically written in 0.25
seconds. The X28HC64 also features DATA Polling and
Toggle Bit Polling, two methods providing early end of
write detection. In addition, the X28HC64 includes a
user-optional software data protection mode that further
enhances Xicor’s hardware write protect capability.
Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years.
TSOP
PIN CONFIGURATIONS
PLASTIC DIP
FLAT PACK
CERDIP
SOIC
WE
A7
3
26
NC
A6
4
25
A5
5
A4
6
A3
7
A2
8
21
A10
A1
9
20
CE
A0
I/O0
I/O1
10
19
11
18
I/O7
I/O6
12
17
I/O2
VSS
13
16
14
2
1 32 31 30
NC
3
WE
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
X28HC64
A6
5
29
A8
A5
6
28
A9
A8
A4
7
27
A11
24
A9
A3
8
26
NC
23
A11
A2
9
25
OE
22
OE
A1
10
24
A10
A0
11
23
CE
I/O1
I/O2
I/O3
I/O5
I/O6
12
13
15
17
18
NC
12
22
I/O7
I/O6
I/O0
A0
11
10
15
I/O3
21
13
14 15 16 17 18 19 20
I/O5
I/O3
I/O4
NC
9
A3
7
A3
A4
A5
A6
A7
A12
NC
NC
VCC
NC
WE
NC
A8
A9
A11
OE
3857 ILL F22
PGA
A1
VSS
I/O5
I/04
I/O0
X28HC64
I/O1
I/O2
X28HC64
NC
VCC
27
NC
28
2
A12
1
A7
NC
A12
VCC
LCC
PLCC
A2
A1
A0
I/O0
I/O1
I/O2
NC
VSS
NC
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
VSS
I/O4
I/O7
14
16
19
A2
8
X28HC64
A4
6
CE
20
A10
21
OE
22
A11
23
3857 FHD F03
A5
5
A6
3857 FHD F02.1
4
A12
2
A7
3
VCC
A9
28
24
NC
1
WE
27
A8
25
NC
26
3857 FHD F04
BOTTOM VIEW
© Xicor, Inc. 1994, 1995, 1996 Patents Pending
3857-3.0 8/5/97 T1/C0/D0 EW
1
Characteristics subject to change without notice
X28HC64
PIN DESCRIPTIONS
PIN NAMES
Addresses (A0–A12)
Symbol
A0–A12
I/O0–I/O7
WE
CE
OE
VCC
VSS
NC
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption
is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read operations.
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Ground
No Connect
3857 PGM T01
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X28HC64 through the
I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28HC64.
FUNCTIONAL DIAGRAM
65,536-BIT
E2PROM
ARRAY
X BUFFERS
LATCHES AND
DECODER
A0–A12
ADDRESS
INPUTS
I/O BUFFERS
AND LATCHES
Y BUFFERS
LATCHES AND
DECODER
I/O0–I/O7
DATA INPUTS/OUTPUTS
CE
OE
WE
CONTROL
LOGIC AND
TIMING
VCC
VSS
3857 FHD F01
2
X28HC64
DEVICE OPERATION
Write Operation Status Bits
Read
The X28HC64 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data
bus will be in a high impedance state when either OE or
CE is HIGH.
Figure 1. Status Bit Assignment
Write
I/O
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28HC64 supports both a
CE and WE controlled write cycle. That is, the address
is latched by the falling edge of either CE or WE,
whichever occurs last. Similarly, the data is latched
internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated,
will automatically continue to completion, typically within
2ms.
DP
TB
5
4
3
2
1
0
RESERVED
TOGGLE BIT
DATA POLLING
3857 FHD F11
DATA Polling (I/O7)
The X28HC64 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a simple
bit test operation to determine the status of the X28HC64,
eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the
complement of that data on I/O7 (i.e. write data = 0xxx
xxxx, read data = 1xxx xxxx). Once the programming
cycle is complete, I/O7 will reflect true data.
Page Write Operation
The page write feature of the X28HC64 allows the entire
memory to be written in 0.25 seconds. Page write allows
two to sixty-four bytes of data to be consecutively written
to the X28HC64 prior to the commencement of the
internal programming cycle. The host can fetch data
from another device within the system during a page
write operation (change the source address), but the
page address (A6 through A12) for each subsequent
valid write cycle to the part during this operation must be
the same as the initial page address.
Toggle Bit (I/O6)
The X28HC64 also provides another method for determining when the internal write cycle is complete. During
the internal programming cycle I/O6 will toggle from
HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to sixty-three bytes in the
same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW
transition, must begin within 100µs of the falling edge of
the preceding WE. If a subsequent WE HIGH to LOW
transition is not detected within 100µs, the internal
automatic programming cycle will commence. There is
no page write window limitation. Effectively the page
write window is infinitely wide, so long as the host
continues to access the device within the byte load cycle
time of 100µs.
3
X28HC64
DATA POLLING I/O7
Figure 2. DATA Polling Bus Sequence
WE
LAST
WRITE
CE
OE
VIH
A0–A12
VOH
HIGH Z
I/O7
VOL
An
An
An
X28HC64
READY
An
An
An
An
3857 FHD F12
Figure 3. DATA Polling Software Flow
DATA Polling can effectively reduce the time for writing
to the X28HC64. The timing diagram in Figure 2 illustrates the sequence of events on the bus. The software
flow diagram in Figure 3 illustrates one method of
implementing the routine.
WRITE DATA
NO
WRITES
COMPLETE?
YES
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
IO7
COMPARE?
NO
YES
READY
3857 FHD F13
4
X28HC64
THE TOGGLE BIT I/O6
Figure 4. Toggle Bit Bus Sequence
WE
LAST
WRITE
CE
OE
VOH
I/O6
*
HIGH Z
VOL
*
X28HC64
READY
* Beginning and ending state of I/O6 will vary.
3857 FHD F14
Figure 5. Toggle Bit Software Flow
The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28HC64 memories that is frequently updated.
Toggle Bit Polling can also provide a method for status
checking in multiprocessor applications. The timing
diagram in Figure 4 illustrates the sequence of events on
the bus. The software flow diagram in Figure 5 illustrates
a method for polling the Toggle Bit.
LAST WRITE
LOAD ACCUM
FROM ADDR n
COMPARE
ACCUM WITH
ADDR n
COMPARE
OK?
NO
YES
READY
3857 FHD F15
5
X28HC64
HARDWARE DATA PROTECTION
ture. The internal software data protection circuit is
enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain
set for the life of the device unless the reset command
is issued.
The X28HC64 provides two hardware features that
protect nonvolatile data from inadvertent writes.
• Default VCC Sense—All write functions are inhibited
when VCC is ≤3V typically.
• Write Inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle during
power-up and power-down, maintaining data integrity.
Once the software protection is enabled, the X28HC64
is also protected from inadvertent and accidental writes
in the powered-up state. That is, the software algorithm
must be issued prior to writing additional data to the
device.
SOFTWARE DATA PROTECTION
The X28HC64 offers a software controlled data protection feature. The X28HC64 is shipped from Xicor with
the software data protection NOT ENABLED; that is, the
device will be in the standard operating mode. In this
mode data should be protected during power-up/-down
operations through the use of external circuits. The host
would then have open read and write access of the
device once VCC was stable.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific addresses. Refer to Figure 6 and 7 for the sequence. The
three-byte sequence opens the page write window
enabling the host to write from one to sixty-four bytes of
data. Once the page load cycle has been completed, the
device will automatically be returned to the data protected state.
The X28HC64 can be automatically protected during
power-up and power-down without the need for external
circuits by employing the software data protection fea-
6
X28HC64
SOFTWARE DATA PROTECTION
Figure 6. Timing Sequence—Byte or Page Write
VCC
(VCC)
0V
DATA
ADDR
AA
1555
55
0AAA
A0
1555
WRITES
OK
tWC
WRITE
PROTECTED
CE
≤tBLC MAX
BYTE
OR
PAGE
WE
3857 FHD F16
Figure 7. Write Sequence for
Software Data Protection
Regardless of whether the device has previously been
protected or not, once the software data protection
algorithm is used, the X28HC64 will automatically disable further writes unless another command is issued to
deactivate it. If no further commands are issued the
X28HC64 will be write protected during power-down
and after any subsequent power-up.
WRITE DATA AA
TO ADDRESS
1555
WRITE DATA 55
TO ADDRESS
0AAA
Note:
WRITE DATA A0
TO ADDRESS
1555
BYTE/PAGE
LOAD ENABLED
WRITE DATA XX
TO ANY
ADDRESS
WRITE LAST
BYTE TO
LAST ADDRESS
OPTIONAL BYTE
OR PAGE WRITE
ALLOWED
AFTER tWC
RE-ENTERS DATA
PROTECTED STATE
3857 FHD F17
7
Once initiated, the sequence of write operations
should not be interrupted.
X28HC64
RESETTING SOFTWARE DATA PROTECTION
Figure 8. Reset Software Data Protection Timing Sequence
Vcc
DATA AA
ADDR 1555
55
0AAA
80
1555
AA
1555
55
0AAA
20
1555
≥tWC
STANDARD
OPERATING
MODE
CE
WE
3857 ILL F18.2
Figure 9. Software Sequence to
Deactivate Software Data Protection
In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an E2PROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC,
the X28HC64 will be in standard operating mode.
WRITE DATA AA
TO ADDRESS
1555
Note:
WRITE DATA 55
TO ADDRESS
0AAA
WRITE DATA 80
TO ADDRESS
1555
WRITE DATA AA
TO ADDRESS
1555
WRITE DATA 55
TO ADDRESS
0AAA
WRITE DATA 20
TO ADDRESS
1555
3857 ILL F19.2
8
Once initiated, the sequence of write operations
should not be interrupted.
X28HC64
prime concern. Enabling CE will cause transient current
spikes. The magnitude of these spikes is dependent on
the output capacitive loading of the I/Os. Therefore, the
larger the array sharing a common bus, the larger the
transient spikes. The voltage peaks associated with the
current transients can be suppressed by the proper
selection and placement of decoupling capacitors. As a
minimum, it is recommended that a 0.1µF high frequency ceramic capacitor be used between VCC and
VSS at each device. Depending on the size of the array,
the value of the capacitor may have to be larger.
SYSTEM CONSIDERATIONS
Because the X28HC64 is frequently used in large memory
arrays, it is provided with a two line control architecture
for both read and write operations. Proper usage can
provide the lowest possible power dissipation and eliminate the possibility of contention where multiple I/O pins
share the same bus.
To gain the most benefit it is recommended that CE be
decoded from the address bus and be used as the
primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation, this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is outputting data on the bus.
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between VCC and VSS for each
eight devices employed in the array. This bulk capacitor
is employed to overcome the voltage droop caused by
the inductive effects of the PC board traces.
Because the X28HC64 has two power modes, standby
and active, proper decoupling of the memory array is of
Normalized ICC(RD) by Temperature
Over Frequency
Normalized ICC(RD) @ 25% Over
the VCC Range and Frequency
1.4
1.4
1.2
- 55°C
+ 25°C
1.0
+ 125°C
5.5 VCC
1.2
ICC RD
NORMALIZED (mA)
ICC RD
NORMALIZED (mA)
5.5 VCC
0.8
0.6
0.4
5.0 VCC
1.0
4.5 VCC
0.8
0.6
0.4
0.2
0.2
0
10
FREQUENCY (MHz)
20
0
10
FREQUENCY (MHz)
3857 FHD F20.1
9
20
3857 FHD F21.1
X28HC64
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias
X28HC64 ..................................... –10°C to +85°C
X28HC64I, X28HC64M ............. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to VSS ....................................... –1V to +7V
D.C. Output Current ............................................. 5mA
Lead Temperature
(Soldering, 10 seconds) .............................. 300°C
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Supply Voltage
Limits
Commercial
Industrial
Military
0°C
–40°C
–55°C
+70°C
+85°C
+125°C
X28HC64
5V ±10%
3857 PGM T03.1
3857 PGM T02.1
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.(1)
Max.
Units
Test Conditions
CE = OE = VIL, WE = VIH, All
I/O’s = Open, Address Inputs =
TTL Levels @ f = 10 MHz
CE = VIH, OE = VIL
All I/O’s = Open, Other Inputs = VIH
CE = VCC – 0.3V, OE = GND
All I/O’s = Open, Other Inputs =
VCC – 0.3V
VIN = VSS to VCC
VOUT = VSS to VCC, CE = VIH
ICC
VCC Current (Active)
(TTL Inputs)
15
40
mA
ISB1
VCC Current (Standby)
(TTL Inputs)
VCC Current (Standby)
(CMOS Inputs)
1
2
mA
100
200
µA
±10
±10
0.8
VCC + 1
0.4
µA
µA
V
V
V
V
ISB2
ILI
ILO
VlL(2)
VIH(2)
VOL
VOH
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
–1
2
2.4
IOL = 5mA
IOH = –5mA
3857 PGM T04.2
Notes: (1) Typical values are for TA = 25°C and nominal supply voltage
(2) VIL min. and VIH max. are for reference only and are not tested.
10
X28HC64
ENDURANCE AND DATA RETENTION
Parameter
Min.
Max.
Minimum Endurance
Data Retention
100,000
100
Unit
Cycles
Years
3857 PGM T05.3
POWER-UP TIMING
Symbol
Parameter
Typ. (1)
Units
tPUR(3)
Power-up to Read Operation
Power-up to Write Operation
100
5
µs
ms
tPUW(3)
3857 PGM T06
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol
Parameter
Max.
Units
Test Conditions
CI/O(3)
CIN(3)
Input/Output Capacitance
Input Capacitance
10
6
pF
pF
VI/O = 0V
VIN = 0V
3857 PGM T07.1
A.C. CONDITIONS OF TEST
Input Pulse Levels
MODE SELECTION
0V to 3V
Input Rise and
Fall Times
Input and Output
Timing Levels
5ns
CE
L
L
H
OE
L
H
X
WE
H
L
X
X
X
L
X
X
H
1.5V
3857 PGM T08.1
Mode
Read
Write
Standby and
Write Inhibit
Write Inhibit
Write Inhibit
I/O
DOUT
DIN
High Z
Power
Active
Active
Standby
—
—
—
—
3857 PGM T09
Note:
(3) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUITS
SYMBOL TABLE
5V
WAVEFORM
1.92KΩ
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
OUTPUT
1.37KΩ
30pF
3857 FHD F22.3
11
X28HC64
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Read Cycle Limits
X28HC64-70
X28HC64-90
X28HC64-12
–55°C to +125°C –55°C to +125°C –55°C to +125°C
Symbol
Parameter
Min.
tRC
tCE
tAA
tOE
tLZ(4)
tOLZ(4)
tHZ(4)
tOHZ(4)
tOH
Read Cycle Time
Chip Enable Access Time
Address Access Time
Output Enable Access Time
CE LOW to Active Output
OE LOW to Active Output
CE HIGH to High Z Output
OE HIGH to High Z Output
Output Hold from
Address Change
70
Max.
Min.
Max.
90
70
70
35
0
0
Max. Units
120
90
90
40
0
0
30
30
0
Min.
120
120
50
0
0
30
30
0
30
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
3857 PGM T10.1
Read Cycle
tRC
ADDRESS
tCE
CE
tOE
OE
VIH
WE
tOLZ
tOHZ
tLZ
DATA I/O
tOH
HIGH Z
tHZ
DATA VALID
DATA VALID
tAA
3857 FHD F05
Notes: (4) tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured from the
point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
12
X28HC64
WRITE CYCLE LIMITS
Symbol
tWC(5)
tAS
tAH
tCS
tCH
tCW
tOES
tOEH
tWP
tWPH(6)
tDV(6)
tDS
tDH
tDW(6)
tBLC
Parameter
Typ.(1)
Min.
Write Cycle Time
Address Setup Time
Address Hold Time
Write Setup Time
Write Hold Time
CE Pulse Width
OE HIGH Setup Time
OE HIGH Hold Time
WE Pulse Width
WE HIGH Recovery
Data Valid
Data Setup
Data Hold
Delay to Next Write
Byte Load Cycle
2
Max.
5
0
50
0
0
50
0
0
50
50
1
50
0
10
0.15
100
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
µs
µs
3857 PGM T11.2
WE Controlled Write Cycle
tWC
ADDRESS
tAS
tAH
tCS
tCH
CE
OE
tOES
tOEH
tWP
WE
tDV
DATA IN
DATA VALID
tDS
tDH
HIGH Z
DATA OUT
3857 FHD F06
Notes: (5) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
(6) tWPH and tDW are periodically sampled and not 100% tested.
13
X28HC64
CE Controlled Write Cycle
tWC
ADDRESS
tAS
tAH
tCW
CE
tOES
OE
tOEH
tCS
tCH
WE
tDV
DATA IN
DATA VALID
tDS
tDH
HIGH Z
DATA OUT
3857 FHD F07
Page Write Cycle
(7)
OE
CE
tWP
tBLC
WE
tWPH
(8)
ADDRESS *
I/O
LAST BYTE
BYTE 0
BYTE 1
BYTE 2
BYTE n
*For each successive write within the page write operation, A6–A12 should be the same or
writes to an unknown address could occur.
BYTE n+1
BYTE n+2
tWC
3857 FHD F08
Notes: (7) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE
HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively
performing a polling operation.
(8) The timings shown above are unique to page write operations. Individual byte load operations within the page write must
conform to either the CE or WE controlled write cycle timing.
14
X28HC64
DATA Polling Timing Diagram(9)
ADDRESS
An
An
An
CE
WE
tOEH
tOES
OE
tDW
I/O7
DIN=X
DOUT=X
DOUT=X
tWC
3857 FHD F09
Toggle Bit Timing Diagram(9)
CE
WE
tOES
tOEH
OE
tDW
I/O6
HIGH Z
*
*
tWC
* I/O6 beginning and ending state will vary, depending upon actual tWC.
Note:
(9) Polling operations are by definition read cycles and are therefore subject to read cycle timings.
15
3857 FHD F10
X28HC64
PACKAGING INFORMATION
28-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
1.460 (37.08)
1.400 (35.56)
0.550 (13.97)
0.510 (12.95)
PIN 1 INDEX
PIN 1
0.085 (2.16)
0.040 (1.02)
1.300 (33.02)
REF.
0.160 (4.06)
0.125 (3.17)
SEATING
PLANE
0.030 (0.76)
0.015 (0.38)
0.150 (3.81)
0.125 (3.17)
0.110 (2.79)
0.090 (2.29)
0.062 (1.57)
0.050 (1.27)
0.020 (0.51)
0.016 (0.41)
0.610 (15.49)
0.590 (14.99)
0°
15°
TYP. 0.010 (0.25)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F04
16
X28HC64
PACKAGING INFORMATION
28-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D
1.490 (37.85)
1.435 (36.45)
0.610 (15.49)
0.500 (12.70)
PIN 1
0.100 (2.54)
0.035 (0.89)
1.30 (33.02)
REF.
0.225 (5.72)
0.140 (3.56)
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
TYP. 0.100 (2.54)
0.070 (1.78)
0.030 (0.76)
TYP. 0.055 (1.40)
0.026 (0.66)
0.014 (0.36)
TYP. 0.018 (0.46)
0.620 (15.75)
0.590 (14.99)
TYP. 0.614 (15.60)
0°
15°
TYP. 0.010 (0.25)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F08
17
X28HC64
PACKAGING INFORMATION
32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J
0.420 (10.67)
0.050 (1.27) TYP.
0.045 (1.14) x 45°
0.021 (0.53)
0.013 (0.33)
TYP. 0.017 (0.43)
0.495 (12.57)
0.485 (12.32)
TYP. 0.490 (12.45)
SEATING PLANE
±0.004 LEAD
CO – PLANARITY
—
0.015 (0.38)
0.095 (2.41)
0.060 (1.52)
0.140 (3.56)
0.100 (2.45)
TYP. 0.136 (3.45)
0.453 (11.51)
0.447 (11.35)
TYP. 0.450 (11.43)
0.048 (1.22)
0.042 (1.07)
0.300 (7.62)
REF.
PIN 1
0.595 (15.11)
0.585 (14.86)
TYP. 0.590 (14.99)
0.553 (14.05)
0.547 (13.89)
TYP. 0.550 (13.97)
0.400
(10.16)REF.
3° TYP.
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
3926 FHD F13
18
X28HC64
PACKAGING INFORMATION
28-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.2980 (7.5692)
0.2920 (7.4168)
0.4160 (10.5664)
0.3980 (10.1092)
0.0192 (0.4877)
0.0138 (0.3505)
0.7080 (17.9832)
0.7020 (17.8308)
0.1040 (2.6416)
0.0940 (2.3876)
BASE PLANE
SEATING PLANE
0.0110 (0.2794)
0.0040 (0.1016)
0.050 (1.270)
BSC
0.0160 (0.4064)
X 45°
0.0100 (0.2540)
0.0125 (0.3175)
0.0090 (0.2311)
0° – 8°
0.0350 (0.8890)
0.0160 (0.4064)
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
3. BACK EJECTOR PIN MARKED “KOREA”
4. CONTROLLING DIMENSION: INCHES (MM)
3926 FHD F17
19
X28HC64
PACKAGING INFORMATION
32-PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE E
0.150 (3.81) BSC
0.020 (0.51) x 45° REF.
0.095 (2.41)
0.075 (1.91)
PIN 1
0.022 (0.56)
0.006 (0.15)
0.055 (1.39)
0.045 (1.14)
TYP. (4) PLCS.
0.200 (5.08)
BSC
0.028 (0.71)
0.022 (0.56)
(32) PLCS.
0.050 (1.27) BSC
0.040 (1.02) x 45° REF.
TYP. (3) PLCS.
0.458 (11.63)
0.442 (11.22)
0.088 (2.24)
0.050 (1.27)
0.458 (11.63)
––
0.300 (7.62)
BSC
0.120 (3.05)
0.060 (1.52)
0.560 (14.22)
0.540 (13.71)
0.400 (10.16)
BSC
0.558 (14.17)
––
PIN 1 INDEX CORDER
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: ±1% NLT ±0.005 (0.127)
3926 FHD F14
20
X28HC64
PACKAGING INFORMATION
28-LEAD CERAMIC PIN GRID ARRAY PACKAGE TYPE K
12
13
15
17
18
11
10
14
16
19
A
0.008
9
8
20
21
7
6
22
23
0.050
A
5
2
28
24
25
4
3
1
27
26
0.080
0.070
TYP. 0.100
ALL LEADS
PIN 1 INDEX
NOTE: LEADS 4,12,18 & 26
0.080 4 CORNERS
0.070
0.100
0.080
0.072
0.061
0.020
0.016
0.660 (16.76)
0.640 (16.26)
A
A
0.185 (4.70)
0.175 (4.44)
0.561 (14.25)
0.541 (13.75)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F15
21
X28HC64
PACKAGING INFORMATION
28-LEAD CERAMIC FLAT PACK
0.019 (0.48)
0.015 (0.38)
PIN 1 INDEX
1
28
0.050 (1.27) BSC
0.740 (18.80)
MAX.
0.045 (1.14) MAX.
0.440 (11.18)
MAX.
0.006 (0.15)
0.003 (0.08)
0.370 (9.40)
0.250 (6.35)
TYP. 0.300 2 PLCS.
0.180 (4.57)
MIN.
0.130 (3.30)
0.090 (2.29)
0.045 (1.14)
0.025 (0.66)
0.030 (0.76)
MIN.
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F16
22
X28HC64
PACKAGING INFORMATION
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) TYPE T
SEE NOTE 2
12.50 (0.492)
12.30 (0.484)
PIN #1 IDENT.
O 0.76 (0.03)
0.50 (0.0197) BSC
SEE NOTE 2
8.02 (0.315)
7.98 (0.314)
0.26 (0.010)
0.14 (0.006)
1.18 (0.046)
1.02 (0.040)
0.17 (0.007)
0.03 (0.001)
SEATING
PLANE
0.58 (0.023)
0.42 (0.017)
14.15 (0.557)
13.83 (0.544)
14.80 ± 0.05
(0.583 ± 0.002)
SOLDER PADS
0.30 ± 0.05
(0.012 ± 0.002)
TYPICAL
32 PLACES
15 EQ. SPC. 0.50 ± 0.04
0.0197 ± 0.016 = 7.50 ± 0.06
(0.295 ± 0.0024) OVERALL
TOL. NON-CUMULATIVE
0.17 (0.007)
0.03 (0.001)
1.30 ± 0.05
(0.051 ± 0.002)
0.50 ± 0.04
(0.0197 ± 0.0016)
FOOTPRINT
NOTE:
1. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES).
23
3926 ILL F38.1
X28HC64
ORDERING INFORMATION
X28HC64
X
X
-X
Access Time
–55 = 55ns
–70 = 70ns
–90 = 90ns
–12 = 120ns
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = MIL-STD-883
Package
P = 28-Lead Plastic DIP
D = 28-Lead Cerdip
J = 32-Lead PLCC
S = 28-Lead Plastic SOIC
E = 32-Pad LCC
K = 28-Lead Pin Grid Array
F = 28-Lead Flat Pack
T = 32-Lead TSOP
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes
no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to
discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
US. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967;
4,883,976. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use as critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure
of the life support device or system, or to affect its satety or effectiveness.
24