ETC X28LV010P-12

X28LV010
1M
128K x 8 Bit
3.3 Volt, Byte Alterable E2PROM
FEATURES
DESCRIPTION
• Access Time: 70, 90, 120, 150ns
• Simple Byte and Page Write
—Single 3.3V±10% supply
—No external high voltages or VPP control circuits
—Self-timed
• no erase before write
• no complex programming algorithms
• no overerase problem
• Low Power CMOS
—Active: 20mA
—Standby: 20µA
• Software Data Protection
—Protects data against system level inadvertant
writes
• High Speed Page Write Capability
• Highly Reliable Direct Write™ Cell
—Endurance: 100,000 write cycles
—Data retention: 100 Years
• Early End of Write Detection
—DATA polling
—Toggle bit polling
The Xicor X28LV010 is a 128K x 8 E2PROM, fabricated with Xicor's proprietary, high performance, floating gate CMOS technology. Like all Xicor
programmable non-volatile memories the X28LV010
requires a single voltage supply. The X28LV010 features the JEDEC approved pinout for byte-wide memories, compatible with industry standard EPROMs.
The X28LV010 supports a 256-byte page write operation, effectively providing a 12µs/byte write cycle and
enabling the entire memory to be typically written in
less than 2.5 seconds. The X28LV010 also features
DATA Polling and Toggle Bit Polling, system software
support schemes used to indicate the early completion
of a write cycle. In addition, the X28LV010 supports
Software Data Protection option.
Xicor E2PROMs are designed and tested for applications requiring extended endurance. Data retention is
specified to be greater than 100 years.
BLOCK DIAGRAM
A8–A16
X Buffers
Latches and
Decoder
1M-Bit
E2PROM
Array
A0–A7
Y Buffers
Latches and
Decoder
I/O Buffers
and Latches
I/O0–I/O7
Data Inputs/Outputs
CE
OE
WE
Control
Logic and
Timing
VCC
VSS
Xicor, Inc. 2000 Patents Pending
2000-4003 9/6/00 EP
Characteristics subject to change without notice.
1 of 18
X28LV010
PIN CONFIGURATIONS
PDIP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
54 3 2
6
7
WE
NC
NC
VCC
A12
A15
A16
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
32 31
1
X28LV010
30
29
28
27
26
25
24
23
22
A14
A13
A8
A9
A11
OE
A10
8
X28LV010
9
(Top View)
10
11
CE
12
13
15 16 17 18 1920 21 I/O7
14
I/O4
I/O5
I/O6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I/O1
I/O2
VSS
I/O3
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
TSOP
PLCC
X28LV010
PIN DESCRIPTIONS
A11
A9
A8
A13
A14
NC
NC
NC
WE
VCC
NC
NC
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIN NAMES
Addresses (A0–A16)
Symbol
Description
The Address inputs select an 8-bit memory location
during a read or write operation.
A0–A16
Address Inputs
I/O0–I/O7
Data Input/Output
WE
Write Enable
CE
Chip Enable
OE
Output Enable
VCC
+3.3V
Chip Enable (CE)
The Chip Enable input must be LOW to enable all
read/write operations. When CE is HIGH, power consumption is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers and is used to initiate read operations.
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X28LV010 through
the I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to
the X28LV010.
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
NC
NC
VSS
NC
NC
I/O2
I/O1
I/O0
A0
A1
A2
A3
VSS
Ground
NC
No Connect
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE
LOW. The read operation is terminated by either CE or
OE returning HIGH. This two line control architecture
eliminates bus contention in a system environment.
The data bus will be in a high impedance state when
either OE or CE is HIGH.
Characteristics subject to change without notice.
2 of 18
X28LV010
Write
Write operations are initiated when both CE and WE
are LOW and OE is HIGH. The X28LV010 supports
both a CE and WE controlled write cycle. That is, the
address is latched by the falling edge of either CE or
WE, whichever occurs last. Similarly, the data is
latched internally by the rising edge of either CE or
WE, whichever occurs first. A byte write operation,
once initiated, will automatically continue to completion, typically within 5ms.
Page Write Operation
The page write feature of the X28LV010 allows the
entire memory to be written in 2.5 seconds. Page write
allows two to two hundred fifty-six bytes of data to be
consecutively written to the X28LV010 prior to the
commencement of the internal programming cycle.
The host can fetch data from another device within the
system during a page write operation (change the
source address), but the page address (A8 through
A16) for each subsequent valid write cycle to the part
during this operation must be the same as the initial
page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to two hundred fifty five
bytes in the same manner as the first byte was written.
Each successive byte load cycle, started by the WE
HIGH to LOW transition, must begin within 100µs of
the falling edge of the preceding WE. If a subsequent
WE HIGH to LOW transition is not detected within
100µs, the internal automatic programming cycle will
commence. There is no page write window limitation.
Effectively the page write window is infinitely wide, so
long as the host continues to access the device within
the byte load cycle time of 100µs.
Figure 1. Status Bit Assignment
I/O
DP
TB
5
4
3
2
1
0
Reserved
Toggle Bit
DATA Polling
DATA Polling (I/O7)
The X28LV010 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the
X28LV010, eliminating additional interrupt inputs or
external hardware. During the internal programming
cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e., write
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O7 will reflect true
data. Note: If the X28LV010 is in the protected state
and an illegal write operation is attempted DATA Polling
will not operate.
Toggle Bit (I/O6)
The X28LV010 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle, I/O6 will toggle
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
Write Operation Status Bits
The X28LV010 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Characteristics subject to change without notice.
3 of 18
X28LV010
DATA Polling I/O7
Figure 2. DATA Polling Bus Sequence
WE
Last
Write
CE
OE
VIH
VOH
High Z
I/O7
VOL
A0–A14
An
An
An
Figure 3. DATA Polling Software Flow
Write Data
X28LV010
Ready
An
An
An
An
DATA Polling can effectively halve the time for writing to
the X28LV010. The timing diagram in Figure 2 illustrates the sequence of events on the bus. The software
flow diagram in Figure 3 illustrates one method of
implement-ing the routine.
NO
Writes
Complete?
YES
Save Last Data
and Address
Read Last
Address
IO7
Compare?
NO
YES
X28LV010
Ready
Characteristics subject to change without notice.
4 of 18
X28LV010
The Toggle Bit I/O6
Figure 4. Toggle Bit Bus Sequence
WE
Last
Write
CE
OE
VOH
I/O6
High Z
VOL
Figure 5. Toggle Bit Software Flow
Last Write
Load ACCUM
from ADDR n
prised of multiple X28LV010 memories that is frequently updated. Toggle Bit Polling can also provide a
method for status checking in multiprocessor applications. The timing diagram in Figure 4 illustrates the
sequence of events on the bus. The software flow diagram in Figure 5 illustrates a method for polling the
Toggle Bit.
HARDWARE DATA PROTECTION
The X28LV010 provides three hardware features that
protect nonvolatile data from inadvertent writes.
Compare
ACCUM with
ADDR n
Compare
OK?
X28LV010
Ready
– Noise Protection—A WE pulse less than 10ns will
not initiate a write cycle.
NO
YES
Ready
The Toggle Bit can eliminate the software housekeeping chore of saving and fetching the last address and
data written to a device in order to implement DATA
Polling. This can be especially helpful in an array com-
– Default VCC Sense—All functions are inhibited when
VCC is ≤ 2.5V.
– Write inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle during power-up and power-down, maintaining data
integrity.
SOFTWARE DATA PROTECTION
The X28LV010 offers a software controlled data protection feature. The X28LV010 is shipped from Xicor
with the software data protection NOT ENABLED: that
is the device will be in the standard operating mode. In
this mode data should be protected during power-up/
-down operations through the use of external circuits.
The host would then have open read and write access
of the device once VCC was stable.
Characteristics subject to change without notice.
5 of 18
X28LV010
The X28LV010 can be automatically protected during
power-up and power-down without the need for external circuits by employing the software data protection
feature. The internal software data protection circuit is
enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will
remain set for the life of the device unless the reset
command is issued.
Once the software protection is enabled, the X28LV010
is also protected from inadvertent and accidental
writes in the powered-up state. That is, the software
algorithm must be issued prior to writing additional
data to the device.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific
addresses. Refer to Figures 6 and 7 for the sequence.
The three byte sequence opens the page write window
enabling the host to write from one to two hundred fiftysix bytes of data. Once the page load cycle has been
completed, the device will automatically be returned to
the data protected state.
Software Data Protection
Figure 6. Timing Sequence—Byte or Page Write
VCC
(VCC)
0V
Data
ADDR
AA
5555
55
2AAA
A0
5555
CE
≤ tBLC MAX
WE
tWC
Writes
OK
Write
Protected
Byte
or
Page
Characteristics subject to change without notice.
6 of 18
X28LV010
Figure 7. Write Sequence for Software Data
Protection
Regardless of whether the device has previously been
protected or not, once the software data protection
algorithm is used and data has been written, the
X28LV010 will automatically disable further writes
unless another command is issued to cancel it. If no
further commands are issued the X28LV010 will be
write protected during power-down and after any subsequent power-up. The state of A15 and A16 while executing the algorithm is don’t care.
Write Data AA
to Address
5555
Write Data 55
to Address
2AAA
Note: Once initiated, the sequence of write operations
should not be interrupted.
Write Data A0
to Address
5555
Write Data XX
to any
Address
Optional
Byte/Page
Load Operation
Write Last
Byte to
Last Address
After tWC
Re-Enters Data
Protected State
Resetting Software Data Protection
Figure 8. Reset Software Data Protection Timing Sequence
VCC
Data
ADDR
AA
5555
55
2AAA
80
5555
AA
5555
55
2AAA
20
5555
≥ tWC
Standard
Operating
Mode
CE
WE
Characteristics subject to change without notice.
7 of 18
X28LV010
Figure 9. Software Sequence to Deactivate
Software Data Protection
Write Data AA
to Address
5555
Write Data 55
to Address
2AAA
Write Data 80
to Address
5555
Write Data AA
to Address
5555
Write Data 55
to Address
2AAA
Write Data 20
to Address
5555
In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an E2PROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC,
the X28LV010 will be in standard operating mode.
SYSTEM CONSIDERATIONS
Because the X28LV010 is frequently used in large
memory arrays it is provided with a two line control
architecture for both read and write operations. Proper
usage can provide the lowest possible power dissipation and eliminate the possibility of contention where
multiple I/O pins share the same bus.
To gain the most benefit it is recommended that CE be
decoded from the address bus and be used as the primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is outputting data on the bus.
Because the X28LV010 has two power modes,
standby and active, proper decoupling of the memory
array is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is
dependent on the output capacitive loading of the I/Os.
Therefore, the larger the array sharing a common bus,
the larger the transient spikes. The voltage peaks
associated with the current transients can be suppressed by the proper selection and placement of
decoupling capacitors. As a minimum, it is recommended that a 0.1µF high frequency ceramic capacitor
be used between VCC and VSS at each device.
Depending on the size of the array, the value of the
capacitor may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between VCC and VSS for
each eight devices employed in the array. This bulk
capacitor is employed to overcome the voltage drop
caused by the inductive effects of the PC board traces.
Note: Once initiated, the sequence of write operations
should not be interrupted.
Characteristics subject to change without notice.
8 of 18
X28LV010
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias
X28LV010 ....................................... –10°C to +85°C
X28LV010I .................................... –65°C to +135°C
Storage temperature ........................ –65°C to +150°C
Voltage on any input pins (including
NC pins) with respect to ground .......... –0.5 to 6.25V
Voltage on any output pins with
respect to ground .........................–0.5 to VCC +0.5V
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds)........ 300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
indicated in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
RECOMMEND OPERATING CONDITIONS
Temperature
Min.
Max.
Supply Voltage
Limits
X28LV010
3.3V ±10%
Commercial
0°C
+70°C
Industrial
–40°C
+85°C
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Limits
Symbol
Parameter
ICC
ISB2
Min.
Max.
Units
Test Conditions
VCC Current (Active) (TTL Inputs)
20
mA
CE = OE = VIL, WE = VIH, All I/O’s = Open,
Address Inputs = .4V/2.4V Levels @
f = 10MHz
VCC Current (Standby)
(CMOS Inputs)
Com.
20
µA
Ind.
50
µA
CE = VCC – 0.3V, OE = VIL, All I/O’s = Open,
Other Inputs = VCC
ILI
Input Leakage Current
10
µA
VIN = VSS to VCC
ILO
Output Leakage Current
10
µA
VOUT = VSS to VCC, CE = VIH
(1)
Input LOW Voltage
0.5
0.8
V
(1)
VlH
Input HIGH Voltage
2
VCC + 0.3
V
VOL
Output LOW Voltage
0.4
V
IOL = 2.1mA
VOH
Output HIGH Voltage
V
IOH = –400µA
VlL
2.4
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
POWER-UP TIMING
Symbol
Parameter
Max.
Units
tPUR(2)
Power-up to Read Operation
100
µs
(2)
Power-up to Write Operation
5
ms
tPUW
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol
(2)
CI/O
CIN(2)
Parameter
Max.
Units
Test Conditions
Input/Output Capacitance
10
pF
VI/O = 0V
Input Capacitance
10
pF
VIN = 0V
Characteristics subject to change without notice.
9 of 18
X28LV010
ENDURANCE AND DATA RETENTION
Parameter
Min.
Endurance(2)
10,000
Cycles Per Byte
100,000
Cycles Per Page
100
Years
(2)
Endurance
(2)
Data Retention
Max.
Units
Notes: (2) This parameter is periodically sampled and not 100% tested.
A.C. CONDITIONS OF TEST
SYMBOL TABLE
Input pulse levels
0V to 3V
Input rise and fall times
10ns
Input and output timing levels
1.5V
WAVEFORM
MODE SELECTION
CE
OE
WE
Mode
I/O
Power
L
L
H
Read
DOUT
Active
L
H
L
Write
DIN
Active
H
X
X
Standby and
write inhibit
High Z
Standby
X
L
X
Write inhibit
—
—
X
X
H
Write inhibit
—
—
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
EQUIVALENT A.C. LOAD CIRCUIT
3.3V
1.92KΩ
Output
1.37KΩ
100pF
Characteristics subject to change without notice.
10 of 18
X28LV010
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits
X28LV010-70 X28LV010-90 X28LV010-120 X28LV010-150
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
tCE
Chip Enable Access Time
70
90
120
150
ns
tAA
Address Access Time
70
90
120
150
ns
tOE
Output Enable Access Time
35
40
40
40
ns
tLZ(3)
CE LOW to Active Output
0
0
0
0
ns
tOLZ(3)
OE LOW to Active Output
0
0
0
0
ns
(3)
CE HIGH to High Z Output
40
50
50
50
ns
tOHZ
OE HIGH to High Z Output
40
50
50
50
ns
tOH
Output Hold from Address
Change
tHZ
(3)
0
0
0
0
ns
Notes: (3) tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with CL = 5pF,
from the point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
Read Cycle
tRC
Address
tCE
CE
tOE
OE
VIH
WE
tOLZ
tOHZ
tLZ
Data I/O
High Z
tOH
tHZ
Data Valid
Data Valid
tAA
Characteristics subject to change without notice.
11 of 18
X28LV010
Write Cycle Limits
Symbol
(4)
tWC
Parameter
Min.
Write Cycle Time
Max.
Units
5
ms
tAS
Address Setup Time
0
ns
tAH
Address Hold Time
50
ns
tCS
Write Setup Time
0
ns
tCH
Write Hold Time
0
ns
tCW
CE Pulse Width
50
ns
tOES
OE HIGH Setup Time
0
ns
tOEH
OE HIGH Hold Time
0
ns
tWP
WE Pulse Width
50
ns
WE HIGH Recovery
50
ns
tWPH
tDS
Data Setup
50
ns
tDH
Data Hold
10
ns
tDW
Delay to Next Write
10
µs
tBLC
Byte Load Cycle
0.2
100
µs
Notes: (4) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the
device requires to complete internal write operation.
WE Controlled Write Cycle
tWC
Address
tAS
tAH
tCS
tCH
CE
OE
tOES
tOEH
tWP
WE
tWPH
Data In
Data Valid
tDS
Data Out
tDH
High Z
Characteristics subject to change without notice.
12 of 18
X28LV010
CE Controlled Write Cycle
tWC
Address
tAS
tAH
tCW
CE
tWPH
tOES
OE
tOEH
tCH
tCS
WE
Data Valid
Data In
tDS
Data Out
tDH
High Z
Page Write Cycle
OE(5)
CE
tWP
tBLC
WE
tWPH
Address *(6)
Last Byte
I/O
Byte 0
Byte 1
Byte 2
Byte n
Byte n+1
Byte n+2
tWC
*For each successive write within the page write operation, A8–A16
should be the same or writes to an unknown address could occur.
Notes: (5) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE
HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.
(6) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to
either the CE or WE controlled write cycle timing.
Characteristics subject to change without notice.
13 of 18
X28LV010
DATA Polling Timing Diagram(7)
Address
An
An
An
CE
WE
tOEH
tOES
OE
tDW
I/O7
DIN = X
DOUT = X
DOUT = X
tWC
Toggle Bit Timing Diagram
CE
WE
tOES
tOEH
OE
tDW
I/O6
High Z
*
*
tWC
* I/O6 beginning and ending state will vary.
Notes: (7) Polling operations are by definition read cycles and are therefore subject to read cycle timings.
Characteristics subject to change without notice.
14 of 18
X28LV010
PACKAGING INFORMATION
32-Lead Plastic Leaded Chip Carrier Package Type J
0.030" Typical
32 Places
0.050"
Typical
0.420 (10.67)
0.050"
Typical
0.510"
Typical
0.400"
0.050 (1.27) Typ.
0.300"
Ref.
0.410"
FOOTPRINT
0.045 (1.14) x 45°
0.021 (0.53)
0.013 (0.33)
Typ. 0.017 (0.43)
Seating Plane
±0.004 Lead
CO – Planarity
—
0.015 (0.38)
0.495 (12.57)
0.485 (12.32)
Typ. 0.490 (12.45)
0.095 (2.41)
0.060 (1.52)
0.140 (3.56)
0.100 (2.45)
Typ. 0.136 (3.45)
0.453 (11.51)
0.447 (11.35)
Typ. 0.450 (11.43)
0.300 (7.62)
Ref.
0.048 (1.22)
0.042 (1.07)
Pin 1
0.595 (15.11)
0.585 (14.86)
Typ. 0.590 (14.99)
0.553 (14.05)
0.547 (13.89)
Typ. 0.550 (13.97)
0.400
(10.16)Ref.
3° Typ.
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
Characteristics subject to change without notice.
15 of 18
X28LV010
PACKAGING INFORMATION
32-Lead Plastic Dual In-Line Package Type P
1.665 (42.29)
1.644 (41.76)
0.557 (14.15)
0.510 (12.95)
Pin 1 Index
Pin 1
0.085 (2.16)
0.040 (1.02)
1.500 (38.10)
Ref.
0.160 (4.06)
0.140 (3.56)
Seating
Plane
0.030 (0.76)
0.015 (0.38)
0.160 (4.06)
0.125 (3.17)
0.110 (2.79)
0.090 (2.29)
0.070 (17.78)
0.030 (7.62)
0.022 (0.56)
0.014 (0.36)
0.625 (15.88)
0.590 (14.99)
Typ. 0.010 (0.25)
0°
15°
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
Characteristics subject to change without notice.
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X28LV010
PACKAGING INFORMATION
40-Lead Thin Small Outline Package (TSOP) Type T
0.493 (12.522)
0.483 (12.268)
0.045 (1.143)
0.035 (0.889) Pin #1 Ident
O 0.040 (1.016) 0.005 (0.127) Dp.
O 0.030 (0.762) X 0.003 (0.076) Dp.
(0.038)
0.965
0.048 (1.219)
1
0.0197 (0.500)
0.396 (10.058)
0.392 (9.957)
0.007 (0.178)
15° Typ.
A
0.0025 (0.065)
Seating
Plane
0.557 (14.148)
0.547 (13.894)
Seating
Plane
0.010 (0.254)
0.006 (0.152)
0.040 (1.016)
Detail A
0.032 (0.813) Typ.
0.006 (0.152)
Typ.
0.017 (0.432)
4° Typ.
0.017 (0.432)
0.020 (0.508) Typ.
14.80 ± 0.05
(0.583 ± 0.002)
0.30 ± 0.05
Solder
Pads
FOOTPRINT
(0.012 ± 0.002)
Typical
40 Places
0.17 (0.007)
0.03 (0.001) 1.30 ± 0.05
(0.051 ± 0.002)
15 Eq. Spc.@ 0.50 ± 0.04
0.0197 0.016 = 9.50 ± 0.06
(0.374 ± 0.0024) Overall
Tol. Non-Cumulative
0.50 ± 0.04
(0.0197 ± 0.0016)
NOTE: ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES).
Characteristics subject to change without notice.
17 of 18
X28LV010
Ordering Information
X28LV010
Device
X
X
-X
Access Time
–70 = 70ns
–90 = 90ns
–12 = 120ns
–15 = 150ns
Temperature Range
Blank = Commercial = 0°C to 70°C
I = Industrial = –40°C to +85°C
Package
P = 32-Lead PDIP
J = 32-Lead PLCC
T = 40-Lead TSOP
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express,
statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes
no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and
without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137;
5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and
correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1.
Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2.
A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice.
18 of 18